AD AD5763CSUZ

Preliminary Technical Data
Complete Dual, 16-Bit, High Accuracy,
Serial Input, ±5V DACs
AD5763
FEATURES
GENERAL DESCRIPTION
Complete Dual, 16-bit digital-to-analog
converters (DACs)
Programmable output range:
±4.096 V, ±4.201 V, or ±4.311 V
±1 LSB maximum INL error, ±1 LSB maximum DNL error
Low noise: 60 nV/√Hz
Settling time: 10 µs maximum
Integrated reference buffers
On-chip die temperature sensor
Output control during power-up/brownout
Programmable short-circuit protection
Simultaneous updating via LDAC
Asynchronous CLR to zero code
Digital offset and gain adjust
Logic output control pins
DSP-/microcontroller-compatible serial interface
Temperature range: −40°C to +105°C
iCMOS® process technology1
The AD5763 is a Dual, 16-bit, serial input, bipolar voltage
output digital-to-analog converter that operates from supply
voltages of ±4.75 V up to ±5.25 V. Nominal full-scale output
range is ±4.096 V. The AD5763 provides integrated output
amplifiers, reference buffers and proprietary power-up/powerdown control circuitry. The part also features a digital I/O port,
which is programmed via the serial interface. The parts
incorporate digital offset and gain adjust registers per channel.
APPLICATIONS
Industrial automation
Open-/closed-loop servo control
Process control
Data acquisition systems
Automatic test equipment
Automotive test and measurement
High accuracy instrumentation
The AD5763 is a high performance converter that offers
guaranteed monotonicity, integral nonlinearity (INL) of ±1 LSB,
low noise, and 10 µs settling time. During power-up (when the
supply voltages are changing), the outputs are clamped to 0 V
via a low impedance path.
The AD5763 uses a serial interface that operates at clock rates of up
to 30 MHz and is compatible with DSP and microcontroller
interface standards. Double buffering allows the simultaneous
updating of all DACs. The input coding is programmable to either
twos complement or offset binary formats. The asynchronous clear
function clears all DAC registers to either bipolar zero or zero scale
depending on the coding used. The AD5763 is ideal for both
closed-loop servo control and open-loop control applications. The
AD5763 is available in a 32-lead TQFP, and offers guaranteed
specifications over the −40°C to +105°C industrial temperature
range. See Figure 1, the functional block diagram.
Table 1. Related Devices
Part No.
AD5764
AD5765
1
Description
Complete quad, 16-bit, high accuracy, serial
input, ±10V output DAC
Complete quad, 16-bit, high accuracy, serial
input, ±5V DAC
For analog systems designers within industrial/instrumentation equipment
OEMs who need high performance ICs at higher voltage levels, iCMOS is a
technology platform that enables the development of analog ICs capable of
30 V and operating at ±15 V supplies, allowing dramatic reductions in power
consumption and package size, and increased ac and dc performance.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
AD5763
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Data Register............................................................................... 21
Applications....................................................................................... 1
Coarse Gain Register ................................................................. 21
General Description ......................................................................... 1
Fine Gain Register...................................................................... 22
Revision History ............................................................................... 2
Offset Register ............................................................................ 22
Functional Block Diagram .............................................................. 3
Offset and Gain Adjustment Worked Example...................... 23
Specifications..................................................................................... 4
AD5763 Features ............................................................................ 24
AC Performance Characteristics .................................................... 6
Analog Output Control ............................................................. 24
Timing Characteristics..................................................................... 7
Digital Offset and Gain Control............................................... 24
Absolute Maximum Ratings.......................................................... 10
Programmable Short-Circuit Protection ................................ 24
ESD Caution................................................................................ 10
Digital I/O Port........................................................................... 24
Pin Configuration and Function Descriptions........................... 11
die Temperature Sensor............................................................. 24
Typical Performance Characteristics ........................................... 13
Local Ground Offset Adjust...................................................... 24
Terminology .................................................................................... 17
Applications Information .............................................................. 25
Theory of Operation ...................................................................... 18
Typical Operating Circuit ......................................................... 25
DAC Architecture....................................................................... 18
Layout Guidelines........................................................................... 26
Reference Buffers........................................................................ 18
Galvanically Isolated Interface ................................................. 26
Serial Interface ............................................................................ 18
Microprocessor Interfacing....................................................... 26
Simultaneous Updating via LDAC ........................................... 19
Evaluation Board ........................................................................ 27
Transfer Function ....................................................................... 20
Outline Dimensions ....................................................................... 28
Asynchronous Clear (CLR)....................................................... 20
Ordering Guide .......................................................................... 28
Function Register ....................................................................... 21
REVISION HISTORY
Preliminary Version: PrA December 11, 2007
Rev. PrA | Page 2 of 31
Preliminary Technical Data
AD5763
FUNCTIONAL BLOCK DIAGRAM
PGND
AVDD
AVSS
AVDD
REFGND
AVSS
REFA
DVCC
DGND
REFERENCE
BUFFERS
AD5763
16
SDIN
SCLK
SYNC
SDO
D0
INPUT SHIFT
REGISTER
AND
CONTROL
LOGIC
INPUT
REG A
DAC
REG A
RSTOUT
RSTIN
VOLTAGE
MONITOR
AND
CONTROL
ISCC
G1
16
DAC A
VOUTA
G2
GAIN REG A
AGNDA
OFFSET REG A
INPUT
REG B
DAC
REG B
G1
16
DAC B
VOUTB
G2
D1
GAIN REG B
AGNDB
OFFSET REG B
REFERENCE
BUFFERS
BIN/2SCOMP
CLR
LDAC
Figure 1.
Rev. PrA | Page 3 of 31
REFB
TEMP
SENSOR
TEMP
AD5763
Preliminary Technical Data
SPECIFICATIONS
AVDD = 4.75 V to 5.25 V, AVSS = −4.75 V to −5.25 V, AGNDX = DGND = REFGND = PGND = 0 V; REFA = REFB = 2.048 V;
DVCC = 2.7 V to 5.25 V, RLOAD = 5 kΩ, CLOAD = 200 pF. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
B Grade1
C Grade1
Unit
16
±2
±1
±2
16
±1
±1
±2
Bits
LSB max
LSB max
mV max
Bipolar Zero TC2
Zero-Scale Error
±2
±2
±2
±2
ppm FSR/°C max
mV max
Zero-Scale TC2
Gain Error
±2
±0.02
±2
±0.02
ppm FSR/°C max
% FSR max
±2
0.5
±2
0.5
ppm FSR/°C max
LSB max
2.048
1
±10
1 to 2.1
2.048
1
±10
1 to 2.1
V nominal
MΩ min
µA max
V min to V max
±1% for specified performance
Typically 100 MΩ
Typically ±30 nA
±4.311
±4.42
±13
±15
10
±1
±4.311
±4.42
±13
±15
10
±1
V min/V max
V min/V max
ppm FSR/500 hours typ
ppm FSR/1000 hours typ
mA typ
mA max
REFA, REFB = 2.048V
REFA, REFB = 2.1V
200
1000
0.3
200
1000
0.3
pF max
pF max
Ω max
Parameter
ACCURACY
Resolution
Relative Accuracy (INL)
Differential Nonlinearity
Bipolar Zero Error
Gain TC2
DC Crosstalk2
REFERENCE INPUT2
Reference Input Voltage
DC Input Impedance
Input Current
Reference Range
OUTPUT CHARACTERISTICS2
Output Voltage Range3
Output Voltage Drift vs. Time
Short Circuit Current
Load Current
Capacitive Load Stability
RL = ∞
RL = 10 kΩ
DC Output Impedance
DIGITAL INPUTS2
VIH, Input High Voltage
VIL, Input Low Voltage
Input Current
Pin Capacitance
Test Conditions/Comments
Outputs unloaded
Guaranteed monotonic
At 25°C; error at other
temperatures obtained using
bipolar zero TC
At 25°C; error at other
temperatures obtained using zero
scale TC
At 25°C; error at other
temperatures obtained using gain
TC
RISCC = 6 kΩ, see Figure 29
For specified performance
DVCC = 2.7 V to 5.25 V, JEDEC
compliant
2
0.8
±1
10
2
0.8
±1
10
V min
V max
µA max
pF max
Rev. PrA | Page 4 of 31
Per pin
Per pin
Preliminary Technical Data
Parameter
DIGITAL OUTPUTS (D0, D1, SDO)2
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
High Impedance Leakage Current
High Impedance Output
Capacitance
POWER REQUIREMENTS
AVDD/AVSS
DVCC
Power Supply Sensitivity2
∆VOUT/∆ΑVDD
AIDD
AISS
DICC
Power Dissipation
AD5763
B Grade1
C Grade1
Unit
Test Conditions/Comments
0.4
DVCC − 1
0.4
0.4
DVCC − 1
0.4
V max
V min
V max
DVCC − 0.5
DVCC − 0.5
V min
±1
5
±1
5
µA max
pF typ
DVCC = 5 V ± 5%, sinking 200 µA
DVCC = 5 V ± 5%, sourcing 200 µA
DVCC = 2.7 V to 3.6 V,
sinking 200 µA
DVCC = 2.7 V to 3.6 V,
sourcing 200 µA
SDO only
SDO only
4.75 to 5.25
2.7 to 5.25
4.75 to 5.25
2.7 to 5.25
V min/V max
V min/V max
−85
1.75
1.38
1.2
138
−85
1.75
1.38
1.2
138
dB typ
mA/channel max
mA/channel max
mA max
mW typ
1
Temperature range: -40°C to +105°C; typical at +25°C.
Guaranteed by design and characterization; not production tested.
3
Output amplifier headroom requirement is 0.5 V minimum.
2
Rev. PrA | Page 5 of 31
Outputs unloaded
Outputs unloaded
VIH = DVCC, VIL = DGND, 750 µA typ
±5 V operation output unloaded
AD5763
Preliminary Technical Data
AC PERFORMANCE CHARACTERISTICS
AVDD = 4.75 V to 5.25 V, AVSS = −4.75 V to −5.25 V, AGNDX = DGND = REFGND = PGND = 0 V; REFA = REFB = 2.048 V;
DVCC = 2.7 V to 5.25 V, RLOAD = 5 kΩ, CLOAD = 200 pF. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
DYNAMIC PERFORMANCE1
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Channel-to-Channel Isolation
DAC-to-DAC Crosstalk
Digital Crosstalk
Digital Feedthrough
Output Noise (0.1 Hz to 10 Hz)
Output Noise (0.1 Hz to 100 kHz)
1/f Corner Frequency
Output Noise Spectral Density
Complete System Output Noise Spectral
Density2
1
2
A Grade
B Grade
C Grade
Unit
Test Conditions/Comments
8
10
2
5
8
25
80
8
2
2
8
10
2
5
8
25
80
8
2
2
8
10
2
5
8
25
80
8
2
2
µs typ
µs max
µs typ
V/µs typ
nV-sec typ
mV max
dB typ
nV-sec typ
nV-sec typ
nV-sec typ
Full-scale step to ±1 LSB
0.1
45
1
60
80
0.1
45
1
60
80
0.1
45
1
60
80
LSB p-p typ
µV rms max
kHz typ
nV/√Hz typ
nV/√Hz typ
Guaranteed by design and characterization; not production tested.
Includes noise contributions from integrated reference buffers, 16-bit DAC and output amplifier.
Rev. PrA | Page 6 of 31
512 LSB step settling
Effect of input bus activity on DAC
outputs
Measured at 10 kHz
Measured at 10 kHz
Preliminary Technical Data
AD5763
TIMING CHARACTERISTICS
AVDD = 4.75 V to 5.25 V, AVSS = −4.75 V to −5.25 V, AGNDX = DGND = REFGND = PGND = 0 V; REFA = REFB = 2.048 V;
DVCC = 2.7 V to 5.25 V, RLOAD = 5 kΩ, CLOAD = 200 pF. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1, 2, 3
t1
t2
t3
t4
t54
t6
t7
t8
t9
t10
t11
t12
t13
t14
t155, 6
t16
t17
t18
Limit at TMIN, TMAX
33
13
13
13
13
40
2
5
1.4
400
10
500
10
10
2
25
13
2
170
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
µs min
ns min
ns min
ns max
µs max
ns min
µs max
ns max
ns min
µs min
ns min
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24th SCLK falling edge to SYNC rising edge
Minimum SYNC high time
Data setup time
Data hold time
SYNC rising edge to LDAC falling edge (all DACs updated)
SYNC rising edge to LDAC falling edge (single DAC updated)
LDAC pulse width low
LDAC falling edge to DAC output response time
DAC output settling time
CLR pulse width low
CLR pulse activation time
SCLK rising edge to SDO valid
SYNC rising edge to SCLK falling edge
SYNC rising edge to DAC output response time (LDAC = 0)
LDAC falling edge to SYNC rising edge
1
Guaranteed by design and characterization; not production tested.
All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
See Figure 2, Figure 3, and Figure 4.
4
Standalone mode only.
5
Measured with the load circuit of Figure 5.
6
Daisy-chain mode only.
2
3
Rev. PrA | Page 7 of 31
AD5763
Preliminary Technical Data
t1
SCLK
1
2
24
t3
t6
t2
t4
t5
SYNC
t8
t7
SDIN
DB0
DB23
t10
t9
LDAC
t10
t18
t12
t11
VOUTX
LDAC = 0
t12
t17
VOUTX
t13
CLR
t14
05303-002
VOUTX
Figure 2. Serial Interface Timing Diagram
t1
SCLK
24
t3
t6
48
t2
t5
t16
t4
SYNC
t7
SDIN
t8
DB23
DB0
INPUT WORD FOR DAC N
DB23
DB0
t15
INPUT WORD FOR DAC N–1
DB23
SDO
UNDEFINED
DB0
INPUT WORD FOR DAC N
t9
t10
LDAC
Figure 3. Daisy-Chain Timing Diagram
Rev. PrA | Page 8 of 31
Preliminary Technical Data
AD5763
SCLK
24
48
SYNC
DB23
DB0
DB23
DB0
NOP CONDITION
INPUT WORD SPECIFIES
REGISTER TO BE READ
DB23
SDO
UNDEFINED
DB0
SELECTED REGISTER DATA
CLOCKED OUT
Figure 4. Readback Timing Diagram
200µA
VOH (MIN) OR
VOL (MAX)
CL
50pF
200µA
IOH
Figure 5. Load Circuit for SDO Timing Diagram
Rev. PrA | Page 9 of 31
05303-005
TO OUTPUT
PIN
IOL
05303-004
SDIN
AD5763
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.
Table 5.
Parameter
AVDD to AGNDX, DGND
AVSS to AGNDX, DGND
DVCC to DGND
Digital Inputs to DGND
Digital Outputs to DGND
REFA, REFB to AGNDX, PGND
VOUTA, VOUTB, VOUTC, VOUTD to
AGNDX
AGNDX to DGND
Operating Temperature Range (TA)
Industrial
Storage Temperature Range
Junction Temperature (TJ max)
Power Dissipation
32-Lead TQFP
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature
Soldering
Rating
−0.3 V to +17 V
+0.3 V to −17 V
−0.3 V to +7 V
−0.3 V to DVCC + 0.3 V or 7 V
(whichever is less)
−0.3 V to DVCC + 0.3 V
−0.3 V to AVDD + 0.3V
AVSS to AVDD
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
−0.3 V to +0.3 V
−40°C to +105°C
−65°C to +150°C
150°C
(TJ max – TA)/ θJA
65°C/W
12°C/W
JEDEC Industry Standard
J-STD-020
Rev. PrA | Page 10 of 31
Preliminary Technical Data
AD5763
BIN/2sCOMP
AVDD
AVSS
TEMP
REFGND
NC
REFB
REFA
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
32
SYNC
SCLK
SDIN
SDO
CLR
LDAC
D0
D1
25
1
24
NC
NC
VOUTA
AGNDA
AGNDB
VOUTB
NC
NC
PIN 1
INDICATOR
AD5763
TOP VIEW
(Not to Scale)
8
17
16
RSTOUT
RSTIN
DGND
DVCC
AVDD
PGND
AVSS
ISCC
9
Figure 6. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
Mnemonic
SYNC
2
SCLK
3
4
51
6
SDIN
SDO
CLR1
LDAC
7, 8
D0, D1
9
RSTOUT
10
RSTIN
11
12
13, 31
14
15, 30
16
DGND
DVCC
AVDD
PGND
AVSS
ISCC
17
18
19
NC
NC
VOUTB
20
21
AGNDB
AGNDA
Description
Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low,
data is transferred in on the falling edge of SCLK.
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at
clock speeds up to 30 MHz.
Serial Data Input. Data must be valid on the falling edge of SCLK.
Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode.
Negative Edge Triggered Input. Asserting this pin sets the DAC registers to 0x0000.
Load DAC. Logic input. This is used to update the DAC registers and consequently the analog outputs.
When tied permanently low, the addressed DAC register is updated on the rising edge of SYNC. If
LDAC is held high during the write cycle, the DAC input register is updated but the output update is
held off until the falling edge of LDAC. In this mode, all analog outputs can be updated
simultaneously on the falling edge of LDAC. The LDAC pin must not be left unconnected.
D0 and D1 form a digital I/O port. The user can set up these pins as inputs or outputs that are
configurable and readable over the serial interface. When configured as inputs, these pins have weak
internal pull-ups to DVCC. When programmed as outputs, D0 and D1 are referenced by DVCC and DGND.
Reset Logic Output. This is the output from the on-chip voltage monitor used in the reset circuit. If
desired, it can be used to control other system components.
Reset Logic Input. This input allows external access to the internal reset logic. Applying a Logic 0 to
this input clamps the DAC outputs to 0 V. In normal operation, RSTIN should be tied to Logic 1.
Register values remain unchanged.
Digital Ground Pin.
Digital Supply Pin. Voltage ranges from 2.7 V to 5.25 V.
Positive Analog Supply Pins. Voltage ranges from 4.75 V to 5.25 V.
Ground Reference Point for Analog Circuitry.
Negative Analog Supply Pins. Voltage ranges from –4.75 V to –5.25 V.
This pin is used in association with an optional external resistor to AGND to program the short-circuit
current of the output amplifiers. Refer to the AD5763 Features section on page 25 for further details.
No Internal Connection
No Internal Connection
Analog Output Voltage of DAC B. Buffered output with a nominal full-scale output range of ±4.096 V. The
output amplifier is capable of directly driving a 5 kΩ, 200 pF load.
Ground Reference Pin for DAC B Output Amplifier.
Ground Reference Pin for DAC A Output Amplifier.
Rev. PrA | Page 11 of 31
AD5763
Preliminary Technical Data
Pin No.
22
Mnemonic
VOUTA
23
NC
24
25
NC
REFA
26
REFB
27
28
29
NC
REFGND
TEMP
32
BIN/2sCOMP
1
Description
Analog Output Voltage of DAC A. Buffered output with a nominal full-scale output range of ±4.096 V. The
output amplifier is capable of directly driving a 5 kΩ, 200 pF load.
Analog Output Voltage of DAC A. Buffered output with a nominal full-scale output range of ±4.096 V. The
output amplifier is capable of directly driving a 5 kΩ, 200 pF load.
No internal connection
Reference Voltage input. Reference input range is 1V to 2.1V; programs the full-scale output voltage.
REFA = 2.048V for specified performance.
Reference Voltage input. Reference input range is 1V to 2.1V; programs the full-scale output voltage.
REFB = 2.048V for specified performance.
No Connect.
Reference Ground Return for the Reference Generator and Buffers.
This pin provides an output voltage proportional to temperature. The output voltage is 1.4V typical at
25°C die temperature; variation with temperature is 5mV/°C.
Determines the DAC Coding. This pin should be hardwired to either DVCC or DGND. When hardwired to
DVCC, input coding is offset binary. When hardwired to DGND, input coding is twos complement
(see Table 7).
Internal pull-up device on this logic input. Therefore, it can be left floating and defaults to a logic high condition.
Rev. PrA | Page 12 of 31
Preliminary Technical Data
AD5763
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 7. Integral Nonlinearity Error vs. Code
Figure 10. Differential Nonlinearity Error vs. Temperature
Figure 8. Differential Nonlinearity Error vs. Code
Figure 11. Integral Nonlinearity Error vs. Supply voltage
Figure 9. Integral Nonlinearity Error vs. Temperature
Figure 12. Differential Nonlinearity Error vs. Supply Voltage
Rev. PrA | Page 13 of 31
AD5763
Preliminary Technical Data
Figure 13.Integral Nonlinearity Error vs. Reference voltage
Figure 16. IDD/ISS vs. VDD/VSS
Figure 14. Differential Nonlinearity Error vs Reference Voltage
Figure 17. Zero-Scale Error vs. Temperature
Figure 15. Total Unadjusted Error vs. Reference Voltage
Figure 18. Bipolar Zero Error vs. Temperature
Rev. PrA | Page 14 of 31
Preliminary Technical Data
AD5763
Figure 19. Gain Error vs. Temperature
Figure 22. Source and Sink Capability of Output Amplifier with Negative
Full-Scale Loaded
Figure 20.DICC vs. Logic Input Voltage
Figure 23. Positive Full-Scale Step
Figure 21. Source and Sink Capability of Output Amplifier with Positive FullScale Loaded
Rev. PrA | Page 15 of 31
Figure 24. Negative Full-Scale Step
AD5763
Preliminary Technical Data
Figure 25. Settling Time vs. Load Capacitance
Figure 28. VOUT vs. AVDD/AVSS on Power-up
Figure 26. Major Code Transition Glitch Energy
Figure 29. Short-Circuit Current vs. RISCC
Figure 27. Peak-to-Peak Noise (100 kHz Bandwidth)
Figure 30. TEMP Output Voltage vs. Temperature
Rev. PrA | Page 16 of 31
Preliminary Technical Data
AD5763
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot can be seen in Figure 7.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic. A
typical DNL vs. code plot can be seen in Figure 8.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant for increasing digital input code. The AD5763 is
monotonic over its full operating temperature range.
Bipolar Zero Error
Bipolar zero error is the deviation of the analog output from the
ideal half-scale output of 0 V when the DAC register is loaded
with 0x8000 (offset binary coding) or 0x0000 (twos complement
coding). A plot of bipolar zero error vs. temperature can be seen
in Figure 18.
Bipolar Zero Temperature Coefficient
Bipolar zero TC is the measure of the change in the bipolar zero
error with a change in temperature. It is expressed in ppm FSR/°C.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code is loaded to the DAC register. Ideally the output voltage
should be 2 × VREF − 1 LSB. Full-scale error is expressed in
percentage of full-scale range.
Negative Full-Scale Error/Zero Scale Error
Negative full-scale error is the error in the DAC output voltage
when 0x0000 (offset binary coding) or 0x8000 (twos
complement coding) is loaded to the DAC register. Ideally, the
output voltage should be −2 × VREF. A plot of zero-scale error vs.
temperature can be seen in Figure 17.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for the
output to settle to a specified level for a full-scale input change.
Slew Rate
The slew rate of a device is a limitation in the rate of change of
the output voltage. The output slewing speed of a voltageoutput D/A converter is usually limited by the slew rate of the
amplifier used at its output. Slew rate is measured from 10% to
90% of the output signal and is given in V/µs.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percentage of the full-scale range. A plot of
gain error vs. temperature can be seen in Figure 19.
Total Unadjusted Error
Total unadjusted error (TUE) is a measure of the output error
considering all the various errors. A plot of total unadjusted
error vs. reference can be seen in Figure 15.
Zero-Scale Error TC
Zero-scale error TC is a measure of the change in zero-scale
error with a change in temperature. Zero-scale error TC is
expressed in ppm FSR/°C.
Gain Error TC
Gain error TC is a measure of the change in gain error with
changes in temperature. Gain Error TC is expressed in
(ppm of FSR)/°C.
Digital-to-Analog Glitch Energy
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-secs
and is measured when the digital input code is changed by 1 LSB at
the major carry transition (0x7FFF to 0x8000) (see Figure 26).
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC but is measured when the DAC output is not updated. It is
specified in nV-secs and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s, and vice versa.
Power Supply Sensitivity
Power supply sensitivity indicates how the output of the DAC is
affected by changes in the power supply voltage.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is
measured with a full-scale output change on one DAC while
monitoring another DAC, and is expressed in LSBs.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
output change of another DAC. This includes both digital and
analog crosstalk. It is measured by loading one of the DACs
with a full-scale code change (all 0s to all 1s and vice versa) with
LDAC low and monitoring the output of another DAC. The
energy of the glitch is expressed in nV-sec.
Channel-to-Channel Isolation
Channel-to-channel isolation is the ratio of the amplitude of the
signal at the output of one DAC to a sine wave on the reference
input of another DAC. It is measured in dB.
Digital Crosstalk
Digital crosstalk is a measure of the impulse injected into the
analog output of one DAC from the digital inputs of another
DAC but is measured when the DAC output is not updated. It is
specified in nV-secs and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s, and vice versa.
Rev. PrA | Page 17 of 31
AD5763
Preliminary Technical Data
THEORY OF OPERATION
The AD5763 is a Dual, 16-bit, serial input, bipolar voltage output
DAC and operates from supply voltages of ±4.75 V to ±5.25 V and
has a buffered output voltage of up to ±4.311 V. Data is written to
the AD5763 in a 24-bit word format, via a 3-wire serial interface.
The device also offers an SDO pin, which is available for daisychaining or readback.
SERIAL INTERFACE
The AD5763 incorporates a power-on reset circuit, which
ensures that the DAC registers power up loaded with 0x0000.
The AD5763 features a digital I/O port that can be programmed
via the serial interface, on-chip reference buffers and per
channel digital gain, and offset registers.
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK. The input register consists of a read/write
bit, three register select bits, three DAC address bits and 16 data
bits as shown in Table 8. The timing diagram for this operation
is shown in Figure 2.
The AD5763 is controlled over a versatile 3-wire serial interface
that operates at clock rates of up to 30 MHz and is compatible
with SPI®, QSPI™, MICROWIRE™, and DSP standards.
Input Shift Register
DAC ARCHITECTURE
The DAC architecture of the AD5763 consists of a 16-bit
current mode segmented R-2R DAC. The simplified circuit
diagram for the DAC section is shown in Figure 31.
The four MSBs of the 16-bit data word are decoded to drive 15
switches, E1 to E15. Each of these switches connects one of the
15 matched resistors to either AGNDX or IOUT. The remaining
12 bits of the data-word drive switches S0 to S11 of the 12-bit
R-2R ladder network.
R
VREF
2R
2R
2R
R
2R
R
2R
2R
Upon power-up, the DAC registers are loaded with zero code
(0x0000) and the outputs are clamped to 0 V via a low impedance
path. The outputs can be updated with the zero code value at this
time by asserting either LDAC or CLR. The corresponding output
voltage depends on the state of the BIN/2sCOMP pin. If the
BIN/2sCOMP pin is tied to DGND, then the data coding is twos
complement and the outputs update to 0 V. If the BIN/2sCOMP
pin is tied to DVCC, then the data coding is offset binary and the
outputs update to negative full-scale. To have the outputs power-up
with zero code loaded to the outputs, the CLR pin should be held
low during power-up.
2R
Standalone Operation
E15
R/8
E14
E1
S11
S10
S0
IOUT
4 MSBs DECODED INTO
15 EQUAL SEGMENTS
VOUTX
05303-060
AGNDX
12-BIT, R-2R LADDER
Figure 31. DAC Ladder Structure
REFERENCE BUFFERS
The AD5763 operates with an external reference. The reference
inputs (REFA and REFB) have an input range up to 2.1 V. This
input voltage is then used to provide a buffered positive and
negative reference for the DAC cores. The positive reference is
given by
+VREF = 2VREF
The negative reference to the DAC cores is given by
−VREF = −2VREF
These positive and negative reference voltages (along with the
gain register values) define the output ranges of the DACs.
The serial interface works with both a continuous and noncontinuous serial clock. A continuous SCLK source can only be
used if SYNC is held low for the correct number of clock cycles.
In gated clock mode, a burst clock containing the exact number
of clock cycles must be used and SYNC must be taken high after
the final clock to latch the data. The first falling edge of SYNC
starts the write cycle. Exactly 24 falling clock edges must be
applied to SCLK before SYNC is brought back high again. If
SYNC is brought high before the 24th falling SCLK edge, then
the data written is invalid. If more than 24 falling SCLK edges
are applied before SYNC is brought high, then the input data is
also invalid. The input register addressed is updated on the
rising edge of SYNC. In order for another serial transfer to take
place, SYNC must be brought low again. After the end of the
serial data transfer, data is automatically transferred from the
input shift register to the addressed register.
When the data has been transferred into the chosen register of
the addressed DAC, all DAC registers and outputs can be
updated by taking LDAC low.
Rev. PrA | Page 18 of 31
Preliminary Technical Data
Readback Operation
AD57631
MOSI
SDIN
SCK
SCLK
PC7
SYNC
PC6
LDAC
MISO
Before a readback operation is initiated, the SDO pin must be
enabled by writing to the function register and clearing the
SDO DISABLE bit; this bit is cleared by default. Readback mode
is invoked by setting the R/W bit = 1 in the serial input register
write. With R/W = 1, Bit A2 to Bit A0, in association with Bit
REG2, Bit REG1, and Bit REG0, select the register to be read.
The remaining data bits in the write sequence are don’t care.
During the next SPI write, the data appearing on the SDO
output contain the data from the previously addressed register.
For a read of a single register, the NOP command can be used
in clocking out the data from the selected register on SDO. The
readback diagram in Figure 4 shows the readback sequence. For
example, to read back the fine gain register of Channel A on the
AD5763, the following sequence should be implemented:
SDO
SDIN
AD57631
SCLK
SYNC
LDAC
SDO
1. Write 0xA0XXXX to the AD5763 input register. This
configures the AD5763 for read mode with the fine gain
register of Channel A selected. Note that all the data bits,
DB15 to DB0, are don’t cares.
2. Follow this with a second write, an NOP condition,
0x00XXXX. During this write, the data from the fine gain
register is clocked out on the SDO line, that is, data clocked
out contain the data from the fine gain register in Bit DB5 to
Bit DB0.
SDIN
AD57631
SCLK
SYNC
LDAC
1ADDITIONAL PINS OMITTED FOR CLARITY
05303-061
SDO
SIMULTANEOUS UPDATING VIA LDAC
Figure 32. Daisy-Chaining the AD5763
Daisy-Chain Operation
For systems that contain several devices, the SDO pin can be
used to daisy-chain several devices together. This daisy-chain
mode can be useful in system diagnostics and in reducing the
number of serial interface lines. The first falling edge of SYNC
starts the write cycle. The SCLK is continuously applied to the
input shift register when SYNC is low. If more than 24 clock
pulses are applied, the data ripples out of the shift register and
appears on the SDO line. This data is clocked out on the rising
edge of SCLK and is valid on the falling edge. By connecting the
SDO of the first device to the SDIN input of the next device in
the chain, a multidevice interface is constructed. Each device in
the system requires 24 clock pulses. Therefore, the total number
of clock cycles must equal 24N, where N is the total number of
AD5763 devices in the chain. When the serial transfer to all
devices is complete, SYNC is taken high. This latches the input
data in each device in the daisy chain and prevents any further
data from being clocked into the input shift register. The serial
clock can be a continuous or a gated clock.
Depending on the status of both SYNC and LDAC, and after
data has been transferred into the input register of the DACs,
there are two ways in which the DAC registers and DAC
outputs can be updated.
Individual DAC Updating
In this mode, LDAC is held low while data is being clocked into
the input shift register. The addressed DAC output is updated
on the rising edge of SYNC.
Simultaneous Updating of All DACs
In this mode, LDAC is held high while data is being clocked
into the input shift register. All DAC outputs are updated by
taking LDAC low any time after SYNC has been taken high.
The update now occurs on the falling edge of LDAC.
A continuous SCLK source can only be used if SYNC is held
low for the correct number of clock cycles. In gated clock mode,
a burst clock containing the exact number of clock cycles must
be used and SYNC must be taken high after the final clock to
latch the data.
OUTPUT
I/V AMPLIFIER
VREFIN
LDAC
16-BIT
DAC
VOUT
DAC
REGISTER
INPUT
REGISTER
SCLK
SYNC
SDIN
INTERFACE
LOGIC
SDO
05303-062
68HC11 1
AD5763
Figure 33. Simplified Serial Interface of Input Loading Circuitry
for One DAC Channel
Rev. PrA | Page 19 of 31
AD5763
Preliminary Technical Data
TRANSFER FUNCTION
The output voltage expression for the AD5763 is given by
Table 7 shows the ideal input code to output voltage
relationship for the AD5763 for both offset binary and twos
complement data coding.
⎡ D ⎤
VOUT = −2 × VREFIN + 4 × VREFIN ⎢
⎣ 65536 ⎥⎦
Table 7. Ideal Output Voltage to Input Code Relationship
where:
D is the decimal equivalent of the code loaded to the DAC.
VREFIN is the reference voltage applied at the REFA, REFB pins.
Digital Input
Analog Output
Offset Binary Data Coding
MSB
1111
1000
1000
0111
0000
1111
0000
0000
1111
0000
1111
0000
0000
1111
0000
LSB
1111
0001
0000
1111
0000
VOUTX
+2VREF × (32767/32768)
+2VREF × (1/32768)
0V
−2VREF × (1/32768)
−2VREF × (32767/32768)
ASYNCHRONOUS CLEAR (CLR)
CLR is a negative edge triggered clear that allows the outputs to
be cleared to either 0 V (twos complement coding) or negative
full scale (offset binary coding). It is necessary to maintain CLR
low for a minimum amount of time (see Figure 2) for the
operation to complete. When the CLR signal is returned high,
the output remains at the cleared value until a new value is
programmed. If at power-on, CLR is at 0 V, then all DAC
outputs are updated with the clear value. A clear can also be
initiated through software by writing the command 0x04XXXX
to the AD5763.
Twos Complement Data Coding
MSB
0111
0000
0000
1111
1000
1111
0000
0000
1111
0000
1111
0000
0000
1111
0000
LSB
1111
0001
0000
1111
0000
VOUTX
+2VREF × (32767/32768)
+2VREF × (1/32768)
0V
−2VREF × (1/32768)
−2VREF × (32767/32768)
Table 8. AD5763 Input Register Format
MSB
LSB
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
R/W
0
REG2
REG1
REG0
A2
A1
A0
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DATA
Table 9. Input Register Bit Functions
Bit
R/W
Description
Indicates a read from or a write to the addressed register.
REG2, REG1, REG0
Used in association with the address bits to determine if a read or write operation is to the data register, offset
register, gain register, or function register.
REG2
REG1
REG0
Function
0
0
0
Function Register
0
1
0
Data Register
0
1
1
Coarse Gain Register
1
0
0
Fine Gain Register
1
0
1
Offset Register
These bits are used to decode the DAC channels.
A2
A1
A0
Channel Address
0
0
0
DAC A
0
0
1
DAC B
1
0
0
BOTH DACs
Data Bits.
A2, A1, A0
D15:D0
Rev. PrA | Page 20 of 31
DB0
Preliminary Technical Data
AD5763
FUNCTION REGISTER
The function register is addressed by setting the three REG bits to 000. The values written to the address bits and the data bits determine
the function addressed. The functions available via the function register are outlined in Table 10 and Table 11.
Table 10. Function Register Options
REG2
0
0
REG1
0
0
REG0
0
0
A2
0
0
A1
0
0
A0
0
1
0
0
0
0
0
0
1
1
0
0
0
1
DB15:DB6
DB5
Don’t Care
LocalGroundOffset Adjust
DB4
DB3
DB2
NOP, Data = Don’t Care
D1
D1
D0
Direction
Value
Direction
DB1
DB0
D0
Value
SDO
Disable
CLR, Data = Don’t Care
LOAD, Data = Don’t Care
Table 11. Explanation of Function Register Options
Option
NOP
Local-GroundOffset Adjust
D0/D1 Direction
Description
No operation instruction used in readback operations.
Set by the user to enable local-ground-offset adjust function. Cleared by the user to disable local-ground-offset adjust
function (default). Refer to Features section for further details.
Set by the user to enable D0/D1 as outputs. Cleared by the user to enable D0/D1 as inputs (default). Refer to the
Features section for further details.
I/O Port Status Bits. Logic values written to these locations determine the logic outputs on the D0 and D1 pins when
configured as outputs. These bits indicate the status of the D0 and D1 pins when the I/O port is active as an input.
When enabled as inputs, these bits are don’t cares during a write operation.
Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default).
Addressing this function resets the DAC outputs to 0 V in twos complement mode and negative full scale in binary mode.
Addressing this function updates the DAC registers and consequently the analog outputs.
D0/D1 Value
SDO Disable
CLR
LOAD
DATA REGISTER
The data register is addressed by setting the three REG bits to 010. The DAC address bits select with which DAC channel the data transfer
is to take place (see Table 9). The data bits are in positions DB15 to DB0 as shown in Table 12.
Table 12. Programming the AD5763 Data Register
REG2
REG1
REG0
0
1
0
A2
A1
A0
DB15
DB14
DB13
DB12
DB11
DB10
DAC Address
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
16-Bit DAC Data
COARSE GAIN REGISTER
The coarse gain register is addressed by setting the three REG bits to 011. The DAC address bits select with which DAC channel the data
transfer is to take place (see Table 9). The coarse gain register is a 2-bit register and allows the user to select the output range of each DAC
as shown in Table 13 and Table 14.
Table 13. Programming the AD5763 Coarse Gain Register
REG2
0
REG1
1
REG0
1
A2
A1
A0
DAC Address
Table 14. Output Range Selection
Output Range
±4.096 V (default)
±4.201 V
±4.331 V
CG1
0
0
1
CG0
0
1
0
Rev. PrA | Page 21 of 31
DB15 …. DB2
Don’t Care
DB1
CG1
DB0
CG0
AD5763
Preliminary Technical Data
FINE GAIN REGISTER
The fine gain register is addressed by setting the three REG bits to 100. The DAC address bits select with which DAC channel the data
transfer is to take place (see Table 9). The fine gain register is a 6-bit register and allows the user to adjust the gain of each DAC channel
by −32 LSBs to +31 LSBs in 1 LSB increments as shown in Table 15 and Table 16. The adjustment is made to both the positive full-scale
and negative full-scale points simultaneously, each point being adjusted by ½ of one step. The fine gain register coding is twos
complement.
Table 15. Programming AD5763 Fine Gain Register
REG2
1
REG1
0
REG0
0
A2
A1
A0
DAC Address
DB15:DB6
Don’t Care
DB5
FG5
DB4
FG4
DB3
FG3
DB2
FG2
DB1
FG1
DB0
FG0
Table 16. AD5763 Fine Gain Register Options
Gain Adjustment
+31 LSBs
+30 LSBs
No Adjustment (default)
−31 LSBs
−32 LSBs
FG5
0
0
0
1
1
FG4
1
1
0
0
0
FG3
1
1
0
0
0
FG2
1
1
0
0
0
FG1
1
1
0
0
0
FG0
1
0
0
1
0
OFFSET REGISTER
The offset register is addressed by setting the three REG bits to 101. The DAC address bits select with which DAC channel the data
transfer is to take place (see Table 9). The AD5763 offset register is an 8-bit register and allows the user to adjust the offset of each channel
by −16 LSBs to +15.875 LSBs in increments of ⅛ LSB as shown in Table 17 and Table 18. The offset register coding is twos complement.
Table 17. Programming the AD5763 Offset Register
REG2
1
REG1
0
REG0
1
A2
A1
A0
DAC Address
DB15:DB8
Don’t Care
DB7
OF7
DB6
OF6
DB5
OF5
DB4
OF4
DB3
OF3
DB2
OF2
DB1
OF1
Table 18. AD5763 Offset Register options
Offset Adjustment
+15.875 LSBs
+15.75 LSBs
No Adjustment (default)
−15.875 LSBs
−16 LSBs
OF7
0
0
0
1
1
OF6
1
1
0
0
0
OF5
1
1
0
0
0
Rev. PrA | Page 22 of 31
OF4
1
1
0
0
0
OF3
1
1
0
0
0
OF2
1
1
0
0
0
OF1
1
1
0
0
0
OF0
1
0
0
1
0
DB0
OF0
Preliminary Technical Data
AD5763
OFFSET AND GAIN ADJUSTMENT WORKED
EXAMPLE
Convert this to a negative twos complement number by
inverting all bits and adding 1: 11011000.
Using the information provided in the previous section, the
following worked example demonstrates how the AD5763
functions can be used to eliminate both offset and gain errors.
As the AD5763 is factory calibrated, offset and gain errors
should be negligible. However, errors can be introduced by the
system that the AD5763 is operating within, for example, a
voltage reference value that is not equal to 2.048 V introduces a
gain error. An output range of ±4.096 V and twos complement
data coding is assumed.
11011000 is the value that should be programmed to the offset
register.
Removing Offset Error
The AD5763 can eliminate an offset error in the range of −2 mV to
+1.98 mV with a step size of ⅛ of a 16-bit LSB.
Note that this twos complement conversion is not necessary in
the case of a positive offset adjustment. The value to be
programmed to the offset register is simply the binary
representation of the adjustment value.
Removing Gain Error
The AD5763 can eliminate a gain error at negative full-scale
output in the range of −2 mV to +1.94 mV with a step size of ½
of a 16-bit LSB.
Calculate the step size of the gain adjustment.
Gain Adjust Step Size =
Calculate the step size of the offset adjustment.
Offset Adjust Step Size =
8.192
= 15.625 µV
216 × 8
Measure the offset error by programming 0x0000 to the data
register and measuring the resulting output voltage, for this
example the measured value is 614 µV.
Measure the gain error by programming 0x8000 to the data
register and measuring the resulting output voltage. The gain
error is the difference between this value and −4.096 V; for this
example, the gain error is −0.8 mV.
Calculate how many gain adjustment steps this value represents.
Calculate the number of offset adjustment steps that this value
represents.
Number of Steps =
Measured Offset Value
614 µV
=
= 40 Steps
Offset Step Size
15.625 µV
The offset error measured is positive, therefore, a negative
adjustment of 40 steps is required. The offset register is 8 bits
wide and the coding is twos complement. The required offset
register value can be calculated as follows:
8.192
= 62.5 µV
216 × 2
Number of Steps =
Measured Gain Value 0.8 mV
=
= 13 Steps
Gain Step Size
62.5 µV
The gain error measured is negative (in terms of magnitude);
therefore, a positive adjustment of 13 steps is required. The gain
register is 6 bits wide and the coding is twos complement, the
required gain register value can be determined as follows:
Convert adjustment value to binary: 001101.
The value to be programmed to the gain register is simply this
binary number.
Convert adjustment value to binary: 00101000.
Rev. PrA | Page 23 of 31
AD5763
AD5763 FEATURES
ANALOG OUTPUT CONTROL
In many industrial process control applications, it is vital that
the output voltage be controlled during power-up and during
brownout conditions. When the supply voltages are changing,
the output pins are clamped to 0 V via a low impedance path.
To prevent the output amp being shorted to 0 V during this
time, transmission gate G1 is also opened (see Figure 34). These
conditions are maintained until the power supplies stabilize and
a valid word is written to the DAC register. At this time, G2
opens and G1 closes. Both transmission gates are also externally
controllable via the reset logic (RSTIN) control input. For
instance, if RSTIN is driven from a battery supervisor chip, the
RSTIN input is driven low to open G1 and close G2 on powerdown or during a brownout. Conversely, the on-chip voltage
detector output (RSTOUT) is also available to the user to
control other parts of the system. The basic transmission gate
functionality is shown in Figure 34.
RSTOUT
DIGITAL I/O PORT
The AD5763 contains a 2-bit digital I/O port (D1 and D0).
These bits can be configured as inputs or outputs independently,
and can be driven or have their values read back via the serial
interface. The I/O port signals are referenced to DVCC and
DGND. When configured as outputs, they can be used as
control signals to multiplexers or can be used to control
calibration circuitry elsewhere in the system. When configured
as inputs, the logic signals from limit switches, for example, can
be applied to D0 and D1 and can be read back via the digital
interface.
DIE TEMPERATURE SENSOR
RSTIN
The on-chip die temperature sensor provides a voltage output
that is linearly proportional to the centigrade temperature scale.
Its nominal output voltage is 1.4 V at +25°C die temperature,
varying at 5 mV/°C, giving a typical output range of 1.175 V to
1.9 V over the full temperature range. Its low output impedance,
and linear output simplify interfacing to temperature control
circuitry and A/D converters. The temperature sensor is
provided as more of a convenience rather than a precise feature;
it is intended for indicating a die temperature change for
recalibration purposes.
VOLTAGE
MONITOR
AND
CONTROL
G1
VOUTA
AGNDA
05303-063
G2
Figure 34. Analog Output Control Circuitry
DIGITAL OFFSET AND GAIN CONTROL
LOCAL GROUND OFFSET ADJUST
The AD5763 incorporates a digital offset adjust function with a
±16 LSB adjust range and 0.125 LSB resolution. The gain
register allows the user to adjust the AD5763 full-scale output
range. The full-scale output can be programmed to achieve fullscale ranges of ±4.096 V, ±4.201 V, and ±4.311 V. A fine gain
trim is also provided.
PROGRAMMABLE SHORT-CIRCUIT PROTECTION
The short-circuit current of the output amplifiers can be programmed by inserting an external resistor between the ISCC
pin and PGND. The programmable range for the current is
500 µA to 10 mA, corresponding to a resistor range of 120 kΩ
to 6 kΩ. The resistor value is calculated as follows:
R≈
If the ISCC pin is left unconnected, the short-circuit current
limit defaults to 5 mA. It should be noted that limiting the short
circuit current to a small value can affect the slew rate of the
output when driving into a capacitive load, therefore, the value
of short-circuit current programmed should take into account
the size of the capacitive load being driven.
The AD5763 incorporates a local-ground-offset adjust feature
which, when enabled in the function register, adjusts the DAC
outputs for voltage differences between the individual DAC
ground pins and the REFGND pin ensuring that the DAC
output voltages are always with respect to the local DAC ground
pin. For instance, if pin AGNDA is at +5 mV with respect to the
REFGND pin and VOUTA is measured with respect to
AGNDA, then a −5 mV error results, enabling the localground-offset adjust feature adjusts VOUTA by +5 mV,
eliminating the error.
60
I SC
Rev. PrA | Page 24 of 31
Preliminary Technical Data
AD5763
APPLICATIONS INFORMATION
TYPICAL OPERATING CIRCUIT
Precision Voltage Reference Selection
Figure 35 shows the typical operating circuit for the AD5763.
The only external components needed for this precision 16-bit
DAC are a reference voltage source, decoupling capacitors on
the supply pins and reference inputs, and an optional shortcircuit current setting resistor. Because the device incorporates
reference buffers, it eliminates the need for an external bipolar
reference and associated buffers. This leads to an overall savings
in both cost and board space.
To achieve the optimum performance from the AD5763 over its
full operating temperature range, a precision voltage reference
must be used. Thought should be given to the selection of a
precision voltage reference. The AD5763 has two reference
inputs, REFA and REFB. The voltages applied to the reference
inputs are used to provide a buffered positive and negative
reference for the DAC cores. Therefore, any error in the voltage
reference is reflected in the outputs of the device.
In Figure 35, AVDD is connected to +5 V and AVSS is connected
to −5 V. In Figure 35, AGNDA is connected to REFGND.
There are four possible sources of error to consider when
choosing a voltage reference for high accuracy applications:
initial accuracy, temperature coefficient of the output voltage,
long term drift, and output voltage noise.
+5V
10µF
ADR420
100nF
2
VOUT 6
GND
VIN
Initial accuracy error on the output voltage of an external reference could lead to a full-scale error in the DAC. Therefore, to
minimize these errors, a reference with low initial accuracy
error specification is preferred. Choosing a reference with an
output trim adjustment, such as the ADR430, allows a system
designer to trim system errors out by setting the reference
voltage to a voltage other than the nominal. The trim adjustment can also be used at temperature to trim out any error.
4
+5V –5V
10µF
10µF
100nF
100nF
100nF
BIN/2sCOMP
1
SYNC
SCLK
2
SCLK
SDIN
3
SDIN
SDO
4
SDO
REFA
NC
REFB
AVSS
TEMP
AVDD
REFGND
SYNC
BIN/2sCOMP
32 31 30 29 28 27 26 25
+5V
NC 24
NC 23
VOUTA 22
AGNDB 20
LDAC
VOUTB 19
D0
7
D0
NC 18
D1
8
D1
NC 17
10µF
ISCC
AVSS
PGND
VOUTB
100nF
NC = NO CONNECT
10µF
+5V
+5V
The temperature coefficient of a reference output voltage affects
INL, DNL, and TUE. A reference with a tight temperature
coefficient specification should be chosen to reduce the
dependence of the DAC output voltage on ambient conditions.
In high accuracy applications, which have a relatively low noise
budget, reference output voltage noise needs to be considered.
Choosing a reference with as low an output noise voltage as
practical for the system resolution required is important.
Precision voltage references such as the ADR420 (XFET® design)
produce low output noise in the 0.1 Hz to 10 Hz region.
However, as the circuit bandwidth increases, filtering the output
of the reference may be required to minimize the output noise.
10µF
100nF
100nF
RSTIN
AVDD
10 11 12 13 14 15 16
DVCC
9
DGND
RSTIN
CLR
6
RSTOUT
5
LDAC
RSTOUT
VOUTA
AGNDA 21
AD5763
Long-term drift is a measure of how much the reference output
voltage drifts over time. A reference with a tight long-term drift
specification ensures that the overall solution remains relatively
stable over its entire lifetime.
–5V
Figure 35. Typical Operating Circuit
Table 19. Some Precision References Recommended for Use with the AD5763
Part No.
ADR430
ADR420
ADR390
Initial Accuracy (mV Max)
±1
±1
±4
Long-Term Drift (ppm Typ)
40
50
50
Temp Drift (ppm/°C Max)
3
3
9
Rev. PrA | Page 25 of 31
0.1 Hz to 10 Hz Noise (µV p-p Typ)
3.5
1.75
5
AD5763
Preliminary Technical Data
LAYOUT GUIDELINES
The power supply lines of the AD5763 should use as large a
trace as possible to provide low impedance paths and reduce
the effects of glitches on the power supply line. Fast switching
signals, such as clocks, should be shielded with digital ground
to avoid radiating noise to other parts of the board, and should
never be run near the reference inputs. A ground line routed
between the SDIN and SCLK lines helps reduce crosstalk
between them (not required on a multilayer board, which has a
separate ground plane, however, it is helpful to separate the
lines). It is essential to minimize noise on the reference inputs,
because it couples through to the DAC output. Avoid crossover
of digital and analog signals. Traces on opposite sides of the
board should run at right angles to each other. This reduces the
effects of feedthrough on the board. A microstrip technique is
recommended, but not always possible with a double-sided
board. In this technique, the component side of the board is
dedicated to ground plane, and signal traces are placed on the
solder side.
GALVANICALLY ISOLATED INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that might occur.
Isocouplers provide voltage isolation in excess of 2.5 kV. The
serial loading structure of the AD5763 makes it ideal for
isolated interfaces because the number of interface lines is kept
to a minimum. Figure 36 shows a 4-channel isolated interface
to the AD5763 using an ADuM1400. For more information, go
to www.analog.com.
µCONTROLLER
SERIAL CLOCK OUT
SERIAL DATA OUT
SYNC OUT
CONTROL OUT
ADuM14001
VIA
VIB
VIC
VID
ENCODE
DECODE
ENCODE
DECODE
ENCODE
DECODE
ENCODE
DECODE
VOA
VOB
VOC
VOD
TO SCLK
TO SDIN
TO SYNC
TO LDAC
05303-065
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure the
rated performance. The printed circuit board on which the
AD5763 is mounted should be designed so that the analog and
digital sections are separated and confined to certain areas of the
board. If the AD5763 is in a system where multiple devices
require an AGND-to-DGND connection, the connection should
be made at one point only. The star ground point should be
established as close as possible to the device. The AD5763 should
have ample supply bypassing of 10 µF in parallel with 0.1 µF on
each supply located as close to the package as possible, ideally
right up against the device. The 10 µF capacitors are the tantalum
bead type. The 0.1 µF capacitor should have low effective series
resistance (ESR) and low effective series inductance (ESI) such as
the common ceramic types, which provide a low impedance path
to ground at high frequencies to handle transient currents due to
internal logic switching.
1ADDITIONAL PINS OMITTED FOR CLARITY
Figure 36. Isolated Interface
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5763 is via a serial bus
that uses a standard protocol that is compatible with microcontrollers and DSP processors. The communications channel
is a 3-wire (minimum) interface consisting of a clock signal, a
data signal, and a synchronization signal. The AD5763 requires
a 24-bit data-word with data valid on the falling edge of SCLK.
For all the interfaces, the DAC output update can be done
automatically when all the data is clocked in, or it can be done
under the control of LDAC. The contents of the DAC register
can be read using the readback function.
AD5763 to MC68HC11 Interface
Figure 37 shows an example of a serial interface between the
AD5763 and the MC68HC11 microcontroller. The serial
peripheral interface (SPI) on the MC68HC11 is configured for
master mode (MSTR = 1), clock polarity bit (CPOL = 0), and the
clock phase bit (CPHA = 1). The SPI is configured by writing to the
SPI control register (SPCR) (see the MC68HC11 User Manual).
SCK of the MC68HC11 drives the SCLK of theAD5763, the MOSI
output drives the serial data line (DIN) of the AD5744/AD5763,
and the MISO input is driven from SDO. The SYNC is driven from
one of the port lines, in this case, PC7.
When data is being transmitted to the AD5763, the SYNC line
(PC7) is taken low and data is transmitted MSB first. Data
appearing on the MOSI output is valid on the falling edge of
SCK. Eight falling clock edges occur in the transmit cycle, so, in
order to load the required 24-bit word, PC7 is not brought high
until the third 8-bit word has been transferred to the DAC
input shift register.
AD57631
MC68HC111
MISO
SDO
MOSI
SDIN
SCK
SCLK
PC7
SYNC
1ADDITIONAL PINS OMITTED FOR CLARITY
Figure 37. AD5763 to MC68HC11 Interface
Rev. PrA | Page 26 of 31
Preliminary Technical Data
AD5763
LDAC is controlled by the PC6 port output. The DAC can be
updated after each 3-byte transfer by bringing LDAC low. This
example does not show other serial lines for the DAC. For
example, if CLR were used, it could be controlled by port
output PC5.
SPISELx
SYNC
SCK
MOSI
SCLK
SDIN
AD5763
ADSP-BF531
AD5763 to 8XC51 Interface
The AD5763 requires a clock synchronized to the serial data.
For this reason, the 8XC51 must be operated in Mode 0. In this
mode, serial data enters and exits through RxD, and a shift
clock is output on TxD.
P3.3 and P3.4 are bit programmable pins on the serial port and
are used to drive SYNC and LDAC, respectively. The 8CX51
provides the LSB of its SBUF register as the first bit in the data
stream. The user must ensure that the data in the SBUF register
is arranged correctly, because the DAC expects the MSB first.
When data is to be transmitted to the DAC, P3.3 is taken low.
Data on RxD is clocked out of the microcontroller on the rising
edge of TxD and is valid on the falling edge. As a result, no glue
logic is required between this DAC and the microcontroller
interface.
8XC511
AD57631
PF10
LDAC
Figure 39. AD5763 to Blackfin Interface
AD5763 to PIC16C6x/7x Interface
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit set to 0. This is done
by writing to the synchronous serial port control register
(SSPCON). See the PIC16/17 Microcontroller User Manual. In
this example, I/O port RA1 is being used to pulse SYNC and
enable the serial port of the AD5763. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, three consecutive write operations are
needed. Figure 40 shows the connection diagram.
AD57631
PIC16C6x/7x1
RxD
SDIN
TxD
SCLK
SDI/RC4
SDO
P3.3
SYNC
SDO/RC5
SDIN
P3.4
LDAC
SCLK/RC3
SCLK
RA1
SYNC
1ADDITIONAL PINS OMITTED FOR CLARITY
Figure 38. AD5763 to 8XC51 Interface
1ADDITIONAL
The 8XC51 transmits data in 8-bit bytes with only eight falling
clock edges occurring in the transmit cycle. Because the DAC
expects a 24-bit word, SYNC (P3.3) must be left low after the
first eight bits are transferred. After the third byte has been
transferred, the P3.3 line is taken high. The DAC can be
updated using LDAC via P3.4 of the 8XC51.
AD5763 to Blackfin DSP interface
Figure 39 shows how the AD5763 can be interfaced to Anlaog
Devices Blackfin DSP. The Blackfin has an integrated SPI port
that can be connected directly to the SPI pins of the AD5763 and
programmable I/O pins that can be used to set the state of a
digital input such as the LDAC pin.
PINS OMITTED FOR CLARITY
Figure 40. AD5763 to PIC16C6x/7x Interface
EVALUATION BOARD
The AD5763 performance can be evaluated via the AD5765
evaluation board.
The AD5765 comes with a full evaluation board to aid
designers in evaluating the high performance of the part with a
minimum of effort. All that is required with the evaluation
board is a power supply and a PC. The AD5765 evaluation kit
includes a populated, tested AD5765 printed circuit board. The
evaluation board interfaces to the USB interface of the PC.
Software is available with the evaluation board, which allows
the user to easily program the AD5765. The software runs on
any PC that has Microsoft® Windows® 2000/XP installed.
An application note is available that gives full details on
operating the evaluation board.
Rev. PrA | Page 27 of 31
AD5763
Preliminary Technical Data
OUTLINE DIMENSIONS
0.75
0.60
0.45
1.20
MAX
9.00 BSC SQ
25
32
24
1
PIN 1
7.00
BSC SQ
TOP VIEW
0.15
0.05
(PINS DOWN)
0° MIN
1.05
1.00
0.95
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
SEATING
PLANE
17
8
9
VIEW A
VIEW A
16
0.80
BSC
LEAD PITCH
ROTATED 90° CCW
0.45
0.37
0.30
COMPLIANT TO JEDEC STANDARDS MS-026ABA
Figure 41. 32-Lead Thin Plastic Quad Flat Package [TQFP]
(SU-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD5763BSUZ
AD5763CSUZ
INL
± 2 LSB
± 1 LSB
Temperature Range
−40°C to +105°C
−40°C to +105°C
Rev. PrA | Page 28 of 31
Package Description
32-lead TQFP
32-lead TQFP
Package Option
SU-32-2
SU-32-2
Preliminary Technical Data
AD5763
NOTES
Rev. PrA | Page 29 of 31
AD5763
NOTES
Rev. PrA | Page 30 of 31
Preliminary Technical Data
AD5763
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR07250-0-12/07(PrA)
Rev. PrA | Page 31 of 31