PLL Frequency Synthesizer ADF4108 FEATURES GENERAL DESCRIPTION 8.0 GHz bandwidth 3.2 V to 3.6 V power supply Separate charge pump supply (VP) allows extended tuning voltage in 3.3 V systems Programmable, dual modulus prescaler 8/9, 16/17, 32/33, or 64/65 Programmable charge pump currents Programmable antibacklash pulse width 3-wire serial interface Analog and digital lock detect Hardware and software power-down mode Loop filter design possible with ADIsimPLL The ADF4108 frequency synthesizer can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction with the dualmodulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R counter), allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). Its very high bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost. APPLICATIONS Broadband wireless access Satellite systems Instrumentation Wireless LANs Base stations for wireless radio FUNCTIONAL BLOCK DIAGRAM AVDD DVDD VP RSET CPGND REFERENCE 14-BIT R COUNTER REFIN PHASE FREQUENCY DETECTOR CHARGE PUMP CP 14 R COUNTER LATCH CLK DATA LE 24-BIT INPUT REGISTER FUNCTION LATCH 22 FROM SDOUT FUNCTION LATCH A, B COUNTER LATCH CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 HIGH Z 19 AVDD MUXOUT MUX 13-BIT B COUNTER SDOUT LOAD M3 M2 M1 6-BIT A COUNTER ADF4108 06015-001 6 AGND CURRENT SETTING 2 LOAD PRESCALER P/P + 1 CE CURRENT SETTING 1 13 N = BP + A RFINA RFINB LOCK DETECT DGND Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. ADF4108 TABLE OF CONTENTS Features .............................................................................................. 1 Phase Frequency Detector and Charge Pump...........................9 Applications....................................................................................... 1 MUXOUT and Lock Detect...................................................... 10 General Description ......................................................................... 1 Input Shift Register .................................................................... 10 Functional Block Diagram .............................................................. 1 Latch Summary........................................................................... 11 Revision History ............................................................................... 2 Reference Counter Latch Map.................................................. 12 Specifications..................................................................................... 3 AB Counter Latch Map ............................................................. 13 Timing Characteristics..................................................................... 5 Function Latch Map................................................................... 14 Absolute Maximum Rating ............................................................. 6 Initialization Latch Map ............................................................ 15 ESD Caution.................................................................................. 6 Function Latch............................................................................ 16 Pin Configuration and Function Descriptions............................. 7 Initialization Latch ..................................................................... 17 Typical Performance Characteristics ............................................. 8 Power Supply Considerations................................................... 17 Theory of Operation ........................................................................ 9 Interfacing ....................................................................................... 18 Reference Input Stage................................................................... 9 ADuC812 Interface .................................................................... 18 RF Input Stage............................................................................... 9 ADSP-2181 Interface ................................................................. 18 Prescaler (P/P + 1)........................................................................ 9 PCB Design Guidelines for Chip Scale Package......................... 19 A and B Counters ......................................................................... 9 Outline Dimensions ....................................................................... 20 R Counter ...................................................................................... 9 Ordering Guide .......................................................................... 20 REVISION HISTORY 4/06—Revision 0: Initial Version Rev. 0 | Page 2 of 20 ADF4108 SPECIFICATIONS AVDD = DVDD = 3.3 V ± 2%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter RF CHARACTERISTICS RF Input Frequency (RFIN) RF Input Sensitivity Maximum Allowable Prescaler Output Frequency 3 REFIN CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity 4 REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency 6 CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy RSET Range ICP Three-State Leakage Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VIH, Input High Voltage VIL, Input Low Voltage IINH, IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOH, Output High Voltage IOH VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD VP IDD (AIDD + DIDD) 7 IP Power-Down Mode (AIDD + DIDD) 8 B Version 1 B Chips 2 (Typ) Unit 1.0/8.0 −5/+5 300 325 1.0/8.0 −5/+5 300 325 GHz min/max dBm min/max MHz max MHz max 20/250 0.8/VDD 10 ±100 20/250 0.8/VDD 10 ±100 MHz min/max V p-p min/max pF max μA max 104 104 MHz max Test Conditions/Comments See Figure 12 for input circuit For lower frequencies ensure slew rate (SR) > 320 V/μs P=8 P = 16 For f < 20 MHz, ensure SR > 50 V/μs Biased at AVDD/2 5 Programmable; see Figure 19 5 625 2.5 3.0/11 1 2 5 625 2.5 3.0/11 1 2 mA typ μA typ % typ kΩ typ nA typ % typ With RSET = 5.1 kΩ See Figure 19 1 nA typical; TA = 25°C 0.5 V ≤ VCP ≤ VP – 0.5 V 1.5 2 1.5 2 % typ % typ 0.5 V ≤ VCP ≤ VP – 0.5 V VCP = VP/2 1.4 0.6 ±1 10 1.4 0.6 ±1 10 V min V max μA max pF max 1.4 VDD − 0.4 100 0.4 1.4 VDD − 0.4 100 0.4 V min V min μA max V max 3.2/3.6 AVDD AVDD/5.5 17 0.4 10 3.2/3.6 AVDD AVDD/5.5 17 0.4 10 V min/V max V min/V max mA max mA max μA typ Rev. 0 | Page 3 of 20 With RSET = 5.1 kΩ Open-drain output chosen; 1 kΩ pull-up resistor to 1.8 V CMOS output chosen IOL = 500 μA AVDD ≤ VP ≤ 5.5 V 15 mA typ TA = 25°C ADF4108 Parameter NOISE CHARACTERISTICS Normalized Phase Noise Floor 9 Phase Noise Performance 10 7900 MHz Output 11 Spurious Signals 7900 MHz Output11 B Version 1 B Chips 2 (Typ) Unit −219 −219 dBc/Hz typ −81 −81 dBc/Hz typ @ VCO output @ 1 kHz offset and 1 MHz PFD frequency –61 –61 dBc typ @ 1 MHz offset and 1 MHz PFD frequency 1 Test Conditions/Comments Operating temperature range (B version) is –40°C to +85°C. The B chip specifications are given as typical values. 3 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is less than this value. 4 AVDD = DVDD = 3.3 V. 5 AC coupling ensures AVDD/2 bias. 6 Guaranteed by design. Sample tested to ensure compliance. 7 TA = 25°C; AVDD = DVDD = 3.3 V; P = 32; RFIN = 8 GHz, fPFD = 200 kHz, REFIN = 10 MHz. 8 TA = 25°C; AVDD = DVDD = 3.3 V; R = 16,383; A = 63; B = 891; P = 32; RFIN = 7.0 GHz. 9 This value can be used to calculate phase noise for any application. Use the formula –219 + 10 log(fPFD) + 20 logN to calculate in-band phase noise performance as seen at the VCO output. The value given is the lowest noise mode. 10 The phase noise is measured with the EVAL-ADF4108EB1 evaluation board, with the Hittite HMC506LP4 VCO. The spectrum analyzer provides the REFIN for the synthesizer (fREFOUT = 10 MHz @ 0 dBm). 11 fREFIN = 10 MHz; fPFD = 1 MHz; fRF = 7900 MHz; N = 7900; loop B/W = 50 kHz, VCO = HMC506LP4, spurs are dominated by the leakage current on the tuning port of the HMC506LP4 VCO. 2 Rev. 0 | Page 4 of 20 ADF4108 TIMING CHARACTERISTICS AVDD = DVDD = 3.3 V ± 2%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter 1 t1 t2 t3 t4 t5 t6 2 Unit ns min ns min ns min ns min ns min ns min Test Conditions/Comments DATA to CLOCK setup time DATA to CLOCK hold time CLOCK high duration CLOCK low duration CLOCK to LE setup time LE pulse width Guaranteed by design but not production tested. Operating temperature range (B Version) is –40°C to +85°C. t3 t4 CLOCK t1 DATA DB23 (MSB) t2 DB22 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t6 LE t5 06015-002 1 Limit 2 (B Version) 10 10 25 25 10 20 LE Figure 2. Timing Diagram Rev. 0 | Page 5 of 20 ADF4108 ABSOLUTE MAXIMUM RATING TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to GND 1 AVDD to DVDD VP to GND VP to AVDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN, RFINA, RFINB to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature TSSOP θJA Thermal Impedance CSP θJA Thermal Impedance (Paddle Soldered) Reflow Soldering Peak Temperature (60 sec) Time at Peak Temperature Transistor Count CMOS Bipolar 1 Rating –0.3 V to +3.9 V –0.3 V to +0.3 V –0.3 V to +5.8 V –0.3 V to +5.8 V –0.3 V to VDD + 0.3 V –0.3 V to VP + 0.3 V –0.3 V to VDD + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly. –40°C to +85°C –65°C to +125°C 150°C 112°C/W 30.4°C/W 260 40 sec 6425 303 GND = AGND = DGND = 0 V. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 6 of 20 ADF4108 16 VP 15 DVDD CP 2 ADF4108 14 MUXOUT CPGND 1 AGND 2 AGND 3 RFINB 4 RFINA 5 TOP VIEW 13 LE (Not to Scale) 12 DATA RFINB 5 AGND 4 AVDD 7 10 CE REFIN 8 9 DGND NOTE: TRANSISTOR COUNT 6425 (CMOS), 303 (BIPOLAR). ADF4108 TOP VIEW (Not to Scale) 15 MUXOUT 14 LE 13 DATA 12 CLK 11 CE AVDD 6 AVDD 7 REFIN 8 DGND 9 DGND 10 11 CLK 06015-030 RFINA 6 PIN 1 INDICATOR Figure 3. TSSOP Pin Configuration for TSSOP 06015-003 RSET 1 CPGND 3 20 CP 19 RSET 18 VP 17 DVDD 16 DVDD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 4. LFCSP_VQ Pin Configuration Table 4. Pin Function Descriptions Pin No. TSSOP LFCSP_VQ 1 19 Mnemonic RSET 2 20 CP 3 4 5 1 2, 3 4 CPGND AGND RFINB 6 7 5 6, 7 RFINA AVDD 8 8 REFIN 9 10 9, 10 11 DGND CE 11 12 CLK 12 13 DATA 13 14 LE 14 15 MUXOUT 15 16, 17 DVDD 16 18 VP Description Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is 25.5 I CP MAX = R SET with RSET = 5.1 kΩ, ICP MAX = 5 mA. Charge Pump Output. When enabled, this pin provides ±ICP to the external loop filter, which in turn drives the external VCO. Charge Pump Ground. This is the ground return path for the charge pump. Analog Ground. This is the ground return path of the prescaler. Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass capacitor, typically 100 pF. See Figure 12. Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO. Analog Power Supply. This voltage may range from 3.2 V to 3.6 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD. Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of 100 kΩ. See Figure 11. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled. Digital Ground. Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state mode. Taking the pin high will power up the device, depending on the status of the power-down bit, F2. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. Serial Data Input. The serial data is loaded MSB first with the 2 LSBs being the control bits. This input is a high impedance CMOS input. Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be accessed externally. Digital Power Supply. This may range from 3.2 V to 3.6 V. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD. Charge Pump Power Supply. This voltage should be greater than or equal to VDD. In systems where VDD is 3.3 V, it can be set to 5 V and used to drive a VCO with a tuning range of up to 5 V. Rev. 0 | Page 7 of 20 ADF4108 TYPICAL PERFORMANCE CHARACTERISTICS ANGS11 –17.2820 –20.6919 –24.5386 –27.3228 –31.0698 –34.8623 –38.5574 –41.9093 –45.6990 –49.4185 –52.8898 –56.2923 –60.2584 –63.1446 –65.6464 –68.0742 –71.3530 –75.5658 –79.6404 –82.8246 –85.2795 –85.6298 –86.1854 –86.4997 –88.8080 –91.9737 –95.4087 –99.1282 –102.748 –107.167 –111.883 –117.548 –123.856 –130.399 –136.744 –142.766 –149.269 –154.884 Freq 4.30000 4.40000 4.50000 4.60000 4.70000 4.80000 4.90000 5.00000 5.10000 5.20000 5.30000 5.40000 5.50000 5.60000 5.70000 5.80000 5.90000 6.00000 6.10000 6.20000 6.30000 6.40000 6.50000 6.60000 6.70000 6.80000 6.90000 7.00000 7.10000 7.20000 7.30000 7.40000 7.50000 7.60000 7.70000 7.80000 7.90000 8.00000 MAGS11 0.45555 0.46108 0.45325 0.45054 0.45200 0.45043 0.45282 0.44287 0.44909 0.44294 0.44558 0.45417 0.46038 0.47128 0.47439 0.48604 0.50637 0.52172 0.53342 0.53716 0.55804 0.56362 0.58268 0.59248 0.61066 0.61830 0.61633 0.61673 0.60597 0.58376 0.57673 0.58157 0.60040 0.61332 0.62927 0.63938 0.65320 0.65804 0 ANGS11 –159.680 –164.916 –168.452 –173.462 –176.697 178.824 174.947 170.237 166.617 162.786 158.766 153.195 147.721 139.760 132.657 125.782 121.110 115.400 107.705 101.572 97.5379 93.0936 89.2227 86.3300 83.0956 80.8843 78.0872 75.3727 73.9456 73.5883 74.1975 76.2136 77.1545 76.1122 74.8359 74.0546 72.0061 69.9926 –0.3dBm –61dBc –60 –80 –100 –120 –2MHz –1MHz 7900MHz 1MHz 2MHz FREQUENCY Figure 5. S Parameter Data for the RF Input Figure 8. Reference Spurs at 7.9 GHz Note: The spurs are dominated by the leakage current of the tuning port on the HMC506LP4 VCO. The leakage current was measured to be 27 nA. 6 0 VDD = 3.3V 5 –5 4 TA = +85°C VPP = 5V ICP SETTLING = 5mA 3 –10 2 –15 ICP (mA) TA = +25°C –20 1 0 –1 –2 –25 –3 –4 –30 2 3 4 5 6 7 8 9 RF INPUT FREQUENCY (GHz) –6 06015-005 1 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 –120 –50 VDD = 3V VP = 5V –60 –130 PHASE NOISE (dBc/Hz) –80 –90 –100 –110 –140 VDD = 3.3V, VP = 5V ICP = 5mA PFD FREQUENCY = 1MHz LOOP BANDWIDTH = 50kHz PHASE NOISE = –82dBc/Hz @ 1kHz HMC506LP4 VCO –150 1kHz 10MHz FREQUENCY OFFSET –140 –150 –160 –170 06015-010 PHASE NOISE (dBc/Hz) –70 –130 5.0 Figure 9. Charge Pump Output Characteristics Figure 6. RF Input Sensitivity –120 4.5 VCP (V) 06015-015 –5 TA = –40°C –35 Figure 7. Phase Noise at 7.9 GHz Phase Noise –180 10k 100k 1M 10M 100M PHASE FREQUENCY DETECTOR (Hz) Figure 10. Phase Noise (Referred to CP Output) vs. PFD Frequency Rev. 0 | Page 8 of 20 06015-014 RF INPUT POWER (dBm) VDD = 3.3V, VP = 5V ICP = 5mA PFD FREQUENCY = 1MHz –20 LOOP BANDWIDTH = 50kHz RES BANDWIDTH = 3kHz VIDEO BANDWIDTH = 3kHz –40 AVERAGES = 1 OUTPUT POWER = –0.3dBm HMC506LP4 VCO 06015-011 MAGS11 0.89148 0.88133 0.87152 0.85855 0.84911 0.83512 0.82374 0.80871 0.79176 0.77205 0.75696 0.74234 0.72239 0.69419 0.67288 0.66227 0.64758 0.62454 0.59466 0.55932 0.52256 0.48754 0.46411 0.45776 0.44859 0.44588 0.43810 0.43269 0.42777 0.42859 0.43365 0.43849 0.44475 0.44800 0.45223 0.45555 0.45313 0.45622 OUTPUT POWER (dB) Freq 0.50000 0.60000 0.70000 0.80000 0.90000 1.00000 1.10000 1.20000 1.30000 1.40000 1.50000 1.60000 1.70000 1.80000 1.90000 2.00000 2.10000 2.20000 2.30000 2.40000 2.50000 2.60000 2.70000 2.80000 2.90000 3.00000 3.10000 3.20000 3.30000 3.40000 3.50000 3.60000 3.70000 3.80000 3.90000 4.00000 4.10000 4.20000 KEYWORD: R 06015-004 FREQ UNIT: GHz PARAM TYPE: s DATA FORMAT: MA ADF4108 THEORY OF OPERATION REFERENCE INPUT STAGE The reference input stage is shown in Figure 11. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down. POWER-DOWN CONTROL NC 100kΩ feedback counter. The counters are specified to work when the prescaler output is 300 MHz or less. Thus, with an RF input frequency of 4.0 GHz, a prescaler value of 16/17 is valid but a value of 8/9 is not valid. Pulse Swallow Function The A and B counters, in conjunction with the dual-modulus prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency divided by R. The equation for the VCO frequency is as follows: f VCO = [(P × B ) + A ] × SW2 REFIN TO R COUNTER NC BUFFER SW1 f REFIN R where: fVCO is the output frequency of external voltage controlled oscillator (VCO). P is the preset modulus of dual-modulus prescaler (8/9, 16/17, and so on.). B is the preset divide ratio of binary 13-bit counter (3 to 8191). A is the preset divide ratio of binary 6-bit swallow counter (0 to 63). fREFIN is the external reference frequency oscillator. 06015-016 SW3 NO Figure 11. Reference Input Stage RF INPUT STAGE The RF input stage is shown in Figure 12. It is followed by a 2-stage limiting amplifier to generate the CML clock levels needed for the prescaler. N = BP + A 500Ω 1.6V AVDD 13-BIT B COUNTER 500Ω FROM RF INPUT STAGE RFINA PRESCALER P/P + 1 MODULUS CONTROL TO PFD LOAD LOAD 6-BIT A COUNTER N DIVIDER RFINB 06015-018 BIAS GENERATOR AGND 06015-017 Figure 13. A and B Counters R COUNTER Figure 12. RF Input Stage PRESCALER (P/P + 1) The dual-modulus prescaler (P/P + 1), along with the A and B counters, enables the large division ratio, N, to be realized (N = BP + A). The dual-modulus prescaler, operating at CML levels, takes the clock from the RF input stage and divides it down to a manageable frequency for the CMOS A and B counters. The prescaler is programmable. It can be set in software to 8/9, 16/17, 32/33, or 64/65. It is based on a synchronous 4/5 core. A minimum divide ratio is possible for contiguous output frequencies. This minimum is determined by P, the prescaler value, and is given by: (P2 – P). A AND B COUNTERS The A and B CMOS counters combine with the dual-modulus prescaler to allow a wide ranging division ratio in the PLL The 14-bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are allowed. PHASE FREQUENCY DETECTOR AND CHARGE PUMP The phase frequency detector (PFD) takes inputs from the R counter and N counter (N = BP + A) and produces an output proportional to the phase and frequency difference between them. Figure 14 is a simplified schematic. The PFD includes a programmable delay element that controls the width of the antibacklash pulse. This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs. Two bits in the reference counter latch, ABP2 and ABP1, control the width of the pulse. (See Figure 17.) Rev. 0 | Page 9 of 20 ADF4108 VP HI D1 Q1 DVDD CHARGE PUMP UP ANALOG LOCK DETECT U1 R DIVIDER DIGITAL LOCK DETECT CLR1 R COUNTER OUTPUT PROGRAMMABLE DELAY MUX CONTROL MUXOUT N COUNTER OUTPUT U3 CP SDOUT ABP1 DGND CLR2 DOWN D2 Q2 HI 06015-020 ABP2 Figure 15. MUXOUT Circuit 06015-019 U2 N DIVIDER CPGND Figure 14. PFD Simplified Schematic and Timing (in Lock) MUXOUT AND LOCK DETECT The output multiplexer on the ADF4108 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 in the function latch. Figure 19 shows the full truth table. Figure 15 shows the MUXOUT section in block diagram form. Lock Detect MUXOUT can be programmed for two types of lock detect: digital lock detect and analog lock detect. INPUT SHIFT REGISTER The ADF4108 digital section includes a 24-bit input shift register, a 14-bit R counter, and a 19-bit N counter, comprising a 6-bit A counter and a 13-bit B counter. Data is clocked into the 24-bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2, C1) in the shift register. These are the 2 LSBs, DB1 and DB0, as shown in the timing diagram of Figure 2. The truth table for these bits is shown in Table 5. Figure 16 shows a summary of how the latches are programmed. Digital lock detect is active high. When the lock detect precision (LDP) bit in the R counter latch is set to 0, digital lock detect is set high when the phase error on three consecutive phase detector (PD) cycles is less than 15 ns. With LDP set to 1, five consecutive cycles of less than 15 ns are required to set the lock detect. It will stay set high until a phase error of greater than 25 ns is detected on any subsequent PD cycle. Table 5. C2 and C1 Truth Table Control Bits C2 C1 0 0 0 1 1 0 1 1 The N-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 kΩ nominal. When lock has been detected, this output will be high with narrow, low-going pulses. Rev. 0 | Page 10 of 20 Data Latch R counter N counter (A and B) Function latch (Including prescaler) Initialization latch ADF4108 LATCH SUMMARY LOCK DETECT PRECISION REFERENCE COUNTER LATCH RESERVED TEST MODE BITS ANTIBACKLASH WIDTH DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 X 0 0 LDP T2 T1 CONTROL BITS 14-BIT REFERENCE COUNTER ABP2 ABP1 R14 R13 R12 R11 R10 R9 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0) RESERVED CP GAIN N COUNTER LATCH 13-BIT B COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 X X G1 B13 B12 B11 B10 B9 B8 B7 B6 CONTROL BITS 6-BIT A COUNTER B5 B4 B3 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 B2 B1 A6 A5 A4 A3 A2 A1 C2 (0) C1 (1) CONTROL BITS FASTLOCK ENABLE CP THREESTATE PD POLARITY POWERDOWN 1 COUNTER RESET DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (0) CONTROL BITS PRESCALER VALUE P2 P1 POWERDOWN 2 FASTLOCK MODE FUNCTION LATCH PD2 CURRENT SETTING 2 CPI6 CPI5 CPI4 CURRENT SETTING 1 CPI3 CPI2 CPI1 TIMER COUNTER CONTROL TC4 TC3 TC2 TC1 F5 MUXOUT CONTROL DB1 DB0 CP THREESTATE PD POLARITY POWERDOWN 1 COUNTER RESET DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 F4 F3 F2 M3 M2 M1 PD1 F1 P2 P1 PD2 CURRENT SETTING 2 CPI6 CPI5 CPI4 CURRENT SETTING 1 CPI3 CPI2 TIMER COUNTER CONTROL CPI1 TC4 TC3 TC2 TC1 F5 Figure 16. Latch Summary Rev. 0 | Page 11 of 20 MUXOUT CONTROL DB1 DB0 C2 (1) C1 (1) 06015-021 FASTLOCK ENABLE DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 PRESCALER VALUE POWERDOWN 2 FASTLOCK MODE INITIALIZATION LATCH ADF4108 LOCK DETECT PRECISION REFERENCE COUNTER LATCH MAP RESERVED TEST MODE BITS ANTIBACKLASH WIDTH DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 X 0 0 LDP T2 T1 ABP2 ABP1 CONTROL BITS 14-BIT REFERENCE COUNTER R14 R13 R12 R11 R10 R9 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0) X = DON’T CARE ABP2 0 0 1 1 ABP1 0 1 0 1 R14 R13 R12 .......... R3 R2 R1 DIVIDE RATIO 0 0 0 0 . . . 0 0 0 0 . . . 0 0 0 0 . . . .......... .......... .......... .......... .......... .......... .......... 0 0 0 1 . . . 0 1 1 0 . . . 1 0 1 0 . . . 1 2 3 4 . . . 1 1 1 .......... 1 0 0 16380 1 1 1 1 1 1 1 1 1 .......... .......... .......... 1 1 1 0 1 1 1 0 1 16381 16382 16383 ANTIBACKLASH PULSE WIDTH 2.9ns 1.3ns 6.0ns 2.9ns TEST MODE BITS SHOULD BE SET TO 00 FOR NORMAL OPERATION. LDP 0 1 OPERATION THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT IS SET. FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT IS SET. 06015-022 BOTH OF THESE BITS MUST BE SET TO 0 FOR NORMAL OPERATION. Figure 17. Reference Counter Latch Map Rev. 0 | Page 12 of 20 ADF4108 CP GAIN AB COUNTER LATCH MAP RESERVED CONTROL BITS 6-BIT A COUNTER 13-BIT B COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 X X G1 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A6 A5 A4 A3 A2 A1 DB1 DB0 C2 (0) C1 (1) X = DON’T CARE B13 B12 B11 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... A1 A COUNTER DIVIDE RATIO 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... 0 0 1 1 . . . 0 0 1 1 0 1 0 1 . . . 0 1 0 1 0 1 2 3 . . . 60 61 62 63 B1 B COUNTER DIVIDE RATIO 0 0 1 1 . . . 0 0 1 1 0 1 0 1 . . . 0 1 0 1 NOT ALLOWED NOT ALLOWED NOT ALLOWED 3 . . . 8188 8189 8190 8191 0 CHARGE PUMP CURRENT SETTING 1 IS PERMANENTLY USED. 0 1 CHARGE PUMP CURRENT SETTING 2 IS PERMANENTLY USED. CHARGE PUMP CURRENT SETTING 1 IS USED. CHARGE PUMP CURRENT IS SWITCHED TO SETTING 2. THE TIME SPENT IN SETTING 2 IS DEPENDENT ON WHICH FASTLOCK MODE IS USED. SEE FUNCTION LATCH DESCRIPTION. 0 A2 B2 0 1 .......... 0 0 0 0 . . . 1 1 1 1 G1 CP GAIN 1 A5 B3 F4 (FUNCTION LATCH) FASTLOCK ENABLE 1 A6 OPERATION N = BP + A, P IS PRESCALER VALUE SET IN THE FUNCTION LATCH. B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTINUOUSLY ADJACENT VALUES OF (N × FREF ), AT THE OUTPUT, NMIN IS (P2 – P). 06015-023 THESE BITS ARE NOT USED BY THE DEVICE AND ARE DON'T CARE BITS. Figure 18. AB Counter Latch Map Rev. 0 | Page 13 of 20 ADF4108 FASTLOCK ENABLE CP THREESTATE PD POLARITY POWERDOWN 1 COUNTER RESET DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 F4 F3 F2 M3 M2 M1 PD1 F1 POWERDOWN 2 FASTLOCK MODE FUNCTION LATCH MAP PRESCALER VALUE P1 PD2 CPI6 CPI5 CPI4 CPI3 CPI2 TIMER COUNTER CONTROL CPI1 TC4 TC3 TC2 TC1 TC4 TC3 TC2 TC1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 3kΩ 1.06 2.12 3.18 4.24 5.30 6.36 7.42 8.50 5.1kΩ 0.625 1.25 1.875 2.5 3.125 3.75 4.375 5.0 CPI6 CPI5 CPI4 CPI3 0 0 0 0 1 1 1 1 CPI2 0 0 1 1 0 0 1 1 CPI1 0 1 0 1 0 1 0 1 PD2 PD1 MODE X X 0 1 X 0 1 1 ASYNCHRONOUS POWER-DOWN NORMAL OPERATION ASYNCHRONOUS POWER-DOWN SYNCHRONOUS POWER-DOWN P1 PRESCALER VALUE 0 1 0 1 8/9 16/17 32/33 64/65 PHASE DETECTOR POLARITY F1 0 1 NEGATIVE POSITIVE 0 1 F3 CHARGE PUMP OUTPUT 0 1 NORMAL THREE-STATE F4 F5 FASTLOCK MODE 0 1 1 X 0 1 FASTLOCK DISABLED FASTLOCK MODE 1 FASTLOCK MODE 2 TIMEOUT (PFD CYCLES) 3 7 11 15 19 23 27 31 35 39 43 47 51 55 59 63 DB1 DB0 C2 (1) C1 (0) COUNTER OPERATION NORMAL R, A, B COUNTERS HELD IN RESET M3 M2 M1 OUTPUT 0 0 0 0 0 1 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 1 0 1 THREE-STATE OUTPUT DIGITAL LOCK DETECT (ACTIVE HIGH) N DIVIDER OUTPUT DVDD R DIVIDER OUTPUT N-CHANNEL OPEN-DRAIN LOCK DETECT SERIAL DATA OUTPUT DGND 11kΩ 0.289 0.580 0.870 1.160 1.450 1.730 2.020 2.320 0 1 1 1 0 0 1 1 F2 CONTROL BITS ICP (mA) CE PIN P2 F5 MUXOUT CONTROL 06015-024 P2 CURRENT SETTING 1 CURRENT SETTING 2 Figure 19. Function Latch Map Rev. 0 | Page 14 of 20 ADF4108 FASTLOCK ENABLE CP THREESTATE PD POLARITY POWERDOWN 1 COUNTER RESET DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 F4 F3 F2 M3 M2 M1 PD1 F1 POWERDOWN 2 FASTLOCK MODE INITIALIZATION LATCH MAP PRESCALER VALUE P1 PD2 CPI6 CPI5 CPI4 CPI3 CPI2 TIMER COUNTER CONTROL CPI1 TC4 TC3 TC2 TC1 TC4 TC3 TC2 TC1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 3kΩ 1.06 2.12 3.18 4.24 5.30 6.36 7.42 8.50 5.1kΩ 0.625 1.25 1.875 2.5 3.125 3.75 4.375 5.0 CPI6 CPI5 CPI4 CPI3 0 0 0 0 1 1 1 1 CPI2 0 0 1 1 0 0 1 1 CPI1 0 1 0 1 0 1 0 1 PD2 PD1 MODE X X 0 1 X 0 1 1 ASYNCHRONOUS POWER-DOWN NORMAL OPERATION ASYNCHRONOUS POWER-DOWN SYNCHRONOUS POWER-DOWN P1 PRESCALER VALUE 0 1 0 1 8/9 16/17 32/33 64/65 PHASE DETECTOR POLARITY F1 0 1 NEGATIVE POSITIVE 0 1 F3 CHARGE PUMP OUTPUT 0 1 NORMAL THREE-STATE F4 F5 FASTLOCK MODE 0 1 1 X 0 1 FASTLOCK DISABLED FASTLOCK MODE 1 FASTLOCK MODE 2 TIMEOUT (PFD CYCLES) 3 7 11 15 19 23 27 31 35 39 43 47 51 55 59 63 DB1 DB0 C2 (1) C1 (1) COUNTER OPERATION NORMAL R, A, B COUNTERS HELD IN RESET M3 M2 M1 OUTPUT 0 0 0 0 0 1 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 1 0 1 THREE-STATE OUTPUT DIGITAL LOCK DETECT (ACTIVE HIGH) N DIVIDER OUTPUT DVDD R DIVIDER OUTPUT N-CHANNEL OPEN-DRAIN LOCK DETECT SERIAL DATA OUTPUT DGND 11kΩ 0.289 0.580 0.870 1.160 1.450 1.730 2.020 2.320 CE PIN 0 0 1 1 F2 CONTROL BITS ICP (mA) 0 1 1 1 P2 F5 MUXOUT CONTROL 06015-025 P2 CURRENT SETTING 1 CURRENT SETTING 2 Figure 20. Initialization Latch Map Rev. 0 | Page 15 of 20 ADF4108 The on-chip function latch is programmed with C2 and C1 set to 1 and 0, respectively. Figure 19 shows the input data format for programming the function latch. fastlock is enabled, this bit determines which fastlock mode is used. If the fastlock mode bit is 0, then Fastlock Mode 1 is selected; and if the fastlock mode bit is 1, then Fastlock Mode 2 is selected. Counter Reset Fastlock Mode 1 FUNCTION LATCH DB2 (F1) is the counter reset bit. When this bit is 1, the R counter and the AB counters are reset. For normal operation, this bit should be 0. Upon powering up, the F1 bit needs to be disabled (set to 0). Then, the N counter resumes counting in close alignment with the R counter. (The maximum error is one prescaler cycle.) Power-Down When the CE pin is low, the device is immediately disabled regardless of the states of PD2 and PD1. In the programmed asynchronous power-down, the device powers down immediately after latching a 1 into the PD1 bit, with the condition that PD2 has been loaded with a 0. In the programmed synchronous power-down, the device power-down is gated by the charge pump to prevent unwanted frequency jumps. Once the power-down is enabled by writing a 1 into PD1 (on condition that a 1 has also been loaded to PD2), then the device will go into power-down on the occurrence of the next charge pump event. When a power-down is activated (either synchronous or asynchronous mode, including CE pin activated power-down), the following events occur: • All active dc current paths are removed. • The R, N, and timeout counters are forced to their load state conditions. • The charge pump is forced into three-state mode. • The digital lock detect circuitry is reset. • The RFIN input is debiased. • The reference input buffer circuitry is disabled. • The input register remains active and capable of loading and latching data. Fastlock Mode 2 The device enters fastlock by having a 1 written to the CP gain bit in the AB counter latch. The device exits fastlock under the control of the timer counter. After the timeout period determined by the value in TC4:TC1, the CP gain bit in the AB counter latch is automatically reset to 0 and the device reverts to normal mode instead of fastlock. See Figure 19 for the timeout periods. Timer Counter Control The user has the option of programming two charge pump currents. The intent is that Current Setting 1 is used when the RF output is stable and the system is in a static state. Current Setting 2 is meant to be used when the system is dynamic and in a state of change (that is, when a new output frequency is programmed). The normal sequence of events is as follows: The user initially decides what the preferred charge pump currents are going to be. For example, the choice may be 2.5 mA as Current Setting 1 and 5 mA as Current Setting 2. At the same time it must be decided how long the secondary current is to stay active before reverting to the primary current. This is controlled by the timer counter control bits, DB14:DB11 (TC4:TC1) in the function latch. The truth table is given in Figure 19. MUXOUT Control The on-chip multiplexer is controlled by M3, M2, and M1 on the ADF4108. Figure 19 shows the truth table. Fastlock Enable Bit DB9 of the function latch is the fastlock enable bit. Fastlock is enabled only when this bit is 1. DB10 of the function latch is the fastlock mode bit. When The device enters fastlock by having a 1 written to the CP gain bit in the AB counter latch. The device exits fastlock by having a 0 written to the CP gain bit in the AB counter latch. The charge pump current is switched to the contents of Current Setting 2. DB3 (PD1) and DB21 (PD2) provide programmable powerdown modes. They are enabled by the CE pin. Fastlock Mode Bit The charge pump current is switched to the contents of Current Setting 2. Now, to program a new output frequency, the user simply programs the AB counter latch with new values for A and B. At the same time, the CP gain bit can be set to 1, which sets the charge pump with the value in CPI6:CPI4 for a period of time determined by TC4–TC1. When this time is up, the charge pump current reverts to the value set by CPI3:CPI1. At the same time, the CP gain bit in the AB counter latch is reset to 0 and is now ready for the next time the user wishes to change the frequency. Note that there is an enable feature on the timer counter. It is enabled when Fastlock Mode 2 is chosen by setting the fastlock mode bit (DB10) in the function latch to 1. Rev. 0 | Page 16 of 20 ADF4108 Charge Pump Currents When the initialization latch is loaded, the following occurs: CPI3, CPI2, and CPI1 program Current Setting 1 for the charge pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the charge pump. The truth table is given in Figure 19. • • Prescaler Value P2 and P1 in the function latch set the prescaler values. The prescaler value should be chosen so that the prescaler output frequency is always less than or equal to 300 MHz. Thus, with an RF frequency of 4 GHz, a prescaler value of 16/17 is valid but a value of 8/9 is not valid. • CE Pin Method PD Polarity This bit sets the phase detector polarity bit. See Figure 19. 1. Apply VDD. 2. Bring CE low to put the device into power-down. This is an asynchronous power-down in that it happens immediately. 3. Program the function latch (10). 4. Program the R counter latch (00). 5. Program the AB counter latch (01). 6. Bring CE high to take the device out of power-down. The R and AB counters will now resume counting in close alignment. CP Three-State This bit controls the CP output pin. With the bit set high, the CP output is put into three-state. With the bit set low, the CP output is enabled. INITIALIZATION LATCH The initialization latch is programmed when C2 and C1 are set to 1 and 1. This is essentially the same as the function latch (programmed when C2, C1 = 1, 0). However, when the initialization latch is programmed, an additional internal reset pulse is applied to the R and AB counters. This pulse ensures that the AB counter is at load point when the AB counter data is latched and the device will begin counting in close phase alignment. If the latch is programmed for synchronous power-down (CE pin is high; PD1 bit is high; PD2 bit is low), the internal pulse also triggers this power-down. The prescaler reference and the oscillator input buffer are unaffected by the internal reset pulse and so close phase alignment is maintained when counting resumes. When the first AB counter data is latched after initialization, the internal reset pulse is again activated. However, successive AB counter loads after this will not trigger the internal reset pulse. Device Programming after Initial Power-Up After initially powering up the device, there are three ways to program the device. Initialization Latch Method 1. Apply VDD. 2. Program the initialization latch (11 in 2 LSBs of input word). Make sure that the F1 bit is programmed to 0. 3. Next, do a function latch load (10 in 2 LSBs of the control word), making sure that the F1 bit is programmed to a 0. 4. Then do an R load (00 in 2 LSBs). 5. Then do an AB load (01 in 2 LSBs). The function latch contents are loaded. An internal pulse resets the R, AB, and timeout counters to load-state conditions and also three-states the charge pump. Note that the prescaler band gap reference and the oscillator input buffer are unaffected by the internal reset pulse, allowing close phase alignment when counting resumes. Latching the first AB counter data after the initialization word will activate the same internal reset pulse. Successive AB loads will not trigger the internal reset pulse unless there is another initialization. Note that after CE goes high, a duration of 1 μs may be required for the prescaler band gap voltage and oscillator input buffer bias to reach steady state. CE can be used to power the device up and down to check for channel activity. The input register does not need to be reprogrammed each time the device is disabled and enabled as long as it has been programmed at least once after VDD was initially applied. Counter Reset Method 1. Apply VDD. 2. Do a function latch load (10 in 2 LSBs). As part of this, load 1 to the F1 bit. This enables the counter reset. 3. Do an R counter load (00 in 2 LSBs). 4. Do an AB counter load (01 in 2 LSBs). 5. Do a function latch load (10 in 2 LSBs). As part of this, load 0 to the F1 bit. This disables the counter reset. This sequence provides the same close alignment as the initialization method. It offers direct control over the internal reset. Note that counter reset holds the counters at load point and three-states the charge pump, but does not trigger synchronous power-down. POWER SUPPLY CONSIDERATIONS The ADF4108 operates over a power supply range of 3.2 V to 3.6 V. The ADP3300ART-3.3 is a low dropout linear regulator from Analog Devices. It outputs 3.3 V with an accuracy of 1.4% and is recommended for use with the ADF4108. Rev. 0 | Page 17 of 20 ADF4108 INTERFACING The ADF4108 has a simple SPI™-compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When LE (Latch Enable) goes high, the 24 bits that have been clocked into the input register on each rising edge of CLK are transferred to the appropriate latch. See Figure 2 for the timing diagram and Table 5 for the latch truth table. ADuC812 INTERFACE Figure 21 shows the interface between the ADF4108 and the ADuC812 MicroConverter®. Since the ADuC812 is based on an 8051 core, this interface can be used with any 8051 based microcontroller. The MicroConverter is set up for SPI master mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF4108 needs a 24-bit word. This is accomplished by writing three 8-bit bytes from the MicroConverter to the device. When the third byte has been written, the LE input should be brought high to complete the transfer. MOSI CLK DATA LE ADuC812 I/O PORTS ADF4108 CE 06015-026 MUXOUT (LOCK DETECT) Figure 21. ADuC812 to ADF4108 Interface ADSP-2181 INTERFACE Figure 22 shows the interface between the ADF4108 and the ADSP-21xx Digital Signal Processor. The ADF4108 needs a 24-bit serial word for each latch write. The easiest way to accomplish this using the ADSP21xx family is to use the autobuffered transmit mode of operation with alternate framing. This provides a means for transmitting an entire block of serial data before an interrupt is generated. Set up the word length for 8 bits and use three memory locations for each 24-bit word. To program each 24-bit latch, store the three 8-bit bytes, enable the autobuffered mode, and then write to the transmit register of the DSP. This last operation initiates the autobuffer transfer. On first applying power to the ADF4108, it needs four writes (one each to the initialization latch, function latch, R counter latch, and N counter latch) for the output to become active. I/O port lines on the ADuC812 are also used to control powerdown (CE input) and to detect lock (MUXOUT configured as lock detect and polled by the port input). When operating in the mode described, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed will be 166 kHz. Rev. 0 | Page 18 of 20 SCLOCK MOSI ADSP-21xx TFS CLK DATA LE ADF4108 CE I/O FLAGS MUXOUT (LOCK DETECT) Figure 22. ADSP-21xx to ADF4108 Interface 06015-027 The maximum allowable serial clock rate is 20 MHz. This means that the maximum update rate possible for the device is 833 kHz or one update every 1.2 μs. This is certainly more than adequate for systems that have typical lock times in hundreds of microseconds. SCLOCK ADF4108 PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE The lands on the chip scale package (CP-20) are rectangular. The printed circuit board pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad. This will ensure that the solder joint size is maximized. The bottom of the chip scale package has a central thermal pad. Thermal vias can be used on the printed circuit board thermal pad to improve thermal performance of the package. If vias are used, they should be incorporated in the thermal pad at 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm and the via barrel should be plated with 1 oz. copper to plug the via. The thermal pad on the printed circuit board should be at least as large as this exposed pad. On the printed circuit board, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. This will ensure that shorting is avoided. The user should connect the printed circuit board thermal pad to AGND. Rev. 0 | Page 19 of 20 ADF4108 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.20 0.09 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 23. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 0.60 MAX 4.00 BSC SQ 0.60 MAX PIN 1 INDICATOR TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING 0.50 PLANE BSC PIN 1 INDICATOR 16 15 20 1 11 10 6 2.25 2.10 SQ 1.95 3.75 BCS SQ 0.80 MAX 0.65 TYP 0.20 REF 0.75 0.55 0.35 5 0.25 MIN 0.30 0.23 0.18 0.05 MAX 0.02 NOM COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1 Figure 24. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Thin Quad (CP-20-1) Dimensions shown in millimeters ORDERING GUIDE Model ADF4108BRUZ 1 ADF4108BRUZ-RL1 ADF4108BRUZ-RL71 ADF4108BCPZ1 ADF4108BCPZ–RL1 ADF4108BCPZ–RL71 EVAL-ADF4108EB1 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Z = Pb-free part. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06015-0-4/06(0) Rev. 0 | Page 20 of 20 Package Option RU-16 RU-16 RU-16 CP-20-1 CP-20-1 CP-20-1