5 V 18-Bit nanoDACTM in a SOT-23 AD5680 FEATURES FUNCTIONAL BLOCK DIAGRAM Single 18-bit nanoDAC 18-bit monotonic 12-bit accuracy guaranteed Tiny 8-lead SOT-23 package Power-on reset to zero scale/midscale 4.5 V to 5.5 V power supply Serial interface Rail-to-rail operation SYNC interrupt facility Temperature range −40°C to +105°C VREF GND VDD VFB POWER-ON RESET DAC REGISTER OUTPUT BUFFER REF(+) 18-BIT DAC AD5680 SYNC SCLK DIN 05854-001 INPUT CONTROL LOGIC APPLICATIONS Closed-loop process control Low bandwidth data acquisition systems Portable battery-powered instruments Gain and offset adjustment Precision setpoint control VOUT Figure 1. GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD5680, a member of the nanoDAC family, is a single, 18-bit buffered voltage-out DAC that operates from a single 4.5 V to 5.5 V supply and is 18-bit monotonic. 1. 18 bits of resolution. 2. 12-bit accuracy guaranteed for 18-bit DAC. The AD5680 requires an external reference voltage to set the output range of the DAC. The part incorporates a power-on reset circuit that ensures the DAC output powers up to 0 V (AD5680-1) or to midscale (AD5680-2) and remains there until a valid write takes place. 3. Available in an 8-lead SOT-23. 4. Low power. Typically consumes 1.6 mW at 5 V. 5. Power-on reset to zero scale or to midscale. The low power consumption of this part in normal operation makes it ideally suited to portable battery-operated equipment. The power consumption is 1.6 mW at 5 V. RELATED DEVICES AD5662 16-bit DAC in SOT-23. The AD5680 on-chip precision output amplifier allows rail-torail output swing to be achieved. For remote sensing applications, the output amplifier’s inverting input is available to the user. The AD5680 uses a versatile 3-wire serial interface that operates at clock rates up to 30 MHz, and is compatible with standard SPI®, QSPI™, MICROWIRE™, and DSP interface standards. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. AD5680 TABLE OF CONTENTS Features .............................................................................................. 1 Output Amplifier........................................................................ 11 Applications....................................................................................... 1 Interpolator Architecture .......................................................... 11 Functional Block Diagram .............................................................. 1 Serial Interface ............................................................................ 12 General Description ......................................................................... 1 Input Shift Register .................................................................... 12 Product Highlights ........................................................................... 1 SYNC Interrupt .......................................................................... 12 Related Devices ................................................................................. 1 Power-On Reset.......................................................................... 12 Revision History ............................................................................... 2 Microprocessor Interfacing....................................................... 13 Specifications..................................................................................... 3 Applications..................................................................................... 14 Timing Characteristics..................................................................... 4 Closed-Loop Applications ........................................................ 14 Absolute Maximum Ratings............................................................ 5 Filter ............................................................................................. 14 ESD Caution.................................................................................. 5 Choosing a Reference for the AD5680.................................... 15 Pin Configuration and Function Description .............................. 6 Using a Reference as a Power Supply for the AD5680 .......... 16 Typical Performance Characteristics ............................................. 7 Using the AD5680 with a Galvanically Isolated Interface .... 16 Terminology .................................................................................... 10 Power Supply Bypassing and Grounding................................ 16 Theory of Operation ...................................................................... 11 Outline Dimensions ....................................................................... 17 DAC Section................................................................................ 11 Ordering Guide .......................................................................... 17 Resistor String ............................................................................. 11 REVISION HISTORY 6/06—Revision 0: Initial Version Rev. 0 | Page 2 of 20 AD5680 SPECIFICATIONS VDD = 4.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREF = VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter STATIC PERFORMANCE 2 Resolution Relative Accuracy Differential Nonlinearity 3 Zero-Code Error Full-Scale Error Offset Error Gain Error Zero-Code Error Drift Gain Temperature Coefficient DC Power Supply Rejection Ratio OUTPUT CHARACTERISTICS3 Output Voltage Range Output Voltage Settling Time Min 18 ±32 2 −0.2 ±64 ±1 ±2 10 −1 ±10 ±1.5 ±2 ±2.5 −100 0 80 Slew Rate Capacitive Load Stability Output Noise Spectral Density 4 Output Noise (0.1 Hz to 10 Hz)4 Total Harmonic Distortion (THD)4 Digital-to-Analog Glitch Impulse Digital Feedthrough DC Output Impedance Short-Circuit Current4 REFERENCE INPUT Reference Current Reference Input Range 5 Reference Input Impedance LOGIC INPUTS Input Current VINL, Input Low Voltage VINH, Input High Voltage Pin Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode) VDD = 4.5 V to 5.5 V POWER EFFICIENCY IOUT/IDD B Grade Typ Max VDD 85 1.5 2 10 80 25 −80 5 0.2 0.5 30 40 0.75 85 V μs Measured in 50 Hz system bandwidth Measured in 300 Hz system bandwidth All 0s loaded to DAC register All 1s loaded to DAC register Of FSR/°C DAC code = midscale; VDD = 5 V ± 10% ¼ to ¾ scale change settling to ±8 LSB RL = 2 kΩ; 0 pF < CL < 200 pF ¼ to ¾ scale RL = ∞ RL = 2 kΩ DAC code = midscale, 10 kHz DAC code = midscale VREF = 2 V ± 300 mV p-p, f = 200 Hz 1 LSB change around major carry VDD = 5 V 75 VDD μA V kΩ VREF = VDD = 5 V ±2 0.8 μA V V pF All digital inputs VDD = 5 V VDD = 5 V 5.5 V 450 μA All digital inputs at 0 V or VDD DAC active and excluding load current VIH = VDD and VIL = GND % ILOAD = 2 mA, VDD = 5 V 2 3 325 Bits LSB LSB LSB mV % FSR mV % FSR μV/°C ppm dB V/μs nF nF nV/√Hz μV p-p dB nV-s nV-s Ω mA 125 4.5 Unit B Version 1 Conditions/Comments 1 Temperature range for B version is −40°C to +105°C, typical at +25°C. DC specifications tested with the outputs unloaded, unless otherwise stated. Linearity calculated using a reduced code range of 2048 to 260096. Guaranteed by design and characterization; not production tested. 4 Output unloaded. 5 Reference input range at ambient where maximum DNL specification is achievable. 2 3 Rev. 0 | Page 3 of 20 AD5680 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2. VDD = 4.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Limit at TMIN, TMAX VDD = 4.5 V to 5.5 V 33 13 13 13 5 4.5 0 33 13 0 Parameter t1 1 t2 t3 t4 t5 t6 t7 t8 t9 t10 Conditions/Comments SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time SYNC rising edge to SCLK fall ignore SCLK falling edge to SYNC fall ignore Maximum SCLK frequency is 30 MHz at VDD = 4.5 V to 5.5 V. t10 t1 t9 SCLK t8 t3 t4 t2 t7 SYNC t5 DIN DB23 t6 DB0 Figure 2. Serial Write Operation Rev. 0 | Page 4 of 20 05854-002 1 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min AD5680 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VDD to GND VOUT to GND VFB to GND VREF to GND Digital Input Voltage to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature (TJ max) Power Dissipation SOT-23 Package (4-Layer Board) θJA Thermal Impedance Reflow Soldering Peak Temperature Pb-free Rating −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. −40°C to +105°C −65°C to +150°C 150°C (TJ max − TA)/θJA 119°C/W 260°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 5 of 20 AD5680 PIN CONFIGURATION AND FUNCTION DESCRIPTION VREF 2 8 AD5680 GND DIN TOP VIEW VFB 3 (Not to Scale) 6 SCLK VOUT 4 7 5 SYNC 05854-003 VDD 1 Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 Mnemonic VDD VREF VFB VOUT SYNC 6 SCLK 7 DIN 8 GND Function Power Supply Input. The part can be operated from 4.5 V to 5.5 V. VDD should be decoupled to GND. Reference Voltage Input. Feedback Connection for the Output Amplifier. VFB should be connected to VOUT for normal operation. Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation. Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. Ground Reference Point (for all circuitry on the part). Rev. 0 | Page 6 of 20 AD5680 TYPICAL PERFORMANCE CHARACTERISTICS 40 0 VDD = VREF = 5V 32 TA = 25°C –0.02 24 –0.04 16 GAIN ERROR –0.06 8 ERROR (% FSR) INL ERROR (LSB) VDD = 5V 0 –8 –16 –0.08 –0.01 –0.12 –0.14 –24 0 40k 80k 120k 160k CODE 200k –0.18 –0.20 –40 240k Figure 4. Typical INL Plot 1.0 1.0 0.4 0.5 0.2 0 ERROR (mV) 20 40 60 TEMPERATURE (°C) 80 100 0 –0.2 –0.4 ZERO-SCALE ERROR –0.5 –1.0 –1.5 –0.6 05854-029 OFFSET ERROR –0.8 0 25k 50k –2.0 –2.5 –40 75k 100k 125k 150k 175k 200k 225k 250k CODE 05302-024 DNL ERROR (LSB) 0 1.5 0.6 –1.0 –20 Figure 7. Gain Error and Full-Scale Error vs. Temperature VDD = VREF = 5V TA = 25°C 0.8 05302-023 05854-028 –0.16 –32 –40 FULL-SCALE ERROR –20 0 80 20 40 60 TEMPERATURE (°C) 100 Figure 8. Zero-Scale Error and Offset Error vs. Temperature Figure 5. Typical DNL Plot in 50 Hz System Bandwidth 0.20 ±4 VDD = 4.5V TO 5.5V T = –40°C TO +105°C 0.15 DAC LOADED WITH ZERO SCALE – SINKING CURRENT VDD = VREF = 5V, 3V TA = 25°C ERROR VOLTAGE (V) 0.10 DNL (LSB) ±2 ±1 0.05 0 –0.05 –0.10 –0.15 0 300 50 SYSTEM BANDWIDTH (Hz) >300 05854-042 0 Figure 6. DNL Performance vs. System Bandwidth –0.25 –5 –4 –3 –2 –1 0 I (mA) 05854-014 DAC LOADED WITH FULL SCALE – SOURCING CURRENT –0.20 1 2 3 4 Figure 9. Headroom at Rails vs. Source and Sink Current Rev. 0 | Page 7 of 20 5 AD5680 450 VDD = VREF = 5V TA = 25°C 400 SCLK 1 350 DIN IDD (µA) 300 250 2 200 Δ: 1.52V Δ: 64.8µs @: 1.20V 150 VOUT 05854-015 100 50 3 0 4000 8000 12000 16000 20000 CH1 2.00V CH3 1.00V 05854-007 0 24000 CODE Figure 10. Supply Current vs. Code CH2 2.00V M 20.0µs CH4 1.30V Figure 13. Full-Scale Settling Time, 5 V 350 VDD = VREF = 5V 300 1 VDD IDD (µA) 250 200 2 VREF VOUT C3 MAX 284mV 150 VOUT C3 MIN –52mV 100 VOUT 50 –20 0 20 40 60 80 100 TEMPERATURE (°C) CH1 3.00V CH2 3.00V CH3 100mV 05854-006 0 –40 05854-016 3 CH1 2.40V Figure 14. Power-On Reset to 0 V Figure 11. Supply Current vs. Temperature 700 M 100µs TA = 25°C 600 VDD = 5V 1 500 VDD VREF VOUT C3 MAX 2.5V 300 VOUT C3 MIN –40mV 200 VOUT 100 0 1 2 3 4 VLOGIC (V) 5 Figure 12. Supply Current vs. Logic Input Voltage 05854-017 0 3 05854-004 IDD (µA) 2 400 CH1 3.00V CH2 3.00V CH3 500mV M 100µs CH1 Figure 15. Power-On Reset to Midscale Rev. 0 | Page 8 of 20 2.40V AD5680 2.502500 16 VDD = VREF = 5V TA = 25°C 13nS/SAMPLE NUMBER 1 LSB CHANGE AROUND MIDSCALE (0x20000 TO 0x1FFFF) GLITCH IMPULSE = 2.723nV.s 2.502250 2.502000 2.501750 2.501500 VREF = VDD TA = 25°C 14 VDD = 3V 12 2.501000 TIME (µs) AMPLITUDE 2.501250 2.500750 2.500500 2.500250 10 VDD = 5V 8 2.500000 2.499750 2.499500 05854-005 2.499000 2.498750 0 50 100 150 200 250 300 350 SAMPLE NUMBER 400 4 450 500 550 05854-027 6 2.499250 0 Figure 16. Digital-to-Analog Glitch Impulse (Negative) 2.5010 2.5006 2.5004 2 3 4 5 6 7 CAPACITANCE (nF) 8 9 10 Figure 19. Settling Time vs. Capacitive Load VDD = VREF = 5V TA = 25°C DAC LOADED WITH MIDSCALED DIGITAL FEEDTHROUGH = 0.201nV 2.5008 1 VDD = VREF = 5V TA = 25°C DAC LOADED WITH MIDSCALE 2.5000 5µV/DIV AMPLITUDE 2.5002 2.4998 2.4996 VREF 1 2.4994 2.4992 2.4988 2.4986 0 50 100 150 200 250 300 350 SAMPLES × 6.5ns 400 450 05854-019 05854-020 2.4990 500 5s/DIV Figure 20. 0.1 Hz to 10 Hz Output Noise Plot Figure 17. Digital Feedthrough –20 1000 VDD = 5V TA = 25°C FULLSCALE LOADED VREF = 2V ±300mV p-p –30 800 –40 NOISE (nV/√Hz) 700 –50 –60 –70 600 500 400 300 –80 –100 0 1 2 3 4 5 6 FREQUENCY (kHz) 7 8 9 10 Figure 18. Total Harmonic Distortion 05854-013 200 –90 05854-018 (dB) VDD = VREF = 5V TA = 25°C MIDSCALE LOADED 900 100 0 100 1k 10k FREQUENCY (Hz) 100k Figure 21. Noise Spectral Density Rev. 0 | Page 9 of 20 1M AD5680 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Figure 4 shows a typical INL vs. code plot. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. Figure 5 shows a typical DNL vs. code plot. Zero-Code Error Zero-code error is a measurement of the output error when zero code (0x00000) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in the AD5680 because the output of the DAC cannot go below 0 V. It is due to a combination of the offset errors in the DAC and the output amplifier. Zero-code error is expressed in mV. A plot of zero-code error vs. temperature can be seen in Figure 7. Full-Scale Error Full-scale error is a measurement of the output error when fullscale code (0x3FFFF) is loaded to the DAC register. Ideally, the output should be VDD − 1 LSB. Full-scale error is expressed in percent of full-scale range. Gain Error This is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal expressed as a percent of the full-scale range. Offset Error Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal) expressed in mV in the linear region of the transfer function. Offset error is measured on the AD5680 with Code 2048 loaded in the DAC register. It can be negative or positive. DC Power Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in dB. VREF is held at 2 V, and VDD is varied by ±10%. Output Voltage Settling Time This is the amount of time it takes for the output of a DAC to settle to a specified level for a ¼ to ¾ full-scale input change and is measured from the 24th falling edge of SCLK. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s, and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x1FFFF to 0x20000). See Figure 16. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-s and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. Total Harmonic Distortion (THD) Zero-Code Error Drift This is a measurement of the change in zero-code error with a change in temperature. It is expressed in μV/°C. Gain Temperature Coefficient This is a measurement of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC. The THD is a measurement of the harmonics present on the DAC output. It is measured in dB. Noise Spectral Density This is a measurement of the internally generated random noise. Random noise is characterized as a spectral density (voltage per √Hz). It is measured by loading the DAC to midscale and measuring noise at the output. It is measured in nV/√Hz. Figure 21 shows a plot of noise spectral density. Rev. 0 | Page 10 of 20 AD5680 THEORY OF OPERATION DAC SECTION OUTPUT AMPLIFIER The AD5680 DAC is fabricated on a CMOS process. The architecture consists of a string DAC followed by an output buffer amplifier. Figure 22 shows a block diagram of the DAC architecture. The output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. This output buffer amplifier has a gain of 2 derived from a 50 kΩ resistor divider network in the feedback path. The output amplifier’s inverting input is available to the user, allowing for remote sensing. This VFB pin must be connected to VOUT for normal operation. It can drive a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in Figure 9. The slew rate is 1.5 V/μs with a ¼ to ¾ fullscale settling time of 10 μs. VDD R REF (+) RESISTOR STRING VOUT REF (–) OUTPUT AMPLIFIER GND 05854-030 DAC REGISTER VFB R Figure 22. DAC Architecture Because the input coding to the DAC is straight binary, the ideal output voltage is given by D ⎞ VOUT = VREF × ⎛⎜ ⎟ ⎝ 262144 ⎠ where D is the decimal equivalent of the binary code that is loaded to the DAC register. It can range from 0 to 262143. RESISTOR STRING The resistor string section is shown in Figure 23. It is simply a string of resistors, each of value R. The code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. R R R TO OUTPUT AMPLIFIER INTERPOLATOR ARCHITECTURE The AD5680 contains a 16-bit DAC with an internal clock generator and interpolator. The voltage levels generated by the 16-bit, 1 LSB step can be subdivided using the interpolator to increase the resolution to 18 bits. The 18-bit input code can be divided into two segments: 16-bit DAC code (DB19 to DB4) and 2-bit interpolator code (DB3 and DB2). The input to the DAC is switched between a 16-bit code (for example, Code 1023) and a 16-bit code + 1 LSB (for example, Code 1024). The 2-bit interpolator code determines the duty cycle of the switching and hence the 18-bit code level. See Table 5 for an example. Table 5. 18-Bit Code DB19 to DB2 4092 4093 4094 4095 4096 16-Bit DAC Code DB19 to DB4 1023 1023 1023 1023 1024 2-Bit Interpolator Code DB3 DB2 0 0 0 1 1 0 1 1 0 0 Duty Cycle 0 25% 50% 75% 0 The DAC output voltage is given by the average value of the waveform switching between 16-bit code (C) and 16-bit code + 1 (C + 1). The output voltage is a function of the duty cycle of the switching. FILTER 18 PLANT C 16 C + 1 MUX 16 +1 R 2 R INTERPOLATOR DAC VOUT C+1 C C+1 C C+1 C 05854-031 CLK Figure 24. Interpolation Architecture Figure 23. Resistor String Rev. 0 | Page 11 of 20 75% DUTY CYCLE 50% DUTY CYCLE 25% DUTY CYCLE 05854-032 18-BIT INPUT CODE AD5680 SERIAL INTERFACE INPUT SHIFT REGISTER The AD5680 has a 3-wire serial interface (SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and MICROWIRE interface standards as well as with most DSPs. See Figure 2 for a timing diagram of a typical write sequence. The input shift register is 24 bits wide (see Figure 25). The first four bits are don’t care bits. The next 18 bits are the data bits followed by two don’t care bits. These are transferred to the DAC register on the 24th falling edge of SCLK. The write sequence begins by bringing the SYNC line low. Data from the DIN line is clocked into the 24-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the AD5680 compatible with high speed DSPs. On the 24th falling clock edge, the last data bit is clocked in and the programmed function is executed, that is, a change in DAC register contents occurs. At this stage, the SYNC line can be kept low or be brought high. In either case, it must be brought high for a minimum of 33 ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. Because the SYNC buffer draws more current when VIN = 2 V than it does when VIN = 0.8 V, SYNC should be idled low between write sequences for even lower power operation. As mentioned previously it must, however, be brought high again just before the next write sequence. SYNC INTERRUPT In a normal write sequence, the SYNC line is kept low for at least 24 falling edges of SCLK, and the DAC is updated on the 24th falling edge. However, if SYNC is brought high before the 24th falling edge, this acts as an interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents nor a change in the operating mode occurs (see Figure 26). POWER-ON RESET The AD5680 family contains a power-on reset circuit that controls the output voltage during power-up. The AD5680-1 DAC output powers up to 0 V, and the AD5680-2 DAC output powers up to midscale. The output remains there until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the output state of the DAC while it is in the process of powering up. DB23 (MSB) X X D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X 05854-033 X DATA BITS Figure 25. Input Register Contents SCLK SYNC DIN DB23 DB0 DB23 DB0 VALID WRITE SEQUENCE, OUTPUT UPDATES ON THE 24TH FALLING EDGE INVALID WRITE SEQUENCE: SYNC HIGH BEFORE 24TH FALLING EDGE Figure 26. SYNC Interrupt Facility Rev. 0 | Page 12 of 20 05854-034 X DB0 (LSB) AD5680 MICROPROCESSOR INTERFACING AD5680 to Blackfin® ADSP-BF53x Interface AD5680 to 80C51/80L51 Interface Figure 27 shows a serial interface between the AD5680 and the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x processor family incorporates two dual-channel synchronous serial ports, SPORT1 and SPORT0, for serial and multiprocessor communications. Using SPORT0 to connect to the AD5680, the setup for the interface is as follows. DT0PRI drives the DIN pin of the AD5680, while TSCLK0 drives the SCLK of the part. The SYNC is driven from TFS0. Figure 29 shows a serial interface between the AD5680 and the 80C51/80L51 microcontroller. The setup for the interface is as follows. TxD of the 80C51/80L51 drives SCLK of the AD5680, while RxD drives the serial data line of the part. The SYNC signal is again derived from a bit-programmable pin on the port. In this case, port line P3.3 is used. When data is to be transmitted to the AD5680, P3.3 is taken low. The 80C51/80L51 transmits data in 8-bit bytes only; thus only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/80L51 outputs the serial data in a format that has the LSB first. The AD5680 must receive data with the MSB first. The 80C51/80L51 transmit routine should take this into account. TFS0 AD5680* SYNC DTOPRI DIN TSCLK0 SCLK 05854-035 ADSP-BF53x* *ADDITIONAL PINS OMITTED FOR CLARITY 80C51/80L51* AD5680* AD5680 to 68HC11/68L11 Interface The SYNC signal is derived from a port line (PC7). The setup conditions for correct operation of this interface are as follows. The 68HC11/68L11 is configured with its CPOL bit as 0 and its CPHA bit as 1. When data is being transmitted to the DAC, the SYNC line is taken low (PC7). When the 68HC11/68L11 is configured this way, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data to the AD5680, PC7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the DAC; PC7 is taken high at the end of this procedure. PC7 SYNC SCLK MOSI DIN DIN Figure 29. AD5680 to 80C51/80L51 Interface AD5680 to MICROWIRE Interface Figure 30 shows an interface between the AD5680 and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock and is clocked into the AD5680 on the rising edge of the SK. MICROWIRE* AD5680* CS SYNC SK SCLK SO DIN *ADDITIONAL PINS OMITTED FOR CLARITY AD5680* SCK SCLK RxD *ADDITIONAL PINS OMITTED FOR CLARITY Figure 30. AD5680 to MICROWIRE Interface 05854-036 68HC11/68L11* SYNC TxD *ADDITIONAL PINS OMITTED FOR CLARITY Figure 28. AD5680 to 68HC11/68L11 Interface Rev. 0 | Page 13 of 20 05854-038 Figure 28 shows a serial interface between the AD5680 and the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 drives the SCLK of the AD5680, while the MOSI output drives the serial data line of the DAC. P3.3 05854-037 Figure 27. AD5680 to Blackfin ADSP-BF53x Interface AD5680 APPLICATIONS CLOSED-LOOP APPLICATIONS The AD5680 is suitable for closed-loop low bandwidth applications. Ideally, the system bandwidth acts as a filter on the DAC output. (See the Filter section for details of the DAC output prefiltering and postfiltering.) The DAC updates at the interpolation frequency of 10 kHz. Δ: 2.09ms @: 1.28ms 2 PLANT CONTROLLER DAC ADC CODE 4094 05854-025 05854-039 CODE 4092 1 CH1 20.0µV CH2 5V M 500µs CH2 1.4V Figure 33. DAC Output with 50 Hz Filter on Output Figure 31. Typical Closed-Loop Application FILTER Δ: 2.09ms @: 1.28ms 2 1 CODE 4092 CODE 4094 05854-026 The DAC output voltage for code transition 4092 to 4094 can be seen in Figure 32. This is the DAC output unfiltered. Code 4092 does not have any interpolation but code 4094 has interpolation with a 50% duty cycle. See Table 5. Figure 33 shows the DAC output with a 50 Hz passive RC filter and Figure 34 shows the output with a 300 Hz passive RC filter. An RC combination of 320 kΩ and 10 nF has been used to achieve the 50 Hz cutoff frequency, and an RC combination of 81 kΩ and 10 nF has been used to achieve the 300 Hz cutoff frequency. CH1 20.0µV CH2 5V M 500µs CH2 1.4V Figure 34. DAC Output with 300 Hz Filter on Output CODE 4092 05854-024 CODE 4094 1 CH1 20.0µV M 500µs CH4 0V Figure 32. DAC Output Unfiltered Rev. 0 | Page 14 of 20 AD5680 CHOOSING A REFERENCE FOR THE AD5680 To achieve the optimum performance from the AD5680, choose a precision voltage reference carefully. The AD5680 has only one reference input, VREF. The voltage on the reference input is used to supply the positive input to the DAC. Therefore any error in the reference is reflected in the DAC. When choosing a voltage reference for high accuracy applications, the sources of error are initial accuracy, ppm drift, longterm drift, and output voltage noise. Initial accuracy on the output voltage of the DAC leads to a full-scale error in the DAC. To minimize these errors, a reference with high initial accuracy is preferred. Also, choosing a reference with an output trim adjustment, such as the ADR425, allows a system designer to trim out system errors by setting a reference voltage to a voltage other than the nominal. The trim adjustment can also be used at temperature to trim out any error. Long-term drift is a measurement of how much the reference drifts over time. A reference with a tight long-term drift specification ensures that the overall solution remains relatively stable during its entire lifetime. The temperature coefficient of a reference’s output voltage affects INL, DNL, and TUE. A reference with a tight temperature coefficient specification should be chosen to reduce temperature dependence of the DAC output voltage in ambient conditions. In high accuracy applications, which have a relatively low noise budget, reference output voltage noise needs to be considered. It is important to choose a reference with as low an output noise voltage as practical for the system noise resolution required. Precision voltage references such as the ADR425 produce low output noise in the 0.1 Hz to 10 Hz range. Examples of recommended precision references for use as supply to the AD5680 are shown in the Table 6. Table 6. Partial List of Precision References for Use with the AD5680 Part No. ADR425 ADR395 REF195 Initial Accuracy (mV max) ±2 ±6 ±2 Temp. Drift (ppmoC max) 3 25 5 Rev. 0 | Page 15 of 20 0.1 Hz to 10 Hz Noise (μV p-p typ) 3.4 5 50 VOUT (V) 5 5 5 AD5680 5V REGULATOR USING A REFERENCE AS A POWER SUPPLY FOR THE AD5680 VDD SCLK 15V 5V 250µA VDD VREF AD5680 VOUT = 0V TO 5V DIN 05854-040 SCLK SCLK AD5680 SDI V1B VOB SYNC DATA V1C VOC DIN VOUT GND Figure 36. AD5680 with a Galvanically Isolated Interface The load regulation of the REF195 is typically 2 ppm/mA, which results in a 2.7 ppm (13.5 μV) error for the 1.33 mA current drawn from it. This corresponds to a 0.177 LSB error. SYNC VOA V1A ADuM1300 325 μA + (5 V/5 kΩ) = 1.33 mA 3-WIRE SERIAL INTERFACE 0.1µF 05854-041 Because the supply current required by the AD5680 is extremely low, an alternative option is to use a voltage reference to supply the required voltage to the part (see Figure 35). This is especially useful if the power supply is quite noisy, or if the system supply voltages are at some value other than 5 V, for example, 15 V. The voltage reference outputs a steady supply voltage for the AD5680; see Table 6 for a suitable reference. If the low dropout REF195 is used, it must supply 325 μA of current to the AD5680, with no load on the output of the DAC. When the DAC output is loaded, the REF195 also needs to supply the current to the load. The total current required (with a 5 kΩ load on the DAC output) is REF195 10µF POWER Figure 35. REF195 as Power Supply to the AD5680 USING THE AD5680 WITH A GALVANICALLY ISOLATED INTERFACE In process-control applications in industrial environments, it is often necessary to use a galvanically isolated interface to protect and isolate the controlling circuitry from any hazardous common-mode voltages that might occur in the area where the DAC is functioning. Isocouplers provide isolation in excess of 3 kV. The AD5680 uses a 3-wire serial logic interface, so the ADuM130x 3-channel digital isolator provides the required isolation (see Figure 36). The power supply to the part also needs to be isolated, which is done by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V supply required for the AD5680. POWER SUPPLY BYPASSING AND GROUNDING When accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. The printed circuit board containing the AD5680 should have separate analog and digital sections, each having its own area of the board. If the AD5680 is in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5680. The power supply to the AD5680 should be bypassed with 10 μF and 0.1 μF capacitors. The capacitors should be located as close as possible to the device, with the 0.1 μF capacitor ideally right up against the device. The 10 μF capacitors are the tantalum bead type. It is important that the 0.1 μF capacitor has low effective series resistance (ESR) and effective series inductance (ESI), for example, common ceramic types of capacitors. This 0.1 μF capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. The power supply line itself should have as large a trace as possible to provide a low impedance path and to reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects on the board. The best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board. Rev. 0 | Page 16 of 20 AD5680 OUTLINE DIMENSIONS 2.90 BSC 8 7 6 5 1 2 3 4 1.60 BSC 2.80 BSC PIN 1 INDICATOR 0.65 BSC 1.95 BSC 1.30 1.15 0.90 1.45 MAX 0.15 MAX 0.38 0.22 0.22 0.08 0.60 0.45 0.30 8° 4° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-178-BA Figure 37. 8-Lead Small Outline Transistor Package [SOT-23] (RJ-8) Dimensions shown in millimeters ORDERING GUIDE Model AD5680BRJZ-1500RL7 1 AD5680BRJZ-1REEL71 AD5680BRJZ-2500RL71 AD5680BRJZ-2REEL71 EVAL-AD5680EB 1 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 8-lead SOT-23 8-lead SOT-23 8-lead SOT-23 8-lead SOT-23 Evaluation Board Package Option RJ-8 RJ-8 RJ-8 RJ-8 Z = Pb-free part. Rev. 0 | Page 17 of 20 Branding D3C D3C D3D D3D Power-On Reset to Code Zero Zero Midscale Midscale Accuracy ±64 LSB INL ±64 LSB INL ±64 LSB INL ±64 LSB INL AD5680 NOTES Rev. 0 | Page 18 of 20 AD5680 NOTES Rev. 0 | Page 19 of 20 AD5680 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05854–0–6/06(0) T T Rev. 0 | Page 20 of 20