Pin-Programmable, Ultralow Noise, 24-Bit, Sigma-Delta ADC for Bridge Sensors AD7191 FEATURES GENERAL DESCRIPTION Pin-programmable output rate Output data rate: 10 Hz, 50 Hz, 60 Hz, 120 Hz Pin-programmable PGA Gain: 1, 8, 64, 128 Pin-programmable power-down and reset RMS noise: 15 nV @ 10 Hz (gain = 128) Up to 21.5 noise free bits (gain = 1) Internal or external clock Bridge power-down switch Offset drift: 5 nV/°C Gain drift: 1 ppm/°C Specified drift over time Simultaneous 50 Hz/60 Hz rejection Internal temperature sensor Power supply: 3 V to 5.25 V Current: 4.35 mA Temperature range: –40°C to +105°C Package: 24-lead TSSOP The AD7191 is a low noise, complete analog front end for high precision measurement applications. It contains a low noise, 24-bit sigma-delta (Σ-Δ) ADC. The on-chip low noise gain stage means that signals of small amplitude can be interfaced directly to the ADC. It contains two differential analog inputs. The part also includes a temperature sensor that can be used for temperature compensation. For ease-of-use, all the features of the AD7191 are controlled by dedicated pins. The on-chip PGA has a gain of 1, 8, 64, or 128, supporting a full-scale differential input of ±5 V, ±625 mV, ±78 mV, or ±39 mV. The output data rate can be programmed to 10 Hz, 50 Hz, 60 Hz, or 120 Hz. Simultaneous 50 Hz and 60 Hz rejection is obtained when the output data rate is set to 10 Hz or 50 Hz; 60 Hz only rejection is obtained when the output data rate is set to 60 Hz. The AD7191 can be operated with the internal clock, or an external clock can be used. The part operates with a power supply of 3 V to 5.25 V. It consumes a current of 4.35 mA. It is available in a 24-lead TSSOP package. INTERFACE 2-wire serial SPI, QSPI™, and MICROWIRE™ compatible Schmitt trigger on SCLK APPLICATIONS Weigh scales Strain gauge transducers Pressure measurement Medical and scientific instrumentation FUNCTIONAL BLOCK DIAGRAM AVDD AGND DVDD DGND REFIN(+) REFIN(–) AD7191 DOUT/RDY AIN1 AIN2 AIN3 MUX Σ-Δ ADC PGA AIN4 SERIAL INTERFACE AND CONTROL LOGIC SCLK PDOWN CHAN CLKSEL TEMPERATURE SENSOR PGA2 CLOCK CIRCUITRY MCLK1 PGA1 MCLK2 ODR2 ODR1 TEMP 08163-001 BPDSW Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. AD7191 TABLE OF CONTENTS Features .............................................................................................. 1 Gain .............................................................................................. 15 Interface ............................................................................................. 1 Analog Input Channels.............................................................. 15 Applications ....................................................................................... 1 Temperature Sensor ................................................................... 16 General Description ......................................................................... 1 Power-Down (PDOWN) ........................................................... 16 Functional Block Diagram .............................................................. 1 Clock ............................................................................................ 16 Revision History ............................................................................... 2 Bipolar Configuration................................................................ 16 Specifications..................................................................................... 3 Data Output Coding .................................................................. 16 Timing Characteristics ................................................................ 6 Bridge Power-Down Switch ...................................................... 16 Timing Diagram ........................................................................... 6 Reference ..................................................................................... 16 Absolute Maximum Ratings............................................................ 7 Digital Interface .......................................................................... 17 ESD Caution .................................................................................. 7 Grounding and Layout .............................................................. 17 Pin Configuration and Function Descriptions ............................. 8 Applications Information .............................................................. 19 Typical Performance Characteristics ........................................... 10 Weigh Scales ................................................................................ 19 RMS Noise and Resolution Specifications .................................. 13 EMI Recommendations............................................................. 19 ADC Circuit Information .............................................................. 14 Outline Dimensions ....................................................................... 20 Overview...................................................................................... 14 Ordering Guide .......................................................................... 20 Filter, Data Rate, and Settling Time ......................................... 14 REVISION HISTORY 5/09—Rev. 0 to Rev A Changes to Gain Error Specification, Normal Mode Rejection Specification..................................................................... 3 Changes to Table 3 ............................................................................ 7 5/09—Revision 0: Initial Version Rev. A | Page 2 of 20 AD7191 SPECIFICATIONS AVDD = 3 V to 5.25 V; DVDD = 2.7 V to 5.25 V; AGND = DGND = 0 V; REFIN(+) = AVDD; REFIN(−) = AGND; MCLK = 4.92 MHz; all specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter 1 Output Data Rate No Missing Codes 2 Resolution AD7191B 10, 50, 60, 120 24 Unit Hz nom Bits min See the RMS Noise and Resolution Specifications section See the RMS Noise and Resolution Specifications section RMS Noise and Update Rates Integral Nonlinearity Gain = 12 Gain > 1 Offset Error Offset Error Drift vs. Temperature Offset Error Drift vs. Time Gain Error Gain Drift vs. Temperature Gain Drift vs. Time Power Supply Rejection Normal Mode Rejection2 Internal Clock @ 50 Hz, 60 Hz @ 60 Hz External Clock @ 50 Hz, 60 Hz @ 60 Hz Common-Mode Rejection @ DC2 @ DC @ 50 Hz, 60 Hz2 @ 50 Hz, 60 Hz2 ANALOG INPUTS Differential Input Voltage Ranges Test Conditions/Comments ±10 ±15 ±5 ±12 ±150/gain ±150/gain ±5 25 ±0.4 ±1 10 90 95 ppm of FSR max ppm of FSR max ppm of FSR typ ppm of FSR typ μV typ nV/°C typ nV/°C typ nV/1000 hours typ % typ ppm/°C typ ppm/1000 hours typ dB typ dB min Gain = 1 Gain = 1, AIN = 1 V 110 dB typical, gain > 1, AIN = 1 V/gain 100 74 97 dB min dB min dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz 50 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz 60 Hz output data rate, 60 ± 1 Hz. 120 82 120 dB min dB min dB min 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 50 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. 60 Hz output data rate, 60 ± 1 Hz 100 110 120 120 dB min dB min dB min dB min Gain = 1, AIN = 1 V Gain > 1, AIN = 1 V/gain 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz 50 ± 1 Hz (50 Hz output data rate), 60 ± 1 Hz (60 Hz output data rate) ±VREF/gain ±(AVDD – 1.25 V)/gain V nom V min/V max VREF = REFIN(+) − REFIN(−), gain = 1, 8, 64, or 128 Gain > 1 AGND + 250 mV AVDD − 250 mV V min V max Absolute AIN Voltage Limits2 Rev. A | Page 3 of 20 ±2 ppm typical, AVDD = 5 V ±2 ppm typical., AVDD = 3 V AVDD = 5 V AVDD = 3 V Gain = 1 or 8 Gain = 64 or 128 Gain = 64 or 128 AD7191 Parameter 1 Analog Input Current Input Current2 Input Current Drift REFERENCE INPUT REFIN Voltage Reference Voltage Range2 Absolute REFIN Voltage Limits2 Average Reference Input Current Average Reference Input Current Drift Normal-Mode Rejection2 Common-Mode Rejection TEMPERATURE SENSOR Accuracy Sensitivity BRIDGE POWER-DOWN SWITCH RON Allowable Current2 INTERNAL/EXTERNAL CLOCK Internal Clock Frequency Duty Cycle External Clock/Crystal Frequency Input Low Voltage, VINL Input High Voltage, VINH Input Current LOGIC INPUTS Input High Voltage, VINH2 Input Low Voltage, VINL2 Hysteresis2 Input Currents LOGIC OUTPUT (DOUT/RDY) Output High Voltage, VOH 2 Output Low Voltage, VOL2 Output High Voltage, VOH2 Output Low Voltage, VOL2 AD7191B Unit Test Conditions/Comments ±2 ±3 ±5 nA max nA max pA/°C typ Gain = 1 Gain > 1 AVDD 1 AVDD V nom V min V max REFIN = REFIN(+) − REFIN(−). AGND – 50 mV AVDD + 50 mV 4.5 ±0.03 V min V max μA/V typ nA/V/°C typ External clock. ±1.3 Same as for analog inputs 100 nA/V/°C typ Internal clock. +2 2815 °C typ Codes/°C typ 10 30 Ω max mA max 4.92 + 4% 50:50 MHz min/MHz max % typ 4.9152 2.4576/5.12 0.8 0.4 2.5 3.5 ±10 MHz nom MHz min/MHz max V max V max V min V min μA max DVDD = 5 V. DVDD = 3 V. DVDD = 3 V. DVDD = 5 V. MCLKIN = DVDD or DGND. 2 0.8 0.1/0.25 ±10 V min V max V min/V max μA max VIN = DVDD or DGND. DVDD − 0.6 0.4 4 0.4 V min V max V min V max DVDD = 3 V, ISOURCE = 100 μA. DVDD = 3 V, ISINK = 100 μA. DVDD = 5 V, ISOURCE = 200 μA. DVDD = 5 V, ISINK = 1.6 mA. The differential input must be limited to ±(AVDD − 1.25 V)/gain when gain > 1. dB typ Rev. A | Page 4 of 20 Applies after user calibration at one temperature. Continuous current. AD7191 Parameter 1 Floating-State Leakage Current Floating-State Output Capacitance Data Output Coding POWER REQUIREMENTS 3 Power Supply Voltage AVDD − AGND DVDD − DGND Power Supply Currents AIDD Current DIDD Current IDD (Power-Down Mode) AD7191B ±10 10 Offset binary Unit μA max pF typ 3/5.25 2.7/5.25 V min/V max V min/V max 0.85 3.6 5 0.4 0.6 1.5 3 mA max mA max mA max mA max mA max mA typ μA max 1 Temperature range: −40°C to +105°C. Specification is not production tested but is supported by characterization data at initial product release. 3 Digital inputs equal to DVDD or DGND. 2 Rev. A | Page 5 of 20 Test Conditions/Comments 0.75 mA typical, gain = 1. 3 mA typical, gain = 8. 4 mA typical, gain = 64 or 128. 0.35 mA typical, DVDD = 3 V. 0.5 mA typical, DVDD = 5 V. External crystal used. AD7191 TIMING CHARACTERISTICS AVDD = 3 V to 5.25 V; DVDD = 2.7 V to 5.25 V; AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted. Table 2. Parameter 1, 2 t3 t4 Read Operation t1 t2 3 t5 5, 6 t6 t7 Limit at TMIN, TMAX (B Version) 100 100 Unit ns min ns min Conditions/Comments SCLK high pulse width SCLK low pulse width 0 60 80 0 60 80 10 80 0 10 ns min ns max ns max ns min ns max ns max ns min ns max ns min ns min PDOWN falling edge to DOUT/RDY active time DVDD = 4.75 V to 5.25 V DVDD = 2.7 V to 3.6 V SCLK active edge to data valid delay 4 DVDD = 4.75 V to 5.25 V DVDD = 2.7 V to 3.6 V Bus relinquish time after PDOWN inactive edge SCLK inactive edge to PDOWN inactive edge SCLK inactive edge to DOUT/RDY high 1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. See Figure 3. 3 These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. 4 The SCLK active edge is the falling edge of SCLK. 5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. 6 RDY returns high after a read of the ADC. The digital word can be read only once. 2 ISINK (1.6mA WITH DVDD = 5V, 100µA WITH DVDD = 3V) TO OUTPUT PIN 1.6V ISOURCE (200µA WITH DVDD = 5V, 100µA WITH DVDD = 3V) 08163-002 50pF Figure 2. Load Circuit for Timing Characterization TIMING DIAGRAM PDOWN (I) t1 t6 t5 DOUT/RDY (O) t2 t7 t3 t4 NOTES 1. I = INPUT, O = OUTPUT Figure 3. Read Cycle Timing Diagram Rev. A | Page 6 of 20 08163-003 SCLK (I) AD7191 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to AGND DVDD to DGND AGND to DGND Analog Input Voltage to AGND Reference Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND AIN/Digital Input Current Operating Temperature Range Rating −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to DVDD + 0.3 V −0.3 V to DVDD + 0.3 V 10 mA −40°C to +105°C Storage Temperature Range Maximum Junction Temperature TSSOP θJA Thermal Impedance θJC Thermal Impedance Lead Temperature, Soldering Reflow −65°C to +150°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 128°C/W 42°C/W 260°C Rev. A | Page 7 of 20 AD7191 MCLK1 1 24 ODR2 MCLK2 2 23 DOUT/RDY SCLK 3 22 ODR1 PDOWN 4 AD7191 21 DVDD CLKSEL 5 TOP VIEW (Not to Scale) 20 AVDD PGA2 6 19 DGND PGA1 7 18 AGND CHAN 8 17 BPDSW TEMP 9 16 REFIN(–) NC 10 15 REFIN(+) AIN1 11 14 AIN4 AIN2 12 13 AIN3 NC = NO CONNECT 08163-004 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic MCLK1 2 MCLK2 3 SCLK 4 PDOWN 5 CLKSEL 6 7 8 PGA2 PGA1 CHAN 9 TEMP 10 11 12 13 14 15 NC AIN1 AIN2 AIN3 AIN4 REFIN(+) 16 17 REFIN(−) BPDSW 18 19 AGND DGND Description When the master clock for the device is provided externally by a crystal, the crystal is connected between MCLK1 and MCLK2. Alternatively, the MCLK1 pin can be driven with a CMOS-compatible clock and MCLK2 left unconnected. When the master clock for the device is provided externally by a crystal, the crystal is connected between MCLK1 and MCLK2. Serial Clock Input. This serial clock input is for controlling data transfers from the ADC. The SCLK has a Schmitt-triggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information transmitted to or from the ADC in smaller batches of data. Power-Down Pin, Digital Input. The PDOWN pin functions as a power-down pin and a reset pin. When PDOWN is taken high, the AD7191 is powered down and the DOUT/RDY pin is tristated. The circuitry and serial interface are also reset. This resets the logic, the digital filter, and the analog modulator. PDOWN must be held high for 100 ns minimum to initiate the reset function. Clock Select, Digital Input Pin. This pin selects the clock source to be used by the AD7191. When CLKSEL is tied low, the external clock/crystal is used as the clock source. When CLKSEL is tied high, the internal 4.92 MHz clock is used as the clock source to the AD7191. Gain Select, Digital Input Pin. This pin is used in conjunction with PGA1 to set the gain. See Table 7. Gain Select, Digital Input Pin. This pin is used in conjunction with PGA2 to set the gain. See Table 7. Channel Select, Digital Input Pin. This pin is used to select the channel. When CHAN is tied low, channel AIN1/AIN2 is selected. When CHAN is tied high, channel AIN3/AIN4 is selected. Temperature Sensor Select, Digital Input Pin. The internal temperature sensor is selected when TEMP is tied high. When TEMP is tied low, the analog input channel AIN1/AIN2 or AIN3/AIN4 is the selected channel (as determined by the CHAN pin). No Connect. This pin should be tied to AGND. Analog Input. AIN1 is the positive input of the fully differential input pair AIN1/AIN2. Analog Input. AIN2 is the negative input of the fully differential input pair AIN1/AIN2. Analog Input. AIN3 is the positive input of the fully differential input pair AIN3/AIN4. Analog Input. AIN4 is the negative input of the fully differential input pair AIN3/AIN4. Positive Reference Input. An external reference can be applied between REFIN(+) and REFIN(−). REFIN(+) can lie anywhere between AVDD and AGND + 1 V. The nominal reference voltage, (REFIN(+) − REFIN(−)), is AVDD, but the part functions with a reference from 1 V to AVDD. Negative Reference Input. This reference input can lie anywhere between AGND and AVDD − 1 V. Bridge Power-Down Switch to AGND. When PDOWN is low, the bridge power-down switch is closed. When PDOWN is high, the bridge power-down switch is opened. Analog Ground Reference Point. Digital Ground Reference Point. Rev. A | Page 8 of 20 AD7191 Pin No. 20 Mnemonic AVDD 21 DVDD 22 23 ODR1 DOUT/RDY 24 ODR2 Description Analog Supply Voltage, 3 V to 5.25 V. AVDD is independent of DVDD. Therefore, DVDD can be operated at 3 V with AVDD at 5 V or vice versa. Digital Supply Voltage, 2.7 V to 5.25 V. DVDD is independent of AVDD. Therefore, AVDD can be operated at 3 V with DVDD at 5 V or vice versa. Output Data Rate, Digital Input Pin. This pin is used with ODR2 to select the output data rate. See Table 5. Serial Data Output/Data Ready Output. DOUT/RDYserves a dual purpose. It functions as a serial data output pin to access the data conversions from the ADC. In addition, DOUT/RDYoperates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The serial interface is reset each time that a conversion is available. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. Data is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. Output Data Rate, Digital Input Pin. This pin is used with ODR1 to select the output data rate. See Table 5. Rev. A | Page 9 of 20 AD7191 TYPICAL PERFORMANCE CHARACTERISTICS 8,388,295 8,388,330 8,388,320 8,388,290 8,388,310 8,388,300 CODE CODE 8,388,285 8,388,290 8,388,280 8,388,280 8,388,270 8,388,260 8,388,275 0 200 400 600 SAMPLE 800 1000 8,388,240 0 Figure 5. Noise (VREF = AVDD, Output Data Rate = 10 Hz, Gain = 128) 200 400 600 SAMPLE 800 1000 Figure 7. Noise (VREF = AVDD, Output Data Rate = 120 Hz, Gain = 128) 150 50 OCCURRENCE 100 50 30 20 10 0 Figure 8. Noise Distribution Histogram (VREF = AVDD, Output Data Rate = 120 Hz, Gain = 128) Figure 6. Noise Distribution Histogram (VREF = AVDD, Output Data Rate = 10 Hz, Gain = 128) Rev. A | Page 10 of 20 8,388,340 8,388,320 8,388,300 8,388,280 8,388,260 8,388,240 CODE 08163-008 CODE 08163-006 8,388,295 8,388,291 8,388,287 8,388,283 8,388,279 0 8,388,275 OCCURRENCE 40 08163-007 8,388,270 08163-005 8,388,250 AD7191 5 8,388,825 4 8,388,820 3 INL (PPM OF FSR) 8,388,810 8,388,805 8,388,800 2 1 0 200 400 600 SAMPLE 800 1000 –2 –4 08163-009 0 –3 Figure 9. Noise (VREF = AVDD, Output Data Rate = 120 Hz, Gain = 1) –2 –1 0 VIN (V) 1 2 3 4 08163-111 –1 8,388,795 Figure 11. INL (Gain = 1) 150 20 15 INL (PPM OF FSR) 10 100 50 5 0 –5 –10 –20 –0.03 08163-010 CODE 8,388,825 8,388,820 8,388,815 8,388,810 8,388,805 0 –0.02 –0.01 0 0.01 VIN (V) Figure 12. INL (Gain = 128) Figure 10. Noise Distribution Histogram (VREF = AVDD, Output Data Rate = 120 Hz, Gain = 1) Rev. A | Page 11 of 20 0.02 0.03 08163-112 –15 8,388,800 OCCURRENCE CODE 8,388,815 AD7191 1.000008 170 1.000006 168 1.000004 166 1.000000 GAIN OFFSET (µV) 1.000002 164 162 0.999998 0.999996 160 0.999994 158 0.999992 156 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 0.999988 –60 –40 Figure 13. Offset Error (Gain = 1) –20 0 20 40 60 TEMPERATURE (°C) 80 100 120 08163-116 0.999990 08163-114 154 –60 Figure 15. Gain Error (Gain = 1) 0.4 128.004 0.2 128.002 0 128.000 127.998 GAIN –0.4 –0.6 127.996 –1.0 127.992 –1.2 127.990 –1.4 –60 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 120 127.988 –60 –40 –20 0 20 40 60 TEMPERATURE (°C) Figure 16. Gain Error (Gain = 128) Figure 14. Offset Error (Gain = 128) Rev. A | Page 12 of 20 80 100 120 08163-117 127.994 –0.8 08163-115 OFFSET (µV) –0.2 AD7191 RMS NOISE AND RESOLUTION SPECIFICATIONS Table 5 shows the rms noise of the AD7191 for the four output data rates and four gains. The numbers given are for an external 5 V reference. These numbers are typical and are generated with a differential input voltage of 0 V. Table 6 shows the effective resolution; the output peak-to-peak (p-p) resolution is listed in brackets. It is important to note that the effective resolution is calculated using the rms noise, whereas the p-p resolution is calculated based on peak-to-peak noise. The p-p resolution represents the resolution for which there is no code flicker. These numbers are typical and are rounded to the nearest half-LSB. The effective resolution (ENOB) is defined as ENOB = log2 (Full-Scale Range/rms Noise) The noise-free bits or p-p resolution is defined as p-p Resolution = log2 (Full-Scale Range/p-p Noise) where Full-Scale Range = 2 × VREF/Gain. Table 5. RMS Noise (nV) vs. Gain and Output Data Rate Using a 5 V Reference ODR2, ODR1 11 10 01 00 Output Data Rate (Hz) 10 50 60 120 Settling Time (ms) 400 80 66.7 33.3 Gain of 1 490 2000 2100 2400 Gain of 8 85 260 273 315 Gain of 64 17 46 48 64 Gain of 128 15 34 38 51 Gain of 64 23 (20.5) 21.5 (19) 21.5 (19) 21 (18.5) Gain of 128 22 (19.5) 20.5 (18) 20.5 (18) 20 (17.5) Table 6. Typical Resolution (Bits) vs. Gain and Output Update Rate Using a 5 V Reference ODR2, ODR1 11 10 01 00 Output Data Rate (Hz) 10 50 60 120 Settling Time (ms) 400 80 66.7 33.3 Gain of 1 24 (21.5) 22 (19.5) 22 (19.5) 22 (19.5) Rev. A | Page 13 of 20 Gain of 8 23.5 (21) 22 (19.5) 22 (19.5) 21.5 (19) AD7191 ADC CIRCUIT INFORMATION OVERVIEW The AD7191 is a low noise, complete analog front end for high precision measurement applications. It contains a low noise, 24-bit, Σ-Δ ADC, a PGA, and an on-chip digital filter intended for measuring wide dynamic range signals. The device has an internal clock and two differential analog inputs. It offers a choice of four output data rates (10 Hz, 50 Hz, 60 Hz, and 120 Hz) and four gain settings (1, 8, 64, and 128). The device also has an internal temperature sensor. These functions are controlled using dedicated pins, which make the interface easy to configure. A 2-wire interface simplifies data retrieval from the AD7191. FILTER, DATA RATE, AND SETTLING TIME The AD7191 has four output data rates, which are selected using the ODR2 and ODR1 pins (see Table 5). When the polarity of ODR2 or ODR1 is changed, the AD7191 modulator and filter are reset immediately. DOUT/RDY is set high, and the ADC then begins conversions using the selected output data rate. The first conversion requires the complete settling time of the filter. Subsequent conversions occur at the selected output data rate. The settling time of the digital filter, tSETTLE, is Figure 19 to Figure 22 show the filter response for each of the allowed output data rates. The filter provides more than −53 dB of rejection in the stop band. When the output data rate is equal to 10 Hz, 60 Hz, or 120 Hz, the first notch occurs at a frequency equal to the output data rate. The other notches occur at multiples of the output data rate. Therefore, when the output data rate is equal to 10 Hz, notches are placed at 50 Hz and 60 Hz, giving simultaneous 50 Hz/60 Hz rejection. When the 60 Hz output data rate is selected, 60 Hz rejection is achieved. When the 50 Hz output data rate is selected, notches are placed at 50 Hz and multiples of 50 Hz. A notch is also placed at 60 Hz. This gives simultaneous 50 Hz/60 Hz rejection for an output data rate of 50 Hz. When the output data rate is changed, DOUT/RDY goes high and remains high until the appropriate settling time has elapsed. Therefore, the user should complete any read operations before changing the output data rate. Otherwise, 1s are read back from the AD7191 as the DOUT/RDY pin is set high following the change in output data rate. 0 –10 –20 When a step change occurs on the analog input, the AD7191 requires several conversion cycles to generate a valid conversion. If the step change occurs synchronous to the conversion period (see Figure 17), then to generate a valid conversion, the settling time of the AD7191 must be allowed. If the step change occurs asynchronous to the end of a conversion (see Figure 18), then to generate a valid conversion, an extra conversion period must be allowed. The diagrams show the case for an output data rate of 50 Hz; therefore, an asynchronous step change can increase the time to generate a valid conversion by 20 ms. The data register is updated with all the conversions but, for an accurate result, the user must allow the required time. –50 –60 –70 –80 –90 –100 –110 –120 0 10 20 30 40 50 60 FREQUENCY (Hz) 70 80 90 100 Figure 19. Filter Profile for the 10 Hz Output Data Rate 0 –10 –20 –30 VALID 20ms 40ms 60ms 80ms 100ms 08163-011 ADC OUTPUT FILTER GAIN (dB) ANALOG INPUT 0ms –40 08163-013 That is, the settling time is equal to four conversion cycles. FILTER GAIN (dB) –30 tSETTLE = 4/Output Data Rate Figure 17. Synchronous Analog Input Step Change –40 –50 –60 –70 –80 –90 –100 ANALOG INPUT –120 0 VALID 0ms 20ms 40ms 60ms 80ms 100ms 120ms 08163-012 ADC OUTPUT Figure 18. Asynchronous Analog Input Step Change Rev. A | Page 14 of 20 30 60 90 120 150 FREQUENCY (Hz) 180 210 Figure 20. Filter Profile for the 50 Hz Output Data Rate 240 08163-014 –110 AD7191 0 When the polarity of the PGA2 pin or PGA1 pin is changed, the AD7191 modulator and filter are reset immediately. DOUT/ RDY is set high. The ADC then begins conversions. DOUT/ RDY remains high until the appropriate settling time for the filter has elapsed. Therefore, any read operations should be completed before changing the gain. Otherwise, all 1s are read back from the AD7191 as the DOUT/RDY pin is set high following the gain change. The complete settling time of the filter is required to generate the first conversion after the gain change, whereas subsequent conversions occur at the selected output data rate. –10 –20 FILTER GAIN (dB) –30 –40 –50 –60 –70 –80 –90 –100 –120 0 30 60 90 120 150 FREQUENCY (Hz) 180 210 240 08163-015 –110 Figure 21. Filter Profile for the 60 Hz Output Data Rate 0 –10 –20 FILTER GAIN (dB) –30 –40 –50 –60 –70 The AD7191 has two differential analog input channels, AIN1/ AIN2 and AIN3/AIN4. Each input channel feeds into a high impedance input stage of the amplifier. Therefore, the input can tolerate high source impedances and is tailored for direct connection to external resistive-type sensors such as strain gauges or loadcells. The channel is selected using the CHAN pin. When CHAN is tied low, channel AIN1/AIN2 is selected, whereas channel AIN3/AIN4 is selected when the CHAN pin is tied high. The absolute input voltage range is restricted to a range between AGND + 250 mV and AVDD − 250 mV. Care must be taken in setting up the common-mode voltage to avoid exceeding these limits. Otherwise, there is degradation in linearity and noise performance. –80 –90 –100 –120 0 30 60 90 120 150 FREQUENCY (Hz) 180 210 240 08163-016 –110 Figure 22. Filter Profile for the 120 Hz Output Data Rate GAIN The AD7191 has four gain options: gain = 1, gain = 8, gain = 64, and gain = 128. The PGA2 and PGA1 pins are used to set the gain. The analog input range is +VREF/gain. Table 7 shows the gains and the corresponding analog input ranges. Table 7. Gain Settings PGA2 0 0 1 1 ANALOG INPUT CHANNELS PGA1 0 1 0 1 GAIN 1 8 64 128 Input Range ±VREF ±VREF/8 ±VREF/64 ±VREF/128 The low noise PGA means that signals of small amplitude can be amplified within the AD7191 while still maintaining excellent noise performance. The amplifier can be configured to have a gain of 1, 8, 64, or 128 using the PGA2 and PGA1 pins. The analog input range is equal to ±VREF/gain. The analog input range must be limited to (AVDD – 1.25 V)/gain because the PGA requires some headroom. Therefore, if AVDD = 5 V, the maximum analog input that can be applied to the AD7191 is ±3.75 V/gain. When the channel is changed, DOUT/RDY goes high and remains high until the appropriate settling time has elapsed. Therefore, any read operations should be completed before changing the channel. Otherwise, all 1s are read back from the AD7191 as the DOUT/RDY pin is set high following the channel change. Rev. A | Page 15 of 20 AD7191 When the polarity of CLKSEL is changed, DOUT/RDY goes high and remains high until the appropriate settling time elapses. TEMPERATURE SENSOR Embedded in the AD7191 is a temperature sensor. The temperature sensor is selected when the TEMP pin is tied high. The TEMP pin has higher priority than the CHAN pin; therefore, when TEMP is high, the temperature sensor is selected irrespective of the polarity on the CHAN pin. BIPOLAR CONFIGURATION When the temperature sensor is selected, the device should return a code of 0x800000 when the temperature is 0 K. A onepoint calibration is needed to get the optimum performance from the sensor. Therefore, a conversion at 25°C should be recorded and the sensitivity calculated. The sensitivity is 2815 codes/°C, approximately. The equation for the temperature sensor is Temp (K) = (Conversion− 0x800000)/2815 K Temp (°C) = Temp (K) − 273 Following the one point calibration, the internal temperature sensor has an accuracy of ±2°C, typically. Each time the temperature sensor is selected, DOUT/RDY goes high and remains high until the appropriate settling time elapses. Therefore, any read operations should be completed before selecting the temperature sensor. Otherwise, all 1s are read back from the AD7191 as the DOUT/RDY pin is set high following the channel change. POWER-DOWN (PDOWN) The PDOWN pin functions as a power-down pin and a reset pin. When PDOWN is taken high, the AD7191 is powered down and the DOUT/RDY pin is tristated. If the on-chip clock is selected, it will be powered down also. If an external crystal is being used, the on-chip oscillator circuitry remains active. With PDOWN high, the circuitry and serial interface are also reset. This resets the logic, the digital filter, and the analog modulator. PDOWN must be held high for 100 ns minimum to initiate the reset function. When PDOWN is taken low, the AD7191 is taken out of powerdown mode. When the on-chip clock has powered up (1 ms, typically), the modulator begins sampling the analog input, and the DOUT/RDY pin becomes active. When an external crystal or clock is used as the master clock source to the AD7191, the 1 ms power-up time is not required. A reset is automatically performed on power-up. CLOCK The AD7191 has an internal 4.92 MHz clock that has a 4% tolerance. The AD7191 can use the internal clock or, alternatively, an external clock or crystal can be used. The CLKSEL pin is used to select the clock source. When CLKSEL is low, an external clock/crystal is selected. When CLKSEL is high, the internal clock is selected. If a crystal is used, the crystal should be connected between MCLK1 and MCLK2. The user should refer to the crystal data sheet for details on the capacitor values. If an external clock source is used, it should be applied to MCLK1. MCLK2 should be left unconnected. The AD7191 accepts a bipolar input range. A bipolar input range does not imply that the part can tolerate negative voltages with respect to system AGND. Signals on the positive analog input pin are referenced to the voltage on the negative analog input pin. For example, if AIN2 is 2.5 V, the analog input range on the AIN1 input is 2.461 V to 2.539 V for a gain of 128 when a 5 V reference is used. DATA OUTPUT CODING The AD7191 uses offset binary coding. Therefore, a negative full-scale voltage results in a code of 000...000, a zero differential input voltage results in a code of 100...000, and a positive full-scale input voltage results in a code of 111...111. The output code for any analog input voltage can be represented as Code = 2N – 1 × [(AIN × Gain/VREF) + 1] where AIN is the analog input voltage (AIN1 – AIN2 or AIN3 – AIN4), Gain is 1, 8, 64, or 128, and N = 24 for the AD7191. BRIDGE POWER-DOWN SWITCH The bridge power-down switch (BPDSW) is useful in batterypowered applications where it is essential that the power consumption of the system be optimized. A 350 Ω load cell consumes 15 mA typically when excited with a 5 V power supply. To minimize the current consumption, the load cell is disconnected when it is not being used. The bridge powerdown switch can be included in series with the load cell. When PDOWN is low, the bridge power-down switch is closed, and the load cell measures the strain. When PDOWN is high, the bridge power-down switch is opened so that no current flows through the load cell. Therefore, the current consumption of the system is minimized. The bridge power-down switch has an on-resistance of 10 Ω maximum, and it is capable of withstanding 30 mA of continuous current. REFERENCE The AD7191 has a fully differential input capability. The common-mode range for these differential inputs is AGND to AVDD. The reference input is unbuffered; therefore, excessive R-C source impedances introduce gain errors. The reference voltage REFIN (REFIN(+) − REFIN(−)) is AVDD nominal, but the AD7191 is functional with reference voltages of 1 V to AVDD. In applications where the excitation (voltage or current) of the transducer connected to the analog input also drives the reference voltage for the part, the effect of the low frequency noise in the excitation source is removed because the application is ratiometric. If the AD7191 is used in a nonratiometric application, a low noise reference should be used. Recommended 2.5 V reference voltage sources for the AD7191 include the ADR421, which is a low noise reference. These references have low output impedances and are, therefore, Rev. A | Page 16 of 20 AD7191 tolerant to decoupling capacitors on REFIN(+) without introducing gain errors in the system. Deriving the reference input voltage across an external resistor means that the reference input sees a significant external source impedance. External decoupling on the REFIN pins is not recommended in this type of circuit configuration. DIGITAL INTERFACE The serial interface of the AD7191 consists of two signals: SCLK and DOUT/RDY. SCLK is the serial clock input for the device, and data transfers occur with respect to the SCLK signal. The DOUT/RDY pin is dual purpose: it functions as a data ready pin and as a data output pin. DOUT/RDY goes low when a new data-word is available in the output register. A 24-bit word is placed on the DOUT/RDY pin when sufficient SCLK pulses are applied. DOUT/RDY is reset high when the conversion has been read. If the conversion is not read, DOUT/RDY goes high prior to the next data register update to indicate when not to read from the device. This ensures that a read operation is not attempted while the register is being updated. Each conversion can be read only once. The data register is updated for every conversion. Thus, when a conversion is complete, the serial interface is reset, and the new conversion is placed in the data register. Therefore, the user must ensure that the complete word is read before the next conversion is complete. When PDOWN is high, the DOUT/RDY pin is tristated. When PDOWN is taken low, the internal clock requires 1 ms approximately to power up. Following this, the ADC continuously converts. The first conversion requires the complete settling time. DOUT/RDY goes high when PDOWN is taken low and returns low only when a conversion is available. The ADC then converts continuously, and subsequent conversions are available at the selected output data rate. Figure 3 shows the timing for a read operation from the AD7191. When the output data rate, gain, channel, or clock source is changed, the modulator and filter are reset immediately. DOUT/RDY is set high. The ADC then begins conversions using the new configuration. DOUT/RDY remains high until the appropriate settling time for the filter elapses. Therefore, any read operations should be completed before changing the operating conditions or channel. Otherwise, all 1s are read back from the AD7191 as the DOUT/RDY pin is set high following the channel change or configuration change. GROUNDING AND LAYOUT Because the analog inputs and reference input on the AD7191 are differential, most of the voltages in the analog modulator are common-mode voltages. The excellent common-mode rejecttion of the part removes common-mode noise on these inputs. The analog and digital supplies to the AD7191 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. The AD7191 can be operated with 5 V analog and 3 V digital supplies or vice versa. The digital filter provides rejection of broadband noise on the power supplies, except at integer multiples of the modulator sampling frequency. A simple R-C low-pass filter on the analog inputs rejects any interference at the clock frequency. The digital filter also removes noise from the analog and reference inputs, provided that these noise sources do not saturate the analog modulator. As a result, the AD7191 is more immune to noise interference than a conventional high resolution converter. However, because the resolution of the AD7191 is so high, and the noise levels from the AD7191 are so low, care must be taken with regard to grounding and layout. The printed circuit board should be designed such that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. A minimum etch technique is generally best for ground planes because it gives the best shielding. Although the AD7191 has separate pins for analog and digital ground, the AGND and DGND pins are tied together within the device via the substrate. The user must not tie these pins externally to separate ground planes unless the ground planes are connected together near the AD7191. Rev. A | Page 17 of 20 AD7191 In systems where the AGND and DGND pins are connected somewhere else in the system(that is, at the system power supply), they should not be connected again at the AD7191 because a ground loop results. In these situations, it is recommended that the AD7191 AGND and DGND pins be tied to the AGND plane. In any layout, it is important that the user keep in mind the flow of currents in the system, ensuring that the return paths for all currents are as close as possible to the paths the currents took to reach their destinations. Avoid forcing digital currents to flow through the AGND sections of the layout. Avoid running digital lines under the device because these couple noise onto the die. The analog ground plane should be allowed to run under the AD7191 to prevent noise coupling. The power supply lines to the AD7191 should use as wide a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, and signals are placed on the solder side. Good decoupling is important when using high resolution ADCs. All analog supplies should be decoupled with 10 μF tantalum capacitors in parallel with 0.1 μF capacitors to AGND. To achieve the best from these decoupling components, they have to be placed as close as possible to the device, ideally right up against the device. All logic chips should be decoupled with 0.1 μF ceramic capacitors to DGND. In systems where a common supply voltage is used to drive both the AVDD and DVDD of the AD7191, it is recommended that the system AVDD supply be used. This supply should have the recommended analog supply decoupling capacitors between the AVDD pin of the AD7191 and AGND, and the recommended digital supply decoupling capacitor between the DVDD pin of the AD7191 and DGND. Rev. A | Page 18 of 20 AD7191 APPLICATIONS INFORMATION the load cell. For this reason, a system calibration that calibrates the offset and full-scale error of the ADC plus the load cell is required. A microprocessor can be used to perform the calibrations. The offset (the conversion result from the AD7191 when no load is applied to the load cell) and the full-scale error (the conversion result from the ADC when the maximum load is applied to the load cell) must be determined. Subsequent conversions from the AD7191 are then corrected using the offset and full-scale coefficients calculated from the above calibrations. The AD7191 provides a low-cost, high resolution analog-todigital function. Because the analog-to-digital function is provided by a ∑-Δ architecture, the part is more immune to noisy environments, making it ideal for use in sensor measurement and industrial and process control applications. WEIGH SCALES Figure 24 shows the AD7191 being used in a weigh scale application. The load cell is arranged in a bridge network and gives a differential output voltage between its OUT+ and OUT– terminals. Assuming a 5 V excitation voltage, the full-scale output range from the transducer is 10 mV when the sensitivity is 2 mV/V. The excitation voltage for the bridge can be used to directly provide the reference for the ADC because the reference input range includes the supply voltage. EMI RECOMMENDATIONS For simplicity, the EMI filters are not included in Figure 24. However, an R-C antialias filter should be included on each analog input. This filter is needed because the on-chip digital filter does not provide any rejection around MCLK/8 or multiples of this frequency. Suitable values are a 100 Ω resistor in series with each analog input, a 0.1 μF capacitor from AIN(+) to AIN(−), and 0.01 μF capacitors from AIN(+)/AIN(−) to AGND (see Figure 23). A second advantage of using the AD7191 in transducer-based applications is that the bridge power-down switch can be fully utilized in low power applications. The bridge power-down switch is connected in series with the low side of the bridge. In normal operation, the switch is closed and measurements can be taken. In applications where power is of concern, the AD7191 can be placed in power-down mode, thus significantly reducing the power consumed in the application. In addition, the bridge power-down switch is opened while in power-down mode, thus avoiding unnecessary power consumption by the front-end transducer. When the part is taken out of powerdown mode and the bridge power-down switch is closed, the user should ensure that the front-end circuitry is fully settled before attempting a read from the AD7191. 0.01µF 100Ω AD7191 AIN(+): AIN1 OR AIN3 0.1µF 100Ω AIN(–): AIN2 OR AIN4 08163-018 0.01µF Figure 23. External Filtering Connections The load cell has an offset or TARE associated with it. This TARE is the main component of the system offset (load cell plus ADC) and is of a magnitude similar to the full-scale signal from 5V AVDD AGND DVDD DGND REFERENCE DETECT REFIN(+) AD7191 IN+ OUT– DOUT/RDY AIN1 AIN2 IN– AIN3 MUX SERIAL INTERFACE AND CONTROL LOGIC Σ-Δ ADC PGA AIN4 SCLK PDOWN CHAN CLKSEL REFIN(–) BPDSW TEMPERATURE SENSOR PGA2 CLOCK CIRCUITRY MCLK1 MCLK2 PGA1 ODR2 ODR1 TEMP Figure 24. Typical Application (Weigh Scale) Rev. A | Page 19 of 20 08163-017 OUT+ AD7191 OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 1.20 MAX SEATING PLANE 0.20 0.09 8° 0° 0.75 0.60 0.45 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 25. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters ORDERING GUIDE Models AD7191BRUZ 1 AD7191BRUZ-REEL1 1 Temperature Range –40°C to +105°C –40°C to +105°C Package Description 24-Lead TSSOP 24-Lead TSSOP Z = RoHS Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08163-0-5/09(A) Rev. A | Page 20 of 20 Package Option RU-24 RU-24