ETC 74ACTQ652MTCX

Revised September 2000
74ACTQ652
Quiet Series Transceiver/Register
General Description
Features
The ACTQ652 consists of bus transceiver circuits with Dtype flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from
internal registers. Data on the A or B bus will be clocked
into the registers as the appropriate clock pin goes to the
HIGH logic level. Output Enable pins (OEAB, OEBA) are
provided to control the transceiver function.
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
The ACTQ652 utilizes Fairchild FACT Quiet Series technology to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in
addition to split ground bus for superior performance.
■ TTL-compatible inputs
■ Guaranteed pin-to-pin skew AC performance
■ Independent registers for A and B buses
■ Multiplexed real-time and stored data
■ Outputs source/sink 24 mA
Ordering Code:
Order Number
74ACTQ652SC
Package Number
M24B
74ACTQ652MTC
MTC24
74ACTQ652SPC
N24C
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
Description
A0–A7, B0–B7
A and B Inputs/3-STATE Outputs
CPAB, CPBA
Clock Inputs
SAB, SBA
Select Inputs
OEAB, OEBA
Output Enable Inputs
FACT, Quiet Series, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation
DS010933
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74ACTQ652 Quiet Series Transceiver/Register
June 1991
74ACTQ652
Function Table
Inputs
Inputs/Outputs (Note 1)
Operating Mode
OEAB
OEBA
CPAB
CPBA
L
H
H or L
H or L
L
H
X
H
H
H
L
X
L
L
H or L
H or L
SAB
SBA
A0 thru A7
B0 thru B7
Input
Input
X
X
X
X
X
X
Input
Not Specified
X
X
Input
Output
X
X
Not Specified
Input
Hold A, Store B
X
X
Output
Input
Store B in Both Registers
Output
Input
L
L
X
X
X
L
L
L
X
H or L
X
H
H
H
X
X
L
X
H
H
H or L
X
H
X
H
L
H or L
H or L
H
H
Isolation
Store A and B Data
Store A, Hold B
Store A in Both Registers
Real-Time B Data to A Bus
Store B Data to A Bus
Real-Time A Data to B Bus
Input
Output
Stored A Data to B Bus
Stored A Data to B Bus and
Output
Output
Stored B Data to A Bus
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled,
i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Data on the A or B data bus, or both can be stored in the
internal D-type flip-flop by LOW-to-HIGH transitions at the
appropriate Clock Inputs (CPAB, CPBA) regardless of the
Select or Output Enable Inputs. When SAB and SBA are in
the real time transfer mode, it is also possible to store data
without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration
each Output reinforces its Input. Thus when all other data
sources to the two sets of bus lines are in a HIGH impedance state, each set of bus lines will remain at its last state.
In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or
both.
The select (SAB, SBA) controls can multiplex stored and
real-time.
The examples in Figure 1 demonstrate the four fundamental bus-management functions that can be performed with
the Octal bus transceivers and receivers.
Note A: Real-Time
Note B: Real-Time
Transfer Bus B to Bus A
Transfer Bus A to Bus B
OEAB OEBA CPAB CPBA
L
L
X
X
SAB
SBA
X
L
OEAB OEBA CPAB CPBA
H
Note C: Storage
H
X
X
SAB
SBA
L
X
Note D: Transfer Storage
Data to A or B
OEAB OEBA CPAB CPBA
X
H
L
X
L
H
X
X
SAB
SBA
X
X
X
X
X
X
OEAB OEBA CPAB CPBA
H
L
H or L H or L
SAB
SBA
H
H
FIGURE 1.
3
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74ACTQ652
Functional Description
74ACTQ652
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions
−0.5V to +7.0V
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
−20 mA
VI = VCC + 0.5V
+20 mA
DC Input Voltage (VI)
Supply Voltage (VCC)
0V to VCC
Output Voltage (VO)
−0.5V to VCC + 0.5V
0V to VCC
−40°C to +85°C
Operating Temperature (TA)
Minimum Input Edge Rate ∆V/∆t
DC Output Diode Current (IOK)
VO = −0.5V
−20 mA
VO = VCC + 0.5V
+20 mA
DC Output Voltage (VO)
4.5V to 5.5V
Input Voltage (VI)
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
−0.5V to VCC + 0.5V
125 mV/ns
DC Output Source
± 50 mA
or Sink Current (IO)
DC VCC or Ground Current
± 50 mA
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
−65°C to +150°C
DC Latch-Up Source
± 300 mA
or Sink Current
Junction Temperature (TJ)
140°C
PDIP
DC Electrical Characteristics
Symbol
VIH
VIL
VOH
Parameter
VCC
TA = +25°C
TA = −40°C to +85°C
(V)
Typ
Guaranteed Limits
Minimum HIGH Level
4.5
1.5
2.0
Input Voltage
5.5
1.5
2.0
2.0
Maximum LOW Level
4.5
1.5
0.8
0.8
Input Voltage
5.5
1.5
0.8
0.8
2.0
Minimum HIGH Level
4.5
4.49
4.4
4.4
Output Voltage
5.5
5.49
5.4
5.4
Units
V
V
V
Conditions
VOUT = 0.1V
or VCC − 0.1V
VOUT = 0.1V
or VCC − 0.1V
IOUT = −50 µA
VIN = VIL or VIH
VOL
4.5
3.86
3.76
5.5
4.86
4.76
V
IOH = −24 mA
IOH = −24 mA (Note 3)
Maximum LOW Level
4.5
0.001
0.1
0.1
Output Voltage
5.5
0.001
0.1
0.1
4.5
0.36
0.44
5.5
0.36
0.44
5.5
± 0.1
± 1.0
µA
5.5
± 0.6
± 6.0
µA
1.5
mA
VI = VCC − 2.1V
V
IOUT = 50 µA
VIN = VIL or VIH
IIN
Maximum Input
Leakage Current
IOZT
Maximum I/O
Leakage Current
IOL = 24 mA
IOL = 24 mA (Note 3)
VI = VCC, GND
VI = VIL, VIH
VO = VCC, GND
ICCT
Maximum ICC/Input
5.5
IOLD
Minimum Dynamic
5.5
75
mA
VOLD = 1.65V Max
IOHD
Output Current (Note 4)
5.5
−75
mA
VOHD = 3.85V Min
ICC
Maximum Quiescent
80.0
µA
VIN = VCC or GND
Supply Current
VOLP
Maximum HIGH Level
Output Noise
VOLV
Maximum LOW Level
Output Noise
VIHD
Minimum HIGH Level
Dynamic Input Voltage
VILD
Maximum LOW Level
Dynamic Input Voltage
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0.6
V
5.5
5.0
8.0
1.1
1.5
V
Figures 2, 3
(Note 5)(Note 6)
Figures 2, 3
5.0
−0.6
−1.2
V
5.0
1.9
2.2
V
(Note 5)(Note 7)
5.0
1.2
0.8
V
(Note 5)(Note 7)
4
(Note 5)(Note 6)
74ACTQ652
DC Electrical Characteristics
(Continued)
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: PDIP package.
Note 6: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND.
Note 7: Max number of data inputs (n) switching. (n − 1) inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (VILD),
0V to threshold (VIHD), f = 1 MHz.
AC Electrical Characteristics
Symbol
Parameter
VCC
TA = +25°C
(V)
CL = 50 pF
(Note 8)
fMAX
Maximum Clock Frequency
tPLH
Propagation Delay
tPHL
Clock to Bus
tPLH
Propagation Delay
tPHL
Bus to Bus
tPLH
Propagation Delay
tPHL
SBA or SAB to A or B
tPZH
Enable Time
tPZL
OEBA to A (Note 8)
tPHZ
Disable Time
tPLZ
OEBA to A (Note 8)
tPZH
Enable Time
tPZL
OEAB to B
tPHZ
Disable Time
tPLZ
OEAB to B
tS(H)
Setup Time, HIGH or
tS(L)
LOW, Bus to Clock
tH(H)
Hold Time, HIGH or
tH(L)
LOW, Bus to Clock
tW(H)
Clock Pulse Width
tW(L)
HIGH or LOW
tOSHL
Output to Output Skew (Note 9)
tOSLH
A to B, B to A or
Min
Typ
TA = −40°C to +85°C
CL = 50 pF
Max
Min
Units
Max
5.0
MHz
5.0
2.0
7.0
9.5
2.0
10.0
ns
5.0
2.0
6.5
9.0
2.0
9.5
ns
5.0
2.5
6.5
10.0
2.5
10.5
ns
5.0
2.0
7.0
10.5
2.0
11.0
5.0
1.0
5.0
8.0
1.0
8.5
5.0
2.0
7.0
10.5
2.0
11.0
5.0
1.0
5.0
8.0
1.0
8.5
5.0
3.0
3.0
ns
5.0
1.5
1.5
ns
5.0
4.0
4.0
ns
5.0
0.5
1.0
1.0
ns
ns
ns
Clock to Output
Note 8: Voltage Range 5.0 is 5.0V ± 0.5V.
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any separate outputs of the same device. The specification applies to any output switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Capacitance
Typ
Units
CIN
Symbol
Input Capacitance
Parameter
4.5
pF
VCC = 5.0V
CPD
Power Dissipation Capacitance
54
pF
VCC = 5.0V
5
Conditions
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74ACTQ652
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
VOLP/VOLV and VOHP/V OHV:
• Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output voltages using a 50Ω coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
• Measure VOLP and VOLVon the quiet output during the
worst case transition for active and enable. Measure
VOHP and VOHV on the quiet output during the worst
case active and enable transition.
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500Ω.
• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
VILD and VIHD:
• Monitor one of the switching outputs using a 50Ω coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the
correct voltage.
• First increase the input LOW voltage level, VIL, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input LOW voltage level at which
oscillation occurs is defined as V ILD.
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measurement.
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
• Next decrease the input HIGH voltage level, VIH until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V IL limits, or on output HIGH levels that
exceed VIH limits. The input HIGH voltage level at which
oscillation occurs is defined as V IHD.
• Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
Note A: VOHV and VOLP are measured with respect to ground reference.
Note B: Input pulses have the following characteristics: f = 1 MHz, tr = 3 ns,
tf = 3 ns, skew < 150 ps.
FIGURE 2. Quiet Output Noise Voltage Waveforms
FIGURE 3. Simultaneous Switching Test Circuit
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74ACTQ652
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
7
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74ACTQ652
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC24
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74ACTQ652 Quiet Series Transceiver/Register
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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