Revised March 1999 74LVX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop General Description Asynchronous Inputs: The LVX74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Features ■ Input voltage level translation from 5V to 3V ■ Ideal for low power/low noise 3.3V applications ■ Guaranteed simultaneous switching noise level and dynamic threshold performance Ordering Code: Order Number 74LVX74M 74LVX74SJ 74LVX74MTC Package Number M14A M14D MTC14 Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names © 1999 Fairchild Semiconductor Corporation DS011606.prf Description D1 , D2 Data Inputs CP1, CP2 Clock Pulse Inputs CD1, CD2 Direct Clear Inputs SD1, SD2 Direct Set Inputs Q1, Q1, Q2, Q2 Outputs www.fairchildsemi.com 74LVX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop May 1993 74LVX74 Logic Symbols IEEE/IEC Truth Table (Each Half) Inputs SD CD Outputs CP Q Q L H X X H L H L X X L H L L X X H H H H L L L H L X Q0 Q0 H H H H H H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition Q0(Q0) = Previous Q(Q) before LOW-to-HIGH Transition of Clock www.fairchildsemi.com D 2 Recommended Operating Conditions (Note 2) −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) Supply Voltage (VCC) VI = −0.5V −20 mA −0.5V to 7V DC Input Voltage (VI) 2.0V to 3.6V Input Voltage (VI) 0V to 5.5V Output Voltage (VO) DC Output Diode Current (IOK) 0V to VCC −40°C to +85°C Operating Temperature (TA) VO = −0.5V −20 mA VO = VCC +0.5V +20 mA Input Rise and Fall Time (∆t/∆V) 0 ns/V to 100 ns/V −0.5V to VCC + 0.5V DC Output Voltage (VO) DC Output Source Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. ±25 mA or Sink Current (IO) DC VCC or Ground Current ±50 mA (ICC or IGND) −65°C to +150°C Storage Temperature (TSTG) Power Dissipation Note 2: Unused inputs must be held HIGH or LOW. They may not float. 180 mW DC Electrical Characteristics Symbol VIH VIL VOH VOL Parameter VCC TA = +25°C Min TA = −40°C to +85°C Typ Max Min HIGH Level 2.0 1.5 Input Voltage 3.0 2.0 2.0 3.6 2.4 2.4 Units Max Conditions 1.5 V LOW Level 2.0 0.5 Input Voltage 3.0 0.8 0.5 0.8 3.6 0.8 0.8 V VIN = VIL or VIH HIGH Level 2.0 1.9 2.0 1.9 Output Voltage 3.0 2.9 3.0 2.9 3.0 2.58 LOW Level 2.0 0.0 0.1 0.1 Output Voltage 3.0 0.0 0.1 0.1 IOH = −50 µA IOH = −50 µA V IOH = −4 mA 2.48 VIN = VIL or VIH IOL = 50 µA IOL = 50 µA V IOL = 4 mA 3.0 0.36 0.44 IIN Input Leakage Current 3.6 ±0.1 ±1.0 µA VIN = 5.5V or GND ICC Quiescent Supply Current 3.6 2.0 20.0 µA VIN = VCC or GND Noise Characteristics (Note 3) Symbol VCC (V) Parameter TA = 25°C Typ Limit Units CL (pF) VOLP Quiet Output Maximum Dynamic VOL 3.3 0.3 0.5 V 50 VOLV Quiet Output Minimum Dynamic VOL 3.3 −0.3 −0.5 V 50 VIHD Minimum High Level Dynamic Input Voltage 3.3 2.0 V 50 VILD Maximum Low Level Dynamic Input Voltage 3.3 0.8 V 50 Note 3: Input tr = tf = 3 ns 3 www.fairchildsemi.com 74LVX74 Absolute Maximum Ratings(Note 1) 74LVX74 AC Electrical Characteristics Symbol VCC (V) Parameter tPLH Propagation Delay tPHL CPn to Qn or Qn TA = +25°C Min Typ 2.7 3.3 ± 0.3 tPLH Propagation Delay tPHL CDn to SDn to Qn or Qn 2.7 tS tREC 15 1.0 18.5 9.8 18.5 1.0 22 5.7 9.7 1.0 11.5 8.2 13.2 1.0 15 15 50 ns 15 50 15.6 1.0 18.5 15 19.1 1.0 22 50 6.6 10.1 1.0 12 9.1 13.6 1.0 15.5 10 3.3 ± 0.3 6 7 2.7 8.0 9.5 5.5 6.5 Hold Time 2.7 0.5 0.5 Dn to CPn 3.3 ± 0.3 0.5 0.5 Recovery Time CL (pF) Units 8.4 3.3 ± 0.3 CPn or SDn to CPn fMAX 7.3 8.5 Setup Time Dn to CPn tH Max 2.7 CPn or CDn or SDn Pulse Width Min 10.9 3.3 ± 0.3 tW TA = −40°C to +85°C Max ns 15 50 ns ns ns 2.7 6.5 7.5 3.3 ± 0.3 5.0 5.0 2.7 55 135 50 15 45 60 40 50 95 145 80 60 85 50 Maximum Clock Frequency 3.3 ± 0.3 ns MHz 15 50 tOSLH Output to Output Skew 2.7 1.5 1.5 tOSHL (Note 4) 3.3 1.5 1.5 50 ns Note 4: Parameter guaranteed by design. tOSLH = |tPLHm–tPLHn|, tOSLH = |tPHLm–tPHLn| Capacitance Symbol TA = +25°C Parameter Min TA = −40°C to +85°C Typ Max 10 CIN Input Capacitance 4 CPD Power Dissipation 25 Min Max 10 Capacitance (Note 5) Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. www.fairchildsemi.com 4 Units pF pF 74LVX74 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Package Number M14A 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 5 www.fairchildsemi.com 74LVX74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.