ETC 7640

To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
DESCRIPTION
• Memory size
ROM .................................................. 32KB on chip
RAM ................................................... 1 KB on chip
• Programmable I/O ports ...................................... 66
.................................................... 8 bit X 7, 5 bit X 2
• Master Bus Interface (MBI) ....................... 17 signals
............................................................. 8 data lines
• Serial I/O ............................. 8 bit clock synchronous
• USB Function Control .............. 4 endpoints,1 control
• Interrupts ................................ 4 external, 19 internal
................................................ 1 software,1 system
• DMAC .......................... 2 channels, 16 address lines
(Max. 6M byte/sec. transfer speed in burst mode)
• Timers ......................................... 8 bit X 3, 16 bit X 2
• Number of Full duplex UARTs available ................... 2
• Supply voltage ............................. Vcc = 4.15~5.25V
• Operating temperature range ................... -20 to 85°C
• Power-saving modes ..... WIT (Idle), STP (Clocks halt)
The 7640 group, an enhanced family of CMOS 8-bit
microcontrollers, offers high-speed operation, large
internal-memory options, and a wide variety of standard peripherals. The series is code compatible with
the 38000, 7200, 7400, and the 7500 series, and provides many performance enhancements to the
instruction set.
This device is a single chip PC peripheral microcontroller based on the Universal Serial Bus (USB)
Version 1.1 specification. This device provides data
exchange between a USB-equipped host computer
and PC peripherals such as telephones, audio systems and digital cameras. See Figure 1.1 for a pin
layout diagram. See Figure 1.2 for the functional
block diagram.
MCU FEATURES
APPLICATIONS
P16/AB14
P17/AB15
P14/AB12
P15/AB13
P12/AB10
P13/AB11
P10/AB8
P11/AB9
P06/AB6
Cameras, games, musical instruments, modems
scanners, and PC peripherals.
P07/AB7
P02/AB2
1.3
P03/AB3
P00/AB0
P01/AB1
P26/DB6
P27/DB7
P24/DB4
P25/DB5
P22/DB2
P23/DB3
P20/DB0
P21/DB1
• Number of basic instructions ................................ 71
• Minimum instruction execution time ................. 83ns
(1-cycle instruction ................................... F = 12 MHz)
•Clock frequency maximum .................. f(Xin) = 24 MHz
........................................................ f(XCin) = 5 MHz
............................................................ F = 12 MHz
P04/AB4
1.2
P05/AB5
1.1
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P74/OBF1
65
40
P30/RDY
P73/IBF1/HLDA
66
39
P31
P72/S1
67
38
P32
P71/(HOLD)
68
37
P33/DMAout
P70/(SOF)
69
36
P34/Φout
USB D+
70
35
P35/SYNCout
USB D-
71
34
P36/WR
Ext. Cap
72
33
P37/RD
Vss
73
32
P80/UTXD2/SRDY
Vcc
74
31
P81/URXD2/SCLK
P67/DQ7
75
30
P82/CTS2/SRXD
P66/DQ6
76
29
P83/RTS2/STXD
P65/DQ5
77
28
P84/UTXD1
P64/DQ4
78
27
P85/URXD1
P63/DQ3
79
26
P86/CTS1
P62/DQ2
80
25
P87/RTS1
P41/INT0
P40/EDMA
P42/INT1
P43/CNTR0
AVss
20 21 22 23 24
P44/CNTR1
LPF
AVcc
Vcc
P54/S0
Xout
P55/A0
10 11 12 13 14 15 16 17 18 19
Xin
P56/R(E)
9
Vss
P57/W(R/W)
8
P50/XCin
P60/DQ0
7
P51/Tout/XCout
6
RESET
5
CNVss/Vpp
4
P53/IBF0
3
P52/OBF0
2
_
1
P61/DQ1
M37640E8FP
M37640M8-XXXFP
Package outline: 80P6N-A
Fig. 1.1. Pin Layout
1
2
Fig. 1.2. Functional Block Diagram
UART1(8)
SIO (8)
P7
6 5 6 6 6 7 68 6 9
25 26 27 28 29 30 31 32
P8
P7(5)
ROM
P8(8)
UART2(8)
11
X COUT
P6(8)
P6
MBI
2
17 16
AVcc
3
4
74
5
6
P5
7
13
VSS
8 11 12
X CIN
TOUT
Key-on Wake-up
VCC
P5(8)
VCC
W(R/W)
R(E),A0
S0,IBF 0
OBF0
RAM
DQ (0-7)
10
RESET
75 76 77 78 79 80 1
SOF
19
D+ D-
70 71
USB
18
LPF AVSS
P4(5)
P4
72
INT1,
INT0
PS
PC L
S
Y
X
A
24
EDMA
P3
34
P2(8)
35
WR SYNCout
DMAOUT
DMA
33
RD
P2
3 3 3 4 3 5 3 6 3 7 3 8 53 79 54 80 5 9 6 0 6 1 6 2 6 3 6 4
P3(8)
TOUT
CNTR1,CNTR0
CPU
PC H
9
Ext.Cap CNVSS
20 21 22 23 24
73
VSS
40
RDY
P0(8)
P1
P0
4 1 4 2 4 3 4 4 4 5 4 64 49 75 40 85 1 5 2 5 3 5 4 5 5 5 6
P1(8)
Timer 3 (8)
Timer 2 (8)
Timer Y (16)
Timer X (16)
68
Timer 1 (8)
66
HLDA HOLD
Ver 1.4
S1,IBF 1
OBF1
12
Frequency Synthesizer
X CIN
15
14
36
X
OUT
X IN
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.4 FUNCTIONAL BLOCK DIAGRAM
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.5 PIN DESCRIPTION AND LAYOUT
Table 1.1. Pin Description and Layout
NAME
I/O
DESCRIPTION
P00/AB0~ P17/AB15
I/O
CMOS I/O port (address bus). When the MCU is in memory expansion or
microprocessor mode, these pins function as the address bus.
P20/DB0 ~ P27/DB7
I/O
CMOS I/O port (data bus). When the MCU is in memory expansion or microprocessor
mode, these pins function as the data bus. These pins may also be used to implement
the Key-on Wake up function.
PIN #
56-41
64-57
P30/RDY
I/O
CMOS I/O port (Ready). When the MCU is in memory expansion or microprocessor
mode, this pin functions as RDY (hardware wait cycle control).
40
P31
I/O
CMOS I/O port.
39
P32
I/O
CMOS I/O port.
38
I/O
CMOS I/O port (DMAout). When the MCU is in memory expansion or microprocessor
mode, this pin is set to a “1” during a DMA transfer.
37
P33/DMAout
P34/Φout
I/O
CMOS I/O port . When the MCU is in memory expansion or microprocessor mode,
this pin becomes Φout pin.
36
P35/SYNCout
I/O
CMOS I/O port (SYNCout). When the MCU is in memory expansion or
microprocessor mode, this pin becomes the SYNCout pin.
35
P36/WR
I/O
mode, this pin becomes WR.
34
P37/RD
I/O
CMOS I/O port. (RD output). When the MCU is in memory expansion or microprocessor
mode, this pin becomes RD.
33
P40/EDMA
I/O
CMOS I/O port (EDMA: Expanded Data Memory Access). When the MCU is in memory
expansion or microprocessor mode, this pin can become the EDMA pin.
24
P41/INT0~ P42/INT1
I/O
CMOS I/O port or external interrupt ports INT0 and INT1. These external interrupts can
be configured to be active high or low.
23-22
I/O
CMOS I/O port or Timer X input pin for pulse width measurement mode and event
counter mode or Timer X output pin for pulse output mode. This pin can also be used as
CMOS I/O port. (WR output). When the MCU is in memory expansion or microprocessor
P43/CNTR0
21
an external interrupt when Timer X is not in output mode. The interrupt polarity is
selected in the Timer X mode register.
CMOS I/O port or Timer Y input pin for pulse period measurement mode, pulse H-L
measurement mode and event counter mode or Timer Y output pin for pulse output
mode. This pin can also be used as an external interrupt when Timer Y is not in output
mode. The interrupt polarity is selected in the Timer Y mode register.
P44/CNTR1
I/O
20
P50/XCin
I/O
CMOS I/O port or XCin.
12
P51/Tout/XCout
I/O
CMOS I/O port or Timer half pulse output pin (can be configured initially high or initially
low), or XCout.
11
P52/OBF0
I/O
CMOS I/O port or OBF0 output to master CPU for data bus buffer 0.
8
P53/IBF0
I/O
CMOS I/O port or IBF0 output to master CPU for data bus buffer 0.
7
P54/S0
I/O
CMOS I/O port or S0 input from master CPU for data bus buffer 0.
6
P55/A0
I/O
CMOS I/O port or A0 input from master CPU.
5
P56/R(E)
I/O
CMOS I/O port or R(E) input from master CPU.
4
P57/W(R/W)
I/O
CMOS I/O port or W(R/W) input from master CPU.
P60/DQ0~ P67/DQ7
I/O
CMOS I/O port or master CPU data bus.
USB D-
I/O
USB D- voltage line interface, a series resistor of 33 Ω should be connected to this pin.
USB D+
I/O
USB D+ voltage line interface, a series resistor of 33 Ω should be connected to this pin.
70
P70/SOF
I/O
CMOS I/O port or USB start of frame pulse output, an 80 ns pulse outputs on this pin for
every USB frame.
69
P71/HOLD
I/O
CMOS I/O port or HOLD pin.
68
P72/S1
I/O
CMOS I/O port or S1 input from master CPU for data bus buffer 1.
67
3
2-1,
80-75
71
3
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
NAME
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O
DESCRIPTION
PIN #
P73/IBF1/HLDA
I/O
CMOS I/O port or IBF1 output to master CPU for data bus buffer 1, or HLDA pin.
IBF1 and HLDA are mutually exclusive. IBF 1 has priority over HLDA
66
P74/OBF1
I/O
CMOS I/O port or OBF1 output to master CPU for data bus buffer 1.
65
P80/UTXD2/SRDY
I/O
CMOS I/O port or UART2 pin UTXD2 or SIO pin SRDY. UART2 and SIO are
mutually exclusive, UART2 has priority over SIO.
32
I/O
CMOS I/O port or UART2 pin URXD2 or SIO pin SCLK. UART2 and SIO are
mutually exclusive, UART2 has priority over SIO.
31
I/O
CMOS I/O port or UART2 pin CTS2 or SIO pin SRXD. UART2 and SIO are
mutually exclusive, UART2 has priority over SIO.
30
P83/RTS2/STXD
I/O
CMOS I/O port or UART2 pin RTS2 or SIO pin STXD. UART2 and SIO are
mutually exclusive, UART2 has priority over SIO.
29
P84/UTXD1
I/O
CMOS I/O port or UART1 pin UTXD1.
28
P85/URXD1
I/O
CMOS I/O port or UART1 pin URXD1.
27
P86/CTS1
I/O
CMOS I/O port or UART1 pin CTS1.
26
P87/RTS1
I/O
CMOS I/O port or UART1 pin RTS1.
25
P81/URXD2/SCLK
P82/CTS2/SRXD
AVcc, AVss
I
Power supply inputs for analog circuitry AVcc = 4.15~ 5.25V, AVss = 0V
17,19
Controls the processor mode of the chip. Normally connected to Vss or Vcc.
CNVss/Vpp
I
When the MCU is in EPROM program mode, this pin supplies the programming
voltage to the EPROM.
Vcc,Vss
I
Power supply inputs: Vcc = 4.15~ 5.25V, Vss = 0V
RESET
I
under normal Vcc conditions). If the crystal or ceramic resonator requires more
9
16/74
13/73
To enter the reset state, this pin must be kept 'L' for more that 2µs (20 Φ cycles
10
time to stabilize, extend this 'L' level time appropriately.
XCin
I
XCout
O
Xin
I
Xout
O
LPF
O
Ext. Cap
I
An external ceramic or quartz crystal oscillator can be connected between the
XCin and XCout pins. If an external clock source is used, connect the clock
source to the XCin pin and leave the XCout pin open.
Input and output signals to and from the internal clock generation circuit.
Connect a ceramic resonator or quartz crystal between Xin and Xout pins to set
the oscillation frequency. If an external clock is used, connect the clock source
to the Xin pin and leave the Xout pin open.
Loop filter for the frequency synthesizer.
12
11
14
15
18
An external capacitor (Ext. Cap) pin. When the USB transceiver voltage
converter is used, a 2µf or larger capacitor should connect between this pin and
Vss to ensure proper operation of the USB line driver. The voltage converter is
enabled by setting bit 4 of the USB control register (0013 16) to a “1”.
4
72
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.6 PART NUMBERING
M 8 -XXX FP
M37640
Package Type:
FP: 80P6N
FS: 80D0
ROM Number
ROM capacity:
32 Kbytes
Memory type:
M: Mask ROM Version
E: EPROM version
One-time PROM version
7640 Group
7600 Series
Fig. 1.3. Type no., memory size, and package
1.7 ROM EXPANSION
Table 1.2. ROM Expansion
ROM
Size (Bytes)
32K
M37640M8-XXXFP
Mask ROM version
M37640E8FP
One-time PROM version
M37640E8FS
EPROM version
1.8 CURRENTLY SUPPORTED PRODUCTS
Table 1.3. Currently Supported Products
Type No.
M37640M8-XXXFP
M37640E8FP
M37640E8FS
ROM
RAM
capacity capacity
32K bytes 1 K bytes
32K bytes 1 K bytes
32K bytes 1 K bytes
Package
type
80P6N-A
80P6N-A
80D0
Remarks
Mask ROM version
One-time PROM version
EPROM version
5
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.9 CENTRAL PROCESSING UNIT
1.9.1 Register Structure
The central processing unit (CPU) has six registers:
Five of the CPU registers are 8-bit registers. These are
the Accumulator (A), Index register X (X), Index Register Y (Y), Stack pointer (S), and the Processor Status
register (PS) as shown in Figure 1.4.
• Accumulator (A)
• Index Register X (X)
• Index Register Y (Y)
The Program counter (PC) is a 16-bit register consisting of two 8-bit registers (PCH and PCL).
• Stack Pointer (S)
• Processor Status Register (PS)
After a hardware reset, bit 2 (I Flag) of the PS is set
high and the values at the address FFFA16 and
FFFB16 are stored in the PC, but the values of the
other bits of the PS and other registers are undefined.
Initialization of the undefined registers may be necessary for some programs.
• Program Counter (PC)
7
7
15
0
Index Register Y
0
7
Stack Pointer
0
7
0
PCL
7
6
Index Register X
0
7
PCH
Fig. 1.4. Register Structure
Accumulator
N V T B D I Z C
Program Counter
0
Processor Status Register
Carry Flag (bit 0)
Zero Flag (bit 1)
Interrupt Disable Flag (bit 2)
Decimal Mode Flag (bit 3)
Break Flag (bit 4)
Index X Mode Flag (bit 5)
Overflow Flag (bit 6)
Negative Flag (bit 7)
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.10 CPU MODE REGISTERS
This device has two CPU mode registers:
• CPU Mode Register A (CPMA)
• CPU Mode Register B (CPMB)
These registers control the processor mode, clock,
slow memory wait and other CPU functions. The bit
representation of each register is described in Figure
1.5 and Figure 1.6.
MSB
CPMA7
7
CPMA6 CPMA5
CPMA4 Re s e r v ed
CPMA2
CPMA1
Address: 0000 16
Access: R/W
Reset: OC 16
LSB
CPMA0 0
CPMA0,1
CPMA2
CPMA3
CPMA4
CPMA5
CPMA6
CPMA7
Processor Mode Bits (bits 1,0)
Bit 1
Bit 0
0
0: Single-Chip Mode
0
1: Memory Expansion Mode
1
0: Microprocessor Mode
1
1: Not Used
Stack Page Selection Bit (bit 2)
0:
In page 0 area
1:
In page 1 area
Reserved (Read/Write “1”)
Clock XCin - XCout Stop Bit (bit 4)
0:
Stop
1:
Oscillator
Clock Xin - Xout Stop Bit (bit 5)
0:
Oscillator
1:
Stop
Internal Clock Selection Bit (bit 6)
0: External Clock
1: fsyn
External Clock Selection Bit (bit 7)
0: Xin - Xout
1: XCin - XCout
Fig. 1.5. CPU Mode Register A (CPMA)
MSB
Re s e r ved Re s e r v ed
7
CPMB5
CPMB4
CPMB3
CPMB2
CPMB1
LSB
CPMB0 0
Address: 0001 16
Access: R/W
Reset: 83 16
CPMB0,1
CPMB2,3
CPB4
CPMB5
CPMB6
CPMB7
Slow Memory Wait Bits (bits 1,0)
Bit 1
Bit 0
0
0: No Wait
0
1: One time wait
1
0: Two time wait
1
1: Three time wait
Slow Memory Mode Bit (bit 3,2)
Bit 3
Bit 2
0
0: Software wait
0
1: Not used
1
0: Fixed wait by RDY pin L
1
1: Extended RDY wait
Expanded Data Memory Access Bit (bit 4)
0:EDMA output disabled (64 Kbyte data access area)
1:EDMA output enabled (greater than 64 Kbytes data access area)
Hold Function Enable Bit (bit 5)
0:HOLD Function Disabled
1:HOLD Function Enabled
Reserved (Read/Write “0”)
Reserved (Read/Write “1”)
Fig.1.6. CPU Mode Register B (CPMB)
7
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.11 MEMORY MAP
The first 112 bytes of memory from 000016 to 006F16
is the special function register (SFR) area and contains the CPU mode registers, interrupt registers, and
other registers to control peripheral functions (see
Figure 1.7).
000016
SFR Area
006F16
007016
Zero Page
RAM
00FF 16
010016
1K bytes
046F16
047016
Not Used
7FFF 16
800016
Reserved Area
807F16
808016
ROM
32K bytes
Special page for
subroutine calls
Interrupt
Vector
FEFF 16
FF0016
FFC916
FFCA16
FFFB16
FFFC16
Reserved Area
FFFF16
Fig. 1.7. Memory Map
8
The general purpose RAM resides from 007016 to
046F16. When the MCU is in memory expansion or
microprocessor mode and external memory is overlaid on the internal RAM, the CPU reads data from
the internal RAM. However, the CPU writes data in
both the internal and external memory. The area from
047016 to 7FFF16 is not used in single-chip mode, but
can be mapped for an external memory device when
the MCU is in memory expansion or microprocessor
mode.
The area from 800016 to 807F16 and from FFFC16 to
FFFF16 are factory reserved areas. Mitsubishi uses it
for test and evaluation purposes. The user can not
use this area in single-chip or memory expansion
modes.
The user 32K byte ROM resides from 808016 to
FFFB16. When the MCU is in microprocessor mode,
the CPU accesses an external area rather than accessing the internal ROM.
1.11.1 Special page
The 256 bytes from address FF0016 to FFFF16 are
called the special page area. In this area special page
addressing can be used to specify memory addresses. This dedicated special page addressing
mode enables access to this area with fewer instruction cycles. Frequently used subroutines are normally
stored in this area.
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.12 PROCESSOR MODES
The operation modes are described below. The memory
maps for the first three modes are shown in Figure 1.8.
Single chip mode is normally entered after reset. However, if the MCU has a CNVss pin, holding this pin high
will cause microprocessor mode to be entered after re-
Memory
Single Chip
Mode
0000
CPMA, CPMB and
Int Registers
P0 - P3
Microprocessor
Mode
Expansion Mode
0000
0007
0008
set. After the reset sequence has completed, the mode
can be changed with software by modifying the value of
bits 0 and 1 of CPMA. However, while CNVss is high,
bit 1 of CPMA is “1” and cannot be changed.
0007
0008
SFR
0000
CPMA, CPMB and
Int Registers
External Memory
0007
0008
SFR
000F
0010
000F
0010
006F
0070
006F
0070
006F
0070
(Zero Page)
00FF
0100
Internal RAM
046F
0470
00FF
0100
Reserved Area
807F
8080
Internal RAM
00FF
0100
7FFF
8000
Internal RAM
(Zero Page)
Internal RAM
046F
0470
External Memory
External Memory
Reserved Area
807F
8080
ROM
ROM
FFC9
FFCA
FFFB
FFFC
(Zero Page)
046F
0470
Inaccessible Area
7FFF
8000
Internal RAM
External Memory
SFR
000F
0010
Internal RAM
CPMA, CPMB and
Int Registers
FFC9
FFCA
Interrupt Vectors
Reserved Area
FFFF
FFFB
FFFC
FFFF
Interrupt Vectors
Reserved Area
FFFF
Fig. 1.8. Operation Modes Memory Maps
9
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
1.12.1 Single Chip
In this mode, all ports take on their primary function and
all internal memory is accessible. Those areas that are
not in internal memory are not accessible. Also, slow
memory wait and EDMA are disabled in this mode.
1.12.2 Memory Expansion
In this mode, Ports 0 and 1 output the address bus
(AB0-AB15), port 2 acts as the data bus input and output, and port 3 bits 7 to 3 output RD, WR, SYNCout, Fout,
and DMAout, respectively. All memory areas that are not
internal memory or SFR area are accessed externally.
Because ports 0 to 3 lose their normal function in this
mode, the address area for the ports and their direction
registers are treated as external memory. In this mode,
slow memory wait and EDMA can be enabled.
1.12.3 Microprocessor
This mode is primarily the same as memory expansion
mode. The difference is that the internal ROM/EPROM
area can not be accessed and is instead treated as
external memory. Slow memory wait and EDMA can be
enabled in this mode.
1.12.4 Slow Memory Wait
The wait function is used when interfacing with external
memories that are too slow to operate at the normal
read/write speed of the MCU. When this is the case, a
wait can be used to extend the read/write cycle. Three
different wait modes are supported; software wait, RDY
wait, and extended RDY wait. The appropriate mode is
chosen by the setting of bits 0 to 3 of CPMB. The wait
function is disabled for internal memory and is valid only
for memory expansion and microprocessor modes.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Software wait is used to extend the read/write cycle by
one, two, or three cycles of F. The cycle number is
determined by the value of bits 0 and 1 of CPMB. When
software wait is selected, the value on the RDY pin is
ignored. The timing for software wait is shown in Figure
1.9.
RDY wait is also used to extend the read/write cycle by
one, two, or three cycles F. In this case, the read/write
cycle is extended if the RDY pin is low when Fout goes
low (taking into account setup and hold times) at the
beginning of the read/write cycle. The extension time is
fixed by the value of bits 0 and 1 of CPMB and does not
depend on the state of the RDY pin once the read/write
cycle has begun. If the RDY pin is high when Fout goes
low at the beginning of the read/write cycle, the read/
write cycle is not extended. The timing for RDY wait is
shown in Figure 1.10.
The extended RDY wait mode is used to extend the
read/write cycle by a variable number of cycles of F.
The exact number is dependent on the state of the RDY
pin and the value of bits 0 and 1 of CPMB. In this mode,
the read/write cycle is extended if the RDY pin is low
when Fout goes low at the beginning of the read/write
cycle. The read/write cycle continues to be extended
until the RDY pin is high when Fout goes low, at which
point the read/write cycle completes in one, two, or three
cycles of F (with respect to the previous low to high
transition of F), dependent on the value in bits 0 and 1
of CPMB. If the RDY pin is high when Fout goes low at
the beginning of the read/write cycle, the read/write cycle
is not extended. The timing for this mode is shown in
Figure 1.11.
The wait function can only be enabled for external
memory access in microprocessor or memory expansion modes. However, the wait function can not be enabled for accesses to addresses 000816 to 000F16 (Port
0 through Port 3 registers) in these modes, even though
the locations are mapped as external memory.
10
Ver 1.4
Fig. 1.9. Software Wait Timing Diagram
Xin
P1
P2
Φout
ADout
DBin/out
In
Out
In
Out
Out
In
RD
WR
RDY
One Time S/W Wait
CPMB = 0116
CPMB = 0016
Two Time S/W Wait
CPMB = 0216
P1
Φout
ADout
In
Out
RD
WR
11
RD
Three Time S/W Wait
Internal Signals
7640 Group
DBin/out
MITSUBISHI MICROCOMPUTERS
P2
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Xin
No Wait
Ver 1.4
Fig. 1.10. RDY Wait Timing Diagram
12
Xin
P1
P2
Φout
ADout
DBin/out
In
In
Out
In
Out
Out
RD
WR
tsu
tsu
tsu
tsu
RDY
One Time Fixed Wait
No Wait
CPMB = 0916
CPMB = 0816
CPMB = 0A16
P1
Φout
ADout
DBin/out
In
Out
tsu
WR
tsu
RDY
Three Time Fixed Wait
CPMB = 0B16
Internal
Signals
7640 Group
RD
MITSUBISHI MICROCOMPUTERS
P2
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Xin
Two Time Fixed Wait
Ver 1.4
Fig. 1.11. Extended RDY Wait Timing Diagram
Xin
P1
P2
Φout
ADout
DBin/out
In
In
Out
Out
In
RD
WR
tsu
tsu
tsu
tsu
/////////
tsu
tsu
tsu
tsu
RDY
tsu
tsu
tsu
tsu
tsu
/////////
One Time Extended RDY Wait
No Wait
Two Time Extended RDY Wait
CPMB = 0D16
CPMB = 0C16
CPMB = 0E16
Xin
P2
ADout
DBin/out
RD
tsu
tsu
Out
In
Out
tsu
tsu
tsu
tsu
tsu
tsu
tsu
tsu
tsu
tsu
tsu
tsu
tsu
tsu
tsu
RDY
Two Time Extended RDY Wait
CPMB = OE16
Three Time Extended RDY Wait
CPMB = 0F16
Internal
Signals
13
7640 Group
WR
MITSUBISHI MICROCOMPUTERS
Φout
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
P1
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.12.5 Hold Function
1.12.6 Expanded Data Memory Access
The hold function is used when the MCU is put in a
system where more than one device will need control
of the external address and data buses. Two signals
are used to implement this function, HOLD (P71) and
HLDA (P73). HOLD is an input to the MCU and is
brought low when an external device wants the MCU
to relinquish the address and data buses. HLDA is an
output from the MCU that signals when the MCU has
relinquished the buses. When this is the case, the
MCU tri-state ports 0 and 1 (address bus) and port 2
(data bus), and holds port P37 (RD) and port P36
(WR) high. Ports P37 and P36 are held high to prevent any external device that is enabled by RD or WR
from being falsely activated. The clocks to the CPU
are stopped, but the peripheral clocks and port P34
(Fout) continue to oscillate. HOLD is brought high to
allow the MCU to regain the address and data buses.
When this occurs, HLDA will go high and ports P1, P2,
P37 and P36 will begin to drive the external buses
again. The timing for the hold function is shown in Figure 1.12. The hold function is only valid for memory
expansion and microprocessor modes. Bit 5 of CPMB
is used to enable the hold function. HLDA will loose
its function when the IBF1 pin functionality is used.
The Expanded Data Memory Access (EDMA) mode
feature allows the user to access a greater than 64
Kbyte data area for instructions LDA (IndY) with T=“0”
and T=“1”, and STA (IndY). Bit 4 of CPMB is used to
enable/disable the EDMA function. If bit 4 of CPMB
equals “1”, then during the data read/write cycle of instructions LDA (IndY) and STA (IndY) Port 40 (EDMA)
is driven low. The EDMA signal output can be used by
an external decoder to indicate when the read/write is
to a different 64 Kbyte bank. The actual determination
of which bank to access can be done by using a few
bits of a port to represent the extended addresses
above AB15. For example, if four banks are accessed,
then two bits are needed to uniquely identify each
bank. Two port bits can be used for this, one representing AB16 and the other AB17. The instruction
sequences for STA (IndY) and LDA (IndY) are shown in
Figure 1.13 and Figure 1.14.
XIN
////////
Φout
////////
------
RD, WR
-----------
ADDRout
DATAin/out
tsu(HOLD-Φout)
HOLD
th(Φout-HOLD)
-----td(Φout-HLDA)
HLDA
Fig. 1.12. Hold Function Timing Diagram
14
------
td(Φout-HLDA)
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Φ
SYNCout
RD
WR
Address
PC
Data
PC +1
BAL, 00
BAL
91
BAL+1, 00
ADL+Y,ADH
Invalid
ADH
ADL
ADL+Y,
ADH+C
PC + 2
Data
Next
OpCode
EDMA
Fig. 1.13. Instruction sequences for STA ($zz) IndY with EDMA Enable
[LDA ($zz),Y (T = “0”)] Instruction Sequence (EDMA)
Φ
SYNCout
RD
WR
Address
PC
PC +1
BAL
B1
Data
BAL, 00
BAL+1, 00
ADL
ADL+Y,ADH
ADH
ADL+Y,
ADH+C
Invalid
PC + 2
Data
Next
OpCode
EDMA
[LDA ($zz),Y (T = “1”)] Instruction Sequence (EDMA)
Φ
SYNCout
RD
WR
Address
Data
PC
PC +1
B1
BAL, 00
BAL
BAL+1, 00
ADL
ADL+Y,ADH
ADH
Invalid
ADL+Y,
ADH+C
X, 00
Data
Invalid
PC
Data
2
Next
OpCode
EDMA
Fig. 1.14. Instruction sequences for LDA ($zz) IndY with EDMA Enable
15
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.13 SPECIAL FUNCTION REGISTERS
The special function registers (SFR) are used for
controlling the functional blocks, such as I/O ports,
Timers, UART, and so forth (see Table 1.4). The reserved addresses should not be read or written to.
Table 1.4.
SFR Addresses
Addr
Description
Acronym and
Value at Reset
Addr
Description
Acronym and
Value at Reset
000016
CPU Mode Register A
CPMA=0C
003816
UART2 Mode Register
U2MOD=00
000116
CPU Mode Register B
CPMB=83
003916
UART2 Baud Rate Generator
U2BRG=XX
000216
Interrupt Request Register A
IREQA=00
003A16
UART2 Status Register
U2STS=03
000316
Interrupt Request Register B
IREQB=00
003B16
UART2 Control Register
U2CON=00
000416
Interrupt Request Register C
IREQC=00
003C16
UART2 Transmit/Receiver Buffer 1
U2TRB1=XX
000516
Interrupt Control Register A
ICONA=00
003D16
UART2 Transmit/Receiver Buffer 2
U2TRB2=XX
000616
Interrupt Control Register B
ICONB=00
003E16
UART2 RTS Control Register
U2RTSC=80
000716
Interrupt Control Register C
ICONC=00
003F16
DMAC Index and Status Register
DMAIS=00
000816
Port P0
P0=00
004016
DMAC Channel x Mode Register 1
DMAxM1=00
000916
Port P0 Direction Register
P0D=00
004116
DMAC Channel x Mode Register 2
DMAxM2=00
000A16
Port P1
P1=00
004216
DMAC Channel x Source Register Low
DMAxSL=00
000B16
Port P1 Direction Register
P1D=00
004316
DMAC Channel x Source Register High
DMAxSH=00
000C16
Port P2
P2=00
004416
DMAC Channel x Destination Register Low
DMAxDL=00
000D16
Port P2 Direction Register
P2D=00
004516
DMAC Channel x Destination Register High
DMAxDH=00
000E16
Port P3
P3=00
004616
DMAC Channel x Count Register Low
DMAxCL=00
000F16
Port P3 Direction Register
P3D=00
004716
DMAC Channel x Count Register High
DMAxCH=00
001016
Port Control Register
PTC=00
004816
Data Bus Buffer register 0
DBB0=00
001116
Interrupt Polarity Selection Register
IPOL=00
004916
Data Bus Buffer status register 0
DBBS0=00
001216
Port P2 pull-up Control Register
PUP2=00
004A16
Data Bus Buffer Control Register 0
DBBC0=00
001316
USB Control Register
USBC=00
004B16
Reserved
001416
Port P6
P6=00
004C16
Data Bus Buffer register 1
DBB1=00
001516
Port P6 Direction Register
P6D=00
004D16
Data Bus Buffer Status Register 1
DBBS1=00
001616
Port P5
P5=00
004E16
Data Bus Buffer Control Register 1
DBBC1=00
001716
Port P5 Direction Register
P5D=00
004F16
Reserved
001816
Port P4
P4=00
005016
USB Address Register
USBA=00
001916
Port P4 Direction Register
P4D=00
005116
USB Power Management Register
USBPM=00
001A16
Port P7
P7=00
005216
USB Interrupt Status Register 1
USBIS1=00
001B16
Port P7 Direction Register
P7D=00
005316
USB Interrupt Status Register 2
USBIS2=00
001C16
Port P8
P8=00
005416
USB Interrupt Enable Register 1
USBIE1=FF
001D16
Port P8 Direction Register
P8D=00
005516
USB Interrupt Enable Register 2
USBIE2=33
001E16
Reserved
005616
USB Frame Number Register Low
USBSOFL=00
001F16
Clock Control Register
CCR=00
005716
USB Frame Number Register High
USBSOFH=00
002016
Timer XL
TXL=FF
005816
USB Endpoint Index
USBINDEX=00
002116
Timer XH
TXH=FF
005916
USB Endpoint x IN CSR
IN_CSR=00
002216
Timer YL
TYL=FF
005A16
USB Endpoint x OUT CSR
OUT_CSR=00
002316
Timer YH
TYH=FF
005B16
USB Endpoint x IN MAXP
IN_MAXP (endpoint dependent)
002416
Timer 1
T1=FF
005C16
USB Endpoint x OUT MAXP
OUT_MAXP (endpoint dependent)
002516
Timer 2
T2=01
005D16
USB Endpoint x OUT WRT_CNT Low
WRT_CNTL=00
002616
Timer 3
T3=FF
005E16
USB Endpoint x OUT WRT_CNT High
WRT_CNTH=00
002716
Timer X Mode Register
TXM=00
005F16
Reserved
002816
Timer Y Mode Register
TYM=00
006016
USB Endpoint 0 FIFO
USBFIFO0=N/A
002916
Timer 123 Mode Register
T123M=00
006116
USB Endpoint 1 FIFO
USBFIFO1=N/A
002A16
SIO Shift Register
SIOSHT=XX
006216
USB Endpoint 2 FIFO
USBFIFO2=N/A
002B16
SIO Control Register 1
SIOCON1=40
006316
USB Endpoint 3 FIFO
USBFIFO3=N/A
002C16
SIO Control Register 2
SIOCON2=18
006416
USB Endpoint 4 FIFO
USBFIFO4=N/A
002D16
Special Count Source Generator1
SCSG1=FF
006516
Reserved
002E16
Special Count Source Generator2
SCSG2=FF
006616
Reserved
002F16
Special Count Source Mode Register
SCSM=00
006716
Reserved
003016
UART1 Mode Register
U1MOD=00
006816
Reserved
003116
UART1 Baud Rate Generator
U1BRG=XX
006916
Reserved
003216
UART1 Status Register
U1STS=03
006A16
Reserved
003316
UART1 Control Register
U1CON=00
006B16
Reserved
003416
UART1 Transmit/Receiver Buffer 1
U1TRB1=XX
006C16
Freq Synthesizer Control
FSC=60
003516
UART1 Transmit/Receiver Buffer 2
U1TRB2=XX
006D16
Freq Synthesizer Multiply Register 1
FSM1=FF
003616
UART1 RTS Control Register
U1RTSC=80
006E16
Freq Synthesizer Multiply Register 2
FSM2=FF
003716
Reserved
006F16
Freq Synthesizer Divide Register
FSD=FF
16
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.14 INPUT AND OUTPUT PORTS
Table 1.5. Input and Output Ports
Pin
Name
P00 – P07
Port 0
P10 – P17
Port 1
Port 2
P20 – P27
Port 3
P30 – P37
Input/
Output
I/O
Format
Non-Port
Function
Related
SFR’s
Input/output,
individual bits
CMOS I/O
port
Address Bus
CPU Mode Register
Input/output,
individual bits
CMOS I/O
port
Address Bus
CPU Mode Register
Input/output,
individual bits
CMOS I/O
port
Data Bus
CPU Mode Register
Input/output,
CMOS I/O
individual bits
port
Control signal I/O
CPU Mode Register
Expanded Data Memory
CPU Mode Register
Ref. Number
Fig. 1.15
Fig. 1.15
Fig. 1.15
Fig. 1.15
Fig. 1.16
P40
Access
P41
External Interrupt Input
Interrupt Edge
(INT0)
Selection Register
External Interrupt Input
(INT1)
Interrupt Edge
Selection Register
Fig. 1.16
P43
External Interrupt Input
(CNTR0)
Timer X Mode
Register
Fig. 1.16
P44
External Interrupt Input
(CNTR1)
Timer Y Mode
Register
Fig. 1.16
P50
Xcin
CPU Mode Register
Fig. 1.17
CPU Mode Register
Fig. 1.17
P42
Port 4
Input/output,
individual bits
CMOS I/O
port
P51
P52
Xcout or T out
Port 5
Input/output,
individual bits
CMOS I/O
port
Fig. 1.16
or T123 Mode
Register
OBF0 Output
MBI Interface
Fig. 1.17
P53
IBF0 Output
MBI Interface
Fig. 1.17
P54
S0 Input
MBI Interface
Fig. 1.17
P55
A0 Input
MBI Interface
Fig. 1.17
P56
R(E) Input
MBI Interface
Fig. 1.17
W(R/W) Input
MBI Interface
Fig. 1.17
MBI Interface
Fig. 1.18
SOF Output
USB Interface
Fig. 1.19
HOLD
CPU Mode Register
Fig. 1.19
S1 Input
MBI Interface
Fig. 1.19
P73
IBF1 Output
MBI Interface
Fig. 1.19
P74
OBF1 Output
MBI Interface
Fig. 1.19
Fig. 1.20
P80
UTXD2/SRDY
UART Mode
Register/SIO Mode
Register
URXD2/SCLK
UART Mode
Register/SIO Mode
Fig. 1.20
P81
P57
Port 6
P60– P67
Input/output,
CMOS I/O
individual bits
port
Input/output,
individual bits
CMOS I/O
port
P70
P71
P72
Port 7
Master CPU data bus
Register
UART Mode
P82
P83
P84
P85
P86
P87
Port 8
Input/output,
CMOS I/O
individual bits
port
CTS2/STXD
Register/SIO Mode
Register
RTS2/SRXD
Register/SIO Mode
Register
UART Mode
Fig. 1.21
Fig. 1.21
UTXD1
UART Mode
Register
Fig. 1.21
UART Mode
Register
Fig. 1.22
URXD1
UART Mode
Fig. 1.22
CTS1
RTS1
Register
UART Mode
Fig. 1.22
Register
17
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.14.1 I/O Ports
This device has 66 programmable I/O pins arranged
as ports P00 to P87. Each port bit can be configured
as input or output. To set the I/O port bit direction,
write a “1” to the corresponding direction register bit
to select output mode, or write a “0” to the direction
register bit to select input mode.
At reset, all of the direction registers are initialized to
0016, setting all of the I/O ports to input mode.
If data is written to a pin and then read from that pin
while it is in output mode, the data read is the value of
the port latch rather than the value of the pin itself.
Therefore, if an external load changes the value of an
output pin, the intended output value will still be read
correctly. Pins set to input mode are floating (provided that the pull up resistors are not being used) to
ensure that the value input to such a pin can be read
accurately. In the case when data is written to a pin
configured as an input, the data is written only to the
port latch; the pin itself remains floating.
Most of the I/O Ports are multiplexed with secondary
functions. When a GPI/O is multiplexed with a second function, the control signal from the peripheral
overrides the direction register. The multiplexing is
briefly described below. The second function signals
to and from the I/O ports are described in detail in
their respective block’s description.
1.14.1.1 Ports P0, P1, and P3
Ports P0 and P1 act as the address bus (AB0-AB15)
in Microprocessor and Memory Expansion modes.
Bits 0 and 3-7 of Port P3 acts as control signals in
Microprocessor and Memory Expansion modes.
1.14.1.2 Port P2
Port P2 is an 8-bit general purpose I/O port when in
single chip mode. In this mode, the port has key-on
wake up circuitry which can be used to restart the
chip externally from a WIT or STP low power mode.
This port also acts as the data bus during microprocessor and memory expansion modes. Port P2 input
level can be set to reduced VIHL level or CMOS level
by bit 6 of the port control register (PTC).
Ports P0, P1, P3
Direction Register
Data Bus
Port Latch
Port P2
Pull-up Control
Direction Register
Data Bus
Port Latch
Key-on Wake up Input
Fig. 1.15. Ports P0, P1, P2, P3 Block Diagram
18
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.14.1.3 Port P4
Port P43- P44
Port 4 is a 5-bit general purpose I/O port that can be
configured to access special second functions. The
port can be set up in any configuration in all three processor modes.
These pins are multiplexed with Timer X and Y functions for P43 and P44 respectively. The timer
functions of the pins are independently defined by
configuring the timer peripheral. P43 acts as Timer X
input pin for pulse width measurement mode and
event counter mode or as Timer X output pin for pulse
output mode. P43 can also be used as an external interrupt (CNTR0) when Timer X in not in output mode.
The polarity is selected in the Timer X mode register.
The external interrupt function is enabled by setting
the bit to “1” in the interrupt control register that corresponds to CNTR0. See section 1.15.1 for more
information on configuring interrupts.
Port P40
This pin is multiplexed with the EDMA (Extended
Data Memory Access) function. When the MCU is in
memory expansion or microprocessor mode and
CPMB4 is set to “1”, this pin operates as the EDMA
output as described in section 1.12.6.
Port P41- P42
These pins are multiplexed with external interrupts 0
and 1 (INT0 and INT1). The external interrupt function
is enabled by setting the bits to “1” in the interrupt
control register that correspond to INT0 and INT1.
The interrupt polarity register can be configured to define INT0 and INT1 as active high or low interrupts.
See section 1.15.1 for more information on configuring interrupts.
P44 acts as Timer Y input pin for pulse period measurement mode, pulse H-L measurement mode, and
event counter mode or as Timer Y output pin for pulse
output mode. P43 can also be used as an external interrupt (CNTR1) when Timer Y in not in output mode.
The polarity is selected in the Timer Y mode register.
The external interrupt function is enabled by setting
the bit to “1” in the interrupt control register that corresponds to CNTR1. See section 1.15.1 for more
information on configuring interrupts.
Port P40
CPMB4
Direction Register
Port P43 and P44
Data Bus
Port Latch
Timer Counter Input Enable
Pulse Output Mode Enable
Direction Register
EDMA Signal
Data Bus
Port Latch
Port P41 and P42
Direction Register
Timer X, Y Output
CNTR0, 1 Input
Data Bus
Port Latch
Interrupt Input
Fig. 1.16. Port P4 Block Diagram
19
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.14.1.4 Port P5
Port 5 is an 8-bit general purpose I/O port that can be
configured to access special second functions. The
port can be set up in any configuration in all three processor modes.
Port P50
This pin is multiplexed with the XCin clock input.
When the XCin clock is activated, the pin’s I/O is disabled.
Port P51
This pin is multiplexed with the XCout clock output
and the Timer 1/2 pulse output. When the XCin clock
is activated, the pin’s I/O is disabled. If XCin is not be-
Port P50
ing used as a system clock or XCout oscillation is disabled, the pin can be configured as the Timer 1/2
pulse output pin. This feature is configured in the
Timer123 mode register as described in section 1.17.
Port P52- P57
These pins are multiplexed with control pins for the
bus interface control block. P52 acts as OBF0 output
to a Master CPU when DBBC00 is “1”.
P53 acts as IBF0 output to a Master CPU when
DBBC01 is “1”.
P54-P57 act as input control signals from a Master
CPU when DBBC06 is “1”. The table featured in Figure 1.17 shows the bus interface control signal that
corresponds to each pin.
Port P53
CPMA4
DBBC01
Direction Register
Direction Register
Data Bus
Port Latch
CPMA4
Data Bus
Port Latch
CPMA4
IBF0
XCin Input
Port P51
Port P54 - P57
DBBC06
Tout Enable Bit
Direction Register
Direction Register
Data Bus
Port Latch
Data Bus
Port Latch
DBBC06
see table
for function
Timer 1/2 Output
Port 54 - P57 Function
Port 52
DBBC00
Direction Register
Data Bus
Port Latch
OBF0
Fig. 1.17. Port P5 Block Diagram
20
Pin
Function
P54
S0
P55
A0
P56
R(E)
P57
W(R/W)
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.14.1.5 Port P6
Port P6 is an 8-bit general purpose I/O port that can
be configured to access special second functions.
The port acts as the data bus interface for the bus interface control block when DBBC06 is “1”. The port
can be set up in any configuration in all three processor modes.
Port P6
MBI Write
S0
S1
MBI Read
Direction Register
Data Bus
Port Latch
S0
MBI Read
Output Buffer 0
A0
Status Register 0
S1
MBI Read
Output Buffer 1
A1
Status Register 1
S0
MBI Write
S1
MBI Write
Input Buffer 0
Input Buffer 1
Fig. 1.18. Port P6 Block Diagram
21
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.14.1.6 Port P7
Port P73
Port P7 is a 5-bit general purpose I/O port that can be
configured to access special second functions.
This pin is multiplexed with the IBF1 output control
signal for a Master CPU and the HLDA function.
When DBBC11 and DBBC17 are “1”, the pin takes on
the function of the IBF1 output control signal. When
the MCU is in memory expansion or microprocessor
mode, CPMB5 is set to “1”, and the IBF1 function is
not enabled.
Port P70
This pin is multiplexed with the USB start of frame
pulse (SOF) output. When USBC6 is a “1”, this pin
outputs the USB SOF.
Port P71
This pin is multiplexed with the HOLD function. When
the MCU is in memory expansion or microprocessor
mode and CPMB5 is set to “1”.
Port P72
Port P74
This pin is multiplexed with the OBF1 control pin for
the bus interface control block. P74 acts as OBF1 output to a Master CPU when DBBC10 and DBBC17 are
“1”.
This pin is multiplexed with the S1 input control signal
from a Master CPU. When DBBC17 is “1”, the pin
takes on the function of the S1 input control signal.
Port P70
Port P73
USBC6
Direction Register
Data Bus
DBBC11
DBBC17
CPMB5
Port Latch
Direction Register
Data Bus
SOF
Port P71
Port Latch
CPMB5
IBF1
Direction Register
HLDA
Data Bus
Port Latch
CPMB5
Port P74
DBBC10
DBBC17
HOLD
Direction Register
Port P72
DBBC17
Data Bus
Direction Register
Data Bus
Port Latch
Port Latch
OBF1
DBBC17
S1
Fig. 1.19. Port P7 Block Diagram
22
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.14.5.7 Port 8
Port 8 is an 8-bit general purpose I/O port that can be
configured to access special second functions. The
port can be set up in any configuration in all three processor modes.
Port P80
This pin is multiplexed with the SIO SRDY signal and
the UART2 TxD signal. When UART2 is in transmit
mode, the pin acts as the TxD output signal. When
the pin is not being used as the UART2 TxD output
and bit 4 of the SIO control register 1 (SIOCON1) is a
“1”, the port acts as the SIO SRDY output signal. If
during this function, the SIO is configured in slave
mode, this pin acts as a slave input from a master.
See section 1.18 for more SIO information.
Port P81
This pin is multiplexed with the SIO SCLK signal and
the UART2 RxD signal. When UART2 is in receive
mode, the pin acts as the RxD input signal. When the
pin is not being used as the UART2 RxD input and bit
Port P80
2 of the SIO control register 1 (SIOCON1) is a “1”, the
port acts as the SIO SCLK signal. In this mode a “1”
in bit 6 of SIOCON1 configures the pin to output
SCLK whereas a “0” configures the pin to input SCLK.
Port P82
This pin is multiplexed with the SIO SRxD signal and
the UART2 CTS signal. When bit 5 of the UART2
control register (U2CON) is a “1”, the port acts as the
CTS input signal. When the pin is not being used as
the UART2 CTS input and bit 2 of the SIO control register 2 (SIOCON2) is a “1”, the port acts as the SIO
SRxD input signal.
Port P83
This pin is multiplexed with the SIO STxD signal and
the UART2 RTS signal. When bit 6 of the UART2
control register (U2CON) is a “1”, the port acts as the
RTS output signal. When the pin is not being used as
the UART2 RTS output and bit 3 of the SIO control
register 1 (SIOCON1) is a “1”, the port acts as the
SIO STxD output signal.
Port P82
SRDY Output Selection Bit
UART2 Transmit Control Bit
SIO Receive Enable Bit
UART2 CTS Enable Bit
SIO Slave mode selection bit
Direction Register
Direction Register
Data Bus
Data Bus
Port Latch
Port Latch
UART2 CTS Enable Bit
SIO Ready Output
SIO Slave mode selection bit
UART2 CTS input
UART2 TxD Output
SIO slave control
Port P81
SIO RxD input
Port P83
SIO Clock Selection Bit
SIO Port Selection Bit
P-Channel Output Disable Bit
UART2 receive control bit
Transmit Complete Signal
UART2 receive control Bit
SIO Port Selection Bit
Direction Register
UART2 RTS Enable Bit
Data Bus
Port Latch
Direction Register
SIO Clock Selection Bit
SIO Clock Output
Data Bus
Port Latch
UART2 receive control bit
UART2 RxD input
SIO TxD Output
UART2 RTS Output
SIO clock input
Fig. 1.20. Port P8 0, P81, P82, P83 Block Diagram
23
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Port P84
Port P86
This pin is multiplexed with the UART1 TxD signal.
When UART1 is in transmit mode, the pin acts as the
TxD output signal.
This pin is multiplexed with the UART1 CTS signal.
When bit 5 of the UART1 control register (U1CON) is
a “1”, the port acts as the CTS input signal.
Port P85
Port P87
This pin is multiplexed with the UART1 RxD signal.
When UART1 is in receive mode, the pin acts as the
RxD input signal.
This pin is multiplexed with the UART1 RTS signal.
When bit 6 of the UART1 control register (U1CON) is
a “1”, the port acts as the RTS output signal.
Port P86
Port P84
UART1 CTS Enable Bit
UART1 Transmit Control Bit
Direction Register
Direction Register
Data Bus
Port Latch
Data Bus
Port Latch
UART1 TxD Output
UART1 CTS input
Port P87
Port P85
UART1 RTS Enable Bit
UART1 receive control Bit
Direction Register
Direction Register
Data Bus
Data Bus
Port Latch
UART1 RxD Input
Fig. 1.21. Port P84, P85, P86 and P87 Block Diagram
24
Port Latch
UART1 RTS Output
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.14.2 Port Control Register (PTC)
1.14.3 Port P2 Pull-up Control Register (PUP2)
This device is equipped with a port control register to
turn on and off the slew rate control and to control the
input levels for Port P2 and the MBI pins (see Figure
1.22).
This device is equipped with internal pull ups on Port
P2 that can be enabled by software. Each bit of the
pull-up control register controls a corresponding pin of
Port P2. The pull-up control register pulls up the port
when the port is in input mode. The value of the pullup control regsiter has no effect when the port is in
output mode (see Figure 1.23).
MSB
7
PTC7
PTC6
PTC5
PTC4
PTC3
PTC2
PTC1
PTC0
L S B Address: 0010 16
Access: R/W
0
Reset: 00 16
PTC0
PTC1
PTC2
PTC3
PTC4
PTC5
PTC6
PTC7
Slew Rate Control Bit Ports P0-P3 (bit 0)
0 : Disabled
1 : Enabled
Slew Rate Control Bit Port P4 (bit 1)
0 : Disabled
1 : Enabled
Slew Rate Control Bit Port P5 (bit 2)
0 : Disabled
1 : Enabled
Slew Rate Control Bit Port P6 (bit 3)
0 : Disabled
1 : Enabled
Slew Rate Control Bit Port P7 (bit 4)
0 : Disabled
1 : Enabled
Slew Rate Control Bit Port P8 (bit 5)
0 : Disabled
1 : Enabled
Port P2 Input Level Select Bit (bit 6)
0 : Reduced VIHL Level Input
1 : CMOS level input
Master Bus Input Level Select Bit (bit 7)
0 : CMOS level input
1 : TTL level input
Fig. 1.22. Port Control Register (PTC)
MSB
7
PUP2 7
PUP2 6
PUP2 5
PUP2 4
PUP2 3
PUP2 2
PUP2 1
PUP2 0
L S B Address: 0012 16
Access: R/W
0
Reset: 00 16
PUP2 0
PUP2 1
PUP2 2
PUP2 3
PUP2 4
PUP2 5
PUP2 6
PUP2 7
Pull-up Control for
0 : Disabled
1 : Enabled
Pull-up Control for
0 : Disabled
1 : Enabled
Pull-up Control for
0 : Disabled
1 : Enabled
Pull-up Control for
0 : Disabled
1 : Enabled
Pull-up Control for
0 : Disabled
1 : Enabled
Pull-up Control for
0 : Disabled
1 : Enabled
Pull-up Control for
0 : Disabled
1 : Enabled
Pull-up Control for
0 : Disabled
1 : Enabled
Port P2 (bit 0)
Port P2 (bit 1)
Port P2 (bit 2)
Port P2 (bit 3)
Port P2 (bit 4)
Port P2 (bit 5)
Port P2 (bit 6)
Port P2 (bit 7)
Fig. 1.23. Pull-up Control Register (PUP2)
25
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.15 INTERRUPT CONTROL UNIT
Table 1.6. Interrupt Registers
This section details a specialized peripheral, the interrupt control unit (ICU).
This series supports a maximum of 23 maskable interrupts, one software interrupts, and one reset vector
that is treated as a non-maskable interrupt.
Table 1.6 describes the interrupt registers. See Table
1.7 for the interrupt sources, jump destination addresses, interrupt priorities, and section references
for the interrupt request sources.
Address
000216
000316
000416
000516
000616
000716
001116
Description
Acronym and
Value at Reset
Interrupt request register A
Interrupt request register B
Interrupt request register C
Interrupt control register A
Interrupt control register B
Interrupt control register C
Interrupt polarity selection
register
IREQA=00
IREQB=00
IREQC=00
ICONA=00
ICONB=00
ICONC=00
IPOL=00
Table 1.7. Interrupt Vector
Priority
Interrupt
Jump Destination
Storage Address
(Vector Address)
High-order
Byte
Low-order
Byte
Reference
1
RSRV1
FFFF
FFFE
2
RSRV2
FFFD
FFFC
Reserved for factory use
Reserved for factory use
3
FFFB
FFFA
User RESET (Non-Maskable)
4
RESET
USB
FFF9
FFF8
USB Function Interrupt
0
5
SOF
FFF7
FFF6
USB SOF Interrupt
1
6
INT0
FFF5
FFF4
External Interrupt 0
2
7
INT1
FFF3
FFF2
External Interrupt 1
3
8
DMA1
FFF1
FFF0
DMAC Channel 0 Interrupt
4
LSB
DMA2
FFEF
FFEE
DMAC Channel 1 Interrupt
5
U1RBF
FFED
FFEC
UART1 Receiver Buffer Full
6
11
U1TX
FFEB
FFEA
UART1 Transmit Interrupt
7
MSB
LSB
FFE9
FFE8
UART1 Error Sum Interrupt
0
U2RBF
FFE7
FFE6
UART2 Receiver Buffer Full
1
IREQB & ICONB
U1ES
13
U2TX
FFE5
FFE4
UART2 Transmit Interrupt
2
15
U2ES
FFE3
FFE2
UART2 Error Sum Interrupt
3
16
TX
FFE1
FFE0
Timer X Interrupt
4
17
TY
FFDF
FFDE
Timer Y Interrupt
5
18
T1
FFDD
FFDC
Timer 1 Interrupt
6
19
T2
FFDB
FFDA
Timer 2 Interrupt
7
MSB
20
T3
FFD9
FFD8
Timer 3 Interrupt
0
LSB
21
CNTR0
FFD7
FFD6
External CNTR0 Interrupt
1
22
CNTR1
FFD5
FFD4
External CNTR1 Interrupt
2
23
SIO
FFD3
FFD2
SIO Interrupt
3
24
IBF
FFD1
FFD0
Input Buffer Full Interrupt
4
25
OBE
FFCF
FFCE
Output Buffer Empty Interrupt
5
26
KEY
FFCD
FFCC
Key-on Wake Up
6
27
BRK
FFCB
FFCA
BRK Instruction (Non-Maskable)
IREQC & ICONC
14
MSB
Section 1.21.2.2
Section 1.15.1
Section 1.15.1
Section 1.23
Section 1.23
Corresponding Register Assignment
9
10
12
Section 1.21.2.1
IREQA & ICONA
26
Remarks
Section 1.19.4.2
Section 1.19.4.1
Section 1.19.4.2
Section 1.19.4.2
Section 1.19.4.1
Section 1.19.4.2
Section 1.17
Section 1.17
Section 1.17
Section 1.17
Section 1.17
Section 1.17.1.2
Section 1.17.2
Section 1.18
Section 1.22
Section 1.22
Section 1.16
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.15.1 Interrupt Control
Each maskable interrupt has associated with it an interrupt request bit and an interrupt enable bit. These
bits, along with the I flag, determine whether interrupt
events can cause an interrupt service request to be
generated. An interrupt request bit is set to “1” when
its corresponding interrupt event is activated. The bit is
cleared to a “0” when the interrupt is serviced or when
a “0” is written to the bit. The bit can not be set high
by writing “1” to it. Each interrupt enable bit deter-
MSB
7
IRA7
IRA6
IRA5
IRA4
IRA3
IRA2
IRA1
IRA0
mines whether the interrupt request bit it is paired with
is seen when the interrupts are polled. When the interrupt enable bit is a “0”, the interrupt request bit is not
seen; and when the enable bit is a “1”, the interrupt request is seen.
The interrupt request registers (IREQ) for the 23
maskable interrupts are shown in Figure 1.24, Figure
1.25, and Figure 1.26. The interrupt control registers
(ICON) for the 23 maskable interrupts are shown in
Figure 1.27, Figure 1.28, and Figure 1.29.
LSB
0
Address:
Access:
Reset:
IRA 0
IRA 1
IRA 2
IRA 3
IRA 4
IRA 5
IRA 6
IRA 7
000216
R/W
0016
USB Function Interrupt Request (bit 0)
USB SOF Interrupt Request (bit 1)
External Interrupt 0 Request (bit 2)
External Interrupt 1 Request (bit 3)
DMAC channel 0 Interrupt Request (bit 4)
DMAC channel 1 Interrupt Request (bit 5)
UART1 Receive Buffer Full Interrupt Request (bit 6)
UART1 Transmit Interrupt Request (bit 7)
0: No interrupt request issued
1: Interrupt request issued
Fig. 1.24. Interrupt Request Register A (IREQA)
MSB
7
IRB7
IRB6
IRB5
IRB4
IRB3
IRB2
IRB1
IRB0
LSB
0
Address:
Access:
Reset:
IRB 0
IRB 1
IRB 2
IRB 3
IRB 4
IRB 5
IRB 6
IRB 7
000316
R/W
0016
UART1 Error Sum Interrupt Request (bit 0)
UART2 Receive Buffer Full Interrupt Request (bit 1)
UART2 Transmit Interrupt Request (bit 2)
UART2 Error Sum Interrupt Request (bit 3)
Timer X Interrupt Request (bit 4)
Timer Y Interrupt Request (bit 5)
Timer 1 Interrupt Request (bit 6)
Timer 2 Interrupt Request (bit 7)
0: No interrupt request issued
1: Interrupt request issued
Fig. 1.25.
MSB
Interrupt Request Register B (IREQB)
Reserved
IRC6
IRC5
IRC4
IRC3
IRC2
IRC1
IRC0
LSB
0
Address:
Access:
Reset:
IRC 0
IRC 1
IRC 2
IRC 3
IRC 4
IRC 5
IRC 6
000416
R/W
0016
Timer 3 Interrupt Request (bit 0)
External CNTR0 Interrupt Request (bit 1)
External CNTR1 Interrupt Request (bit 2)
SIO Interrupt Request (bit 3)
Input Buffer Full Interrupt Request (bit 4)
Output Buffer Empty Interrupt Request (bit 5)
Key-on Wake up Interrupt Request (bit 6)
0: No interrupt request issued
1: Interrupt request issued
Bit 7
Reserved (Read/Write “0”)
Fig. 1.26. Interrupt Request Register C (IREQC)
27
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
MSB
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ICA7
ICA6
ICA5
ICA4
ICA3
ICA2
ICA1
ICA0
LSB
0
Address:
Access:
Reset:
ICA 0
ICA 1
ICA 2
ICA 3
ICA 4
ICA 5
ICA 6
ICA 7
000516
R/W
0016
USB Function Interrupt Enable (bit 0)
USB SOF Interrupt Enable (bit 1)
External Interrupt 0 Enable (bit 2)
External Interrupt 1 Enable (bit 3)
DMAC channel 0 Interrupt Enable (bit 4)
DMAC channel 1 Interrupt Enable (bit 5)
UART1 Receive Buffer Full Interrupt Enable (bit 6)
UART1 Transmit Interrupt Enable (bit 7)
0: Interrupt Disable
1: Interrupt Enable
Fig. 1.27 Interrupt Control Register A (ICONA)
MSB
7
ICB7
ICB6
ICB5
ICB4
ICB3
ICB2
ICB1
ICB0
LSB
0
Address:
Access:
Reset:
ICB 0
ICB 1
ICB 2
ICB 3
ICB 4
ICB 5
ICB 6
ICB 7
000616
R/W
0016
UART1 Error Sum Interrupt Enable (bit 0)
UART2 Receive Buffer Full Interrupt Enable (bit 1)
UART2 Transmit Interrupt Enable (bit 2)
UART2 Error Sum Interrupt Enable (bit 3)
Timer X Interrupt Enable (bit 4)
Timer Y Interrupt Enable (bit 5)
Timer 1 Interrupt Enable ( bit 6)
Timer 2 Interrupt Enable (bit 7)
0: Interrupt Disable
1: Interrupt Enable
Fig. 1.28. Interrupt Control Register B (ICONB)
MSB
7
Reserved
ICC6
ICC5
ICC4
ICC3
ICC2
ICC1
ICC0
LSB
0
Address:
Access:
Reset:
ICC 0
ICC 1
ICC 2
ICC 3
ICC 4
ICC 5
ICC 6
000716
R/W
0016
Timer 3 Interrupt Enable (bit 0)
External CNTR0 Interrupt Enable (bit 1)
External CNTR1 Interrupt Enable (bit 2)
SIO Interrupt Enable (bit 3)
Input Buffer Full Interrupt Enable (bit 4)
Output Buffer Empty Interrupt Enable (bit 5)
Key-on Wake up Interrupt Enable (bit 6)
0: Interrupt Disable
1: Interrupt Enable
ICC 7
Reserved (Read/Write “0”)
Fig. 1.29. Interrupt Control Register C (ICONC)
The interrupt polarity register allows the user to select the edge that will trigger an external interrupt
MSB
7
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
request. The polarity register (IPOL) for the external
interrupts is shown in Figure 1.30.
LSB Address:
INT1 Pol INT0 Pol 0
Access:
Reset:
INT0 Pol
INT1 Pol
Bits 2-7
Fig. 1.30. Interrupt Polarity Register (IPOL)
28
001116
R/W
0016
INT0 Interrupt Edge Selection Bit
0: Falling edge selected
1: Rising edge selected
INT1 Interrupt Edge Selection Bit
0: Falling edge selected
1: Rising edge selected
Reserved (Read/Write “0”)
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.16 KEY-ON WAKE UP
This device contains a key-on wake up interrupt function. The key-on wake up interrupt function is one way
of returning from a power-down state caused by the
STP or WIT instructions. This interrupt is generated
by applying low level to any pin of Port P2. If a key
matrix is connected as shown in Figure 1.31, the microcomputer can be returned to a normal state by
pressing any one of the keys. Key-on wake up is enabled in single-chip mode only.
Port PXx
L level output from arbitrary port Xx
Pull P2 register
bit 7
Port P27
latch
Port P2
direction
register
Key-on
wake up
Interrupt
Request
bit 7 = 1
P27 output
Pull P2 register
bit 6
Port P26
latch
Port P2
direction register
bit 6 = 1
Port P25
latch
Port P2
direction register
bit 5 = 1
P26 output
Pull P2 register
bit 5
P25 output
Pull P2 register
bit 4
Port P24
latch
Port P2
direction register
bit 4 = 1
Port P23
latch
Port P2
direction register
bit 3 = "0"
Port P22
latch
Port P2
direction register
bit 2 = "0"
Port P21
latch
Port P2
direction register
bit 1 = "0"
P24 output
P23 input
Pull P2 register
bit 2
Port P2 input read circuit
Pull P2 register
bit 3
P22 input
Pull P2 register
bit 1
P21 input
Pull P2 register
bit 0
Port P20
latch
Port P2
direction register
bit 0 = "0"
P20 input
Off Chip
On Chip
Fig. 1.31. Port P2 with Key-on Wake up function
29
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.17 TIMERS
an underflow occurs at the next count pulse and the
contents of the corresponding timer reload latch are
reloaded into the timer. When a timer underflows, the
interrupt request bit corresponding to that timer is set
to a “1”.
This device has five built-in timers: Timer X, Timer Y,
Timer 1, Timer 2, and Timer 3.
The contents of the timer latch, corresponding to
each timer, determine the divide ratio. The timers can
be read or written at any time. However, the read and
write operations on the high and low-order bytes of
the 16-bit timers (Timer X and Y) must be performed
in a specific order.
The divide ratio of a timer is given by 1/(n + 1), where
n is the value written to the timer. When the STP instruction is executed or RESET is asserted, 0116 is
loaded into Timer 2 and the Timer 2 reload latch, and
FF16 is loaded into Timer 1 and the Timer 1 reload
latch.
The timers are all down count timers; when the count
of a timer reaches 0016 (000016 for Timer X and Y),
Figure 1.32 is a block diagram of the five timers.
SCSGCLK
1
TXM2,1
TXM3
Timer X Divider
n
(1/ )
0
TXM5,4
n=8, 16, 32, 64
TYM3,2
Timer Y Divider
11
00
01
n
(1/ )
Φ
TXM0
TXM7
Timer XL Latch(8) Timer XH Latch(8)
Timer XL (8)
Timer XH (8)
Timer X Interrupt Request
10
1/8
CNTR0
CNTR0 Interrupt Request
1
TXM5,4= 01
TXM6
0
TXM6
0
Q
T
1
TXM5, 4 = 01
Q
TYM5,4= 11
Rising Edge Detector
Falling Edge Detector
TYM5,4= 01
or
11
TYM0
TYM5,4
00
01
11
TYM7
Timer YL Latch(8)Timer YH Latch(8)
Timer YH (8)
Timer YL (8)
Timer Y Interrupt Request
11
CNTR1
1
TYM5,4
10
TYM6
0
TYM1= 11 and TYM5,4 = 0
TYM6
0
Q
S
CNTR1 Interrupt Request
00
01
10
T
Φ
1
TYM= 1 & TYM5, 4 = 00
Q
T123M7
XCin/2
T123M5
0
1
Q
T123M2
1
TOUT
Q S
T123M7
Timer 1 Latch(8)
Timer 1 (8)
T
1
Timer 2 Latch(8)
Timer 2 (8)
T123M3
0
0
T123M0 0
T123M1
Timer 1
Interrupt Request
T123M6= 1
T123M6= 1
1
Timer 2
Interrupt Request
0
Q
T
T123M5
1
Q S
T123M6 =1
0
T123M4
1
Fig. 1.32. Block diagram of Timers X, Y, 1, 2, and 3
30
Timer 3 Latch(8)
Timer3 (8)
Timer 3
Interrupt Request
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
MSB
7
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TXM7
TXM6
TXM5
TXM4
TXM3
TXM2
TXM1
TXM0
L S B Address: 0027 16
Access: R/W
0
Reset: 00 16
TXM0
TXM2,1
TXM3
TXM5,4
TXM6
TXM7
Timer X Data Write Control Bit (bit 0)
0 : Write data in latch and timer
1 : Write data in latch only
Timer X Frequency Division Ratio Bits (bits 2,1)
Bit 2
Bit 1
0
0 : . divided by 8
0
1 : . divided by 16
1
0 : . divided by 32
1
1: .divided by 64
Timer X Internal Clock Select (bit 3)
0 : ./n
1 : SCSGCLK (from chip special count source generation)
Timer X Mode Bits (bits 5,4)
Bit 5
Bit 4
0
0 : Timer Mode
0
1 : Pulse output mode
1
0 : Event counter mode
1
1 : Pulse width measurement mode
CNTR0 Polarity Select Bit (bit 6)
0 : For event counter mode, clocked by rising edge
For pulse output mode, start from high level output
For CNTR0 inter rupt request, falling edge active
For pulse width measurement mode, measure high period
1 : For event counter mode, clocked on falling edge
For pulse output mode, start from low level output
For CNTR0 interrupt request, rising edge active
For pulse with measurement mode, measure low period
Timer X Stop Bit (bit 7)
0 : Count start
1 : Count stop
Fig. 1.33. Timer X Mode Register (TXM )
1.17.1 Timer X
•Read Method
Timer X is a 16-bit timer that has a 16-bit reload latch,
and can be placed in one of four modes by setting bits
TXM4 and TXM5 (bits 4 and 5 of the Mode Register,
TXM). The bit assignment of the TXM is shown in Figure 1.33.
When reading Timer X, the high-order byte is real
first. Reading the high-order byte causes the values
of Timer XH and Timer XL to be placed in temporary
registers assigned the same addresses as Timer
XH and Timer XL. The low-order byte of Timer X is
then read from its temporary register. This operation
assures the correct reading of Timer X while it is
counting.
1.17.1.1 Read and Write Method
Read and write operations on the high and low-order
bytes of Timer X must be performed in a specific order.
•Write Method
When writing to the timer, the lower order byte is
written first. This data is placed in a temporary register that is assigned the same address as Timer
XL. Next, the higher order byte is written. When this
is done, the data is placed in the Timer XH reload
latch and the low-order byte is transferred from its
temporary register to the Timer XL reload latch. At
this point, if the Timer X Data Write Control Bit
(TXM0) (bit 0) is “0”, the value in the Timer X reload
latch is also loaded in Timer X. If TXM0 is “0”, the
data in the Timer X reload latch is loaded in Timer X
after Timer X underflows.
1.17.1.2 Count Stop Control
If the Timer X Count Stop Bit (TXM7) (bit 7 of the TXM)
is set to a “1”, Timer X stops counting in all four modes.
•Timer Mode
Count Source: F/n (where n is 8, 16, 32, or 64) or
SCSGCLK
In this mode, each time the timer underflows, the corresponding timer interrupt request bit is set to a “1”,
the contents of the timer latch are loaded into the
timer, and the count down sequence begins again.
31
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
•Pulse Output Mode
•Pulse Width Measurement Mode
Count Source:F/n (where n is 8, 16, 32, or 64) or
SCSGCLK
Count Source: F/n (where n is 8, 16, 32, or 64) or
SCSGCLK
Each time the timer X underflows, the output of the
CNTR0 pin is inverted, and the corresponding Timer
X interrupt request bit is set to a “1”. The repeated
inversion of the CNTR0 pin output produces a rectangular waveform with a duty ratio of 50 percent. The
initial level of the output is determined by the CNTR0
polarity select bit (bit 6). When this bit is low, the output starts from a high level. When this bit is high, the
output starts from a low level.
This mode measures either the high or low-pulse
width of the signal on the CNTR0 pin. The pulse width
measured is determined by the CNTR0 polarity select bit (bit 6). When this bit is “0”, the high pulse is
measured. When this bit is “1”, the low pulse is measured.
•Event Counter Mode
Count Source: CNTR0
Timer countdown is triggered by inputs to the CNTR0
pin. Each time a timer underflows, the corresponding
timer interrupt request bit is set to a “1”, the contents
of the timer reload latch are loaded into the timer,
and the countdown sequence begins again.
The edge used to clock Timer X is determined by the
CNTR0 polarity select bit (bit 6).
32
The timer counts down while the level on the CNTR0
pin is the polarity selected by the CNTR0 polarity select bit. When the timer underflows, the Timer X interrupt request bit is set to a “1”, the contents of the
timer reload latch are reloaded into the timer, and the
timer continues counting down. Each time the signal
polarity switches to the inactive state, a CNTR0 interrupt occurs indicating that the pulse width has been
measured. The width of the measured pulse can be
found by reading Timer X during the CNTR0 interrupt service routine.
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
MSB
7
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TYM7
TYM6
TYM5
TYM4
TYM3
TYM2
TYM1
TYM0
L S B Address: 0028 16
Access: R/W
0
Reset: 00 16
TYM0
TYM1
TYM3,2
TYM5,4
TYM6
TYM7
Timer Y Data Write Control Bit (bit 0)
0 : Write data in latch and timer
1 : Write data in latch only
Timer Y Output Control Bit (bit 1)
0 : TYOUT output disable
1 : TYOUT output enable
Timer Y Frequency Division Ratio Bits (bit 3,2)
Bit 2
Bit 1
0
0 : . divided by 8
0
1 : . divided by 16
1
0 : . divided by 32
1
1 : . divided by 64
Timer Y Mode Bits (bits 5,4)
Bit 2
Bit 1
0
0 : Timer Mode
0
1 : Pulse period measurement mode
1
0 : Event counter mode
1
1 : HL pulse width measurement mode (continuously measures high period and low period)
CNTR1 Polarity Select Bit (bit 6)
0 : For event counter mode, clocked by rising edge
For pulse period measurement mode, falling edge detection
For CNTR1 interrupt request, falling edge active
For TYOUT, start on high output
1 : For event counter mode, clocked on falling edge
For pulse period measurement mode, rising edge detection
For CNTR1 interrupt request, rising edge active
For TYOUT, start on low output
Timer Y Stop Bit (bit 7)
0 : Count start
1 : Count stop
Fig. 1.34. Timer Y Mode Register (TYM)
1.17.2 Timer Y
•Read Method
Timer Y is a 16-bit timer that has a 16-bit reload latch,
and can be placed in any of four modes by setting
TYM4 and TYM5 (bits 4 and 5) (see Figure 1.34). The
desired mode is selected by modifying the values of
TYM4 and TYM5.
1.17.2.1 Read and Write Method
When reading Timer Y, the high-order byte is read
first. Reading the high-order byte causes the values
of Timer YH and Timer YL to be placed in temporary
registers that are assigned the same addresses as
Timer YH and Timer YL. The low-order byte of
Timer Y is then read from its temporary register.
This operation assures the correct reading of Timer
Y while it is counting.
Read and write operations on the high and low-order
bytes of Timer Y must be performed in a specific order.
•Write Method
When writing to the timer, the lower order byte is
written first. This data is placed in a temporary register that is assigned the same address as Timer
YL. Next, the high-order byte is written. Then, the
data is placed in the Timer YH reload latch and the
low-order byte is transferred from its temporary register to the Timer YL reload latch. At this point, if the
Timer Y Data Write Control Bit (TYM0) (bit 0) is low,
the value in the Timer Y reload latch is also loaded
in Timer Y. If TYM0 is “1”, the data in the Timer Y
reload latch is loaded in Timer Y after Timer Y
underflows.
1.17.2.2 Count Stop Control
If the Timer Y Count Stop Bit (TYM7) (bit 7) is set to a
“1”, Timer Y stops counting in all four modes.
•Timer Mode
Count Source:F/n (where n is 8, 16, 32, or 64)
In this mode, each time the timer underflows, the
corresponding timer interrupt request bit is set to a
“1”, the contents of the timer latch are loaded into
the timer, and the count down sequence begins
again.
In Timer mode, the signal TYOUT can also be
brought out on the CNTR1 pin. This is controlled by
TYM1 (bit1).
33
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
Each time the Timer Y underflows, the output of the
CNTR1 pin is inverted, and the corresponding Timer
Y interrupt request bit is set to a “1”. The repeated inversion of the CNTR1 pin output produces a
rectangular waveform with a duty ratio of 50 percent.
The initial level of the output is determined by the
CNTR1 polarity select bit (bit 6). When this bit is low,
the output starts from a high level. When this bit is
high, the output starts from a low level.
•Pulse Period Measurement Mode
Count Source:F/n (where n is 8, 16, 32, or 64).
This mode measures the period of the event waveform input to the CNTR1 pin.
•Event Counter Mode
Count Source: CNTR1
Timer countdown is triggered by input to the CNTR1
pin. Each time a timer underflows, the corresponding timer interrupt request bit is set to a “1”, the
contents of the timer reload latch are loaded into the
timer, and the countdown sequence begins again.
The edge used to clock Timer Y is determined by
the CNTR1 polarity select bit (bit 6). When these
bits are “0”s, the timers are clocked on the rising
edge. When these bits are “1”s, the timers are
clocked on the falling edge
•HL Pulse-width Measurement Mode
•CNTR1 Polarity Select Bit (TYM6) = “0”
Count Source:F/n (where n is 8, 16, 32, or 64).
When the falling edge of an event waveform is detected on the CNTR1 pin, the contents of Timer Y
are stored in the temporary register that is assigned the same address as Timer Y.
Simultaneously, the value in the Timer Y reload
latch is transferred to Timer Y, and Timer Y continues counting down. The falling edge of an event
waveform also causes the CNTR1 interrupt request; therefore, the period of the event waveform
from falling edge to falling edge is found by reading Timer Y in the CNTR1 interrupt routine. The
data read from Timer Y is the data previously
stored in its temporary register.
This mode continuously measures both the logical
high pulse width and the logical low pulse width of
an event waveform input to the CNTR1 pin. When
the falling (or rising) edge of the event waveform is
detected on the CNTR1 pin, the contents of Timer Y
are stored in the temporary register that is assigned
the same address as Timer Y, regardless of the setting of the CNTR1 polarity select bit. Simultaneously,
the value in the Timer Y reload latch is transferred to
Timer Y, which continues counting down. The falling
or rising edge of an event waveform causes the
CNTR1 interrupt request; therefore, the width of the
event waveform from the falling or rising edge to rising or falling edge is found by reading Timer Y in the
CNTR1 interrupt routine. The data read from Timer Y
is the data previously stored in its temporary register.
•CNTR1 Polarity Select Bit (TYM6) = “1”
When the rising edge of an event waveform is detected on the CNTR1 pin, the contents of Timer Y
are stored in the temporary register that is assigned the same address as Timer Y.
Simultaneously, the value in the Timer Y reload
latch is transferred to Timer Y, and Timer Y continues counting down.
The rising edge of an event waveform also causes
the CNTR1 interrupt request; therefore, the period
of the event waveform from rising edge to rising
edge is found by reading Timer Y in the CNTR1 interrupt routine. The data read from Timer Y is the
data previously stored in its temporary register.
Each time the timer underflows, the Timer Y interrupt
request bit is set to a “1”, the contents of the timer reload latch are loaded into the timer, and the
countdown sequence begins again.
34
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Each time the timer underflows, the Timer Y interrupt
request bit is set to a “1”, the contents of the timer
reload latch are loaded into the timer, and the countdown sequence begins again.
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
MSB
7
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
T123M7
T123M6
T123M5
T123M4
T123M3
T123M2
T123M1
T123M0
L S B Address: 0029 16
Access: R/W
0
Reset: 00 16
T123M0
T123M1
T123M2
T123M3
T123M4
T123M5
T123M6
T123M7
Fig. 1.35.
TOUT Source Selection Bit (bit 0)
0 : TOUT = Timer 1 output
1 : TOUT = Timer 2 output
Timer 1 Stop Bit (bit 1)
0 : Timer r unning
1 : Timer stopped
Timer 1 Count Source Select Bit (bit 2)
0 : . divided by 8
1 : XCin divided by 2
Timer 2 Count Source Select Bit (bit 3)
0 : Timer 1 underflow signal
1: .
Timer 3 Count Source Select Bit (bit 5)
0 : Timer 1 underflow signal
1: .divided by 8
TOUT Output Active Edge Selection Bit (bit 5)
0 : Start on high output
1 : Start on low output
TOUT Output Control Bit (bit 6)
0 : TOUT output disabled
1 : TOUT output enabled
Timer 1 and 2 Data Write Control Bit (bit 7)
0 : Write data in latch and timer
1 : Write data in latch only
Timer 1, 2, 3 Mode Register (T123M)
1.17.3 Timer 1
•Pulse Output Mode
Timer 1 is an 8-bit timer with an 8-bit reload latch and
has a pulse output option (see Figure 1.35).
Count Source: F/8 or XCin/2
T123M7 of Timer123 mode register (T123M) is the
Timer 1 and 2 Data Write Control Bit. If T123M7 is “1”,
data written to Timer 1 is placed only in the Timer 1
reload latch. The latch value is loaded into Timer 1 after Timer 1 underflows. If T123M7 is “0”, the value
written to Timer 1 is placed in Timer 1 and the Timer
1 reload latch. At reset, T123M7 is set to a “0”.
The output signal TOUT is controlled by T123M5 and
T123M6. T123M5 controls the polarity of TOUT. Setting the bit T123M5 to “1” causes TOUT to start at a
low level, and clearing this bit to “0” causes TOUT to
start at a high level. Setting T123M6 to “1” enables
TOUT, and clearing T123M6 to “0” disables TOUT.
Timer 1 Pulse Output mode is enabled by setting
T123M6 to “1” and T123M0 to a “0”. Each time the
Timer 1 underflows, the output of the TOUT pin is
inverted, and the corresponding Timer 1 interrupt
request bit is set to a “1”. The repeated inversion of
the TOUT pin output produces a rectangular waveform with a duty ratio of 50 percent. The initial level
of the output is determined by the TOUT polarity select bit (T123M5). When this bit is “0”, the output
starts from a high level. When this bit is “1”, the output starts from a low level.
•Timer Mode
Count Source: F/8 or XCin/2
In Timer mode, each time the timer underflows, the
corresponding timer interrupt request bit is set to a
“1”, the contents of the timer latch are loaded into
the timer, and the count down sequence begins
again.
35
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.17.4 Timer 2
1.17.5 Timer 3
Timer 2 is an 8-bit timer with an 8-bit reload latch (see
Figure 1.35).
Timer 3 is an 8-bit timer with an 8-bit reload latch (see
Figure 1.35). The Timer 3 reload latch value is not affected by a change of the count source. Because
changing the count source may cause an inadvertent
countdown of the timer, the timer should be rewritten
whenever the count source is changed.
T123M7 (bit 7 of T123M) is the Timer 1 and 2 Data
Write Control Bit. If T123M7 is “1”, data written to
Timer 2 is placed only in the Timer 2 reload latch (see
Figure 1.32). The latch value is loaded into Timer 2
after Timer 2 underflows. If the T123M7 is “0”, the
value written to Timer 2 is placed in Timer 2 and the
Timer 2 reload latch. At reset, T123M2 is set to a “0”.
The Timer 2 reload latch value is not affected by a
change of the count source. However, because
changing the count source may cause an inadvertent
countdown of the timer, the timer should be rewritten
when the count source is changed.
•Timer Mode
Count Source:
•If T123M3 is “0”, the Timer 2 count source is the
Timer 1 underflow output.
•If T123M3 is “1”, the Timer 2 count source is F.
In Timer mode, each time the timer underflows, the
corresponding timer interrupt request bit is set to a
“1”, the contents of the timer latch are loaded into
the timer, and the count down sequence begins
again.
•Pulse Output Mode
Count Source:
•If T123M3 is “0”, the Timer 2 count source is the
Timer 1 underflow output.
•If T123M3 is “1”, the Timer 2 count source is F.
Timer 2 Pulse Output mode is enabled by setting
T123M6 to a “1” and T123M0 to a “1”. Each time the
Timer 2 underflows, the output of the TOUT pin is
inverted, and the corresponding Timer 2 interrupt
request bit is set to a “1”. The repeated inversion of
the TOUT pin output produces a rectangular waveform with a duty ratio of 50 percent. The initial level
of the output is determined by the TOUT polarity select bit (T123M5). When this bit is “0”, the output
starts from a high level. When this bit is “1”, the output starts from a low level.
36
•Timer Mode
Count Source:
•If T123M4 is “0”, the Timer 3 count source is the
Timer 1 underflow output.
•If T123M4 is “1”, the count source is F/8
In Timer mode, each time the timer underflows, the
corresponding timer interrupt request bit is set to a
“1”, the contents of the timer latch are loaded into the
timer, and the count down sequence begins again.
Data written to Timer 3 is always placed in Timer 3
and the Timer 3 reload latch.
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.18 SERIAL I/O
• External Clock
(When SIO synchronous clock select bit is “1”, an
external clock input from the SCLK pin is selected).
The Serial I/O has the following main features:
• Synchronous transmission or reception
•An SPI compatible mode in which the TxD and RxD
pins function as MOSI and MISO pins, respectively.
• Handshaking via SRDY output signal
• 8-bit character length
•Four (SPI compatible) clock phase and polarity options.
• Interrupt after transmission or reception
A block diagram of the clock synchronous SIO is shown
in Figure 1.36.
• Internal Clock
(When serial I/O synchronous clock select bit is “1”,
internal clock source divided by 2, 4, 8, 16, 32, 64,
128, 256 can be selected). If bit 1 of SIO Control Reg
ister 2 is “0”, internal clock source = .; if bit 1 of SIO
Control Register 2 is “1”, internal clock source =
SCSGCLK.)
1
0
0
1
1/4
1
0
CLKSEL
0
P80 Latch
CPol
CPha
SCSel
Divider
1/2
1/16
1/32
1/64
1/128
1/256
SIO Counter
SPI Slave
Synchronous
Circuit
Selected
SPI
Slave
0
1
SRDY
P83 Latch
SCSGCLK
1/8
P81 Latch
External Clock
SIO Shift Register
SPI
Slave
1
Φ
SRDY
RDYSel
1
PSel
PSel
0
SCLK
STXD
SRXD
SPI
SCSel
Data Bus
SIO Interrupt Request
Fig. 1.36. Clock Synchronous SIO Block Diagram
37
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.18.1 SIO Control Registers (SIOCON)
SIO Control Register 2 determines the transfer clock
phase and polarity, and also whether the SIO is to
function in SPI compatible mode (see Figure 1.38). All
of this register’s bits can be read from and written to
by software. At reset, this register is set to 1816.
The Serial I/O Control Register 1 controls various SIO
functions such as transfer direction and transfer clock
divisor (see Figure 1.37). All of this register’s bits can
be read from and written to by software. At reset, this
register is cleared to 0016.
MSB
OCHCont
7
SCSel
TDSel
RDYSel
PSel
L S B Address: 002B 16
Access: R/W
ISCSel2 ISCSel1 ISCSel0 0
Reset: 40 16
ISCSel0-2
PSel
RDYSel
TDSel
SCSel
OCHCont
Internal Synchronization Clock Select Bit (bits 2,1,0)
Bit 2
Bit 1
Bit 0
0
0
0 : Internal Clock Divided
0
0
1 : Internal Clock Divided
0
1
0 : Internal Clock Divided
0
1
1 : Internal Clock Divided
1
0
0 : Internal Clock Divided
1
0
1 : Internal Clock Divided
1
1
0 : Internal Clock Divided
1
1
1 : Internal Clock Divided
SIO Port Selection Bit (bit 3)
0 : I/O Port
1 : TxD output, SCLK function
SRDY Output Select Bit (bit 4)
0 : I/O Port
1 : SRDY signal
Transfer Direction Select Bit (bit 5)
0 : LSB first
1 : MSB first
Synchronization Clock Select Bit (bit 6)
0 : External Clock
1 : Internal Clock
TxD Output Channel Bit (bit 7)
0 : CMOS output
1 : N-Channel open drain output
by
by
by
by
by
by
by
by
2
4
8
16
32
64
128
256
Fig. 1.37. SIO Control Register 1 (SIOCON1)
MSB
7
Reserved
Reserved
Reserved
CPha
CPol
RXDSel
CLKSEL
SP1
LSB Address: 002C16
Access: R/W
0
Reset: 18 16
SPI
CLKSEL
RXDSel
CPol
CPHa
Bit 5-7
Fig. 1.38. SIO Control Register 2 (SIOCON2)
38
SPI Mode Selection Bit (bit 0)
0 : Normal SIO mode
1 : SPI compatibe mode
SIO Internal Clock Selection Bit (bit 1)
0: .
1 : SCSGCLK
SRXD Input Selection Bit (bit 2)
0 : SRXD input disabled
1 : SRXD input enabled
Clock Polarity Selection Bit (bit 3)
0 : Clock is low between transfers
1 : Clock is high between transfers
Clock Phase Selection Bit (bit 4)
0 : Data is captured on the leading edge of serial clock, changes
on the following edge.
1 : Data changes on the leading edge of serial clock, captured on
the following edge.
Reser ved (Read/Write “0”)
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.18.2 SIO Normal Operation
An internal clock or an external clock can be selected
as the synchronous clock. When the internal clock is
chosen, dividers are built in to provide eight different
clock selections. The start of a transfer is initiated by
a write signal to the SIO shift register (address
002A16). The SRDY signal then drops active low. On
the negative edge of the transfer clock SRDY returns
high and the data is transmitted out the STXD pin.
Data is latched in from the SRXD pin on the rising
edge of the transfer clock. If an internal clock is se-
lected, the STXD pin enters a high-impedance state
after an 8-bit transfer is completed. If an external
clock is selected, the contents of the serial I/O register continue to be shifted while the send/receive clock
is being input. Therefore, the clock needs to be controlled by the external source. Also there is no STXD
high-impedance function after data is transferred.
Regardless of whether an internal or external clock is
selected, after an 8-bit transfer, the interrupt request
bit is set. Figure 1.39 shows the timing for the serial I/
O with the LSB-first option selected.
Synchronous Clock
Transfer Clock
SIO Register
Write Signal
Receive Enable
Signal SRDY
SIO Output
See Note
D0 D1 D2 D3 D4 D5 D6 D7
SIO Input
Note:
Interrupt Request Bit Set
When the internal clock is selected, the TxD pin goes into highimpedance after the data is transferred.
Fig. 1.39. Normal Mode SIO Function Timing (with LSB-First selected)
39
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.18.3 SPI Compatible Operation
1.18.3.1 SPI Slave Mode
Setting the SPI bit (bit 0 in SIOCON2) puts the SIO in
an SPI compatible mode. The internal/external clock
select bit (bit 6 in SIOCON1) determines whether the
SIO is an SPI master or slave. If internal clock is selected the SIO is a master, and if external clock is
selected the SIO is in slave mode.
When configured as an SPI slave the SIO does not
initiate any serial transfers. All transfers are initiated
by an external SPI bus master. When the CPha (bit 4
in SIOCON2) is “0” serial transfers begin with the falling edge of the SRDY input. For CPha = “1” serial
transfers begin when the SCLK leaves its idle state
(the clock idle state is defined by CPol, bit 3 in
SIOCON2).
Entering SPI mode has the following effects on operation:
1. The RxD pin functions as a MISO (Master In/Slave
Out) pin. This means that when the SPI is in slave
mode transmit data will be output on this pin. In mas
ter mode receive data is input on this pin.
2. The TxD pin functions as a MOSI (Master Out/Slave
In) pin. When the SPI is in slave mode receive data is
input on this pin. In master mode this pin drives the
transmit data.
3. The SRDY pin functions as a slave/chip select. If the
SPI is in slave mode, this pin functions as a slave se
lect input. When configured as an SPI master, the
SRDY pin functions as a chip select output.
If SRDY is held high, the shift clock is inhibited, SRXD
(MISO) is tri-stated, and the shift count is reset. If
SRDY is held low, then the shift operation is performed. The SRDY input must be deasserted
(brought high) between transfers; this resets the
SIO’s internal bit counter.
When the SIO is in SPI slave mode, all transfers are
initiated by an external SPI bus master, not by the
MCU. Therefore, an application must implement
some form of handshaking or synchronization to
avoid writing to the SIO shift register during a serial
transfer. Writing to the SIO shift register during a
transfer will corrupt the transfer in progress.
Figure 1.40 shows the four possible SPI clock-to-data
relationships.
The CPol and CPha bits (bits 3 and 4 in SIOCON2)
are used to select the format.
SRDY
SCLK
CPol = 1
CPha = 1
SCLK
CPol = 0
CPha = 1
SCLK
CPol = 1
CPha = 0
SCLK
CPol = 0
CPha 0
TxD/RxD
First bit
Last bit
Arrows indicate edge when data is captured
Fig. 1.40. SPI Compatible Transmission Formats
40
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.19 UART
The following descriptions apply to both UARTs.
This chip contains two identical UARTs. Each UART
has the following main features:
The UART receives parallel data from the core or
DMAC, converts it into serial data, and transmits the
results to the send data output terminal UTXDx. The
UART receives serial data from an external source
through the receive data input URXDx, converts it into
parallel data, and makes it available to the core or
DMAC. The UART can detect parity, overrun, and
framing errors in the input stream and report the appropriate status information. A double buffering
configuration is used for the UART’s transmit and receive operations. This double buffering is
accomplished by the use of a transmit buffer and
transmit shift register on the transmit side and the receive buffer and receive shift register on the receive
side.
• Clock selection .................................. F or SCSGCLK
• Prescaler selection ............... x1/x8/x32/x256 divisions
............................................ (both F and SCSGCLK)
• Baud rate .......................................... (at F = 12MHz)
......................... 11.4 bits/second-750 Kbytes/second
• Error detection ...................................... parity/framing/
...................................................... overrun/error sum
• Parity .................................................. odd/even/none
• Stop bits ........................................................... 1 or 2
• Character length .................................... 7, 8, or 9 bits
• Transmit/receive buffer .................................. 2 stages
...................................................... (double buffering)
• Handshaking ............................... Clear-to-Send (CTS)
............................................. Request-to-Send (RTS)
• Interrupt generation conditions ............. Transmit Buffer
..................................... Empty or Transmit Complete
........................................................... Receive Buffer
.................................................... Receive Error Sum
• Address ............... mode for multi-receiver environment
The UART supports an address mode for use in a
multi-receiver environment where an address is sent
before each message to designate which UART or
UARTs are to wake-up and receive the message. Figure 1.41 is a block diagram of the UART. It is valid for
both UART1 and UART2.
Data Bus
UART Mode
Register
UART Status
Register
UART Control
Register
UxMOD
UxSTS
UxCON
Tx Buffer Empty
Transmit
Buffer
Tx Enable
Tx Complete
TBE
TIS = "0"
TCM
Transmit
Shift Register
ST/STP/PA
Generator
___
CTS_SEL
Transmit Interrupt
TIS = "1"
Transmit line to UTXDx
From CTSx
Data Bus
___
RTS_SEL
CLKSEL
Φ
SCSGCLK
PS 1,0
To RTSx
Stop and Start
Detect
Data Format
Bit Counter
Clock Set
Prescaler
/1/8/32/256
RTS Control
Register
LE 1,0; PEN; STB
LE 1,0; PEN; STB
Rx Enable
Baud Rate Generator
Rx Status Errors
Data Format
Bit Counter
Receive
Shift Register
Rx Complete
Receive line from URXDx
Receive Buffer Full Interrupt
Receive
Buffer Register
Receive Error Interrupt
Data Bus
Fig. 1.41. UART Block Diagram
41
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.19.1 UART Mode Register (UxMOD)
1.19.2 UART Control Register (UxCON)
UxMOD defines data formats and selects the clock to
be used (see Figure 1.42).
The UxCON specifies the initialization and enabling of a
transmit/receive process (see Figure 1.43). Data can
be read from and written to the Control Register.
MSB
7
LE1
LE0
PEN
PMD
STB
PS1
PS0
CLK
LSB Address: 003016 ,003816
Access: R/W
0
Reset: 0016
CLK
PS1,0
STB
PMD
PEN
LE1,0
UART Clock Selection Bit (bit 0)
0: .
1: SCSGCLK
Internal Clock Prescaling Selection Bits (bits 2,1)
Bit 2
Bit 1
0
0: Division by 1
0
1: Division by 8
1
0: Division by 32
1
1: Division by 256
Stop Bits Selection Bit (bit 3)
0: 1
1: 2
Parity Selection Bit (bit 4)
0: Even
1: Odd
Parity Enable Bit (bit 5)
0: Off
1: On
Uart Character Length Selection Bits (bits 7,6)
Bit 7
Bit 6
0
0: 7 bits/character
0
1: 8 bits/character
1
0: 9 bits/character
1
1: Reserved
Fig. 1.42. UART Mode Register (U1MOD, U2MOD)
MSB
7
AME
RTS_SEL
CTS_SEL
TIS
RIN
TIN
REN
TEN
LSB
0
Address: 003316 ,003B16
Access: R/W
Reset: 0016
TEN
REN
TIN
RIN
TIS
CTS_SEL
RTS_SEL
AME
Fig. 1.43. UART Control Register (U1CON, U2CON)
42
Transmission Enable Bit (bit 0)
0: Disable the transmit process
1: Enable the transmit process. If the transmit process is disabled (TEN
cleared) during transmission, the transmit will not stop until completed.
Receive Enable Bit (bit 1)
0: Disable the receive process
1: Enable the receive process. If the receive process is disabled (REN
cleared) during reception, the receive will not stop until completed.
Transmission Initialization Bit (bit 2)
0: No action
1: Resets the UART transmit status register bits as well as stopping the
transmission operation. The TEN bit must be set and the transmit
buffer reloaded in order to transmit again. The TIN is automatically
reset one cycle after Tin is set.
Receive Initialization Bit (bit 3)
0: No action
1: Clears the UART receive status flags and the REN bit. If RIN is set
during receive in progress, receive operation is aborted. The RIN bit
is automatically reset one cycle after RIN is set.
Transmit Interrupt Source Selection Bit (bit 4)
0: Transmit interrupt occurs when the Transmit Buffer Empty flag is set.
1: Transmit interrupt occurs when the Transmit Complete flag is set.
Clear-to Send (CTS) Enable Bit (bit 5)
0: CTS function is disabled. P86 (or P82) is used as GPIO pin.
1: CTS function is enabled. P86 (or P82) is used as CTS input.
Request-to-Send (RTS) Enable Bit (bit 6)
0: RTS function is disabled, P8 7 (or P83) is used as GPIO pin.
1: RTS function is enabled, P87 (or p8 3) is used as RTS output.
UART Address Mode Enable Bit (bit 7)
0: Address Mode disabled
1: Address Mode enabled
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.19.3 UART Status Register (UxSTS)
1.19.3.4 Receive Parity Error Flag
The UART Status Register (UxSTS) reflects both the
transmit and receive status (see Figure 1.44). The status register is read only. The MSB is always “0” during
a read operation. Writing to this register has no effect.
Status flags are set and reset under the conditions indicated below. The setting and resetting of the
transmit and receive status are not affected by transmit and receive enable flags. The setting and resetting
of the receive error flags and receive buffer full flag differs when UART address mode is enabled. These
differences are described in section “1.19.7 UART Address Mode”.
The Receive Parity Error Flag (PER) is set when the
parity of received data and the Parity Selection Bit
(PMD, bit 4 of UxMOD) are different. It is enabled only
if the Parity Enable Bit (PEN, bit 5 of UxMOD) is set.
1.19.3.1 Receive Error Sum Flag
The Receive Error Sum Flag (SER) is set when an
overrun, framing, or parity error occurs after completion of a receive operation.
It is reset when the status register is read, the hardware reset is asserted, or the receiver is initialized by
setting the Receive Initialization Bit (RIN). If the receive
operation completes while the status register is being
read, the status information is updated upon completion of the status register read.
1.19.3.2 Receive Overrun Flag
The Receive Overrun Flag (OER) is set if the previous
data in the low-order byte of the receive buffer
(UxTRB1) is not read before the current receive operation is completed. It is also set if a receive error
occurred for the previous data and the status register
is not read before the current receive operation is completed. This flag is reset when the status register is
read. This flag is also reset when the hardware reset is
asserted or the receiver is initialized by RIN. If the receive operation completes while the status register is
being read, the status information is updated upon
completion of the status register read.
1.19.3.3 Receive Framing Error Flag
The Receive Framing Error Flag (FER) is set when the
stop bit of the received data is “0”. If the Stop Bit Selection Bit (STB, bit 3 of UxMOD) is set, the flag is set
if either of the two stop bits is a “0”. This flag is reset
when the status register is read, the hardware reset is
asserted, or the receiver is initialized by RIN. If the receive operation completes while the status register is
being read, the status information is updated upon
completion of the status register read.
This flag is reset when the status register is read, the
hardware reset is asserted, or the receiver is initialized
by RIN. If the receive operation completes while the
status register is being read, the status information is
updated upon completion of the status register read.
1.19.3.5 Receive Buffer Full Flag
The Receive Buffer Full Flag (RBF) is set when the
last stop bit of the data is received. It is not set when
a receive error occurs. This flag is reset when the loworder byte of the receive buffer (UxTRB1) is read, the
hardware reset is asserted, or the receive process is
initialized by RIN. If the receive operation completes
while the status register is being read, the status information is updated upon completion of the status
register read.
1.19.3.6 Transmission Complete Flag
In the case where no data is contained in the transmit
buffer, the Transmission Complete Flag (TCM) is set
when the last bit in the transmit shift register is transmitted. In the case where the transmit buffer does
contain data, the TCM flag is set when the last bit in
the transmit shift register is transmitted if TBE is a “0”
or CTS handshaking is enabled and CTSx is “1”. The
TCM flag is also set when the hardware reset is asserted or when the transmitter is initialized by setting
the Transmit Initialization Bit (TIN, bit 2 of UxCON). It
is reset when a transmission operation begins.
1.19.3.7 Transmission Buffer Empty Flag
The Transmission Buffer Empty Flag (TBE) is set
when the contents of the transmit buffer are loaded
into the transmit shift register. The TBE flag is also
set when the hardware reset is asserted or when the
transmitter is initialized by TIN. It is reset when a write
operation is performed to the low-order byte of the
transmit buffer (UxTRB1).
43
MITSUBISHI MICROCOMPUTERS
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Ver 1.4
MSB
7
Reserved
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SER
OER
FER
PER
RBF
TBE
TCM
LSB
0
TCM
TBE
RBF
PER
FER
OER
SER
Bit 7
Address: 003216 ,003A16
Access: Read only
Reset: 0316
Transmission complete (Transmission Register empty) Flag (Bit 0)
0: Data in Transmission Register
1: No data in Transmission Register
TX Buffer Empty flag (Bit 1)
0: Data in TX Buffer
1: No data in the TX Buffer
RX Buffer Full Flag (Bit 2)
0: No data in RX Buffer
1: Data in RX Buffer
Receive Parity Error Flag (Bit 3)
0: No parity error received
1: Received framing error
Receive Framing Error Flag (Bit 4)
0: No framing error received
1: Received framing error
Receive Overrun Flag (Bit 5)
0: No overrun receive received
1: Received overrun
Receive Error Sum flag (Bit 6)
0: No error received
1: Received error
Reserved (Read “0”)
Fig. 1.44. UART Status Register (U1STS, U2STS)
1.19.4 Transmit/Receive Methods
1.19.4.1 Transmit Method
Setup
•Define the baud rate by writing a value from 0-255 into
the UxBRG (see Figure 1.45).
•Set the Transmission Initialization Bit (TIN, bit 2 of
UxCON), to “1”. This will reset the transmit status to a
value of 0316.
•Select the interrupt source to be either TBE or TCM
by clearing or setting the Transmit Interrupt Source Selection Bit (TIS, bit 4 of UxCON).
• Configure the data format and clock selection by writing the appropriate value to UxMOD.
• Set the Clear-To-Send Enable Bit (CTS_SEL, bit 5 of
UxCON), if CTS handshaking will be used.
•Set the Transmit Enable Bit (TEN, bit 0 of UxCON), to
“1”.
Operation
•When data is written to the low-order byte of the transmit buffer (UxTRB1), TBE is cleared to “0”. If 9-bit
character length has been selected, the high-order byte
of the transmit buffer (UxTRB2) should be written before
the low-order byte (UxTRB1).
44
•If no data is being shifted out of the transmit shift register and CTS handshaking is disabled, the data written
to the transmit buffer is transferred to the transmit shift
register and the TCM flag in UxSTS is cleared to a “0”.
In addition, the TBE flag is set to a “1”, signaling that
the next byte of data can be written to the transmit
buffer. If CTS handshaking is enabled, the operation described above does not take place until CTSx is
brought low.
•Data from the transmit shift register is transmitted one
bit at a time beginning with the start bit and ending with
the stop bit. Note that the LSB is transmitted first.
•If the TEN bit is cleared to a “0” while data is still being transmitted, the transmitter will continue until the
last bit is sent. This is also the case when CTS handshaking is enabled and CTSx is brought back high
during transmission.
•When the last bit is transmitted, the TCM flag is set to
a “1” if the transmit buffer is empty, TEN is a “0”, or
CTS handshaking is enabled and CTSx is “1”. If the
transmit buffer is not empty, TEN is a “1”, and CTS
handshaking is disabled or CTS handshaking is enabled and CTSx is low, the TCM flag is not set
because transfer of the contents of the transmit buffer
to the transmit shift register occurs immediately.
MITSUBISHI MICROCOMPUTERS
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Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
UxBRG
Clock
UxTRB1
Write
TBE
TCM
UTXDx
Start bit
D0
Stop bit
Start bit
Stop bit
Fig. 1.45. UART Transmit Operation Waveform
1.19.4.2 Receive Method
Set up
•Define the baud rate by writing a value from 0-255 into
UxBRG.
•Set the Receive Initialization Bit (RIN, bit 3 in the
UxCON), to "1".
•Configure the data format and the clock selection by
writing the appropriate value to UxMOD.
•Set the Request-To-Send Enable Bit (RTS_SEL, bit 6
of UxCON), if RTS handshaking will be used.
•Set the Receive Enable Bit (REN, bit 1 in the
UxCON), to "1".
Operation
•When a falling edge is detected on the URXDx pin,
the value on the pin is sampled at the basic clock rate,
which is 16 times faster than the baud rate. If the pin is
low for at least two cycles of the basic clock, the start
bit is detected. Sampling is again performed three
times in the approximate middle of the start bit. If two
or more of the samples are low, the start bit is deemed
valid. If two or more of the samples are not low, the
start bit is invalidated and the UART again begins waiting for a falling edge on the URXDx pin.
•Once a valid start bit has been detected, input data received through the URXDx pin is read one bit at a time,
LSB first, into the receive shift register. As is the case
with the start bit, three samples are taken in the approximate middle of each data bit, the parity bit, and
the stop bit(s). If two or more of the samples are low, a
"0" is latched, and if two or more of the samples are
high, a "0" is latched.
•When the number of bits specified by the data format
has been received and the last stop bit is detected, the
contents of the receive shift register are transferred to
the receive buffer and the Receive Buffer Full Flag in
the UxSTS is set to a "1", if a receive error has not occurred (see Figure 1.46). The RBF interrupt request is
also generated at this time if a receive error has not occurred. However, if a receive error did occur, the
appropriate error flags are set and the Receive Error
Sum (SER) interrupt request is generated at this time.
•When the low-order byte of the receive buffer
(UxTRB1) is read, the Receive Buffer Full Flag is
cleared, and the receive buffer is now ready for the next
byte. If 9-bit character length has been selected, the
high-order byte of the receive buffer (UxTRB2) should
be read before reading the low-order byte (UxTRB1).
45
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
URXDx
Start bit
D0
Stop bit
2-of-3
sampling
2-of-3
sampling
Start bit
D0
UxBRG
Clock
Edge
2-of-3
detection sampling
Edg
2-of-3
detection sampling
2-of-3
sampling
RBF
UxTRB1
Read
Fig. 1.46. UART Receive Operation Waveforms
CTS (input)
TXD (output)
start
DATA
stop
RXD (input)
programmable delay
start
DATA
DATA
RTS (output)
In both examples, the Transmit and Receive have already been enabled
Fig. 1.47. CTSx and RTSx Timing Examples
MSB
7
RTS3
RTS2
RTS1
Fig. 1.48. UxRTSC Register
46
RTS0
Reserved
Reserved
Reserved
Reserved
LSB
0
Address: 003616 ,003E16
Access: R/W
Reset: 8016
0-3
Reserved (Read/Write “0’)
RTS3:0
RTS Assertion Delay count 3:0 (bits 7, 6, 5, 4)
0000: No delay, RTS asserts immediately after receive operation completes
0001: RTS asserts 8 bit-times after receive operation completes
0010: RTS asserts 16 bit-times after receive operation completes
0011: RTS asserts 24 bit-times after receive operation completes
1000: RTS asserts 64 bit-times after receive operation completes
1110: RTS asserts 112 bit-times after receive operation completes
1111: RTS asserts 120 bit-times after receive operation completes
MITSUBISHI MICROCOMPUTERS
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Ver 1.4
1.19.5 Interrupts
The transmit and receive interrupts are generated under the conditions described below. The generation of
the receive interrupts differs when UART Address
mode is enabled.
1.19.5.1 Transmit interrupts
The UART generates a Transmit interrupt to the CPU
core. The source of the Transmit interrupt is selectable by setting TIS.
•If TIS = “0”, the Transmit interrupt is generated when
the transmit buffer register becomes empty (that is,
when TBE flag set).
•If TIS = “1”, the Transmit interrupt is generated after
the last bit is sent out of the transmit shift register and
no data has been written to the transmit buffer or CTS
handshaking is enabled and CTSx is high (that is,
when TCM flag set).
1.19.5.2 Receive Interrupts
The UART generates the Receive Buffer Full (RBF)
and Receive Error Sum (SER) interrupts to the CPU
core when receiving.
•The RBF interrupt is generated when a receive operation completes and a receive error is not generated.
•The SER interrupt is generated when an overrun, framing or parity error occurs.
1.19.6 Clear-to Send (CTSx) and Request-to-Send
(RTSx) Signals
The UART, as a transmitter, can be configured to recognize the Clear-to-Send (CTSx) input as a
handshaking signal. As a receiver, the UART can be
configured to generate the Request-to-Send (RTSx)
handshaking signal.
1.19.6.1 Clear-to-Send (CTSx) Input
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
pins will remain under the control of the UART until
the end of the transmission. If CTS handshaking is
disabled and TEN is a “1”, the UART begins the transmission process as soon as data is available in the
low-order byte of the transmit buffer (UxTRB1). Figure
1.47 shows a timing example for CTSx.
1.19.6.2 Request-to-Send (RTSx) Output
RTS handshaking is enabled by setting the Requestto-Send Enable Bit (RTS_SEL, bit 6 of UxCON) to a
“1”. When RTS handshaking is enabled, the UART
drives the RTSx output low or high based on the following conditions:
•Assertion conditions (driven low):
•The Receive Enable Bit (REN) is set to a “1”.
•Receive operation has completed with the reception of
the last stop bit, REN is still a “1”, and the programmable assertion delay has expired.
•De-assertion conditions (driven high):
•A valid start bit is detected and REN is a “1”.
•REN is cleared to a “0” before a receive operation is in
progress.
•Receive operation has completed and REN is a “0”.
•UART Receiver is initialized (RIN is set to a “1”).
The delay time from the reception of the last stop bit
to the re-assertion of RTSx is programmable. The
amount of delay is selected by setting the RTS Assertion Delay Count Bits (RTS 3~0, bits 3 to 0 of
UxRTSC) (see Figure 1.48 ). The time can be from no
delay to 120 bit-times, with the delay beginning from
the middle of the last stop bit. If a start bit is detected
before the assertion delay has expired, the delay
countdown is stopped and the RTSx pin remains high.
A full assertion delay countdown will begin again once
the last stop bit of the incoming data has been received. See Figure 1.47 for a timing example for
RTSx.
CTS handshaking is enabled by setting the Clear-toSend Enable Bit (CTS_SEL, bit 5 of UxCON) to a “1”.
If CTS handshaking is enabled, when TEN is a “1” and
the low-order byte of the transmit buffer (UxTRB1) is
loaded, the UART begins the transmission process
when the CTSx pin is asserted (low input). After beginning a send operation, the UART does not stop
sending until the transmission is completed, even if
CTSx is deasserted (high input). If TEN is cleared to
“0”, the UART will not stop transmitting and the port
47
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
1.19.7 UART Address Mode
The UART address mode is intended for use in a
multi-receiver environment where an address is sent
before each message to designate which UART or
UARTs are to wake-up and receive the message. An
address is identified by the MSB of the incoming data
byte being a “1”. The bit is “0” for non-address data.
UART address mode can be used in either 8-bit or 9bit character length mode. The character length is
chosen by writing the appropriate values to the UART
Character Length Selection Bits (LE1,0).
UART address mode is enabled by setting the UART
Address Mode Enable Bit (AME) to “1”. When UART
address mode is enabled, the MSB of a newly received byte of data (that is either 8 or 9 bits in length)
is examined if a valid stop bit is detected and a parity
error has not occurred (if parity is enabled). If the MSB
is “1”, then the receive buffer full interrupt and flag are
set and AME is automatically cleared, disabling UART
address mode. If the MSB is “0”, then the receive
buffer full interrupt is not set. However, the RBF flag is
still set for this case. If a valid stop bit is not detected
or a parity error has occurred, neither the receive buffer
full flag nor interrupt is set and the MSB of the data is
not examined. Instead, either the framing error or parity error flag is set, the error sum flag is set, and the
error sum interrupt is set.
48
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
While in UART address mode, the generation of overrun errors is disabled after the first byte of data is
received. Therefore, when non-address data is received without errors while in the UART address mode,
it is not necessary to read the UART receive buffer
prior to the reception of the next byte of data. Also, if
a framing or parity error occurs while in UART address
mode, it is not necessary to read the UxSTS prior to
the reception of the next byte of data. However, an
overrun error will occur if an address byte is received
and the UART receive buffer is not read before a new
byte of data is received. This is the case because the
UART address mode was automatically disabled when
the address byte was received. Also, an overrun error
will occur for the first byte received after UART address
mode is enabled if the preceding byte received did not
generate an error and the UART receive buffer was not
read, or the preceding byte did generate an error and
UxSTS was not read.
MITSUBISHI MICROCOMPUTERS
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Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.20 SPECIAL COUNT SOURCE GENERATOR
This device has a built-in special count source generator. It cons ists of two 8-bit timers: SCSG1, and
SCSG2 (see Figure 1.49). The contents of the timer
latch, corresponding to each timer, determine the divide ratio. The timers can be written to at any time.
The output of the special count source generator can
be a clock source for Timer X, SIO and the two
UARTs.
1.20.1 SCSG Operation
The SCSG1 and SCSG2 are both down count timers.
When the count of a timer reaches 0016, an underflow
occurs at the next count pulse and the contents of the
corresponding timer reload latch are loaded into the
timer. For the count operation for SCSG1 with the
Data Write Mode set to write to the latch only (see
Figure 1.50).
A memory map and the initial values after reset of the
timers and timer reload latches are detailed above.
The divide ratio of each timer is given by 1/(n + 1),
where n is the value written to the timer. The output of
the first timer (SCSG1) is effectively ANDed with the
original clock (F) to provide a count source for the
second timer (SCSG2). This results in a count source
of n/(n + 1) being fed to SCSG2.
The output of the SCSG is a clock, SCSGCLK. The
frequency is calculated as follows:
SCSGCLK = B• SCSG1 •
1
SCSC1+1 SCSG2+1
where SCSG1 is the value written to SCSG1 and
SCSG2 is the value written to SCSG2.
See Figure 1.51 for the Special Count Source Mode
Register.
SCSGM0
SCSGM1
SCSGM3
SCSG1 Reload Latch (8)
Φ
SCSGM1
Count Source
SCSG1 (8)
SCSG1 Contents
SCSGM1
SCSGM2
SCSGM3
1 0 n n-1
1 0 m m-1
SCSG1 Underflow
SCSG2 Reload Latch (8)
SCSG1 Latch Contents
SCSG (8)
n
m
SCSG1 reload latch contents loaded int SCSG1
SCSGM3
SCSGCLK
(To UARTs, Timer X and SIO)
Fig. 1.50. Timer Count Operation for SCSG1
Fig. 1.49. SCSG Block Diagram
MSB
Re s e r v ed
7
Re s e r ved
Re s e r ved
Re s e r ved
SCSGM3
SCSGM2
SCSGM1
SCSGM0
L S B Address: 002F 16
Access: R/W
0
Reset: 00 16
SCSGM0
SCSGM1
SCSGM2
SCSGM3
Bits 4-7
SCSG1 Data Write Control Bit (bit 0)
0 : Write data in latch and timer
1 : Write data in latch only
SCSG1 Count Stop Bit (bit 1)
0 : Count start
1 : Count stop
SCSG2 Data Write Control Bit (bit 2)
0 : Write data in latch an timer
1 : Write data in latch only
SCSGCLK Output Control Bit (bit 3)
0 : SCSGCLK output disabled (SCSG1 and SCSG2 off)
1 : SCSGCLK output enable.
Reserved (Read/Write “0”)
Fig. 1.51. Special Count Source Mode Register (SCSM)
49
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.21 UNIVERSAL SERIAL BUS
The Universal Serial Bus (USB) has the following features:
•Complete USB Specification (version 1.1) Compatibility
•Error Handling capabilities
•FIFOs:
•Endpoint 0:
IN 16-byte OUT 16-byte
•Endpoint 1:
IN 512-byte OUT 800-byte
•Endpoint 2:
IN 32-byte OUT 32-byte
•Endpoint 3:
IN 16-byte OUT 16-byte
•Endpoint 4:
IN 16-byte OUT 16-byte
•Five independent IN endpoints
•Five independent OUT endpoints
•Complete Device Configuration
•Supports All Device Commands
•Supports Full-Speed Functions
•Support of All USB Transfer Types:
•Isochronous
•Bulk
•Control
•Interrupt
•Suspend/Resume Operation
•On-chip USB Transceiver with voltage converter
•Start-of-frame interrupt and output pin
1.21.1 USB Function Control Unit (USBFCU)
The implementation of the USB by this device is accomplished chiefly through the device’s USB Function
Control Unit. The Function Control Unit’s overall purpose is to handle the USB packet protocol layer. The
Function Control Unit notifies the MCU that a valid token has been received. When this occurs, the data
portion of the token is routed to the appropriate FIFO.
The MCU transfers the data to, or from, the host by
interacting with that endpoint’s FIFO and CSR register (see Figure 1.51).
The USB Function Control Unit is composed of five
sections:
•Serial Interface Engine (SIE)
•Generic Function Interface (GFI)
•Serial Engine Interface Unit (SIU)
•Microcontroller Interface (MCI)
•USB Transceiver
1.21.1.1 Serial Interface Engine
The SIE interfaces to the USB serial data and handles
deserialization/serialization of data, NRZI encoding/
decoding, clock extraction, CRC generation and
checking, bit stuffing, and other specifications pertaining to the USB protocol such as handling inter-packet
time-outs and PID decoding 1.
1.21.1.2 Generic Function Interface
The GFI handles all USB standard requests from the
host through the control endpoint (endpoint 0), and
handles Bulk, Isochronous and Interrupt transfers
through Endpoints 1-4. The GFI handles read pointer
reversal for re-transmission of the current data set;
write pointer reversal for re-reception of the last data
set, and data toggle synchronization.
1.21.1.3 Serial Engine Interface Unit
The SIU block decodes the Address and Endpoint
fields from the USB host.
1.21.1.4 Microcontroller Interface Unit
The MCI block handles the microcontroller interface
and performs address decoding and synchronization
of control signals.
1.21.1.5 USB Transceiver
The USB transceiver, designed to interface with the
physical layer of the USB, is compliant with the USB
Specification (version 1.1) for high speed devices. It
consists of two 6-ohm drivers, a receiver, and Schmitt
triggers for single-ended receive signals.
SIU
CPU
MCI
SIE
GFI
FIFOs
Fig. 1.51. USB Function Control Unit Block Diagram
50
Transceiver
D+
D-
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
1.21.2 USB Interrupts
There are two types of USB interrupts in this device.
USB function (including overrun/underrun, reset, suspend and resume) interrupt, which is used to control
the flow of data.
The second type is start-of-frame (SOF) interrupt,
which is used to monitor the transfer of isochronous
(ISO) data.
1.21.2.1 USB Function Interrupts
Endpoints 1-4 each have two interrupt status flags associated with them to control data transfer or to report
a STALL/UNDER_RUN/OVER_RUN condition. The
USB Endpoint x Out Interrupt Status Flag is set when
the USB FCU successfully receives a packet of data,
or the USB FCU sets the FORCE_STALL bit or the
OVER_RUN bit of the Endpoint x OUT CSR. The
USB Endpoint x In Interrupt Status Flag is set when
the USB FCU successfully sends a packet of data or
sets the UNDER_RUN bit of the Endpoint x IN CSR.
Endpoint 0 (the control endpoint) has one interrupt
status bit associated with it to control data transfer or
report a STALL condition. The USB Endpoint 0 Interrupt Status Flag is set when the USB FCU
successfully receives/sends a packet of data, sets the
SETUP_END bit or the FORCE_STALL bit, or clears
the DATA_END bit in the Endpoint 0 IN CSR. Each
endpoint interrupt is enabled by setting the corresponding bit in the USB Interrupt Enable Register 1
and 2 (see Figure 1.57 and Figure 1.58). The USB Interrupt Status Register 1 and 2, shown in Figure 1.55
and Figure 1.56, are used to indicate pending interrupts for a given endpoint. The USB FCU sets the
interrupt status bits. The CPU writes a “1” to clear the
corresponding status bit. By writing back the same
value it read, the CPU will clear all the existing interrupts. The CPU must read then write both status
registers, writing status register 1 first and status register 2 second to guarantee proper operation.
The Suspend Signaling Interrupt Status Flag is set if
the USB FCU does not detect any bus activity on D+/
D- for at least 3ms. The Resume Signaling Interrupt
Status Flag is set when a USB FCU is in the suspend
state and detects non-idle signaling on D+/D-. There
is an interrupt enable bit for the suspend interrupt (bit
7 of Interrupt Enable Register 2), but not one for the
resume interrupt. The resume interrupt is always enabled.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
The USB Reset Interrupt Status Flag is set if the USB
FCU sees a SE0 present on D+/D- for at least 2.5ms.
When this bit is set, all USB internal registers (except
for this bit) are reset to their default values. This bit is
cleared by the CPU writing a “1” to it. When the CPU
detects a USB reset interrupt, it needs to re-initialize
the USB FCU in order for it to accept packets from
the host. The USB reset interrupt is always enabled.
The Overrun/Underrun Interrupt Status Flag is set
(applicable to endpoints used for isochronous data
transfer) when an overrun condition occurs in an endpoint (CPU is too slow to unload the data from the
FIFO), or when an underrun condition occurs in an
endpoint (CPU is too slow to load the data to the
FIFO).
The USB Function Interrupt (sum of all individual
function interrupts) is enabled by setting bit 0 of Interrupt Control Register A (ICONA) to a “1”.
1.21.2.2 USB SOF Interrupt
The USB SOF (Start-Of-Frame) interrupt is used to
control the transfer of isochronous data. The USB
FCU generates a start-of-frame interrupt when a
start-of-frame packet is received. The USB SOF interrupt is enabled by setting bit 1 of ICONA to a “1”.
1.21.3 USB Endpoint FIFOs
The USB FCU has an IN (transmit) FIFO and an OUT
(receive) FIFO for each endpoint. Each endpoint (except endpoint 0) can be configured to support both
single packet mode (only a single data packet is allowed to reside in the endpoint’s FIFO) or dual packet
mode (up to two data packets are allowed to reside in
the endpoint’s FIFO), which provides support for
back-to-back transmission or back-to-back reception.
The mode configuration is automatically set by the
MAXP value. When MAXP > 1/2 of the endpoint’s
FIFO size, single packet mode is set. When MAXP <=
1/2 of the endpoint’s FIFO size, dual packet mode is
set.
Throughout this specification, the terms “IN FIFO”
and “OUT FIFO” refer to the FIFOs associated with
the current endpoint as specified by the Endpoint Index Register.
In the event of a bad transmission/reception, the USB
FCU handles all the read/write pointer reversal and
data set management tasks when it is applicable.
51
MITSUBISHI MICROCOMPUTERS
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1.21.3.1 IN (Transmit) FIFOs
The CPU/DMA writes data to the endpoint’s IN FIFO
location specified by the FIFO write pointer, which automatically increments by “1” after a write. The CPU/
DMA should only write data to the IN FIFO if the
IN_PKT_RDY bit of the IN CSR is a “0”.
•Endpoint 0 IN FIFO Operation:
The CPU writes a “1” to the IN_PKT_RDY bit after it
finishes writing a packet of data to the IN FIFO. The
USB FCU clears the IN_PKT_RDY bit after the
packet has been successfully transmitted to the host
(ACK is received from the host) or the SETUP_END
bit of the IN CSR is set to a “1”.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
to accept another data packet. (The FIFO can hold
up to two data packets at the same time in this configuration for back-to-back transmission). Since the
set and the clear operations could be as fast as
83ns (one 12MHz clock period) apart from each
other, the set may be transparent to the user.
A software or a hardware flush causes the USB FCU
to act as if a packet has been successfully transmitted out to the host. If there is one packet in the IN
FIFO, a flush will cause the IN FIFO to be empty. If
there are two packets in the IN FIFO, a flush will
cause the older packet to be flushed out from the IN
FIFO. A Flush will also update the IN FIFO status bits
IN_PKT_RDY and TX_NOT_EMPTY.
•Endpoint 1-4 IN FIFO Operation when AUTO_SET The status of endpoint 1-4 IN FIFOs for both of the
(bit 7 of IN CSR) = “0”:
MAXP > 1/2 of the IN FIFO size: The CPU writes a
“1” to the IN_PKT_RDY bit after the CPU/DMAC
finishes writing a packet of data to the IN FIFO. The
USB FCU clears the IN_PKT_RDY bit after the
packet has been successfully transmitted to the
host (ACK is received from the host).
MAXP <= 1/2 of the IN FIFO size: The CPU writes
a “1” to the IN_PKT_RDY bit after the CPU/DMAC
finishes writing a packet of data to the IN FIFO. The
USB FCU clears the IN_PKT_RDY bit as soon as
the IN FIFO is ready to accept another data packet.
(The FIFO can hold up to two data packets at the
same time in this configuration for back-to-back
transmission). Since the set and the clear operations could be as fast as 83ns (one 12MHz clock
period) apart from each other, the set may be transparent to the user.
•Endpoint 1-4 IN FIFO Operation when AUTO_SET
(bit 7 of IN CSR) = “1”:
MAXP > 1/2 of the IN FIFO size: When the number
of bytes of data equal to the MAXP (maximum
packet size) is written to the IN FIFO by the CPU/
DMAC, the USB FCU sets the IN_PKT_RDY bit to
a “1” automatically. The USB FCU clears the
IN_PKT_RDY bit after the packet has been successfully transmitted to the host (ACK is received
from the host).
MAXP <= 1/2 of the IN FIFO size: When the number of bytes of data equal to the MAXP (maximum
packet size) is written to the IN FIFO by the CPU/
DMAC, the USB FCU sets the IN_PKT_RDY bit to
a “1” automatically. The USB FCU clears the
IN_PKT_RDY bit as soon as the IN FIFO is ready
52
above cases can be obtained from the IN CSR of the
corresponding IN FIFO as shown in Table 1.8.
Table 1.8. Endpoint 1_4 IN FIFO Status
IN_PKT_RDY
0
TX_NOT_EMPTY
0
0
1
1
0
1
1
TX FIFO Status
No Data packet in TX FIFO
One data packet in TX FIFO if MAXP <=
1/2 of the FIFO size
Invalid if MAXP > 1/2 of the FIFO size/
Invalid
Two data packets in TX FIFO if MAXP <=
1/2 of the FIFO size
OR
One data packet in TX FIFO if MAXP >
1/2 of the FIFO size
•Interrupt Endpoints:
Any endpoint can be used for interrupt transfers. For
normal interrupt transfers, the interrupt transactions
behave the same as bulk transactions, i.e.; no special
setting is required. The IN endpoints may also be
used to communicate rate feedback information for
certain types of isochronous functions. This is done
by setting the INTPT bit in the IN CSR register of the
corresponding endpoint. When the INTPT bit is set,
the data toggle bits will be changed after each packet
is sent to the host without regard to the presence or
type of handshake packet.
MITSUBISHI MICROCOMPUTERS
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The following outlines the operation sequence for an
IN endpoint used to communicate rate feedback information:
1. Set MAXP > 1/2 of the endpoint’s FIFO size
2. Set the INTPT bit of the IN CSR
3. Flush the old data in the FIFO
4. Load interrupt status information and set the
IN_PKT_RDY bit in the IN CSR
5. Repeat steps 3 and 4 for all subsequent interrupt
status updates.
In real applications, if an interrupt endpoint is used for
rate feedback, the function always has data to send
back to the host, even if that data conveys that everything is ‘fine’. Therefore the device never NAKs an IN
token from the host. The device always sends out the
data in the FIFO in response to an IN token irrespective of the IN_PKT_RDY bit.
1.21.3.2 OUT (Receive) FIFOs
The USB FCU writes data to the endpoint’s OUT
FIFO location specified by the FIFO write pointer,
which automatically increments by one after a write.
When the USB FCU has successfully received a data
packet, it sets the OUT_PKT_RDY bit to a “1” in the
OUT CSR. The CPU/DMAC should only read data
from the OUT FIFO if the OUT_PKT_RDY bit of the
OUT CSR is a “1”, with the exception of endpoint 1
(see detailed description below).
•Endpoint 0 OUT FIFO Operation:
The USB FCU sets the OUT_PKT_RDY bit to a “1”
after it has successfully received a packet of data
from
the
host.
The
CPU
sets
bit
SERVICED_OUT_PKT_RDY to a “1” to clear the
OUT_PKT_RDY bit after the packet of data has been
unloaded from the OUT FIFO by the CPU.
•Endpoint 1-4 OUT FIFO Operation when
AUTO_CLR (bit 7 of OUT CSR) = “0”:
MAXP > 1/2 of the OUT FIFO size: The USB FCU
sets the OUT_PKT_RDY bit to a “1” after it has successfully received a packet of data from the host.
The CPU writes a “0” to the OUT_PKT_RDY bit after the packet of data has been unloaded from the
OUT FIFO by the CPU/DMAC.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
the OUT FIFO by the CPU/DMAC. In this configuration, the FIFO can hold up to two data packets at
the same time for back-to-back reception. Therefore, the OUT_PKT_RDY bit will remain set after
the CPU writes a “0” to it if there is another packet
in the OUT FIFO.
•Endpoint 1-4 OUT FIFO Operation when
AUTO_CLR (bit 7 of OUT CSR) = “1”:
MAXP > 1/2 of the OUT FIFO size: The USB FCU
sets the OUT_PKT_RDY bit to a “1” after it has successfully received a packet of data from the host.
The USB FCU clears the OUT_PKT_RDY bit to a
“0” automatically when the number of bytes of data
equal to the MAXP (maximum packet size) have
been unloaded from the OUT FIFO by the CPU/
DMAC.
MAXP <= 1/2 of the OUT FIFO size: The USB
FCU sets the OUT_PKT_RDY bit to a “1” after it
has successfully received a packet of data from the
host. The USB FCU clears the OUT_PKT_RDY bit
to a “0” automatically when the number of bytes of
data equal to the MAXP (maximum packet size)
have been unloaded from the OUT FIFO by the
CPU/DMAC. In this configuration, the FIFO can
hold up to two data packets at the same time for
back-to-back
reception.
Therefore,
the
OUT_PKT_RDY bit will remain set after one packet
(size equal to MAXP) of data has been unloaded if
there is another packet in the OUT FIFO.
A software flush causes the USB FCU to act as if a
packet has been unloaded from the OUT FIFO. If
there is one packet in the OUT FIFO, a flush will
cause the OUT FIFO to be empty. If there are two
packets in the OUT FIFO, a flush will cause the older
packet to be flushed out from the OUT FIFO.
Special case for OUT Endpoint 1:
In addition to the OUT FIFO operations described
above, the DMAC can also start unloading the OUT
FIFO as soon as there is data in it (byte-by-byte
transfer). This feature should only be used with ISO
transfers. See DMAC section for details.
MAXP <= 1/2 of the OUT FIFO size: The USB
FCU sets the OUT_PKT_RDY bit to a “1” after it
has successfully received a packet of data from the
host. The CPU writes a “0” to the OUT_PKT_RDY
bit after the packet of data has been unloaded from
53
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.21.4 USB Special Function Registers
The MCU controls USB operation through the use of
special function registers (SFR). This section describes in detail each USB related SFR. Certain USB
SFRs are endpoint-indexed: the Control & Status
Registers (IN CSR and OUT CSR), the Maximum
Packet Size Registers (IN MAXP and OUT MAXP),
and the Write Count Registers (OUT WRT CNT). To
access each endpoint-indexed SFR, the target endpoint number should be written to the Endpoint Index
Register first. The lower 3 bits (EPINDX2:0) of the
Endpoint Index Register are used for endpoint selection.
Note: Each endpoint’s FIFO Register is NOT endpoint-indexed.
Some USB special function registers have a mix of
read/write, read only, and write-only register bits. Ad-
MSB
7
USBC7
USBC6
USBC5
USBC4
USBC3
Re s e r v ed
USBC1
ditionally, the bits may be configured to allow the user
to write only a “0” or a “1” to individual bits. When accessing these registers, writing a “0” to a register that
can only be set to a “1” by the CPU will have no affect
on that register bit. Each figure and description of the
special function registers will detail this operation.
The USB Control Register (USBC), shown in Figure
1.52, is used to control the USB FCU. A USB reset
signaling does not reset this register. After the USB is
enabled (USBC7 set to “1”), a minimum delay of 250
ns (three 12Mhz clock periods) is needed before performing any other USB register read/write operations.
The USB Function Address Register (USBA),
shown in Figure 1.53, maintains the 7-bit USB address assigned by the host. The USB FCU uses this
register value to decode USB token packet addresses. At reset, when the device is not yet
configured, the value is 0016.
Re s e r v ed
LSB
0
Address: 0013 16
Access: R/W
Reset: 00 16
Bit 0
USBC1
Reserved (Read/Write “0”)
USB Default State Selection Bit (bit 1)
0: In default state after power/reset
1: In default state after USB reset signaling received
Bit 2
Reserved (Read/Write “0”)
USBC3
Transceiver Voltage Converter High/Low Current Mode Select Bit (bit 3)
0: High current mode
1: Low current mode
USB Transceiver Voltage Converter Bit (bit 4)
0: USB transceiver voltage converter disabled
1: USB transceiver vlotage converter enabled
USB Clock Enabled Bit (bit 5)
0: 48 MHz clock to the USB block is disabled
1: 48 Mhz clock to the USB block is enabled
USB SOF Port Select Bit (bit 6)
0: USB SOF output is disabled P70 is used to GPIO pin
1: USB SOF output is enabled
USB Enable Bit (bit 7)
0: USB block is disabled, all USB internal registers are held at their default values
1: USB block is enabled
USBC4
USBC5
USBC6
USBC7
Fig. 1.52. USB Control Register (USBC)
MSB
Re s e r ved
7
FUNAD6
FUNAD5
FUNAD4
FUNAD3
Fig. 1.53. Function Address Register (USBA)
54
FUNAD2
FUNAD1
FUNAD0
LSB
0
Address: 0050 16
Access: R/W
Reset: 00 16
FUNAD6:0
7-bit programmable Function Address (bit 6-0)
Bit 7
Reserved (Read/Write “0”)
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
The USB Power Management Register, shown in
Figure 1.54, is used for power management in the
USB FCU.
•USB Suspend Detection Flag (SUSPEND)
When the USB FCU does not detect any bus activity on D+/D- for at least 3ms, it sets the Suspend
Detection Flag (SUSPEND) and generates an interrupt. This bit is cleared when signaling (from the
host) is detected on D+/D- [which sets the Resume
Detection Flag (RESUME) and generates an interrupt] or the Remote Wake-up Bit (WAKEUP) is set
and then cleared by the CPU. If the USB clock was
disabled during the suspend state, the SUSPEND
bit is not cleared until after the USB clock is re-enabled.
MSB
Re s e r v ed
7
Re s e r ved
Re s e r ved
Re s e r ved
Re s e r ved
WAKEUP
RESUME SUSPEND
•USB Resume Detection Flag (RESUME)
When the USB FCU is in the suspend state and detects signaling on D+/D- (from the host), it sets the
Resume Detection Flag (RESUME) and generates
an interrupt. The CPU writes a “1” to INST14 (bit 6
of USB Interrupt Status Register 2) to clear this
flag.
•USB Remote Wake-up Bit (WAKEUP)
The CPU writes a “1” to the WAKEUP bit for remote
wake-up. While this bit is set, and the USB FCU is
in suspend mode, it will generate resume signaling
to the host. The CPU must keep this bit set for a
minimum of 10ms and a maximum of 15ms before
writing a “0” to this bit.
LSB
0
Address: 0051 16
Access: R/W
Reset: 00 16
SUSPEND
RESUME
WAKEUP
Bit7:3
USB Suspend Detection Flag (bit 0) (Read only)
0: No USB suspend detected
1: Idle state for greater than 3ms (USB suspend) detected
USB Resume Detection Flag (bit 1)(Read only)
0: No USB resume signaling detected
1: USB resume signaling detected
USB Remote Wake-up Bit (bit 2)
0: End remote resume signaling
1: Send remote resume signaling (only if SUSPEND = “1”)
Reserved (Read/Write “0”)
Fig. 1.54. USB Power Management Register (USBPM)
55
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
The USB FCU is able to generate a USB function interrupt as discussed in section 1.21.2.1. The USB
Interrupt Status Registers (USBIS1, USBIS2),
shown in Figure 1.55 and Figure 1.56, are used to indicate the condition that caused a USB function
interrupt to be generated. A “1” indicates that the corresponding condition caused a USB function interrupt.
The USB Interrupt Status Register can be cleared by
MSB
7
INTST7
INTST6
INTST5
INTST4
INTST3
INTST2
Re s e r ved
INTST0
writing back to the register the same value that was
read. To ensure proper operation, the CPU should read
both USB interrupt status registers, then write back
the same values it read to these two registers for
clearing the status bits. The CPU must write to USB
Interrupt Status Register 1 first and then to USB Interrupt Status Register 2. The registers cannot be
cleared by writing a “0” to the bits that are a “1”.
LSB
0
Address: 0052 16
Access: R/W
Reset: 00 16
INTST0
USB Endpoint 0 Interrupt Status Flag (bit 0)
Bit 1
Reserved (Read/Write “0”)
INTST2
INTST3
INTST4
INTST5
INTST6
INTST7
USB
USB
USB
USB
USB
USB
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
0:
1:
1
1
2
2
3
3
IN Interrupt Status Flag (bit 2)
OUT Interrupt Status Flag (bit 3)
IN Interrupt Status Flag (bit 4)
OUT Interrupt Status Flag (bit 5)
IN Interrupt Status Flag (bit 6)
OUT Interrupt Status Flag (bit 7)
No interrupt request issued
Interrupt request issued
Fig. 1.55. USB Interrupt Status Register 1 (USBIS1)
MSB
INTST15
7
INTST14
INTST13
INTST12
Re s e r ved
Re s e r ved
INTST9
INTST8
LSB
0
Address: 0053 16
Access: R/W
Reset: 00 16
INTST8
USB Endpoint 4 In Interrupt Status Flag (bit 0)
INTST9
USB Endpoint 4 Out Interrupt Status Flag (bit 1)
Bit 3:2
Reserved (Read/Write “0”)
INTST12
INTST13
INTST14
INTST15
USB
USB
USB
USB
Overrun/Underrun Interrupt Status Flag (bit 4)
Reset Interrupt Status Flag (bit 5)
Resume Signaling Interrupt Status Flag (bit 6)
Suspend Signaling Interrupt Status Flag (bit 7)
0:
1:
Fig. 1.56. USB Interrupt Status Register 2 (USBIS2)
56
No interrupt request issued
Interrupt request issued
MITSUBISHI MICROCOMPUTERS
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MSB
INTEN7
7
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTEN6 INTEN5 INTEN4 INTEN3
LSB
INTEN2 Re s e r ved INTEN0 0
Address: 0054 16
Access: R/W
Reset: FF 16
INTST0
USB Endpoint 0 Interrupt Status Flag (bit 0)
Bit 1
Reserved (Read/Write “0”)
INTST2
INTST3
INTST4
INTST5
INTST6
INTST7
USB
USB
USB
USB
USB
USB
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
Endpoint
0:
1:
1
1
2
2
3
3
IN Interrupt Enable Bit (bit 2)
OUT Interrupt Enable Bit (bit 3)
IN Interrupt Enable Bit (bit 4)
OUT Interrupt Enable Bit (bit 5)
IN Interrupt Enable Bit (bit 6)
IN Interrupt Enable Bit (bit 7)
Interrupt disabled
Interrupt enabled
Fig. 1.57. USB Interrupt Enable Register 1 (USBIE1)
MSB
INTEN15
7
Re s e r v ed
Re s e r v ed
INTEN12
Re s e r v ed
Re s e r ved
INTEN9
INTEN8
LSB
0
Address: 0055 16
Access: R/W
Reset: 33 16
INTEN8
INTEN9
USB Endpoint 4 IN Interrupt Enable Bit (bit 0)
USB Endpoint 4 Out Interrupt Enable Bit (bit 1)
Bit 3:2
Reserved (Read/Write “0”)
INTST12
USB Overrun/Underrun Interrupt Enable Bit (bit 4)
Bit 5
Bit 6
Reserved (Read/Write “1”)
Reserved (Read/Write “0”)
INTEN15
USB Suspend Signaling Interrupt Enable Bit (bit 7)
0: Interrupt disabled
1: Interrupt enabled
Fig. 1.58. USB Interrupt Enable Register 2 (USBIE2)
The USB Interrupt Enable Registers (USBIE1,
USBIE2) shown in Figure 1.57 and Figure 1.58, are
used to enable the corresponding interrupt status
conditions that can generate a USB function interrupt.
If the bit to a corresponding interrupt condition is “0”,
that condition will not generate a USB function interrupt. If the bit is a “1”, that condition can generate a
USB function interrupt. Upon reset, all USB interrupt
status conditions are enabled except the USB Suspend Signaling Interrupt (bit 7 of USB Interrupt Enable
Register 2), which is disabled. The USB Reset Interrupt and USB Resume Signaling Interrupt are always
enabled.
INTST0 is set to a “1” by the USB FCU if (in Endpoint
0 IN CSR):
•A packet of data is successfully received
•A packet of data is successfully sent
•IN0CSR3 (DATA_END) bit is cleared (by USB FCU)
•IN0CSR4 (FORCE_STALL) bit is set (by the USB
FCU)
•IN0CSR5 (SETUP_END) bit is set (by the USB FCU)
INTST2, INTST4, INTST6 or INTST8 is set to a “1” by
USB FCU if (in Endpoint x IN CSR):
•A packet of data is successfully sent
•INXCSR1 (UNDER_RUN) bit is set (by USB FCU)
INTST3, INTST5, INTST7 or INTST9 is set to a “1” by
USB FCU if (in Endpoint xOUT CSR):
•A packet of data is successfully received
•OUTXCSR1 (OVER_RUN) bit is set (by USB FCU)
•OUTXCSR4 (FORCE_STALL) bit is set (by USB
FCU)
INTST12 is set to a “1” by the USB FCU if an overrun
or underrun condition occurs in any of the endpoints.
INTST13 is set to a “1” by the USB FCU if USB reset
signaling from the host is received. All USB internal
registers other than this bit are reset to their default
values when the USB reset is received.
INTST14 is set to a “1” by the USB FCU when the
USB FCU is in the suspend state and non-idle signaling on D+/D- is received.
INTST15 is set to a “1” by the USB FCU when D+/Dare in the idle state for more than 3ms.
57
MITSUBISHI MICROCOMPUTERS
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MSB
7
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FN7
FN6
FN5
FN4
FN3
FN2
FN1
FN0
LSB
0
Address: 0056 16
Access: R
Reset: 00 16
FN7:0
Lower 8 bits of 11-bit frame number issued with a SOF token
LSB
0
Address: 0057
Access: R
Reset: 00 16
FN10:8
Upper 3 bits of the 11-bit frame number issued with a SOF token
Bits 7:3
Reserved (Read "0")
Fig. 1.59. USB Frame Number Low Register (USBSOFL)
MSB
Re s e r ved
7
Re s e r v ed
Re s e r v ed
Re s e r v ed
Re s e r ved
FN10
FN9
FN8
Fig. 1.60. USB Frame Number High Register (USBSOFH)
MSB
ISO_UPD AUTO_FL Re s e r ved Re s e r ved Re s e r v ed
7
EPINDX2
EPINDX1
EPINDX0
LSB
0
Address: 0058 16
Access: R/W
Reset: 00 16
EPINDX2:0 Endpoint Index:
Bit 2
Bit 1
0
0
0
0
0
1
0
1
1
0
Others:
Bit 0
0:
1:
0:
1:
0:
Function Endpoint
Function Endpoint
Function Endpoint
Function Endpoint
Function Endpoint
Undefined
Bits 3:5
Reser ved (Read/Write "0")
AUTO_FL
AUTO_FLUSH Bit (bit 6)
0:
Hardware auto FIFO flush disabled
1:
Hardware auto FIFO flush enabled
ISO_UPDATE Bit (Bit 7)
0:
ISO_UPDATE disabled
1:
ISO_UPDATE enabled
ISO_UPD
0
1
2
3
4
Fig. 1.61. USB Endpoint Index Register (USBINDEX)
The USB Frame Number Low Register
(USBSOFL), shown in Figure 1.59, contains the
lower 8 bits of the 11-bit frame number received from
the host.
The USB Frame Number High Register
(USBSOFH), shown in Figure 1.60, contains the upper 3 bits of the 11-bit frame number received from
the host.
The USB Endpoint Index Register (USBINDEX),
shown in Figure 1.61, identifies the endpoint pair. It
serves as an index to endpoint-specific IN CSR, OUT
CSR, IN MAXP, OUT MAXP and OUT WRT CNT registers.
This register also contains two global bits, ISO_UPD
and AUTO_FL, which affect isochronous data transfers for endpoints 1-4.
58
If ISO_UPD = “0”, a data packet in an endpoint’s IN
FIFO is always ‘ready to transmit’ upon receiving the
next IN_TOKEN from the host (with matched address
and endpoint number). If ISO_UPD = “1” and the ISO
bit of the corresponding endpoint’s IN CSR is set,
then the internal ‘ready to transmit’ signal to the transmit control logic is delayed until the next SOF. In this
way the data loaded in frame n will be transmitted out
in frame n+1. The ISO_UPD bit is a global bit for endpoints 1 to 4, and works with isochronous pipes only.
If AUTO_FL = “1”, ISO_UPD = “1”, and a particular IN
endpoint’s ISO bit is set, then when the USB FCU detects an SOF packet, if the corresponding IN
endpoint’s IN_PKT_RDY = “1”, the USB FCU automatically flushes the oldest packet from the IN FIFO.
In this case, IN_PKT_RDY = “1” indicates that two
data packet are in the IN FIFO. Since, for ISO transfer, double buffering is a requirement; MAXP must set
to be less than or equal to 1/2 of the FIFO size.
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MSB
LSB
INOCSR7 INOCSR6 INOCSR5 INOCSR4 INOCSR3 INOCSR2 INOCSR1 INOCSR0
7
0
INOCSR0
INOCSR1
INOCSR2
INOCSR3
INOCSR4
INOCSR5
INOCSR6
INOCSR7
Address: 0059 16
Access: R/W
Reset: 00 16
OUT_PKT_RDY Flag (bit 0) (Read Only - Write "0")
0: Out packet is not ready
1: Out packet is ready
IN_PKT_RDY Bit (bit 1)(Write "1" only or Read)
0: In packet is not ready
1: In packet is ready
SEND_STALL Bit (bit 2)(Write "1" only or Read)
0: No action
1: Stall Endpoint 0 by the CPU
DATA_END Bit (bit 3)(Write "1" only or Read)
0: No action
1: Last packet of data transfered from/to the FIFO
Force_STALL Flag (bit 4)(Write "0" only or Read)
0: No action
1: Stall Endpoint 0 by the USB FCU
SETUP_END Flag (bit 5) (Read Only - Write "0")
0: No Action
1: Control transfer ended before the specific length of data is transferred during
the data phase
SERVICED_OUT_PKT_RDY Bit (bit 6) (Write Only - Read "0")
0: No change
1: Clear the OUT_PKT_RDY bit (INOCSR0)
SERVICED_SETUP_END Bit (bit 7)(Write Only - Read "0")
0: No change
1: Clear the SETUP_END bit (INOCSR5)
Fig. 1.62. USB Endpoint 0 IN CSR (IN_CSR)
The USB Endpoint 0 IN CSR Control & Status
Register, shown in Figure 1.62, contains the control
and status information of Endpoint 0.
IN0CSR0 (OUT_PKT_RDY): The USB FCU sets this
bit to a “1” upon receiving a valid SETUP/OUT token
from the host. The CPU clears this bit after unloading
the FIFO, by way of writing a “1” to IN0CSR6. The
CPU should not clear the OUT_PKT_RDY bit before it
finishes decoding the host request. If IN0CSR2
(SEND_STALL) needs to be set (because the CPU
decodes an invalid or unsupported request), the setting of IN0CSR6 = “1” and IN0CSR2 = “1” should be
done in the same CPU write.
IN0CSR1 (IN_PKT_RDY): The CPU writes a “1” to
this bit after it finishes writing a packet of data to the
endpoint 0 FIFO. The USB FCU clears this bit after
the packet has been successfully transmitted to the
host, or the IN0CSR5 (SETUP_END) bit is set.
IN0CSR2 (SEND_STALL): The CPU writes a “1” to
this bit if it decodes an invalid or unsupported request
from the host. If the OUT_PKT_RDY bit is a “1” at the
time the CPU wants to set the SEND_STALL bit is to
a
“1”,
the
CPU
must
also
set
SERVICED_OUT_PKT_RDY to a “1” to clear the
OUT_PKT_RDY. The USB FCU returns a STALL handshake for all subsequent IN/OUT transactions (during
control transfer data or status stages) while this bit is
set. The CPU writes a “0” to this bit to clear it.
IN0CSR3 (DATA_END): For control transfers, the CPU
writes a “1” to this bit after it writes (IN data phase) or
reads (OUT data phase) the last packet of data from/
to the FIFO. This bit indicates to the USB FCU that
the specific amount of data in the setup phase has
been transferred. The USB FCU will advance to the
status phase once this bit is set. When the status
phase completes, the USB FCU clears this bit. When
this bit is set to a “1” and the host again requests or
sends more data to the device, the USB FCU returns
a STALL handshake and terminates the current control
transfer.
IN0CSR4 (FORCE_STALL): The USB FCU sets this bit
to a “1” to report an error status if the one of the following occurs:
•Host sends an IN or OUT token in the absence of a
SETUP stage
•Host sends a bad data toggle in the STATUS stage,
i.e. DATA0 is used
•Host sends a bad data toggle in the SETUP stage,
i.e. DATA1 is used
•Host requests more data than specified in the
SETUP stage, i.e. IN token comes after DATA_END
bit is set
•Host sends more data than specified in the SETUP
stage, i.e. OUT token comes after DATA_END bit is
set
•Host sends larger data packet than MAXP size of the
corresponding endpoint.
59
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
All of the conditions stated on the preceeding page
(except the bad data toggle in the SETUP state case)
cause the device to send a STALL handshake for the
IN/OUT token in question. In the bad data toggle in
the SETUP stage case, the device sends ACK for the
SETUP stage and then sends STALL for the next IN/
OUT token. A STALL handshake caused by the
above conditions lasts for only one transaction and
terminates the ongoing control transfer. Any packet
after the STALL handshake will be seen as the beginning of a new control transfer.
The CPU writes a “0” to clear this FORCE_STALL
status bit.
IN0CSR5 (SETUP_END): The USB FCU sets this bit
to a “1” if a control transfer has ended before the specific length of data is transferred during the data
phase. The CPU clears this bit by way of writing a “1”
to IN0CSR7. Once the CPU sees the SETUP_END
bit set, it should stop accessing the FIFO to service
the previous setup transaction. If OUT_PKT_RDY is
set at the same time that SETUP_END is set, it indicates that the previous setup transaction ended and a
new SETUP token is in the FIFO.
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
IN0CSR6 and IN0CSR7: These bits are used to clear
IN0CSR0 and IN0CSR5 respectively. Writing a “1” to
these bits will clear the corresponding register bit.
The USB Endpoint x IN CSR, shown in Figure 1.63,
contains control and status information of the respective IN endpoint 1-4. The USB Endpoint Index Register
selects the specific endpoint.
INXCSR0
(IN_PKT_RDY)
and
INXCSR5
(TX_FIFO_NOT_EMPTY): These two bits are read
together to determine IN FIFO status. A “1” can be
written to the INXCSR0 bit by the CPU to indicate a
packet of data is written to the FIFO (See Chapter.
for detail).
INXCSR1 (UNDER_RUN): This bit is used in ISO
mode only to indicate to the CPU that a FIFO
underrun has occurred. The USB FCU sets this bit to
a “1” at the beginning of an IN token if no data packet
is in the FIFO. Setting this bit will cause the INST12
bit of the Interrupt Status Register 2 to set. The CPU
writes a “0” to clear this bit.
INXCSR2 (SEND_STALL): The CPU writes a “1” to
this bit when the endpoint is stalled (transmitter halt).
The USB FCU returns a STALL handshake while this
bit is set. The CPU writes a “0” to clear this bit.
MSB
LSB
INXCSR7 INXCSR6 INXCSR5 INXCSR4 INXCSR3 INXCSR2 INXCSR1 INXCSR0
7
0
INXCSR0
INXCSR1
INXCSR2
INXCSR3
INXCSR4
INXCSR5
INXCSR6
INXCSR7
Fig. 1.63. USB Endpoint x IN CSR (IN_CSR)
60
Address: 0059 16
Access: R/W
Reset: 00 16
IN_PKT_RDY Bit (bit 0)(Write "1" only or Read)
0: In packet is not ready
1: In packet is ready
UNDER_RUN Flag (bit 1)(Write "0" only or Read)
0: No FIFO underrun
1: FIFO underrun has occurred
SEND_STALL Bit (bit 2)
0: No action
1: Stall IN Endpoint X by the CPU
ISO/TOGGLE_INIT Bit (bit 3)
0: Select non-isochronous transfer (0->1->0) reset data tog gle to DATA0
1: Select isochronous transfer
INTPT Bit (bit 4)
0: Select non-rate feedback interr upt transfer
1: Select rate feedback interr upt transfer
TX_NOT_EPT Flag (bit 5) (Read Only - Write "0")
0: Transmit FIFO is empty
1: Transmit FIFO is not empty
FLUSH Bit (bit 6) (Write Only - Read "0")
0: No action
1: Flush the FIFO
AUTO_SET Bit (bit 7)
0: AUTO_SET disabled
1: AUTO_SET enabled
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INXCSR3 (ISO/TOGGLE_INIT): When the endpoint is
used for isochronous data transfer, the CPU sets this
bit to a “1” for the entire duration of the isochronous
transfer. With the ISO bit set to a “1”, the device uses
DATA0 as the PID for all packets sent back to the
host.
When the endpoint is required to initialize the data
toggle sequence bit (reset to DATA0 for the next data
packet), the CPU sets this bit to a “1” and then resets
it to a “0” to initialize the respective endpoint’s data
toggle.
As with any other method to initialize the data toggle,
this set/reset of the TOGGLE_INIT bit method assumes that there is no active IN transaction to the
respective endpoint on the bus at the time the initialization process is ongoing. Set/reset of the
TOGGLE_INIT bit is performed only when an endpoint experiences a configuration event.
INXCSR4 (INTPT): The CPU writes a “1” to this bit to
initialize this endpoint as a status change endpoint for
IN transactions. This bit is set only if the corresponding endpoint is to be used to communicate rate
feedback information (see section 1.21.3.1 for details).
MSB
Re s e r ved
7
Re s e r v ed
Re s e r v ed
Re s e r v ed
Re s e r ved
Re s e r v ed
Re s e r v ed
Re s e r v ed
INXCSR5 (TX_FIFO_NOT_EMPTY): The USB FCU
sets this bit to a “1” when there is data in the IN FIFO.
This bit in conjunction with IN_PKT_RDY bit will provide the transmit FIFO status information (see section
1.21.3.1 for details).
INXCSR6 (FLUSH): The CPU writes a “1” to this bit
to flush the IN FIFO. If there is one packet in the IN
FIFO, a flush will cause the IN FIFO to be empty. If
there are two packets in the IN FIFO, a flush will
cause the older packet to be flushed out from the IN
FIFO. Setting the INXCSR6 (FLUSH) bit during transmission could produce unpredictable results.
INXCSR7 (AUTO_SET): If the CPU sets this bit to a
“1”, the IN_PKT_RDY bit is set automatically by the
USB FCU after the number of bytes of data equal to
the maximum packet size (MAXP) are written into the
IN FIFO (see section 1.21.3.1 for details).
All bits in USB Endpoint 0 OUT CSR (Control &
Status Register), shown in Figure 1.64, are reserved
(all control and status information is in Endpoint 0 IN
CSR)
LSB
0
Address: 005A 16
Access: R
Reset: 00 16
Bits 7:0
Reser ved (Read "0")
Fig. 1.64. USB Endpoint 0 OUT CSR (OUT_CSR)
61
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
MSB
7
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
OUTXCSR7
OUTXCSR6
OUTXCSR5
OUTXCSR4
OUTXCSR3
OUTXCSR2
OUTXCSR1
OUTXCSR0
LSB
0
OUTXCSR0
OUTXCSR1
OUTXCSR2
OUTXCSR3
OUTXCSR4
OUTXCSR5
OUTXCSR6
OUTXCSR7
Address: 005A 16
Access: R/W
Reset: 00 16
OUT_PKT_RDY Flag (bit 0) (Write "0" onlyor Read)
0: Out packet is not ready
1: Out packet is ready
OVER_RUN Flag (bit 1) (Write "0" only or Read)
0: No FIFO overrun
1: FIFO overrun occurred
SEND_Stall Bit (bit 2)
0: No action
1: Stall OUT Endpoint X by the CPU
ISO/TOGGLE_INIT Bit (bit 3)
0: Select non-isochronous transfer (0->1->0) reset data toggle to DATA0)
1: Select isochronous transfer
FORCE_STALL Flag (bit 4) (Write "0" only or Read)
0: No action
1: Stall Endpoint X by the USB FCU
DATA_ERR Flag (bit 5) (Write "0" only or Read)
0: No error
1: CRC or bit stuffing error received in an ISO packet
FLUSH Bit (bit 6) (Write Only - Read "0")
0: No action
1: Flush the FIFO
AUTO_CLR Bit (bit 7)
1: AUTO_CLR disabled
0: AUTO_CLR enabled
Fig. 1.65. USB Endpoint x OUT CSR (OUT_CSR)
The USB Endpoint x OUT CSR (Control & Status
Register), shown in Figure 1.65, contains control and
status information of the respective OUT endpoint 14. The USB Endpoint Index Register selects the
specific endpoint.
OUTXCSR0 (OUT_PKT_RDY): The USB FCU sets
this bit to a “1” after it successfully receives a packet
of data from the host. This bit is cleared by the CPU
or by the USB FCU after a packet of data has been
unloaded from the FIFO (See section 1.21.3.2 for details).
OUTXCSR1 (OVER_RUN): This bit is used in ISO
mode only to indicate to the CPU that a FIFO overrun
has occurred. The USB FCU sets this bit to a “1” at
the beginning of an OUT token if the OUTXCSR0
(OUT_PKT_RDY) bit is not cleared. Setting this bit
will cause the INST12 bit of the Interrupt Status Register 2 to set. The CPU writes a “0” to clear this bit.
OUTXCSR2 (SEND_STALL): The CPU writes a “1”
to this bit when the endpoint is stalled (receiver halt).
The USB FCU returns a STALL handshake while this
bit is set. The CPU writes a “0” to clear this bit.
OUTXCSR3 (ISO/TOGGLE_INIT): When the endpoint is used for isochronous data transfer, the CPU
sets this bit to a “1” for the entire duration of the isochronous transfer. With the ISO bit set to a “1”, the
device accepts either DATA0 or DATA1 for the PID
sent by the host.
When the endpoint is required to initialize the data
toggle sequence bit (reset to DATA0 for the next data
packet), the CPU sets this bit to a “1” and then resets
62
it to a “0” to initialize the respective endpoint’s data
toggle.
As with any other method to initialize the data toggle,
this set/reset of the TOGGLE_INIT bit method assumes that there is no active OUT transaction to the
respective endpoint on the bus at the time the initialization process is ongoing. Set/reset of the
TOGGLE_INIT bit is performed only when an endpoint experiences a configuration event.
OUTXCSR4 (FORCE_STALL): The USB FCU sets
this bit to a “1” if the host sends out a larger data
packet than the MAXP size. The USB FCU returns a
STALL handshake while this bit is set. The CPU
writes a “0” to clear this bit.
OUTXCSR5 (DATA_ERR): The USB FCU sets this
bit to a “1” to indicate the reception of a CRC error or
a bit stuffing error in an ISO packet. The CPU writes a
“0” to clear this bit.
OUTXCSR6 (FLUSH): The CPU writes a “1” to flush
the OUT FIFO. If there is one packet in the OUT
FIFO, a flush will cause the OUT FIFO to be empty. If
there are two packets in the OUT FIFO, a flush will
cause the older packet to be flushed out from the
OUT FIFO. Setting the OUTXCSR6 (FLUSH) bit during reception could produce unpredictable results.
OUTXCSR7 (AUTO_CLR): If the CPU sets this bit to
a “1”, the OUT_PKT_RDY bit is cleared automatically
by the USB FCU after the number of bytes of data
equal to the maximum packet size (MAXP) is unloaded from the OUT FIFO (see section 1.21.3.2 for
details).
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
The USB Endpoint x IN MAXP, shown in Figure 1.66,
indicates the maximum packet size (MAXP) of an
Endpoint x IN packet. The default value for Endpoint 0
and 2-4 is 8. The default value for Endpoint 1 is 1. The
CPU can change this value as negotiated with the
host controller through the SET_DESCRIPTOR command. The setting of this register also affects the
configuration of single/dual packet operation. When
MAXP > 1/2 of the FIFO size, single packet mode is
set. When MAXP <= 1/ 2 of the FIFO size, dual
packet mode is set.
The USB Endpoint x OUT MAXP, shown in Figure
1.67, indicates the maximum packet size (MAXP) of
an Endpoint x OUT packet. The default value for Endpoint 0 and 2-4 is 8. The default value for endpoint 1
is 1. For endpoint 0, the IN_MAXP and OUT_MAXP
registers shadow each other. Changing one register’s
value effectively changes the other register’s value.
MSB
IMAXP7
IMAXP6
IMAXP5
IMAXP4
IMAXP3
IMAXP2
IMAXP1
The CPU can change this value as negotiated with the
host controller through the SET_DESCRIPTOR command. The setting of this register also affects the
configuration of single/dual packet operation. When
MAXP > 1/2 of the FIFO size, single packet mode is
set. When MAXP <= 1/2 of the FIFO size, dual packet
mode is set.
The USB Endpoint x OUT WRT CNT Low and the
USB Endpoint x OUT WRT CNT High registers,
shown in Figure 1.68 and Figure 1.69, contain the
number of bytes in the Endpoint x OUT FIFO. The
USB FCU sets the values in these two Write Count
Registers after having successfully received a packet
of data from the host. The CPU reads these two registers to determine the number of bytes to be read
from the FIFO. The CPU should read WRT CNT Low
first and then WRT CNT High.
IMAXP0
LSB
IMAXP7:0
Address: 005B 16
Maximum packet size (MAXP) of Endpoint x IN packet
MAXP = n for endpoint 0,2,3,4
MAXP = n * 8 for endpoint 1
n is the value written to this register. For endpoints that support a smaller
Fig. 1.66. USB Endpoint x IN MAXP Register (IN_MAXP)
MSB
7
OMAXP7
OMAXP6
OMAXP5
OMAXP4
OMAXP3
OMAXP2
OMAXP1
OMAXP0
LSB
0
Address: 005C 16
Access: R/W
OMAXP7:0 Maximum packet size (MAXP) of Endpoint x OUT packet
MAXP = n for endpoint 0,2,3,4
MAXP = n * 8 for endpoint 1
n is the value written to this register. For endpoints that support a smaller
FIFO size, unused bits are not implemented(always write "0" to those bits)
Fig. 1.67. USB Endpoint x OUT MAXP Register (OUT_MAXP)
MSB
7
W_CNT7
W_CNT6
W_CNT5
W_CNT4
W_CNT3
W_CNT2
W_CNT1
W_CNT0
LSB
0
Address: 005D 16
Access: R
Reset: 00 16
W_CNT7:0
Byte Count. This register contains the lower 8 bits of the byte count register
Fig. 1.68. USB Endpoint x OUT WRT CNT Low Register (WRT_CNTL)
MSB
7
Re s e r ved
Re s e r v ed
Re s e r v ed
Re s e r v ed
Re s e r ved
Re s e r v ed
W_CNT9
W_CNT8
LSB
0
Address: 005E 16
Access: R
Reset: 00 16
W_CNT9:8
Byte Count. This register contains the upper 2 bits of the byte count register
Bits 7:2
Reser ved (Read "0")
Fig. 1.69. USB Endpoint x OUT WRT CNT High Register (WRT_CNTH)
63
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
The USB Endpoint x FIFO Registers, shown in Figure 1.70 through Figure 1.74, are the USB IN
(transmit) and OUT (receive) FIFO data registers.
The CPU writes data to these registers for the corresponding Endpoint IN FIFO and reads data from
these registers for the corresponding Endpoint OUT
FIFO.
MSB
DATA_7
7
DATA_6 DATA_5
DATA_4 DATA_3
DATA_2
DATA_1
LSB
DATA_0 0
Data_7:0
Address: 0060 16
Access: R/W
Reset: N/A
Endpoint 0 IN/OUT FIFO register
Fig. 1.70. USB Endpoint 0 FIFO Register (USBFIFO0)
MSB
DATA_7
7
DATA_6 DATA_5
DATA_4 DATA_3
DATA_2
DATA_1
LSB
DATA_0 0
Data_7:0
Address: 0061 16
Access: R/W
Reset: N/A
Endpoint 1 IN/OUT FIFO register
Fig. 1.71. USB Endpoint 1 FIFO Register (USBFIFO1)
MSB
DATA_7
7
DATA_6
DATA_5 DATA_4 DATA_3
DATA_2
DATA_1
LSB
DATA_0 0
Data_7:0
Address: 0062 16
Access: R/W
Reset: N/A
Endpoint 2 IN/OUT FIFO register
Fig. 1.72. USB Endpoint 2 FIFO Register (USBFIFO)
MSB
DATA_7
7
DATA_6 DATA_5
DATA_4 DATA_3
DATA_2
DATA_1
LSB
DATA_0 0
Data_7:0
Address: 0063 16
Access: R/W
Reset: N/A
Endpoint 3 IN/OUT FIFO register
Fig. 1.73. USB Endpoint 3 FIFO Register (USBFIFO3)
MSB
DATA_7
7
DATA_6 DATA_5
DATA_4 DATA_3
DATA_2
DATA_1
LSB
DATA_0 0
Data_7:0
Fig. 1.74. USB Endpoint 4 FIFO Register (USBFIFO4)
64
Address: 0064 16
Access: R/W
Reset: N/A
Endpoint 4 IN/OUT FIFO register
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.22 MASTER CPU BUS INTERFACE
When the bus interface is operating, DQ0-DQ7 become a 3-state data bus that sends and receives
data, command, and status to and from the master
CPU. At the same time, W, R, S0, S1, and A0 become
host CPU control signal input pins.
This device has a bus interface function with 2 I/O buffers that can be operated in slave mode by control
signals from the master CPU (see Figure 1.75). Bus
Interface Circuit). The bus interface can be connected
directly to either a R/W type of CPU or a CPU with RD
and WR separate signals. Slave mode is selected
with the bit 7 of the data buffer control register 0. The
single data bus buffer mode and the double data bus
buffer mode are selected with bit 7 of the Data Bus
Buffer Control register 1. When selecting the double
data bus buffer mode, Port P72 becomes S1 input.
Prior to enabling the MBI, Port 6 must be placed in input mode by writing 0016 to P6D (001516).
The two input buffer full interrupt requests and two output buffer full requests are multiplexed as shown in
Figure 1.76.
The bus interface can be operated under normal
MCU control or under on-chip DMA control for fast
data transfer. If a master CPU has a large amount of
data to be transferred, use of the on-chip DMA controller is highly recommended.
The bus interface signal input level can be programmed as CMOS level (default) or as TTL level.
Bit7 of the Port Control Register (PTC7) is used for the
input level selection.
When data is written to the MCU from the master
CPU, an input buffer full interrupt request occurs.
Similarly, when data is read from the master CPU, an
output buffer empty interrupt request occurs.
OBF0 IBF0 A0 S0 R
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
W
W
R S1 A0 IBF1OBF1
Input Data Bus Buffer 0
Output Data Bus Buffer 0
U6
U5
RD
WR
DBB 0
U4
A00
b7
U7
U6
U5
RD
WR
DBB 1
U4
A01
DBBS 0 DBBS1
U2
U2
b1
IBF 0
IBF1
b1
b0
OBF 0
OBF1
b0
b0
Data Bus Buffer Control Register 1
U7
Output Data Bus Buffer 1
b7
Input Data Bus Buffer 1
Data Bus Buffer Control Register 0
System Bus
b0
Data Bus
Fig. 1.75. Bus Interface Circuit
Input buffer full flag 0
IBF0
Input buffer full flag 1
IBF1
Output buffer full flag 0
OBF0
Output buffer full flag 1
OBF1
Rising Edge
detection circuit
One-shot pulse
generating circuit
Rising Edge
detection circuit
One-shot pulse
generating circuit
Rising Edge
detection circuit
One-shot pulse
generating circuit
Rising Edge
detection circuit
One-shot pulse
generating circuit
Input Buffer full interrupt
request signal IBF
Output Buffer Empty interrupt
request signal OBE
IBF0
IBF1
IBF
Set interrupt request at this rising edge
OBF0
(OBE0)
OBF1
(OBE1)
OBE
Set interrupt request at this rising edge
Fig. 1.76. Data Bus Buffer Interrupt Request Circuit
65
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.22.1 Data Bus Buffer Status Registers
(DBBS0, DBBS1)
A0 Flag (A00, A01)
The level of the A0 pin is latched when data has been
written from the host CPU to the input data bus buffer.
The data bus buffer status register is an 8-bit register
that indicates the data bus status, with bits 0, 1, and 3
being dedicated read-only bits. Bits 2, 4, 5, 6, and 7
are user definable flags set by software, and can be
read and write. When the A0 pin is high, the master
CPU can read the contents of this register. See Figures 1.77 to 1.80.
Output Buffer Full Flag (OBF0, OBF1)
1.22.2 Input Data Bus Buffer Registers
(DBBIN0, DBBIN1)
The data on the data bus is latched into DBBIN0 or
DBBIN1 by a write request from the master CPU. The
data in DBBIN0 or DBBIN1 can be read from the data
bus buffer register in the SFR area.
1.22.3 Output Data Bus Buffer Registers
(DBBOUT0, DBBOUT1)
The OBF0 and the OBF1 flags are set high when data
is written to the output data bus buffer by the slave
CPU and is cleared to “0” when data is read by the
master CPU.
Data is set in DBBOUT0 or DBBOUT1 by writing to
the data bus buffer register in the SFR area. When
the A0 pin is low, the data of this register is output by
a read request from the host CPU.
Input Buffer Full Flag (IBF0, IBF1)
The IBF0 and the IBF1 flags are set high when data is
written to the input data bus buffer by the master CPU
and is cleared to “0” when data is read by the slave
CPU.
MSB
7
DBBS07
DBBS06
DBBS05
DBBS04
DBBS03
DBBSO2
DBBS01
DBBS00
L S B Address: 0049 16
Access: R/W
0
Reset: 00 16
DBBS00
DBBS01
DBBS02
DBBS03
DBBS04
DBBS05
DBBS06
DBBS07
Output Buffer Full (OBF 0) Flag (bit 0)
0 : Output buffer emopty.
1 : Output buffer full.
Input Buffer Full (BF0) Flag (bit 1)
0 : Input buffer empty.
1 : Input buffer full.
User Definable (U2) Flag (bit 2)
A0(A 00) Flag (bit 3)
Indicates the A 0 status when IBF flag is set
User Definable (U4) Flag (bit 4)
User Definable (U5) Flag (bit 5)
User Definable (U6) Flag (bit 6)
User Definable (U7) Flag (bit 7)
Fig. 1.77. Data Bus Buffer Status Register 0 (DBBS0)
MSB
7
DBBC07
DBBC06
Re s e r ved
DBBC04
DBBC03
DBBCO2
DBBC01
DBBC00
L S B Address: 004A 16
Access: R/W
0
Reset: 00 16
DBBC00
DBBC01
DBBC02
DBBC03
DBBC04
DBBC05
DBBC06
DBBC07
Fig. 1.78. Data Bus Buffer Control Register 0 (DBBC0)
66
OBF Output Selection Bit (bit 0)
0 : P5 2 pin is operated as GPIO
1 : P5 2 pin is operated as OBF 0 output pin
IBF Output Selection Bit (bit 1)
0 : P5 3 pin is operated as GPIO
1 : P5 3 pin is operated as IBF 0 output pin
IBF 0 Interrupt Selection Bit (bit 2)
0 : IBF0 interrupt is generated by both write-data (A 0= “0”) and writecommand (A0 = “1”)
1 : IBF 0 interrupt is generated by write-command (A 0 = “1”) only
Output buffer 0 empty interrupt disable Bit (bit 3)
0 : Ena bled
1 : Disa bled
Input buffer 0 full interrupt disable Bit (bit 4)
0 : Ena bled
1 : Disa bled
Reser ved (Read/Write “0”)
Master CPU Bus Interface Enable Bit (bit 6)
0 : P6 0-P6 7, P5 4 -P5 7 are GPIO pins
1 : P6 0-P6 7, P5 4-P5 7 are bus interface signals DQ0-DQ7, S 0, A 0 ,
R,W respectively
Bus Interface Type Selection Bit (bit 7)
0 : RD, WR separate type bus
1 : R/W type bus.
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
MSB
7
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DBBS17
DBBS16
DBBS15
DBBS14
DBBS13
DBBS12
DBBS11
DBBS10
L S B Address: 004D 16
Access: R/W
0
Reset: 00 16
DBBS10
DBBS11
DBBS12
DBBS13
DBBS14
DBBS15
DBBS16
DBBS17
Output Buffer Full (OBF 1) Flag (bit 0)
0 : Output buffer empty.
1 : Output buffer full.
Input Buffer Full (BF0 1) Flag (bit 1)
0 : Input buffer empty.
1 : Input buffer full.
User Definable (U2) Flag (bit 3)
A 0(A 01) Flag (bit 2)
Indicates the A 0 status when IBF flag is set
User Definable (U4) Flag (bit 4)
User Definable (U5) Flag (bit 5)
User Definable (U6) Flag (bit 6)
User Definable (U7) Flag (bit 7)
Fig. 1.79. Data Bus Buffer Status Register 1 (DBBS1)
MSB
7
DBBC17
Re s e r ved
Re s e r ved
DBBC14
DBBC13
DBBC12
DBBC11
DBBC10
L S B Address: 004E 6
Access: R/W
0
Reset: 00 16
DBBC10
DBBC11
DBBC12
DBBC13
DBBC14
DBBC15
DBBC16
DBBC17
OBF 1 Output Selection Bit (bit 0)
0 : P7 4 pin is operated as GPIO
1 : P74 pin is operated as PBF1 output pin if DBBC17 = “1”
IBF1 Output Selection Bit (bit 1)
0 : P7 3 pin is operated as GPIO
1 : P73 pin is operated as IBF1 output pin if DBBC17= “1”
IBF1 Interrupt Selection Bit (bit 2)
0 : IBF1 interrupt is generated by both write-data (A0= “0”) and writecommand (A0 = “1”)
1 : IBF 1 interrupt is generated by write-command (A 0 = “1”)only
Output Buffer 1 Empty interrupt disable Bit (bit 3)
0 : Ena bled
1 : Disabled
Input Buffer 0 Full interrupt disable Bit (bit 4)
0 : Ena bled
1 : Disabled
Reser ved (Read/Write “0”)
Reser ved (Read/Write “0”)
Data Bus Buffer Function Selection Bit (bit 7)
0 : Single data bus buffer - P7 2 is used as BPIO
1 : Double data bus buffer - P7 2 is used as S 1 input
Fig. 1.80. Data Bus Buffer Control Register 1 (DBBC1)
67
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Each channel of the DMAC is made up of the following:
1.23 DIRECT MEMORY ACCESS CONTROLLER
•
•
•
•
16-bit source and destination registers
A 16-bit transfer count register
Two mode registers
Status flags contained in a status register shared by
the two channels
• Control and timing logic
This device contains a two-channel Direct Memory
Access Controller (DMAC). Each channel performs
fast data transfers between any two locations in the
memory map initiated by specific peripheral events or
software triggers.
The main features of the DMAC are as follows:
The 16-bit source and destination registers allow accesses to any two locations in the 64K byte memory
area. The 16-bit transfer count register decrements by
one for each transfer performed and causes an interrupt
and flag to be set when it underflows. The mode registers control the configuration and operation of the DMAC
channel associated with the registers. A block diagram
of the DMAC is shown in Figure 1.81.
• Two independent channels
• Single-byte and burst transfer modes
• 16-bit source and destination address registers
(for a 64K byte address space)
• 16-bit transfer count registers
(for up to 64K bytes transferred before underflow)
• Source/Destination register automatic
increment/decrement and no-change options
• Source/Destination/Transfer count register reload on
write or after transfer count register underflow options
• Transfer requests from USB (9), MBI (4), external
interrupts (4), UART1 (2), UART2 (2), SIO (1),
TimerX (1), TimerY (1), Timer1 (1), and
software triggers
• Closely coupled with USB and MBI for efficient data
transfers
• Interrupt generated for each channel when their
respective transfer count register underflows
• Fixed channel priority (channel 0 > channel 1)
• Two cycles of F required per byte transferred
The SFR addresses for the two mode, source, destination, and transfer count registers of a channel are the
same for each channel. The accessible channel registers are is determined by the value of the DMAC
Channel Index Bit (DCI) (bit 7 of the DMAC Index and
Status Register (DMAIS). When this bit is a “0”, channel
0 registers are accessible, and when this bit is a “1”,
channel 1 registers are accessible.
The configuration of DMAIS and the mode registers are
shown in Figures 1.82, 1.83, 1.84, and 1.85.
Sample timing diagrams are shown in Figures 1.86,
1.87, and 1.88, for a single-byte transfer initiated by a
hardware source, a single-byte transfer initiated by the
software trigger, and a burst transfer initiated by a hardware source, respectively.
Interrupts: UART1 Rx & Tx, SIO, ExtInt0,
TimerY, CNTR1
Signals: OBE0, IBF0(data), EP1, EP2,
EP3 OUT_PKT_RDY or
IN_PKT_RDY,
EP1 OUT_FIFO_NOT_EMPTY
INT Detect, I-flag
Address Bus
Ch 0 Timing Generator
Ch 0 Source Reg
(D0TMS)
(D0CEN; D0CRR;
D0UMIE; D0SWT;
D0HRS3,2,1,0)
(DTSC)
(D0SRCE,
D0SRID,
D0RLD)
Ch 0 Destination Reg
(D0DRCE.
D0DRID,
(DRLDD) D0RLD)
Ch 0 Count Reg
(DRLDD)
Int
Gen
DMAC Ch 0
Interrupt
(D0DAUE)
(D0UF)
Mode Reg 1
Interrupts: UART2 Rx & Tx, ExtInt1,
Timer1, TimerX, CNTR0
Signals: OBE1, IBF1(data), EP1, EP2,
EP4 OUT_PKT_RDY or
IN_PKT_RDY,
EP OUT_FIFO_NOT_EMPTY
(D0UF,
D0SFI)
Temp Reg
Data Bus
Fig. 1.81. DMAC Block Diagram
68
Ch 0 Source Latch
Mode Reg 2
15
DMAC Channel 0
INT Detect, I-flag
(D1UF, D1SFI)
Index &
Status Reg
(D0DWC)
DMAC Channel 1
(D0DWC)
(D0DWC)
Ch 0 Destination Latch
0 15
Ch 0 Count Latch
0 15
0
Data Bus
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
MSB
7
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DCI
Re s e r ved
DRLDD
DTSC
DISFI
DIUF
DOSFI
DOUF
L S B Address: 003F 16
Access: R/W
0
Reset: 00 16
D0UF
D0SFI
D1UF
D1SFI
DTSC
DRLDD
Bit 6
DCI
DMAC Channel 0 Count Register Underflow Flag (bit 0)
0 : Channel 0 transfer count register underflow has not occurred
1 : Channel 0 transfer count register underflow has occured
DMAC Channel 0 Suspend (dur to interrupt service request) Flag (bit 1)
0 : Channel 0 transfer has not been suspended
1 : Channel 0 transfer has been suspended
DMAC Channel 1 Count Register Underflow Flag (bit 2)
0 : Channel 1 transfer count register underflow has not occurred
1 : Channel 1 transfer count register underflow has occurred
DMAC Channel 1 Suspend (due to interrupt service request ) Flag (bit 3)
0 : Channel 1 transfer has not been suspended
1 ; Channel 1 transfer has been suspended
DMAC Transfer Suspend Control Bit (bit 4)
0 : Only burst transfers are suspended during interrupt servicing
1 : Both burst and single-byte transfers are suspended during
interrupt servicing
DMAC Register Reload Disable Bit (bit 5)
0 : Reload of source and destination registers of both channels
enabled
1 : Reload of source and destination registers of both channels
disabled
Reserved (Read/Write “0”)
Channel Index Bit (bit 7)
0 : Channel 0 mode,source, destination, and transfer count registers
accessible
1 : Channel 1 mode, source, destination, and transfer count registers
accessible
Fig. 1.82. DMAC Index and Status Mode Register (DMAIS)
MSB
DxTMS
DxRLD
DxDAUE
DxDWC
DxDRCE
DxDRID
DxSRCE
DxSRID
LSB Address: 004016
Access: R/W
DxSRID
DxSRCE
DxDRID
DxDRCE
DxDWC
DxDAUE
DxRLD
DxTMS
DMAC
0:
1:
DMAC
0:
1:
DMAC
0:
1:
DMAC
0:
1:
DMAC
0:
1:
DMAC
0:
1:
DMAC
0:
1:
Channel x Source Register Increment/Decrement Select Bit (bit 0)
Increment after transfer
Decrement after transfer
Channel x Source Register Increment/Decrement Enable Bit (bit 1)
Increment/Decrement disabled (No change after transfer)
Increment/Decrement enabled
Channel x Destination Resgister Increment/Decrement Select Bit (bit 2)
Increment after transfer
Decrement after transfer
Channel x Destination Register Increment/Decrement Enable Bit (bit 3)
Increment/Decrement disabled (No change after transfer)
Increment/Decrement enabled
Channel x Data Write Control Bit (bit 4)
Write data in reload latches and registers
Write data in reload latches only
Channel x Disable After Count Register Underflow Enable Bit (bit 5)
Channel x not disabled after count register underflow
Channel x disabled after count register underflow
Channel x Register Reload Bit (bit 6)
No action (Bit is always read as “0”)
Setting to “1” causes the source, destination, and transfer count
registers of channel x to be reloaded
DMAC Channel x Transfer Mode Selection Bit (bit 7)
0: Single-byte transfer mode
1: Burst transfer mode
Fig. 1.83. DMAC Channel x Mode Register 1 (DMAxM1)
69
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
MSB
D0CEN
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
D0CRR
D0UMIE
D0SWT
D0HRS3
D0HRS2
D0HRS1
D0HRS0
LSB Address: 004116
Access: R/W
D0HRS3,2,1,0 DMAC Channel 0 Hardware Transfer Request Source Bits (bits 3,2,1,0)
0000: Disable
0001: UART1 receive interrupt
0010: UART1 transmit interrupt
0011: TimerY interrupt
0100: External Interrupt 0
0101: USB EndPoint 1 IN_PKT_RDY signal (falling edge active)
0110: USB EndPoint 2 IN_PKT_RDY signal (falling edge active)
0111: USB EndPoint 3 IN_PKT_RDY signal (falling edge active)
1000: USB EndPoint 1 OUT_PKT_RDY signal (rising edge active)
1001: USB EndPoint 1 OUT_FIFO_NOT_EMPTY signal (rising edge active)
1010: USB EndPoint 2 OUT_PKT_RDY signal (rising edge active)
1011: USB EndPoint 3 OUT_PKT_RDY signal (rising edge active)
1100: MBI OBE0 signal (rising edge active)
1101: MBI IBF0 (data) signal (rising edge active)
1110: SIO receive/transmit interrupt
1111: CNTR1 interrupt
DOSWT
DMAC Channel 0 Software Transfer Trigger (bit 4)
0: No action (Bit is always read as “0”)
1: Writing “1” requests a channel 0 transfer
D0UMIE
DMAC Channel 0 USB and MBI Enable Bit (bit 5)
0: Disabled
1: Enabled
D0CRR
DMAC Channel 0 Transfer Initiation Source Capture Register Reset (bit 6)
0: No action (Bit is always read as “0”)
1: Setting to “1” causes reset of the channel 0 capture register
D0CEN
DMAC Channel 0 Enable Bit (bit 7)
0: Channel 0 disabled
1: Channel 0 enabled
Fig. 1.84. DMAC Channel 0 Mode Register 2 (DMA0M2)
MSB
7
D1CEN
D1CRR
D1UMIE
D1SWT
D1HRS3
D1HRS2
D1HRS1
D1HRS0
L S B Address: 0041 16
Access: R/W
0
Reset: 00 16
D1HRS3,2,1,0 DMAC Channel 1 Hardware Transfer Request Source Bits (bits 3,2,1,0)
0000: Disable
0001: UART2 receive interrupt
0010: UART2 transmit interrupt
0011: TimerX interrupt
0100: External Interrupt 1
0101: USB EndPoint 1 IN_PKT_RDY signal (falling edge active)
0110: USB EndPoint 2 IN_PKT_RDY signal (falling edge active)
0111: USB EndPoint 4 IN_PKT_RDY signal (falling edge active)
1000: USB EndPoint 1 OUT_PKT_RDY signal (rising edge active)
1001: USB EndPoint 1 OUT_FIFO_NOT_EMPTY signal (rising edge active)
1010: USB EndPoint 2 OUT_PKT_RDY signal (rising edge active)
1011: USB EndPoint 4 OUT_PKT_RDY signal (rising edge active)
1100: MBI OBE1 signal (rising edge active)
1101: MBI IBF1 (data) signal (rising edge active)
1110: Timer interrupt
1111: CNTR0 interrupt
D1SWT
DMAC Channel 1 Software Transfer Trigger (bit 4)
0: No action (Bit is always read as “0”)
1: Writing “1” requests a channel 0 transfer
D1UMIE
DMAC Channel 1 USB and MBI Enable Bit (bit 5)
0: Disabled
1: Enabled
D1CRR
DMAC Channel 1 Transfer Initiation Source Capture Register Reset (bit 6)
0: No action (Bit is always read as “0”)
1: Setting to “1” causes reset of the channel 1 capture register
D1CEN
DMAC Channel 1 Enable Bit (bit 7)
0: Channel1 disabled
1: Channel 1 enabled
Fig. 1.85. DMAC Channel 1 Mode Register 2 (DMA1M2)
70
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Φout
SYNCout
RD
WR
STA $zz
(first cycle)
LDA$zz
Address
PC
Data
PC + 1
ADL1, 00
A5
PC + 2
ADL1
Data
DMAC Transfer
DMA Dest.
Address
DMA Source
Address
85
STA $zz (last 2 cycles)
DMA Data
ADL2, 00
PC + 3
DMA Data
PC + 4
Data
ADL2
Next
Inst.
OpCode3
DMAC Transfer
Signal (Port33)
Transfer Request
Source (active low)
Transfe Request
Source Sampling
Transfer Request
Source Sample
Latch Reset
Fig. 1.86. DMAC Transfer-Hardware Source Initiated
Φout
SYNCout
RD
WR
Address
LDM #$90, $41
PC
Data
PC + 1
Single cycle Single cycle Single cycl
Inst.
Inst.
Inst.
PC + 2
3C
18
42,00
41
OpCode2
90
DMA Source
Address
PC + 5
PC + 4
PC + 3
OpCode3
Next
Inst.
DMAC Transfer
OpCode4
DMA Dest.
Address
DMA Data
PC + 6
OpCode5
DMA Data
DMAC Transfer
Signal (Port33)
Transfer Request
Source (active low)
Transfer Request
Source Sampling
Transfer Request
Source Sample
Latch Reset
Fig. 1.87. DMAC Transfer-Software Trigger Initiated
Φout
SYNCout
RD
WR
STA $zz
(first cycle)
LDA $zz
Address
Data
PC
PC + 1
A5
ADL1, 00
ADL1
DMA Source
Address1
PC + 2
Data
DMAC Transfer
85
DMA Dest.
Address1
DMA Data1
STA $zz (second cycle)
DMA Source
Address2
DMA Data1
DMA Dest.
Address2
DMA Data2
PC + 3
DMA Data2
ADL2
DMAC Transfer
Signal (Port33)
Transfer Request
Source (active low)
Transfe Request
Source Sampling
Transfer Request
Source Sample
Latch Reset
Fig. 1.88. DMAC Transfer-Burst Transfer Initiated
71
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.24 OSCILLATOR CIRCUIT
An on-chip oscillator provides the system and peripheral clocks as well as the USB clock necessary for
operation. This oscillator circuit is comprised of amplifiers that provide the gain necessary for oscillation,
oscillation control logic, a frequency synthesizer, and
buffering of the clock signals.
A Clock Control register (CCR) is shown in Figure 1.89
and a flow diagram for the oscillator circuit is shown in
Figure 1.90.
The following external clock inputs are supported:
• A quartz crystal oscillator of up to 24 MHz, connected
to the Xin and Xout pins.
• A ceramic resonator or quartz crystal oscillator of
32.768 kHz, connected to the XCin and XCout pins.
• An external clock signal of up to 5.00 MHz, connected
to the XCin pin.
The frequency synthesizer can be used to generate a
48MHz clock signal (fUSB) needed by the USB block
and clock fSYN, which can be chosen as the source
for the system and peripheral clocks. Both fUSB and
MSB
7
CCR7
CCR6
CCR5
Re s e r v ed
Re s e r v ed
Re s e r v ed
Re s e r v ed
Re s e r v ed
fSYN are phase-locked frequency multiples of the frequency synthesizer input. The inputs to the frequency
synthesizer can be either Xin or XCin.
The two-phase non-overlapping system clock (CPU
and peripherals) is derived from the source to the
clock circuit and is half the frequency of the source.
(i.e. Source = 24 MHz, system clock = 12 MHz) Any
one of four clock signals can be chosen as the source
for the system and peripheral clocks; f(Xin)/2, f(Xin),
f(XCin), or fSYN. The selection is based on the values of
bits CPMA6, CPMA7 and CCR7. The default source
after reset is fXin/2.
The default source for the system and peripheral
clocks is f(Xin)/2. If f(Xin)= 24MHz, then the CPU will
be running at F = 6MHz (low frequency mode. For the
CPU to run in high frequency mode, i.e., source of
clock = f(Xin), write a “1” to bit 7 of the clock control
register. (If an external clock signal is input to Xin or
XCin, the inverting amplifiers can be disabled by
means of the CCR6 and CCR7 bits, respectively, in order to reduce power consumption).
LSB
0
Bits 0-4
Reserved (Read/Write “0”)
CCR5:
XCout Oscillation Drive Diable Bit (bit 5).
0: XCout oscillation drive is enabled (when XCin oscillation is enabled).
1: XCout oscillation drive is disabled.
Xout Oscillation Drive Disable Bit (bit 6).
0: XCout oscillation drive is enabled (when XCin oscillation is enabled).
1: XCout oscillation drive is disabled.
Xin Divider Select Bit (bit 7).
0: f(Xin)/2 is used for the system clock source when CMPA 7:6=00.
1: f(Xin) is used for the system clock source when CMPA 7:6=10.
CCR6:
CCR7:
Fig. 1.89. Clock Control Register (CCR)
72
Address: 001F 16
Access: R/W
Reset: 00 16
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET
Stop
Note 1
Wait
1
Stop
Note 1
Wait
Note 1
Wait
0
0
Wait
CPMA6
1
0
Xin clock on
XCin clock stopped
PLL clock on
Φ=f(PLL)/2
CPMA=4C, FSC=41
Wait
FSC0
1
0
Xin clock on
XCin clock on
PLL clock on Note 3
Φ=f(Xin)/4 Note 2
CPMA=1C, FSC=41
CPMA6
1
Xin clock on
XCin clock on
PLL clock on
Φ=f(PLL)/2
CPMA=5C, FSC=41
Xin clock on
XCin clock on
PLL clock on Note 3
Φ=f(XCin)/2
CPMA=9C, FSC=41
CPMA6
1
Xin clock stopped
XCin clock on
PLL clock on Note 3
Φ=f(XCin)/2
CPMA7=BC, FSC=49
CPMA6
1
0
Wait
Xin clock on
XCin clock on
PLL clock on
Φ=f(PLL)/2
CPMA=DC, FSC=41
Wait
Xin clock stopped
XCin clock on
PLL clock on
Φ=f(PLL)/2
CPMA7=FC, FSC=49
Wait
CPMA7
FSC0
1
0
0
0
CPMA5
Note 1
Xin clock on
XCin clock stopped
PLL clock on Note 3
Φ=f(Xin)/4 Note 2
CPMA=0C FSC=41
CPMA4
Xin clock on
XCin clock on
PLL clock stopped
Φ=f(XCin)/2
CPMA=9C, FSC=60
1
Stop
0
Xin clock on
XCin clock on
PLL clock stopped
Φ=f(Xin)/4 Note 2
CPMA=1C, FSC=60
1
Stop
FSC0
1
Xin clock on
XCin clock stopped
PLL clock stopped
Φ=f(Xin)/4 Note 2
CPMA=0C, FSC=60
Xin clock stopped
XCin clock on
PLL clock stopped
Φ=f(XCin)/2
CPMA=BC, FSC=68
Note 4
FSC0
1
0
0
Note 1:
Stop mode stops the oscillators that are also the inputs to the frequency synthesizer. However, the
frequency synthesizer is not disabled and so its output is unstable. So, always set the system clock
to an external oscillator and disable the frequency synthesizer before entering stop mode.
Note 2:
. = f(Xin)/4 can be interchanged with. = f(Xin)/2 by setting CCR7 to “1”. The same flow chart applies to both
cases.
Note 3:
The input to the frequency synthesizer is independent of the system clock. It can be either Xin or XCin depend
ing on bit 3 of FSC. In the above flow, the input has been chosen to be the same as the system clock only for
simplicity. The oscillator selected to be the input to the frequency synthesizer must be enable before the
frequency synthesizer is enabled.
Note 4:
The input clock for the frequency synthesizer must be set to XCin by setting FIN (bit 3 of FSC) to a "1" before
Xin oscillation can be disabled.
Note:
CPMA values shown assume single-chip mode with stack in one page.
Fig. 1.90. Clock Flow Diagram
73
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.24.1 Frequency Synthesizer Circuit
The Frequency Synthesizer Circuit generates a 48MHz
clock needed by the USB block and a clock fSYN that
are both a multiple of the external input reference
clock fIN. A block diagram of the circuit is shown in
Figure 1.91.
The frequency synthesizer consists of a prescaler, frequency multiplier macro, a frequency divider macro,
and four registers, namely FSM1, FSM2, FSC and
FSD. Two multiply registers (FSM1, FSM2) control the
frequency multiply amount. Clock fIN is prescaled using FSM2 to generate fPIN. fPIN is multiplied using
FSM1 to generate an fVCO clock which is then divided
using FSD to produce the clock fSYN. The fVCO clock
is optimized for 48 MHz operation and is buffered and
sent out of the frequency synthesizer block as signal
fUSB. This signal is used by the USB block. The clock
block diagram is shown in Figure 1.92.
Clock fPIN is a divided down version of clock fIN, which
can be either f(Xin) or f(XCin). The default clock after reset is fXin. The relationship between fPIN and the clock
input to the prescaler (fIN) is as follows:
•fPIN = fIN/2(n+1) where n is a decimal number between
0 and 254. (See Figure 1.95).
Setting FSM2 to 255 disables the prescaler and fPIN =
f IN.
fIN
Prescaler
The relationship between fPIN, fVCO, fSYN, and fUSB is
as follows:
•fVCO = fPIN x 2(n+1) where n is the decimal equivalent
of the value loaded in FSM1. (See Figure 1.94).
n must be chosen such that fVCO equals 48 MHz.
•fSYN = fVCO / 2(m+1) where m is the decimal equivalent of the value loaded in FSD. (See Figure 1.96).
Setting m=255 disables the divider and disables fSYN.
•fUSB is a buffered version of fVCO, i.e., FSD has no effect on fUSB.
Setting USB control register bit 5 to “0” disables fUSB
by tri-stating the buffer.
The FSC0 bit in the FSC Register (FSC) enables the
frequency synthesizer block. When disabled (FSC0 =
“0”), fVCO is held at either a high or low state. When
the frequency synthesizer control bit is active (FSC0
= “1”), a lock status (LS = “1”) indicates that fSYN and
fVCO are the correct frequency. The LS and FSCO
control bits in the FSC register are shown in Figure
1.93.
When using the frequency synthesizer, a low-pass filter must be connected to the LPF pin.
Once the frequency synthesizer is enabled, a delay of
2-5ms is recommended before the output of the frequency synthesizer is used. This is done to allow the
output to stabilize. It is also recommended that none
of the registers be modified once the frequency synthesizer is enabled as it will cause the output to be
temporarily (2-5ms) unstable.
Frequency
Multiplier
fPIN
fVCO
Frequency
Divider
fSYN
8 Bit
8 Bit
fUSB
FSM2
FSM1
LS
Bit
006E
006D
FSC
006C
FSD
006F
Data Bus
Fig. 1.91. Frequency Synthesizer Circuit
74
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
P1HATRSTB P2LATRSTB
D Q
D Q
PIN1 T
R
PIN2 T
PIN1 T
R
D Q
D Q
R
P2+ T
R Q
RESETB
PIN1 T
S
R
D Q
PadResetB
D Q
P2+ T
STP
P2LATRSTB
P2 Peripheral
P1 Peripheral
R Q
Oscillator Countdown
Timer 1->2
R Q
STP
STP S
T
P1HATRSTB
D Q
STP
Delay
PIN2
WIT S
S
Φout
CPMA4
P1
PIN1,PIN2
XCOD
XCDOSCSTP
CCR7 o
fXin
LPF
LPF
XOSCSTP
Slow Memory Wait
CPMB0
CPMB1
CPMB2
CPMB3
P1+,P2+
RDY
CPMA7
1/2
fXCin
FIN(FSC3)
XCOSCSTP
fEXT CPMA6
fIN
XDOSCSTP
P2
P1HATRSTB
XCOSCSTP
XCDOSCSTP
Frequency Synthesizer
XCin
FSC0
XCout
fSYN
1/2
2 (Tw Phase)
USB 48 MHz Clock
enable
Xout
Q
R
P2+ T
XDOSCSTP
Xin
S
P1 Out
T
D Q
CPMA5
XOD
P2 Out
P2LATRSTB
R QB
OSCSTP
XOSCSTP
P1 Peripheral
S
R Q
Interrupt Request
I Flag
PadResetB
P2 Peripheral
D Q
LPF
Fig. 1.92. Clock Block Diagram
MSB
7
LS
Re s e r ve d Re s e r ve d Re s e r ved
FIN
Re s e r ved
Re s e r ved
FSE
LSB
0
FSE
Bit 2,1
FIN
Bit 5,4
Bit 6
LS
Address: 006C 16
Access: R/W
Reset: 60 16
Frequency Synthesizer Enable Bit (bit 0)
0: Disabled
1: Enabled
Reserved (Read/Write “0”)
Frequency Synthesiszer Input Selector Bit (bit 3)
0: Xin
1: XCin
Reserved (Read/Write “0”)
Reserved (Read/Write “1”)
Frequency Synthesizer Lock Status Bit (bit 7) (Read only; Write “0”)
0: Unlocked
1: Locked
Fig. 1.93. Frequency Synthesizer Control Register (FSC)
75
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
MSB
7
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Bit 7
Bit 6
Bit 5
Bit 3
Bit 4
Bit 2
FSM1
f PIN
320.00 KHz
2.00 MHz
4.00 MHz
6.00 MHz
12.00 MHz
24.00 MHz
Bit 0
LSB
0
Address: 006D16
Access: R/W
Reset: FF16
Bit 0-7
Frequency synthesizer multiply value, n, that is used to multiply the prescaler
output frequency, f PIN, up to 48.00 MHz
f VCO
n16
n10
Bit 1
74
4A
11
0B
5
05
3
03
1
01
00
0
fVCO = 2 x fPIN x (n+1)
48.00
48.00
48.00
48.00
48.00
48.00
MHz
MHz
MHz
MHz
MHz
MHz
Fig. 1.94. Frequency Synthesizer Multiply Control Register (FSM1)
MSB
7
Bit 7
Bit 6
Bit 5
Bit 2
FSM2
fIN
24.00
24.00
24.00
24.00
24.00
24.00
Bit 3
Bit 4
n10
MHz
MHz
MHz
MHz
MHz
MHz
Bit 1
Bit 0
LSB
0
Bit 0-7
Frequency synthesizer prescaler divide value, n. The input clock, fIN, is
divided by this value to produce the intermediate frequency, fPIN, which is
then multiplied up to 48.00 MHz. A value of 255 (FF16) turns the prescaler
off (no division of f IN).
LSB
0
Address: 006F16
Access: R/W
Reset: FF16
Bit 0-7
Frequency synthesizer divide value, m, by which the 48.00 MHz VCO
frequency is divided to produce the F SYN system clock frequency.
f PIN
n16
255
FF
11
0B
5
05
3
03
1
01
00
0
fPIN = fIN / (2 x (n+1))
Address: 006E16
Access: R/W
Reset: FF16
24.00 MHz
1.00 MHz
2.00 MHz
3.00 MHz
6.00 MHz
12.00 MHz
Fig. 1.95. Frequency Synthesizer Multiply Control Register (FSM2)
MSB
7
Bit 7
Bit 6
Bit 5
f VCO
48.00
48.00
48.00
48.00
48.00
48.00
MHz
MHz
MHz
MHz
MHz
MHz
Bit 3
Bit 4
FSD
m10
m16
0
00
2
02
5
05
127
7F
128
80
FF
255
fSYN = fVCO / (2 x (m+1))
Bit 2
Bit 1
fSYN
24.00 MHz
8.00 MHz
4.00 KHz
187.50 KHz
93.75 KHz
0.00 KHz
Fig. 1.96. Frequency Synthesizer divided Ratio Register (FSD)
76
Bit 0
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.25 LOW POWER MODES
This device has two low-power dissipation modes:
•Stop
•Wait
1.25.1 Stop Mode
Use of the stop mode allows the MCU to be placed in
a state where no internal excitation of the circuitry is
taking place, thus resulting in extremely low power
dissipation. The MCU enters the stop mode when the
STP instruction is executed. The internal state of the
mcu after execution of the STP instruction is as follows:
Oscillation is restarted when a reset or an external interrupt is received. The interrupt control bit of the
interrupt used to release the stop mode must be set
to a "1" and the I flag set to a "0" prior to the execution
of the STP instruction. To allow the oscillation source
time to stabilize, the oscillation source is connected
as the clock source for the wake-up timer (Timer 1
and Timer 2 cascaded). When Timer 2 underflows,
the MCU services the interrupt that caused the return
from the stop state. Afterwards, it services any other
enabled interrupts that occurred, in the order of their
respective priorities, and returns to its state prior to
the execution of the STP instruction. The timing for
the STP instruction is shown in Figure 1.97.
•Timer 1 and Timer 2 are loaded with FF16 and 0116
respectively.
•All T123M mode register bits are reset to their default
value except bit 4.
•The count source for Timer 1 is set to F/8 and the
count source for Timer 2 is set to Timer 1 underflow.
Xin
Φout
INTREQ
STPSIG
CPUOSC
SYNCout
RD
WR
Address
Data
PC
PC + 1
Opcode
Invalid
Timer Countdown
(Oscillator stabilization)
Timer 2 underflow
ote: Return from a STP Instruction is caused by an interrupt, followed by the countdown and underflow of Time 2
Sleep Period
S,CPMA2
(PC + 1)H
Start of Interrupt Service
Routine
Fig. 1.97. STP Cycle Timing Diagram (STP)
77
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.25.2 Wait Mode
Use of the wait mode allows the microcomputer to be
placed in a state where excitation of the CPU is
stopped, but the clocks to the peripherals continue to
oscillate. This mode provides lower power dissipation
during the idle periods and quick wake-up time. The
microcomputer enters the wait mode when the WIT
instruction is executed.
Returning from wait mode is accomplished just as it is
when returning from stop mode, with the exception
that you need not provide time for the oscillator to stabilize, because the oscillation never stopped.
Additionally, any peripheral interrupt can be used to
bring the microcomputer out of the wait mode. The
timing for the WIT instruction is shown in Figure 1.98.
Xin
Φout
INTREQ
STPSIG
SYNCout
RD
WR
Address
Data
PC
Opcode
Note: Return from a WIT instruction is caused by a interrupt.
Fig. 1.98. WIT Cycle Timing Diagram (WIT)
78
PC + 1
Invalid
Sleep Period
S,CPMA2
(PC + 1)
Start of Interrupt Service Routine
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.26 RESET
bilize, a delay is generated by the countdown of Timer
1 and Timer 2 cascaded with FF16 loaded in Timer 1
and 0116 loaded in Timer 2. After the reset sequence
completes, program execution begins at the address
whose high-order byte is the contents of address
FFFA16 and whose low-order byte is the contents of
address FFFB16.
This device is reset if the RESET pin is held low for a
minimum of 2ms while the supply voltage is set between 4.15 and 5.25V. When the RESET pin returns
high, the reset sequence commences (see Figure
1.99). To allow the oscillation source the time to sta-
Φout
Reset
SYNCout
Address
?
?
?
Data
?
?
?
?
?
?
FFFA
?
ADH
FFFB
ADL ADH
ADL
First
Opcode
Timer countdown from 01FF16
Fig. 1.99. Internal Processing Sequence after RESET
79
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
2.1 ABSOLUTE MAXIMUM RATINGS
Table 2.1 Absolute Maximum Ratings
Symbol
Parameter
Conditions
Unit
-0.3 to 6.5
V
VCC
Power supply
AVCC
Analog power supply
-0.3 to V CC + 0.3
V
Input voltage P0, P1, P2, P3, P4, P5, P6, P7, P8
-0.3 to V CC + 0.3
V
-0.3 to V CC + 0.3
V
-0.3 to 13
V
-0.5 to 3.8
V
-0.3 to V CC + 0.3
V
-0.5 to 3.8
V
750
mW
VI
VI
Input voltage RESET, Xin, XCin
VI
Input voltage CNVSS
VI
Input voltage USB D+, D-
VO
Output voltage P0, P1, P2, P3, P4, P5, P6, P7, P8, Xout,
XCout, LPF
VO
Output voltage USB D+, D-
PD
Power dissipation
(Note)
Values are with respect to
VSS. Output transistors are
in off state.
Ta = 25°C
TOPR
Operating temperature
-20 to +85
°C
TSTG
Storage temperature
-40 to +125
°C
Note: Maximum power dissipation is based on heat dissipation characteristics not chip power consumption.
80
Limits
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
2.2 RECOMMENDED OPERATING CONDITIONS
Table 2.2. Recommended Operating Conditions (Vcc = 4.15 to 5.25V, Vss = 0V, Ta = -20 to 85°C unless otherwise noted)
Symbol
Parameter
Limits
Unit
Min.
Typ.
Max.
5
5.25
V
5
VCC
V
VCC
Supply voltage
4.15
AVCC
Analog supply voltage
4.15
VSS
Supply voltage
0
AVSS
Analog supply voltage
0
VIH
H input voltage
RESET, Xin, XCin, CNVSS
0.8VCC
VCC
V
VIH
H input voltage
P0, P1, P2, P3, P4, P5, P6, P7,
P8
0.8VCC
VCC
V
VIH
H input voltage
P2
0.5VCC
VCC
V
VIH
H input voltage
P57-P54, P6, P72
2.0
VCC
V
VIH
H input voltage
USB D+, D-
VIL
L input voltage
VIL
L input voltage
VIL
L input voltage
VIL
L input voltage
VIL
L input voltage
(When PTC6 = “0”)
(When MBI inputs and PTC7 = “1”)
V
V
2.0
3.8
V
RESET, Xin, XCin, CNVSS
0
0.2VCC
V
P0, P1, P2, P3, P4, P5, P6, P7,
P8
0
0.2VCC
V
0
0.16VCC
V
0
0.8
V
0
P2
(When PTC6 = “0”)
P57-P54, P6, P72
(When MBI inputs and PTC7 = “1”)
USB D+, D-
0.8
V
IOL (peak) L peak output current Note 1
P0, P1, P2, P3, P4, P5, P6, P7,
P8
10
mA
IOL (avg) L average output current Note 2
P0, P1, P2, P3, P4, P5, P6, P7,
P8
5
mA
IOH (peak) H peak output current Note 1
P0, P1, P2, P3, P4, P5, P6, P7,
P8
-10
mA
IOH (avg) H average output current Note 2
P0, P1, P2, P3, P4, P5, P6, P7,
P8
-5
mA
ΣΙOL
(peak)
L total peak output current Note 3
P0, P1, P2, P3, P4, P5, P6, P7,
P8
80
mA
ΣIOL (avg)
L total average output
current Note 4
P0, P1, P2, P3, P4, P5, P6, P7,
P8
40
mA
ΣIOH
(peak)
H total peak output current Note 3
P0, P1, P2, P3, P4, P5, P6, P7,
P8
-80
mA
ΣIOL (avg)
H total average output
current Note 4
P0, P1, P2, P3, P4, P5, P6, P7,
P8
-40
mA
MHz
f(CNTR0) TimerX - input frequency
Note 5
5
f(CNTR1) TimerY - input frequency Note 5
5
MHz
f(Xin)
Clock frequency
Note 5,7
24
MHz
f(XCin)
Clock frequency
Note 5,6
50/5.0
KHz/MHz
Note
Note
Note
Note
Note
Note
1.
2.
3.
4.
5.
6.
Note 7.
4
32.768
The peak output current is the peak current flowing through any pin of the listed ports.
The average output current is an average current value measured over 100 ms.
The total peak output current is the peak current flowing throught all pins of the listed ports.
The total average output current is an average current value measured over 100 ms.
The oscillation frequency has a 50% cycle.
The maximum oscillation frequency of 50 KHz is for a crystal oscillator connected between XCin and XCout.
An external signal having a maximum frequency of 5 MHz can be input to XCin.
When using Frequency Synthesizer Circuit, minimum limit is 4 MHz. And when using USB, put internal clock
f(.)to more than 6 MHz.
81
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
2.3 ELECTRICAL CHARACTERISTICS
Table 2.3. Electrical Characteristics (Vcc = 4.15 to 5.25V, Vss = 0V, Ta = -20 to 85°C unless otherwise noted)
Symbol
Parameters
Limits
Test Conditions
Min Typ. Max
VOH
H output
voltage
P0, P1, P2, P3, P4, P5, P6, P7, P8
Ioh = -10mA
VOH
H output
voltage
USB D+, D-
USB D+, USB D- pins pull down to Vss by 15
KΩ ± 5% and USB D+ pin pull up to ExtCap
pin by 1.5 KΩ ± 5%
VOL
L output
voltage
P0, P1, P2, P3, P4, P5, P6, P7, P8
VOL
L output
voltage
USB D+, D-
VT +
~VT-
Hysteresis
VCC 2.0
H input current
V
3.6
V
Iol = 10mA
2.0
V
USB D+, USB D- pins pull down to Vss by 15
KΩ ± 5% and USB D+ pin pull up to ExtCap
pin by 1.5 KΩ ± 5%
0.3
V
2.8
CNTR0, CNTR1, INT0, INT1, RDY,
HOLD, P2
0.5
V
URXD1, URXD2 (SCLK), CTS2
(SRXD), SRDY, CTS1
0.5
V
0.5
RESET
P0, P1, P2, P3, P4, P5, P6, P7, P8
IIH
RESET, USB D+, USB D-, CNVSS
Xin
Vi = V CC
V
P0, P1, P3, P4, P5, P6, P7, P8
P2
VRAM
Vi = V SS
-5
µA
Vi = V SS (Pullups off)
-5
µA
-140
µA
-5
µA
-30
-75
-20
-20
µA
-5
µA
5.25
V
70
90
mA
7.5
10
mA
6
10
µA
Transceiver voltage converter on with USBC3
= “1” (low current mode)
200
250
µA
Ta = 25°C, transceiver voltage converter off
0.1
-9
Clocks stopped
2.0
f(Xin) = 24MHz, Φ = 12MHz,
USB operating, frequency synthesizer on,
Normal Mode
µA
µA
XCin
RAM
retention
voltage
5
µA
Vi = V SS
Xin
µA
5
VCC = 5V, Vi = V SS (Pullups on)
L input current RESET, USB D+, USB DCNVSS
5
20
9
XCin
IIL
Unit
Note 1
f(Xin) = 24MHz, Φ = 12MHz,
USB suspended, frequency synthesizer on,
USB clock disabled Note 2
Supply current
(Output
transistors are Wait Mode
isolated)
ICC
f(XCin) = 32KHz, Φ = 16KHz,
USB disabled, frequency synthesizer off,
transceiver voltage converter off Note 3
Stop Mode
Note 1:
Icc test conditions
Ta = 85°C, transceiver voltage converter off
Note 2:
Icc test conditions
1
µA
10
µA
Note 3:
Icc test conditions
Single chip mode (run state)
Single chip mode (wait state)
Single chip mode (wait state)
Square wave clock input on Xin (Xout drive disabled)
Square wave clock input on Xin (Xout drive disabled)
Xin/Xout oscillation disabled
I/O pins isolated
I/O pins isolated
Square wave clock input on XCin (XCout drive disabled)
Frequency synthesizer running
Frequency synthesizer running
I/O pins isolated
USB operating with transceiver voltage converter enabled
USB in suspend state with USB clock disabled
Frequency synthesizer disabled
CPU and DMAC running
Transceiver voltage converter enabled
USB and USB clock disabled
Timers and SCSG running
Timers and SCSG running
Transceiver voltage converter disabled
BothUARTs transmitting
CPU and DMAC not running
Timers and SCSG running
MBI and SIO disabled
Both UARTs, SIO, and MBI disabled
CPU and DMAC not running
Both UARTs, SIO, and MBI disabled
82
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
2.4 TIMING REQUIREMENTS AND SWITCHING CHARACTERISCTICS
Table 2.4 Timing Requirements and Switching Characterisctics
(Vcc = 4.15 to 5.25V, Vss = 0V, Ta = -20 to 85°C unless otherwise noted)
Symbol
Parameter
Limits
Min
Unit
Typ. Max
Inputs
tw(RESET)
RESET input “Low” pulse width
2
_s
tc(Xin)
Clock input cycle time
41.66
ns
twh(Xin)
Clock input “High” pulse width
0.4*tc(Xin)
ns
twl(Xin)
Clock input “Low” pulse width
0.4*tc(Xin)
ns
tc(XCin)
Clock input cycle time
twh(XCin)
Clock input “High” pulse width
twl(XCin)
Clock input “Low” pulse width
200
ns
0.4*tc(XCin)
0.4*tc(XCin)
ns
INT0, INT1 input cycle time
200
ns
twh(INT)
INT0, INT1 input “High” pulse width
90
ns
twl(INT)
INT0, INT1 input “Low” pulse width
90
ns
tc(CNTRI)
CNTR0, CNTR1 input cycle time
200
ns
ns
Interrupts
tc(INT)
twh(CNTRI)
CNTR0, CNTR1 input “High” pulse width
80
ns
twl(CNTRI)
CNTR0, CNTR1 input “Low” pulse width
80
ns
Timers
td(Φ-TOUT)
TIMER TOUT delay time (Note)
15
ns
td(Φ-CNTR0)
TIMER CNTR0 delay time (pulse output mode) (Note)
15
ns
tc(CNTRE0)
TIMER CNTR0 input cycle time (event counter mode)
200
ns
twh(CNTRE0)
TIMER CNTR0 input “High” pulse width (event counter mode)
0.4*tc(CNTRE0)
ns
0.4*tc(CNTRE0)
twl(CNTRE0)
TIMER CNTR0 input “Low” pulse width (event counter mode)
td(Φ-CNTR1)
TIMER CNTR1 delay time (pulse output mode) (Note)
tc(CNTRE1)
TIMER CNTR1 input cycle time (event counter mode)
twh(CNTRE1)
twl(CNTRE1)
ns
15
ns
200
ns
TIMER CNTR1 input “High” pulse width (event counter mode)
0.4*tc(CNTRE1)
ns
TIMER CNTR1 input “Low” pulse width (event counter mode)
0.4*tc(CNTRE1)
ns
SIO
tc(SCLKE)
SIO external clock input cycle time
400
ns
twh(SCLKE)
SIO external clock input “High” pulse width
190
ns
twl(SCLKE)
SIO external clock input “Low” pulse width
180
ns
tsu(SRXD-SCLKE)
SIO receive setup time (external clock)
15
ns
th(SCLKE-SRXD)
SIO receive hold time (external clock)
10
ns
td(SCLKE-STXD)
_____
tv(SCLKE-SRDY)
SIO transmit delay time (external clock)
_____
SIO SRDY valid time (external clock)
tc(SCLKI)
SIO internal clock output cycle time
twh(SCLKI)
twl(SCLKI)
tsu(SRXD-SCLKI)
25
ns
26
ns
166.66
ns
SIO internal clock output “High” pulse width
0.5*tc(SCLKI)-5
ns
SIO internal clock output “Low” pulse width
0.5*tc(SCLKI)-5
ns
SIO receive setup time (internal clock)
20
ns
th(SCLKI-SRXD)
SIO receive hold time (internal clock)
5
td(SCLKI-STXD)
SIO transmit delay time (internal clock)
ns
5
ns
83
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 2.4 Timing Requirements and Switching Characterisctics (continued)
(Vcc = 4.15 to 5.25V, Vss = 0V, Ta = -20 to 85°C unless otherwise noted)
Parameter
Symbol
__
_
MBI (Separate
R
and
W
Type
Mode)
_
Limits
Min
Typ.
Unit
Max
th(W-S)
_
_ _
S
_ 0, S
_ 1 setup time for read
S
_ 0, S
_ 1 setup time for write
S0, S1 hold time for read
_ _
S0, S1 hold time for write
0
ns
tsu(A-R)
A0 setup time for read
10
ns
tsu(A-W)
_
A0 setup time for write
10
ns
th(R-A)
A0 hold time for read
0
ns
th(W-A)
_
A0 hold time for write
0
ns
tw(R)
Read pulse width
50
ns
tw(W)
Write pulse width
50
ns
tsu(D-W)
Data input setup time before write
25
ns
th(W-D)
Data input hold time after write
0
ns
tsu(S-R)
tsu(S-W)
_
th(R-S)
0
ns
0
ns
0
ns
_
ta(R-D)
_
tv(R-D)
_
Data output enable time after read
tv(R-OBF)
OBF output transmission time after read
40
ns
td(W-IBF)
__
IBF output transmission time after write
40
ns
MBI (R/W Type Mode)
tsu(A-E)
_ _
S
_ 0, S
_ 1 setup time
S0, S1 hold time
A0 setup time
th(E-A)
A0 hold time
tsu(R/W-E)
th(E-R/W)
tw(E)
Enable pulse width
50
ns
tw(E-E)
Enable pulse interval
50
ns
tsu(D-E)
Data input setup time before write
25
ns
th(E-D)
Data input hold time after write
0
ns
tsu(S-E)
th(E-S)
Data output disable time after read
40
10
ns
ns
0
ns
0
ns
10
ns
0
ns
R/W setup time
10
ns
R/W hold time
10
ns
ta(E-D)
Data output enable time after read
tv(E-D)
Data output disable time after read
tv(E-OBF)
OBF output transmission time after E inactive
40
ns
td(E-IBF)
IBF output transmission time after E inactive
40
ns
84
40
10
ns
ns
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
_______
tw(RESET)
Inputs
0.8Vcc
RESET
0.2Vcc
tc(Xin)
twh(Xin)
Xin
twl(Xin)
0.8Vcc
0.2Vcc
tc(XCin)
twh(XCin)
XCin
twl(XCin)
0.8Vcc
0.2Vcc
Interrupts
tc(INT), tc(CNTRI)
twh(INT),twh(CNTRI)
_____
_____
INT0, INT1,
CNTR0, CNTR1
Timers
twl(INT),twl(CNTRI)
Φ
0.8Vcc
0.2Vcc
0.5Vcc
td(Φ-TOUT)
0.5Vcc
TOUT
td(Φ-CNTR0,1)
CNTR0, CNTR1
0.5Vcc
tc(CNTRE0,1)
twh(CNTRE0,1)
CNTR0, CNTR1
twl(CNTRE0,1)
0.8Vcc
0.2Vcc
Fig. 2.1. Reset, Clock, Interrupts and Timers Timing Diagram
85
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
__
tsu(A-R)
Read
__
th(R-A)
0.8Vcc (2.0V)
0.2Vcc (0.8V)
A0
th(R-S)
tsu(S-R)
0.2Vcc (0.8V)
S0, S1
tw(R)
0.8Vcc (2.0V)
0.2Vcc (0.8V)
R
0.8Vcc
0.2Vcc
0.8Vcc
0.2Vcc
DQ0-DQ7
__
tv(R-D)
ta(R-D)
tv(R-OBF)
0.2Vcc
OBF
th(W-A)
tsu(A-W)
Write
0.8Vcc (2.0V)
0.2Vcc (0.8V)
A0
th(W-S)
tsu(S-W)
0.2Vcc (0.8V)
S0, S1
tw(W)
0.8Vcc (2.0V)
0.2Vcc (0.8V)
W
tsu(D-W)
th(W-D)
0.8Vcc (2.0V)
0.2Vcc (0.8V)
DQ0-DQ7
td(W-IBF)
0.2Vcc
IBF
Note: TTL input levels in parenthesis (TTL levels selected when PTC7 = “1”)
Fig. 2.2. MBI Timing Diagram (Separate R and W Type Mode)
tw(E)
tw(E-E)
E
0.8Vcc (2.0V)
0.2Vcc (0.8V)
0.2Vcc (0.8V)
tsu(A-E)
A0
R/W
th(E-A)
0.8Vcc (2.0V)
0.2Vcc (0.8V)
__
th(E-RW)
tsu(S-E)
S0, S1
th(E-S)
0.2Vcc (0.8V)
Read
0.8Vcc
0.2Vcc
DQ0-DQ7
tv(E-D)
ta(E-D)
Write
DQ0-DQ7
tsu(E-D)
th(E-D)
0.8Vcc (2.0V)
0.2Vcc (0.8V)
tv(E-OBF)
td(E-IBF)
OBF, IBF
Fig. 2.3. MBI Timing Diagram (R/W Type Mode)
86
0.2Vcc
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 2.5. Memory Expansion Mode and Microprocessor Mode Timing
(Vcc = 4.15 to 5.25V, Vss = 0V, Ta = -20 to 85°C unless otherwise noted)
Symbol
Limits
Parameter
Min.
Typ.
Max.
Unit
tc(Φ)
Φ clock cycle time
83.33
ns
twh(Φ)
Φ clock “H” pulse width
0.5*tc(Φ)-5
ns
twl(Φ)
Φ clock “L” pulse width
0.5*tc(Φ)-5
td(Φ-AH)
Address bus AB15-AB8 delay time with respect to Φ
tv(Φ-AH)
Address bus AB15-AB8 valid time with respect to Φ
td(Φ-AL)
Address bus AB7-AB0 delay time with respect to Φ
tv(Φ-AL)
Address bus AB7-AB0 valid time with respect to Φ
td(Φ-WR)
WR delay time
tv(Φ-WR)
WR valid time
td(Φ-RD)
RD delay time
ns
31
ns
33
ns
6
ns
6
ns
5
ns
5
ns
3
ns
tv(Φ-RD)
RD valid time
td(Φ-SYNC)
SYNCOUT delay time
3
ns
tv(Φ-SYNC)
SYNCOUT valid time
td(Φ-DMA)
DMAOUT delay time
tv(Φ-DMA)
DMAOUT valid time
5
ns
tsu(RDY-Φ)
RDY setup time with respect to Φ
21
ns
th(Φ-RDY)
RDY hold time with respect to Φ
0
ns
tsu(HOLD-Φ)
HOLD setup time
21
ns
th(Φ-HOLD)
HOLD hold time
0
td(Φ-HLDAL)
HLDAL delay time
6
ns
25
ns
4
tv(Φ-HLDAH)
HLDAH delay time
tsu(DB-Φ)
Data bus setup time with respect to Φ
7
th(Φ-DB)
Data bus hold time with respect to Φ
0
td(Φ-DB)
Data bus delay time with respect to Φ
ns
ns
25
ns
25
ns
ns
ns
22
ns
tv(Φ-DB)
Data bus valid time with respect to Φ
13
ns
twl(WR)
WR pulse width
0.5*tc(Φ)-5
ns
twl(RD)
RD pulse width
0.5*tc(Φ)-5
ns
td(AH-WR)
WR delay time after stable address AB15-AB8
0.5*tc(Φ)-28
ns
td(AL-WR)
WR delay time after stable address AB7-AB0
0.5*tc(Φ)-30
ns
tv(WR-AH)
Address bus AB15-AB8 valid time with respect to WR
0
ns
tv(WR-AL)
Address bus AB7-AB0 valid time with respect to WR
0
ns
(Note)
td(AH-RD)
RD delay time after stable address AB15-AB8
0.5*tc(Φ)-28
ns
td(AL-RD)
RD delay time after stable address AB7-AB0
0.5*tc(Φ)-30
ns
tv(RD-AH)
Address bus AB15-AB8 valid time with respect to RD
0
tv(RD-AL)
Address bus AB7-AB0 valid time with respect to RD
0
ns
tsu(RDY-WR)
RDY setup time with respect to WR
27
ns
th(WR-RDY)
RDY hold time with respect to WR
0
ns
tsu(RDY-RD)
RDY setup time with respect to RD
27
ns
th(RD-RDY)
RDY hold time with respect to RD
0
ns
tsu(DB-RD)
Data bus setup time with respect to RD
13
ns
th(RD-DB)
Data bus hold time with respect to RD
0
td(WR-DB)
Data bus delay time with respect to WR
ns
ns
20
ns
tv(WR-DB)
Data bus valid time with respect to WR Note
10
tr(D+), tr(D-)
USB output rise time, CL=50 pF
4
20
ns
tf (D+), tf(D-)
USB output fall time, CL=50 pF
4
20
ns
Note :
ns
Measurement conditions: Iohl = ±5ma, CL = 50pF
87
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
tc( Φ )
twh(Φ)
Φ
twl(Φ)
0.5Vcc
0.5Vcc
td(Φ - AH)
AB15-AB8
tv(Φ - AH)
0.5Vcc
td(Φ - AL )
AB7-AB0
tv(Φ - AL)
0.5Vcc
tv(Φ - WR)
tv(Φ - RD)
td(Φ - WR)
td(Φ - RD)
RD, WR
0.5Vcc
td(Φ - SYNC)
SYNCOUT
tv(Φ - SYNC)
0.5Vcc
td(Φ - DMA)
DMAOUT
tv(Φ - DMA)
(n cycles of Φ)
0.5Vcc
tsu(RDY - Φ)
th(Φ - RDY)
RDY
0.8Vcc
0.2Vcc
_______
tsu(HOLD - Φ)
_______
th(Φ - HOLD)
HOLD
(Enter state)
0.8Vcc
0.2Vcc
_______
td(Φ - HLDAL)
HLDA
0.5Vcc
_______
tsu(HOLD - Φ)
_______
th(Φ - HOLD)
HOLD
(Exit state)
0.8Vcc
0.2Vcc
_______
td(Φ - HLDAH)
HLDA
0.5Vcc
tsu(DB - Φ)
th(Φ - DB)
0.8Vcc
DB0-DB7
(CPU Read Phase)
0.2Vcc
td(Φ - DB)
tv(Φ - DB)
DB0-DB7
(CPU Write Phase)
USB D+
USB D-
0.5Vcc
tf(D+)
tf(D-)
tr(D+)
tr(D-)
0.9VoH
0.1VoH
Fig. 2.4. Microprocessor and Memory Expansion Mode Timing Diagram 1
88
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
___
___
twl(RD), twl(WR)
RD, WR
0.5Vcc
___
___
tv(WR
___ - AH)
tv(RD - AH)
td(AH - WR)
___
td(AH - RD)
AB15-AB8
0.5Vcc
___
___
td(AL - WR)
___
td(AL - RD)
AB7-AB0
tv(WR
___ - AL)
tv(RD - AL)
0.5Vcc
___
tsu(RDY WR)
___
tsu(RDY - RD)
___
th(WR
___ - RDY)
th(RD - RDY)
0.8Vcc
RDY
0.2Vcc
___
tsu(DB - RD)
___
th(RD - DB)
0.8Vcc
DB0-DB7
(CPU Read Phase)
0.2Vcc
___
td(WR - DB)
___
tv(WR - DB)
DB0-DB7
(CPU Write Phase)
0.5Vcc
Fig. 2.5. Microprocessor and Memory Expansion Mode Timing Diagram 2
tc(SCLKE,I)
SIO
twl(SCLKE,I)
twh(SCLKE,I)
0.8Vcc
SCLK
0.2Vcc
tsu(SRXD-SCLKE,I)
th(SCLKE,I-SRXD)
0.8Vcc
SRXD
0.2Vcc
td(SCLKE,I-STXD)
STXD
0.5Vcc
__
tv(SCLKE-SRDY)
0.8Vcc
SRDY
Fig. 2.6. SIO Timing Diagram
1kΩ
Measurement output pin
Measurement output pin
100pF
CMOS Output
100pF
N-channel Open-drain Output
Fig. 2.7. Output Switching Characteristics Measurements Circuits
89
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DATA REQUIRED FOR MASK ORDERS
ROM PROGRAMMING METHOD
The following are necessary when ordering a mask
ROM production:
The built-in PROM of the blank One-time PROM version and built-in EPROM version can be read or
programmed with a general-purpose PROM programmer using a special programming adapter. (See Table
2.6).
1.
2.
3.
Mask ROM Order Confirmation Form
Mark Specification Form
Data to be written to ROM, in EPROM form
three identical copies) or in floppy disk form.
Table 2.6. Programming adapter
Package
80P6N-A
Name of Programming Adapter
PCA7440FP
80D0
PCA7440FS
The PROM of the blank One Time PROM version is
not tested or screened in the assembly process and
following processes. To ensure proper operation after
programming, the procedure shown in Figure 2.8 is
recommended to verify programming.
Programming with PROM
programmer
Screening (Caution)
(150 °C for 40 hours)
Verification with
PROM programmer
Functional check in
target device
Caution : The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Fig. 2.8. Programming and testing of One-Time PROM version
90
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH57-30B<9XA0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37640M8-XXXFP
MITSUBISHI ELECTRIC
We recommend the use of the following pseudo-command to set the start address of the assembler source program
because ASCII codes of the product name are written to addresses 000016 to 000816 of EPROM.
EPROM type
The pseudo-command
27512
*=
.BYTE
$0000
‘M37640M8-’
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation
form, the ROM will not be processed.
Ordering by floppy disk
We will produce masks based on the mask file generating utility. We shall assume the responsibility for errors
only if the mask ROM data on the products differs from this mask file. Therefore, extreme care must be taken to
verify the accuracy of the mask file submitted.
The floppy disk must be 3.5-inch 2HD type and DOS/V format. Only one mask file per floppy disk should be
submitted.
* 1.
File Code
(hexadecimal notation)
Mask file name
.MSK (equal or less than eight characters)
Mark specification
Mark specification must be submitted using the correct form for the package being ordered. Fill out
the appropriate mark specification form 80P6N and attach it to the mask ROM confirmation form.
* 2.
Usage conditions
Please answer the following questions about usade for use in our product inspection.
(1) How will you use the Xin-Xout oscillator?
Quartz crystal
Other (
External clock input
)
At what frequency?
f(Xin) =
MHz
(2) Which function will you use the pins P50/XCin and P51/XCout as P50 and P51, or XCin and XCout ?
Ports P50 and P51 function
XCin and XCout function (external resonator)
* 3. Comments
91
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GZZ-SH57-30B<9XA0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M37640M8-XXXFP
MITSUBISHI ELECTRIC
Receipt
Date:
Section head Supervisor
signature
signature
*
Customer
TEL
(
Company
name
Date
issued
)
Date:
Issuance
signature
Note : Please fill in all items marked *.
Submitted by
Supervisor
*1 Confirmation
Three EPROMs are required for each pattern if this order is performed by EPROMs.
One floppy disk is required for each pattern if this order is performed by a floppy disk.
Ordering by EPROMs
If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based
on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we
produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM
(hexadecimal notation)
EPROM type (indicate the type used)
27512
EPROM address
000016
Product name
000F16
001016
807F16
808016
FFFB16
FFFC16
FFFF16
ASCII code :
‘M37640M8-’
In the address space of the microcomputer, the internal ROM area is from address 808016 to FFFB16. The reset vector is stored in addresses FFFA16 and
FFFB16.
data
ROM 32K-132 bytes
(1) Set the data in the unused area (the shaded area of
the diagram) to “FF16”.
(2) The ASCII codes of the product name “M37640M8-”
must be entered in addresses 000016 to 000816.
And set the data “FF16” in addresses 000916 to
000F 16.
The ASCII codes and addresses are listed to the
right in hexadecimal notation.
92
Address
0000 16
000116
0002 16
0003 16
0004 16
0005 16
0006 16
0007 16
‘M’
‘3’
‘7’
‘6’
‘4’
‘0’
‘M’
‘8’
=
=
=
=
=
=
=
=
4D16
3316
3716
3616
3416
3016
4D16
3816
Address
0008 16
0009 16
000A16
000B 16
000C 16
000D 16
000E 16
000F16
‘-’ = 2D16
FF16
FF16
FF16
FF16
FF16
FF16
FF16
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
80P6n (80-PIN QFP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name
Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed).
Notes
A. Standard Mitsubishi Mark
41
64
40
65
Mitsubishi IC catalog name
Mitsubishi product number
(6-digit, or 7-digit)
25
80
1
24
B. Customerís Parts Number + Mitsubishi IC Catalog Name
41
64
40
65
Customerís Parts Number
Note: The fonts and size of characters are standard
Mitsubishi type.
Mitsubishi IC catalog name
Notes
25
80
24
1
C. Special Mark Required
64
41
40
65
25
80
1
24
1: The mark field should be written right aligned.
2: The fonts and size of characters are standard
Mitsubishi type.
3: Customerís parts number can be up to 14 alphanumeric characters for capital letters, hyphens, commas,
periods and so on.
1: If special mark is to be printed, indicate the desired layout of the mark in Figure C. The layout will be duplicated
technically as close as possible. Mitsubishi product number (6-digit, or 7-digit) and Mask ROM number (3-digit) are
always marked for sorting the products.
2: If special character fonts (e,g., customerís trade mark
logo) must be used in Special Mark, check the box below.
For the new special character fonts, a clean font original
(ideally logo drawing) must be submitted.
Special character fonts required
93
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
80P6N-A
Plastic 80pin 14✕20mm body QFP
EIAJ Package Code
QFP80-P-1420-0.80
Weight(g)
1.58
Lead Material
Alloy 42
MD
e
JEDEC Code
–
80
ME
HD
D
b2
65
1
64
I2
24
Symbol
HE
E
Recommended Mount Pad
41
A
40
25
c
A2
L1
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
x
y
y
94
b
x M
A1
F
e
L
Detail F
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
–
–
3.05
0.1
0.2
0
–
–
2.8
0.3
0.35
0.45
0.13
0.15
0.2
13.8
14.0
14.2
19.8
20.0
20.2
–
0.8
–
16.5
16.8
17.1
22.5
22.8
23.1
0.4
0.6
0.8
1.4
–
–
–
–
0.2
0.1
–
–
o
o
0
10
–
0.5
–
–
1.3
–
–
14.6
–
–
–
–
20.6
MITSUBISHI MICROCOMPUTERS
7640 Group
Ver 1.4
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to
personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-
•
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual
property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application
examples contained in these materials.
All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by
Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or
errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).
When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final
decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric
Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical,
aerospace, nuclear, or undersea repeater use.
The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved
destination.
Notes regarding these materials
•
•
•
•
•
•
© 2000 MITSUBISHI ELECTRIC CORP.
New publication, effective August 2000.
Specifications subject to change without notice.
REVISION HISTORY
Rev.
No.
1.4
7640 GROUP DATA SHEET
Revision Description
First Edition
Rev.
date
09/05/00
(1/1)