ETC 805DPFCTD

Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
56F805
Digital Power
Factor Correction
using
Processor
ExpertTM
Targeting Document
56F805
Hybrid Controller
805DPFCTD/D
Rev 0, 12/2003
MOTOROLA.COM/SEMICONDUCTORS
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Specifications
Digital Power Factor Correction
This application exercises simple control of the Power Factor Correction (PFC) without motor
control on the 56F805EVM board and the EVM Motor Kit.
1.
Specifications
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The Digital PFC application performs power factor correction for 3-Phase AC/BLDC High-Voltage
Power Stage hardware without motor drive. This demonstration evaluates the basic algorithm of power
factor correction for the current hardware implementation. The PFC software was designed for use
with motor control applications; the Digital PFC application allows target memory configuration of
RAM and Flash.
The input power line must meet the following requirements:
•
•
Input voltage value 115V and 60Hz
Input voltage value 230V and 50Hz
The applications run at 230V, 50Hz by default. To switch to 115V, 60Hz, comment this line in
Digital_PFC.c:
#define MILESTONE_OFFSET MKS_TO_TICK(570L)
//For 50 Hz, 230 V
And uncomment this line:
//#define MILESTONE_OFFSET MKS_TO_TICK(1498L) //For 60 Hz, 115 V
The Digital PFC application may be used in the Manual Operating Mode. The remote control
functionality of the PC master software application is not implemented.
The application can run on:
•
•
2
External RAM
Flash
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Specifications
1.1 Manual Operating Mode
The PFC conversion is controlled by the RUN/STOP switch (S6); see Figure 1-1. The green USER
LED (LED3; see Figure 1-2) indicates the application states. When the application is ready, the USER
LED blinks at a 2Hz frequency. A fault state turns on the red LED1 and turns off the green LED3.
.
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RUN / STOP
switch
Figure 1-1. RUN/STOP Switch
User green LED
Figure 1-2. User LED
The PFC conversion can be enabled after the RUN/STOP switch is moved to the RUN position. The
normal PFC conversion process is indicated by the USER LED, which will light continuously. To
disable PFC conversion, the RUN/STOP switch must be moved to the STOP position.
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Specifications
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Table 1-1. Motor Application States
Application State
Digital PFC State
LED State
Stopped
Stopped
Green LED blinking
Red LED off
Running
Spinning
Green LED on
Red LED off
Fault
Stopped
Green LED off
Red LED on
1.2 PC Master Software (Remote) Operating Mode
The drive is monitored remotely from a PC through the SCI communication channel of the device via
an RS-232 physical interface.
PC master software displays the following information:
•
•
•
Application mode
Application status
DCBus Voltage
Application Mode Project files for the PC master software are located in:
..\PC_Master\external memory.pmp, uses Map file to run in the external memory
..\PC_Master\internal pROM-xRAM.pmp, uses Map file to run in the internal memory
..\PC_Master\internal xROM-xRAM.pmp, uses Map file to run in the internal memory
Start the PC master software window’s application, external_memory.pmp. Figure 1-3 illustrates the
PC master software control window after this project has been launched.
4
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Specifications
Figure 1-3. PC Master Software Control Window
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Hardware Set-up
2.
Hardware Set-up
Figure 2-1 illustrates the hardware set-up for the Digital PFC application, which requires a motor
drive. The 3-Phase AC/BLDC High-Voltage Power Stage board contains the JP201 jumper that selects
the power supply device. Pins 2 and 3 of the JP201 connection correspond to a simple
rectifier-capacitor power stage. The PFC hardware set-up requires closing pins 1and 2 of the JP201
connection; see Figure 2-2.
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Motor Power
Connector
AC Power Line
Connector
Optoisolation
Board
3-ph AC BLDC
HV Power Stage
Power Supply
Serial cable
Controller
board
Parallel
cable
Figure 2-1. Digital PFC Application Set-up
The system is comprised of the following components:
•
•
•
Controller board for 56F805
— Supplied as 56F805EVM
— Described in 56F805 Evaluation Module Hardware User’s Manual
3-Phase AC BLDC High-Voltage Power Stage, 180W
— Supplied in a kit with optoisolation board as ECOPTHIVACBLDC
— Described in 3-Phase Brushless DC High-Voltage Power Stage
Optoisolation Board
— Supplied with 3-Phase AC/BLDC HighVoltage Power Stage as ECOPTHIVACBLDC
or
— Supplied alone as ECOPT - optoisolation board
— Described in Optoisolation Board User’s Manual
Warning: It is strongly recommended that optoisolation (optocouplers and optoisolation amplifiers) be
used during development to avoid damage to the development equipment.
Note:
6
Documentation for all components can be found at
http://motorola.com/semiconductors
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Hardware Set-up
PFC Jumper
JP201
3
1
2
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Figure 2-2. Jumper JP201 on the 3-Phase AC BLDC Power Stage
For detailed information, see the 56F805 Evaluation Module Hardware Reference Manual. The
serial cable is needed for the PC master software debugging tool only.
2.1 EVM Jumper Settings
To execute the Digital PFC application, the 56F805EVM board requires the strap settings shown in
Figure 2-3 and Table 2-1.
J20
J23
J24
J26
J25
JG14
J9
J32
1
JG17
1
J6
J29
J8
J17
1
1
JG6
1
J3
1
1
JG12
JG13
JG4
1
J31
JG18
J1
J30
JG15
JG8
1
1
J14
JG1
JG2
J22
1
J4
1
JG3 1
J5 J7
J27
JG7 J2
1
J19
S4
1
P3
JG8
1
S5
JG5
S6
1
JG9
JG11
J16
S1
S2
S3
P1
Figure 2-3. 56F805EVM Jumper Reference
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Hardware Set-up
Table 2-1. 56F805EVM Jumper Settings
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Jumper
Group
Comment
Connections
JG1
PD0 input selected as a high
1-2
JG2
PD1 input selected as a high
1-2
JG3
Primary UNI-3 serial selected
1-2, 3-4, 5-6, 7-8
JG4
Secondary UNI-3 serial selected
1-2, 3-4, 5-6, 7-8
JG5
Enables on-board parallel JTAG Command Converter Interface
NC
JG6
Uses on-board crystal for oscillator input
2-3
JG7
Selects Mode 0 operation upon exit from reset
1-2
JG8
Enables on-board SRAM
1-2
JG9
Enables RS-232 output
1-2
JG10
Secondary UNI-3 Analog temperature input unused
NC
JG11
Uses Host power for Host target interface
1-2
JG12
Primary Encoder input selected for Quad Encoder signals
2-3, 5-6, 8-9
JG13
Secondary Encoder input selected
2-3, 5-6, 8-9
JG14
Primary UNI-3 3-Phase Current Sense selected as Analog Inputs
2-3, 5-6, 8-9
JG15
Secondary UNI-3 Phase A Overcurrent selected for FAULTA1
1-2
JG16
Secondary UNI-3 Phase B Overcurrent selected for FAULTB1
1-2
JG17
CAN termination unselected
NC
JG18
Uses on-board crystal for DSP oscillator input
1-2
Note: When running the EVM target system in a stand-alone mode from Flash, the JG5 jumper must
be set in the 1-2 configuration to disable the command converter parallel port interface.
8
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Build
3.
Build
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When building the Digital PFC Application, the user can create an application that runs from
internal Flash or External RAM. To select the type of application to build, open the
digital_PFC.mcp project and choose the target build type; see Figure 3-1. A definition of the
projects associated with these target build types may be viewed under the Targets tab of the
project window.
Figure 3-1. Target Build Selection
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Build
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The project may now be built by executing the Make command, as shown in Figure 3-2. This will
build and link the Digital PFC Application and all needed Metrowerks and Processor Expert libraries.
Figure 3-2. Execute Make Command
For more information about these commands, see:
<...>\CodeWarrior Manuals\PDF\Targeting_56800.pdf
10
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Projects Files
4.
Projects Files
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The Digital PFC application is composed of the following files:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
5.
...\Project Directory\“Project File Name”.mcp, application project file
...\Project Directory\“Project File Name”.pe, Processor Expert software file
...\Project Directory\“Project File Name”.G_C, Processor Expert software file
...\Project Directory\“Project File Name”.dsk, Processor Expert software file
...\Project Directory\bin\*.xMAP, map file
...\Project Directory\bin\*.elf standard binary file
...\Project Directory\startup\*.c, *.h, *.asm, initialization files
...\Project Directory\Code\adcPrimary.*, files generated by the PE for adcPrimary bean
...\Project Directory\Code\PC_M1.*, files generated by the PE for PC_M1 bean
...\Project Directory\Code\tiAux.*, files generated by the PE for tiAux bean
...\Project Directory\Code\tmrD2.*, files generated by the PE for tmrD2 bean
...\Project Directory\Code\Cpu.*, files generated by the PE for the CPU used
...\Project Directory\Code\Events.*, files generated by the PE for events
...\Project Directory\Code\PE_Const.*, PE internal definitions of the constants
...\Project Directory\Code\PE_Error.*, PE internal definitions of the error constants
...\Project Directory\Code\PE_Types.*, PE internal definitions of the types
...\Project Directory\Code\PESL.*, configuration file for PESL library
...\Project Directory\Code\Vectors.*, definitions of the interrupt vectors
Execute
To execute the Digital PFC Application, select the Project/Debug command in the CodeWarrior IDE,
followed by the Run command. For more help with these commands, refer to the CodeWarrior tutorial
documentation in the following file, located in the CodeWarrior installation directory:
<...>\CodeWarrior Manuals\PDF\Targeting_56800.pdf
If the Flash target is selected, CodeWarrior will automatically program the device’s internal Flash with
the executable generated during Build. If the External RAM target is selected, the executable will be
loaded to off-chip RAM.
Once Flash has been programmed with the executable, the EVM target system may be run in a
stand-alone mode from Flash. To do this, set the JG5 jumper in the 1-2 configuration to disable the
parallel port, and press the RESET button.
To enable the PFC conversion, set the RUN/STOP switch to the RUN position. If this switch was in
the RUN position before the application started, move it to the STOP position first, then back to the
RUN position. The USER LED should light continuously when the PFC conversion is enabled. To
disable the PFC conversion, move the RUN/STOP switch to the STOP position, causing the USER
LED to blink again.
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805DPFCTD/D
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