High Performance HDMI/DVI Transmitter AD9889A FEATURES FUNCTIONAL BLOCK DIAGRAM SCL SDA INT MCL MDA INTERRUPT HANDLER I2C SLAVE HPD HDCP CORE HDCP-EDID MICROCONTROLLER REGISTER CONFIGURATION LOGIC I2C MASTER CLK DDCSDA DDCSCL VSYNC HSYNC VIDEO DATA CAPTURE DE D[23:0] Tx0[1:0] COLOR SPACE CONVERSION 4:2:2 TO 4:4:4 CONVERSION HDMI Tx CORE XOR MASK Tx1[1:0] Tx2[1:0] TxC[1:0] S/PDIF MCLK I2S[3:0] AUDIO DATA CAPTURE LRCLK AD9889A SCLK 06148-001 General HDMITM/DVI transmitter compatible with HDMI v1.2a, DVI v1.0, and HDCP 1.1 Single 1.8 V power supply Video/audio inputs accept logic level s from 1.8 V to 3.3 V 76-ball CSP_BGA, Pb-free package Digital video 80 MHz operation supports all resolutions from 480i to 720p/1080i and XGA-75 Hz Programmable two-way color space converter Supports RGB, YCbCr, DDR Supports ITU656 based embedded syncs Auto input video format timing detection (CEA-861B) Digital audio Supports standard S/PDIF for stereo LPCM or compressed audio up to 192 kHz 8-channel uncompressed LPCM I2S audio up to 192 kHz Special features for easy system design On-chip MPU with I2C® master to perform HDCP operations and EDID reading operations 5 V tolerant I2C and HPD I/Os, no extra device needed No audio master clock needed for supporting S/PDIF and I2S On-chip MPU reports HDMI events through interrupts and registers Figure 1. APPLICATIONS DVD players and recorders Digital set-top boxes A/V receivers Digital cameras and camcorders HDMI repeater/splitter GENERAL DESCRIPTION The AD9889A-BBCZ is an 80 MHz, high definition multimedia interface (HDMI) v.1.2a transmitter. It supports HDTV formats up to 720p/1080i, and computer graphic resolutions up to XGA (1024 × 768 @ 75 Hz). With the inclusion of HDCP, the AD9889A allows the secure transmission of protected content as specified by the HDCP v1.1 protocol. The AD9889A supports both S/PDIF and 8-channel I2S audio. Its high fidelity 8-channel I2S can transmit either stereo or 7.1 surround audio at 192 kHz. The S/PDIF can carry stereo LPCM audio or compressed audio including Dolby® Digital, DTS®, and THX®. The AD9889A helps to reduce system design complexity and cost by incorporating such features as an internal MPU for HDCP operations, an I2C master for EDID reading, a single 1.8 V power supply and 5 V tolerance on I2C and hot plug detect pins. Fabricated in an advanced CMOS process, the AD9889A is available in a space saving, 76-ball, CSP_BGA surfacemount package. The CSP_BGA package is specified from −25°C to +90°C. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. AD9889A TABLE OF CONTENTS Features .............................................................................................. 1 Applications........................................................................................7 Applications....................................................................................... 1 Design Resources ..........................................................................7 Functional Block Diagram .............................................................. 1 Document Conventions ...............................................................7 General Description ......................................................................... 1 PCB Layout Recommendations.......................................................8 Revision History ............................................................................... 2 Power Supply Bypassing ...............................................................8 Specifications..................................................................................... 3 Digital Inputs .................................................................................8 Absolute Maximum Ratings............................................................ 4 External Swing Resistor................................................................8 Explanation of Test Levels ........................................................... 4 Output Signals ...............................................................................8 ESD Caution.................................................................................. 4 Outline Dimensions ..........................................................................9 Pin Configuration and Function Descriptions............................. 5 Ordering Guide..............................................................................9 REVISION HISTORY 10/06—Revision 0: Initial Version Rev. 0 | Page 2 of 12 AD9889A SPECIFICATIONS Table 1. Parameter DIGITAL INPUTS Input Voltage, High (VIH) Input Voltage, Low (VIL) Input Capacitance DIGITAL OUTPUTS Output Voltage, High (VOH) Output Voltage, Low (VOL) THERMAL CHARACTERISTICS Thermal Resistance θJC Junction-to-Case θJA Junction-to-Ambient Ambient Temperature DC SPECIFICATIONS Input Leakage Current, IIL Input Clamp Voltage Differential High Level Output Voltage Differential Output Short-Circuit Current POWER SUPPLY VDD (All) Supply Voltage VDD Supply Voltage Noise Power-Down Current Transmitter Supply Current2 Transmitter Total Power AC SPECIFICATIONS CLK Frequency TMDS Output CLK Duty Cycle Worst Case CLK Input Jitter Input Data Setup Time Input Data Hold Time TMDS Differential Swing VSYNC and HSYNC Delay from DE Falling Edge VSYNC and HSYNC Delay to DE Rising Edge DE High Time DE Low Time Differential Output Swing Low-to-High Transition Time High-to-Low Transition Time AUDIO AC TIMING Sample Rate I2S Cycle Time I2S Setup Time I2S Hold Time Audio Pipeline Delay Conditions Temp Test Level1 Min Full Full 25°C VI VI V 1.4 Full Full VI VI VDD − 0.1 Full V V V 25°C 25°C 25°C −16 mA +16 mA With active video applied 80 MHz, typical random pattern I2S and S/PDIF 1 See Explanation of Test Levels section. Using low output drive strength. 3 UI = unit interval. 2 Rev. 0 | Page 3 of 12 Typ Max Unit 0.7 V V pF 3 −25 15.2 59 +25 0.4 V V +90 °C/W °C/W °C VI V V V IV −10 +10 Full Full 25°C 25°C Full IV V IV IV VI 1.71 25°C 25°C Full Full Full 13.5 48 25°C 25°C IV IV IV IV IV VI VI VI VI VI 25°C 25°C VII VII 75 75 490 490 ps ps Full 25°C 25°C 25°C 25°C IV IV IV IV IV 32 192 1 kHz UI ns ns μs −0.8 +0.8 AVCC 10 1.8 9 143 257 1 1 800 1.89 50 155 280 80 52 2 1000 1 1 1200 8191 138 15 0 75 μA V V V μA V mV p-p mA mA mW MHz % ns ns ns mV UI3 UI UI UI AD9889A ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS Table 2. Parameter Digital Inputs Digital Output Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Maximum Case Temperature Rating 5 V to 0.0 V 20 mA −40°C to +90°C −65°C to +150°C 150°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. I. 100% production tested. II. 100% production tested at 25°C and sample tested at specified temperatures. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. 100% production tested at 25°C; guaranteed by design and characterization testing. VII. Limits defined by HDMI specification; guaranteed by design and characterization testing. ESD CAUTION Rev. 0 | Page 4 of 12 AD9889A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J 06148-004 K BOTTOM VIEW (Not to Scale) Figure 2. 76-Ball BGA Configuration (Top View) Table 3. Pin Function Descriptions Pin No. A1 to A10, B1 to B10, C9, C10, D9, D10 D1 C2 C1 D2 J3 K3 Mnemonic D[23:0] Type 1 I Description Video Data Input. Digital input in RGB or YCbCr format. Supports CMOS logic levels from 1.8 V to 3.3 V. CLK DE HSYNC VSYNC EXT_SW HPD I I I I I I E2 S/PDIF I E1 MCLK I F2, F1, G2, G1 I2S[3:0] I H2 H1 J7 SCLK LRCLK PD/A0 I I I K1, K2 TxC−/TxC+ O K10, J10 Tx2−/Tx2+ O K7, K8 Tx1−/Tx1+ O K4, K5 Tx0−/Tx0+ O H10 INT O J2, J5, J8, K9 D5, D6, D7, E7 AVDD DVDD P P G4, G5, J1 PVDD P D4, E4, F4, J4, G6, J6, K6, F7, G7, H9, J9 GND P Video Clock Input. Supports CMOS logic levels from 1.8 V to 3.3 V. Data Enable Bit for Digital Video. Supports CMOS logic levels from 1.8 V to 3.3 V. Horizontal SYNC Input. Supports CMOS logic levels from 1.8 V to 3.3 V. Vertical SYNC Input. Supports CMOS logic levels from 1.8 V to 3.3 V. Sets internal reference currents. Place 887 Ω resistor (1% tolerance) between this pin and ground. Hot Plug Detect Signal. This indicates to the interface whether the receiver is connected. 1.8 V to 5.0 V CMOS logic level. S/PDIF (Sony/Philips Digital Interface) Audio Input. This is the audio input from a Sony/Philips digital interface. Supports CMOS logic levels from 1.8 V to 3.3 V. Audio Reference Clock. 128 × N × fS with N = 1, 2, 3, or 4. Set to 128 × sampling frequency (fS), 256 × fS, 384 × fS, or 512 × fS. 1.8 V to 3.3 V CMOS logic level. I2S Audio Data Inputs. These represent the eight channels of audio (two per input) available through I2S. Supports CMOS logic levels from 1.8 V to 3.3 V. I2S Audio Clock. Supports CMOS logic levels from 1.8 V to 3.3 V. Left/Right Channel Selection. Supports CMOS logic levels from 1.8 V to 3.3 V. Power-Down Control and I2C Address Selection. The I2C address and the PD polarity are set by the PD/A0 pin state when the supplies are applied to the AD9889A. 1.8 V to 3.3 V CMOS logic level. Differential Clock Output. Differential clock output at pixel clock rate; transition minimized differential signaling (TMDS) logic level. Differential Output Channel 2. Differential output of the red data at 10× the pixel clock rate; TMDS logic level. Differential Output Channel 1. Differential output of the green data at 10× the pixel clock rate; TMDS logic level. Differential Output Channel 0. Differential output of the blue data at 10× the pixel clock rate; TMDS logic level. Interrupt. CMOS logic level. A 2 kΩ pull up resistor to interrupt the microcontroller IO supply is recommended. 1.8 V Power Supply for TMDS Outputs. 1.8 V Power Supply for Digital and I/O Power Supply. These pins supply power to the digital logic and I/Os. They should be filtered and as quiet as possible. 1.8 V PLL Power Supply. The most sensitive portion of the AD9889A is the clock generation circuitry. These pins provide power to the clock PLL. The designer should provide quiet, noise-free power to these pins. Ground. The ground return for all circuitry on-chip. It is recommended that the AD9889A be assembled on a single, solid ground plane with careful attention given to ground current paths. Rev. 0 | Page 5 of 12 AD9889A Pin No. F9 Mnemonic SDA Type1 C2 F10 SCL C2 E10 E9 G9 G10 MDA MCL DDCSDA DDCSCL C2 C2 C2 C2 1 2 Description Serial Port Data I/O. This pin serves as the serial port data I/O slave for register access. Supports CMOS logic levels from 1.8 V to 3.3 V. Serial Port Data Clock. This pin serves as the serial port data clock slave for register access. Supports CMOS logic levels from 1.8 V to 3.3 V. Serial Port Data I/O Master to HDCP Key EEPROM. Supports CMOS logic levels from 1.8 V to 3.3 V. Serial Port Data Clock Master to HDCP Key EEPROM. Supports CMOS logic levels from 1.8 V to 3.3 V. Serial Port Data I/O to Receiver. This pin serves as the master to the DDC bus. 5 V CMOS logic level. Serial Port Data Clock to Receiver. This pin serves as the master clock for the DDC bus. 5 V CMOS logic level. I = input, O = output, P = power supply, C = control. For a full description of the 2-wire serial interface and its functionality obtain documentation by contacting NDA from [email protected]. Rev. 0 | Page 6 of 12 AD9889A APPLICATIONS DESIGN RESOURCES DOCUMENT CONVENTIONS Analog Devices, Inc. evaluation kits, reference design schematics, and other support documentation is available under NDA from [email protected]. In this data sheet, data is represented using the conventions described in Table 4. Table 4. Document Conventions Other resources include: Data Type 0xNN EIA/CEA-861B that describes audio and video infoframes as well as the E-EDID structure for HDMI. It is available from Consumer Electronics Association (CEA). 0bNN The HDMI v1.2a, a defining document for HDMI Version 1.2a, and the HDMI Compliance Test Specification Version 1.2a are available from HDMI Licensing, LLC. NN Bit The HDCP v1.1 is the defining document for HDCP Version 1.1. available from Digital Content Protection, LLC. Rev. 0 | Page 7 of 12 Format Hexadecimal (Base-16) numbers are represented using the C language notation, preceded by 0x. Binary (Base-2) numbers are represented using the C language notation, preceded by 0b. Decimal (Base-10) numbers are represented using no additional prefixes or suffixes. Bits are numbered in little endian format, that is, the least significant bit of a byte or word is referred to as Bit 0. AD9889A PCB LAYOUT RECOMMENDATIONS The AD9889A is a high precision, high speed analog device. As such, to get the maximum performance out of the part, it is important to have a well laid out board. POWER SUPPLY BYPASSING It is recommended to bypass each power supply pin with a 0.1 μF capacitor. The exception is when two or more supply pins are adjacent to each other. For these groupings of powers/grounds, it is necessary to have only one bypass capacitor. The fundamental idea is to have a bypass capacitor within about 0.5 cm of each power pin. Also, avoid placing the capacitor on the opposite side of the PC board from the AD9889A, as that interposes resistive vias in the path. The bypass capacitors should be physically located between the power plane and the power pin. Current should flow from the power plane to the capacitor to the power pin. Do not make a power connection between the capacitor and the power pin. Placing a via underneath the capacitor pads, down to the power plane, is generally the best approach. It is particularly important to maintain low noise and good stability of PVDD (the PLL supply). Abrupt changes in PVDD can result in similarly abrupt changes in sampling clock phase and frequency. This can be avoided by careful attention to regulation, filtering, and bypassing. It is best practice to provide separate regulated supplies for each of the analog circuitry groups (AVDD and PVDD). It is also recommended to use a single ground plane for the entire board. Experience has repeatedly shown that the noise performance is the same or better with a single ground plane. Using multiple ground planes can be detrimental because each separate ground plane is smaller, and long ground loops can result. DIGITAL INPUTS Video and Audio Data Input Signals The digital inputs on the AD9889A are designed to work with signals ranging from 1.8 V to 3.3 V logic level. Therefore, no extra components need to be added when using 3.3 V logic. Any noise that gets onto the clock input (labeled CLK) trace adds jitter to the system. Therefore, minimize the video clock input (Pin 6: CLK) trace length and do not run any digital or other high frequency traces near it. Make sure to match the length of the input data signals to optimize data capture, especially for high frequency modes (such as 720p or XGA 75 MHz) and double data rate input formats. Other Input Signals The PD/A0 input pin can be connected to GND or supply (through a resistor or a control signal). The device address and power-down polarity are set by the state of the PD/A0 pin when the AD9889A supplies are applied/enabled. For example, if the PD/A0 pin is low (when the supplies are turned on), then the device address is 0x72 and the power down is active high. If the PD/A0 pin is high (when the supplies are turned on), the device address is 0x7A and the power down is active low. The SCL and SDA pins should be connected to the I2C master. A pull-up resistor of 2 kΩ to 1.8 V or 3.3 V is recommended. EXTERNAL SWING RESISTOR The external swing resistor must be connected directly to the EXT_SWG pin and ground. The external swing resistor must have a value of 887 Ω (±1% tolerance). Avoid running any high speed ac or noisy signals next to, or close to, the EXT_SWG pin. OUTPUT SIGNALS TMDS Output Signals The AD9889A has three TMDS data channels (0, 1, and 2) that output signals up to 800 MHz as well as the TMDS output data clock. To minimize the channel-to-channel skew, make the trace length of these signals the same. Also, these traces need to have a 50 Ω characteristic impedance and routed as 100 Ω differential pairs. It is also recommended to route these lines on the top PCB layer avoiding the use of vias. Other Output Signals (non TMDS) DDCSCL and DDCSDA The DDCSCL and DDCSDA outputs need to have a minimum amount of capacitance loading to ensure the best signal integrity. The DDCSCL and DDCSDA capacitance loading must be less than 50 pF to meet the HDMI compliance specification. The DDCSCL and DDCSDA must be connected to the HDMI connector and a pull-up resistor to 5 V is required. The pull-up resistor must have a value between 1.5 kΩ and 2 kΩ. INT Pin The INT pin is an output that should be connected to the microcontroller of the system. A pull-up resistor to 1.8 V or 3.3 V is required for proper operation: the recommended value is 2 kΩ. MCL and MDA The MCL and MDA outputs should be connected to the EEPROM containing the HDCP key (if HDCP is implemented). Pull-up resistors of 2 kΩ are recommended. The HPD must be connected to the HDMI connector. A 10 kΩ pull-down resistor to ground is also recommended. Rev. 0 | Page 8 of 12 AD9889A OUTLINE DIMENSIONS A1 CORNER INDEX AREA 6.10 6.00 SQ 5.90 10 9 8 7 6 5 4 3 2 1 A B BALL A1 PAD CORNER TOP VIEW C 4.50 BSC SQ D E 0.50 BSC F G H J K DETAIL A BOTTOM VIEW 0.75 REF *1.40 MAX DETAILA 0.65 MIN 0.15 MIN COPLANARITY 0.08 MAX *COMPLIANT TO JEDEC STANDARDS MO-225 WITH THE EXCEPTION TO PACKAGE HEIGHT. 012006-0 0.35 SEATING 0.30 PLANE 0.25 BALL DIAMETER Figure 3. 76-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 6 mm × 6 mm × 1.4 mm (BC-76) Dimensions shown in millimeters ORDERING GUIDE Model AD9889ABBCZ-80 1 AD9889ABBCZRL-801 AD9889A/PCB 1 Temperature Range −25°C to +90°C −25°C to +90°C Package Description 76-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 76-Ball Chip Scale Package Ball Grid Array [CSP_BGA] Evaluation Board Z = Pb-free part. Rev. 0 | Page 9 of 12 Package Option BC-76 BC-76 AD9889A NOTES Rev. 0 | Page 10 of 12 AD9889A NOTES Rev. 0 | Page 11 of 12 AD9889A NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06148-0-10/06(0) Rev. 0 | Page 12 of 12