®
CUSTOMIZING THE DDC112 EVALUATION FIXTURE
By Jim Todsen
This application note supplements the DDC112 Evaluation
Fixture data sheet (DEM-DDC112U). It provides additional
information on the operation of the PC Interface Board
(PCIB). It is intended to provide the user with information
needed to write custom software for a PC to control the
PCIB over the parallel port. This bulletin discusses the
details of the PCIB and assumes a familiarity with the basic
operation of the Evaluation Fixture. For general instructions
on how to use the DDC112 Evaluation Fixture, please refer
to the data sheet.
board before loading the registers. This insures correct alignment of the side A/B bit on the PCIB. This bit is used by the
software to determine the side (A or B) for each 20-bit data
from the DDC112.
An 8-bit bus is used to write data to the registers. This bus is
used for both the address and the data. The 8th bit determines
whether the bus has an address or data, and the lower 7 bits
represent either an address or data value. When LOW, the 8th
bit signals that the bus contains an address and conversely, if
HIGH, the bus contains data to be written into the addressed
register. A strobe bit latches either the address or the data on
the bus. Lines 2 through 9 of the parallel port corresponds to
U0 - U7 in Figure 2, the 8-bit bus. Line 1 of the parallel port
corresponds to STO in Figure 2, the strobe bit.
The heart of the DDC112 Evaluation Fixture is the PCIB. It
provides full control of DDC112, supplying the SCLK,
CONV, DCLK, etc., to the DUT board. Up to 32,768 data
points from the DDC112 can be collected in the PCIB’s
RAM. During readback, the software directs the PCIB to
transfer the data from the RAM to the PC via the parallel port.
To write to a register, first send the register address on U0 - U6
with bit U7 LOW. Toggle the strobe bit, STO, from HIGH to
LOW and back to HIGH. The STO bit should be normally
held HIGH. The register address has now been selected. Send
the data to be written to the register on U0 - U6 with bit U7
HIGH and again toggle STO as before. Data will be written to
the last register addressed. It is recommended that you always
send the register address before sending the register data. This
insures you are writing to the correct register.
Two Xilinx Field Programmable Arrays provide the necessary logic for the PCIB. Registers on these arrays determine
various settings, such as gain and integration time. Control
and readback of the DDC112 is accomplished by programming these registers though the PC’s parallel port. Table I
gives the addresses and a description of each of the registers.
Figure 1 shows the PCIB RAM’s memory map. The PCIB’s
schematic is shown in Figure 2. The schematics for the two
Xilinx arrays are shown in Figures 3 through 9. The logic
described in these schematics is stored in ROMs U5 and U6
on the PCIB, which automatically configure arrays U1 and
U2 on power-up. Finally, source code for an example
program is given in Listing 1.
The valid register addresses are xxx0000 to xxx1011 (0 to
11). The lower 4 bits of the address space map to the
registers. The upper 3 bits are used in the readback process
described below. It is suggested that when writing to a
register, the upper 3 bits be set to “111”.
DATA COLLECTION AND READBACK FROM THE PCIB
LOCATING THE PC’S PARALLEL PORT’S ADDRESS
Once the PCIB is initialized by loading the registers, it is
always in one of two modes: data collection or data readback.
Register Ctrl 1, bit 5 (“W/RB” in the schematics) controls
the mode: “1” for data collection, “0” for readback.
The PCIB communicates with the PC via the PC’s parallel
port. The address for the parallel port is found by reading the
PC’s BIOS memory. LPT1, parallel port 1’s address, is
located at hexadecimal address $40, $08 (segment, offset).
LPT2, parallel port 2’s address, is located at hexadecimal
address $40, $0A.
Collection
In the data collection mode, the PCIB stores data from the
DDC112 in the PCIB’s 32K x 24bit RAM. Twenty of the
bits are used to store the actual DDC112 data, bit 22 stores
the side A/B bit. The other three bits are unused. Upon
sensing a negative transition in DVALID from the DDC112,
the PCIB forces DXMIT LOW after a delay set by registers,
RDLY. Two groups of twenty DCLKs per DDC112 are used
to shift the DDC112’s Channel 1 and 2 data into a shift
register. Afterwards, the data is stored in the RAM using an
8-bit bus. The RAM memory pointer is automatically
incremented after all 24 bits are stored in the RAM. All the
REGISTERS
There are 12 registers in the Xilinx arrays that are used to
configure the Evaluation Fixture. The clock speeds, integration time, gain settings, etc., of the DDC112 are controlled
through these registers. Table I lists the address and gives a
short description for each of these registers.
Before the Evaluation Fixture can be used, the registers must
be initialized as they power-up with all bits LOW. For
proper initialization, power must be applied to the DUT
©
1998 Burr-Brown Corporation
AB-125
Printed in U.S.A. January, 1998
1
3
4
5
6
Readback
Unlike data collection, data readback is orchestrated by the
software, not the PCIB. Due to the limited number of I/Os
in the parallel port, the DDC112 data must be multiplexed;
the PCIB uses 4 bit nibbles during readback. The software
controls the multiplexing. The software also must reassemble the nibbles once they are in the PC’s memory.
(During data collection, the PCIB continues to generate
DXMIT and DCLK signals that load the DDC112 data into
the shift register. However, the data is prevented from being
stored in the RAM by tri-state buffers.) Lines 10 through 13
and Line 15 of the parallel port correspond to bits B6, B7,
B5, B4 and B3 in Figure 2, respectively. B4 - B7 are used
to read back 4-bit nibbles while B3 is used as a “busy bit”
to indicate that data from the DDC112 is available.
The upper 3 bits of the address space control the multiplexer
(the lower 4 bits are used to address the registers as previously described). The multiplexer is addressed the same as
a register, only there is no need to send a data word
afterwards. As shown in Table I, the RAM addresses use the
upper portion of the address space: 000xxxx through 110xxxx.
As was the case with the register addresses, it is recommended that the unused bits (the lower 4 bits this time) be
set to “1111”.
To read back from the RAM, begin by first decrementing the
RAM pointer by selecting address $6F and then toggling the
strobe bit, STO. After decrementing the RAM pointer, cycle
the multiplexer through all six 4 bit nibbles, retrieving and
recombining them along the way, by selecting addresses $0F
through $5F. Nibble 5 contains the side A/B bit. When the data
readback is complete, return bit 5 of register Ctrl 1 to HIGH to
allow new data collection from the DDC112 to fill the RAM.
RAM
Pointer
It’s interesting to note that the software doesn’t need to
know the actual value of the RAM pointer. The pointer is
adjusted relatively, either incrementing or decrementing
after each data point during data collection or readback. It is
important that enough time be given for the RAM to fill as
required before beginning the readback Otherwise, it’s possible that the data readback will be corrupted with old data.
EXAMPLE SOFTWARE
Example.pas shows a simple DOS program as an example of
how to communicate with the PCIB. This program is written
in Pascal for Borland’s Turbo Pascal. It is designed to
illustrate how to control and read back data from the PCIB.
As such, its functionality is very limited. The software
included with the Evaluation Fixture is more flexible and
more helpful in evaluating the performance of the DDC112.
Upon running the program, the user is prompted to enter the
number of data points to retrieve. The software allows time
for the PCIB to collect this data, then retrieves it from the
RAM over the parallel port and displays it on the screen. The
data is not scaled or offset and is displayed in decimal
notation.
The main procedure of the program is ReadData. It cycles
through the steps of decrementing the RAM pointer and
reading the six 4-bit nibbles and recombining them to form
the 20-bit data. The side A/B bit is checked the first time the
data is read. If the first point happens to be from side B, it
and all subsequent side B data is ignored until the first side
A data is found. Afterwards, the software knows that data
will alternate between sides A and B and doesn’t need to
continue checking the sign of the side A/B.
0
Side A/B Bit
0
0
DDC112 Data Bit 19 (MSB)
Figure 1 shows a donut-like structure that represents the
RAM’s memory map for a single DDC112 DUT board. It’s
shown circular in shape because the 15-bit RAM pointer is
allowed to roll over to 0 when reaching 32,767 while
incrementing (and likewise, roll over to 32,767 from 0 while
decrementing). As data is written to the RAM, the pointer is
incremented, or moves, clockwise in Figure 1. If enough
time is given during the data collection, the pointer will wrap
completely around and the oldest memory locations will
begin being overwritten with new data. This is not a problem, it’s just a result of the 32K data maximum. Once the
readback process starts, the RAM pointer is decremented
(moves counter-clockwise) to retrieve the most recent data
first. In other words, the memory is last-in, first-out.
•
•
1a d
ata
2a data
1b data
2b data
ta
1a da
ata
2a d
•
•
23
22
21
20
19
•
•
•
•
0
ta Readback
Da
Collection
Data
•
•
•
•
DDC112 Data Bit 0 (LSB)
signals, shifting, etc., necessary to store the data in the RAM
are generated by the PCIB; no action from the software is
required during data collection once bit 5 of the Ctrl 1
register is set HIGH.
•
FIGURE 1. RAM Memory Map for a Single DDC112 DUT Board.
2
NAME
ADDRESS
SHORT DESCRIPTION
DCLKRATE
01110000
Sets the speed of DCLK by dividing down the 20MHz crystal clock. For values less than 8, DCLK is:
DCLK = (20MHz)/(2N + 2), where N is the register value.
Example: If N = 1, then DCLK = 5MHz.
For N ≥ 8, DCLK equals the 20MHz crystal clock.
SCLKRATE
01110001
Sets the speed of SCLK by dividing down the 20MHz crystal clock. For values less than 8, SCLK is:
SCLK = (20MHz) / (2N+2), where N is the register value.
Example: If N = 0, then SCLK = 10MHz.
For N ≥ 8, SCLK equals the 20MHz crystal clock.
CONV: msb
mid2
mid1
Isb
01110010
01110011
01110010
01110101
Sets CONV period which in turn sets the Integration Time (TINT). A programmable counter running off
SCLK is used to generate an adjustable period 50% duty cycle CONV signal. TINT (CONV’s width) is:
(SCLK Period) (N + 1), where N are the register values.
Example: If N = 4999 and the SCLK = 10MHz then:
TINT = (1/10MHz) ( 4999 + 1) = 500µs.
To prevent glitches on CONV when changing the programmable counters, the clock to the counter
should be held until the counters are completely updated. This is accomplished using bit 0 in the CTRL2
register.
CTRL1
01110110
Bit
0
1
2
3
4
5
6
Name
G0
G1
G2
TEST_EN
Unused
W/RB
DCK_SOURCE
Description
Gain 0 (connected to DDC112 G0 input)
Gain 1 (connected to DDC112 G1 input)
Gain 2 (connected to DDC112 G2 input)
Test (connected to DDC112 TEST input)
Bit
0
1
2
3
4
5
6
Name
CONV_HOLD
CONV_LO
Unused
Unused
CONV_X
CONV_XSYNC
CONV_NEGSYNC
Description
Holds the CONV signal, used when changing TINT
Toggles sign of CONV
Registers
CTRL2
01110111
“1” write DDC112 data to RAM, “0” read RAM to PC
“1” external DCLK through BNC, “0” internal DCLK
“1” external CONV via the BNC on PCIB, “0” CONV generated on PCIB
“1” external CONV signal is sync’d to SCLK
“1” sync’d to neg edge, “0” CONV sync’d to pos edge of SCLK
RDLY: msb
IsB
01111000
01111001
Sets the readback delay; the delay between DVALID and DXMIT. That is, when the DDC112 signals
that data is ready by taking DVALID LOW, the PCIB responds by taking DXMIT LOW after a delay.
That delay is: (SCLK Period) • N, where N are the register values.
Example: If N = 100 and SCLK = 10MHz, then the readback delay = (1/10MHz) • 100 = 10µs.
NUM DDCS
01111010
Sets the number of DDC112s on DUT Board. The maximum value is 64.
TEST PULSES
01111011
Sets the number of test charge packets dumped into the DDC112's integrators while in test mode. This
is accomplished by pulsing the TEST line. If TEST is held HIGH, one packet is injected. If TEST is
toggled once, two packets are injected (refer to the DDC112 data sheet for a more detailed explanation
of how the test mode works).
The number of charge packets injected = N+2, where N is the register value.
To program one charge packet injection, set N = $7F.
Nibble 0
00001111
DDC112 data bits 3 to 0
Nibble 1
00011111
DDC112 data bits 7 to 4
Nibble 2
00101111
DDC112 data bits 11 to 8
Nibble 3
00111111
DDC112 data bits 15 to 12
Nibble 4
01001111
DDC112 data bits 19 to 16
Nibble 5
01011111
Data bits 23 to 20. Side A/B bit is bit 22: “1” side A, “0” side B.
Decrement Pointer
01101111
Decrements RAM pointer to next data word.
NOTE: For proper operation, the registers must be programmed with at least N = 1.
Readback Multiplexer
TABLE I. Register and RAM Addresses and Descriptions.
3
DDC112 TEST FIXTURE SOFTWARE
Written in Turbo Pascal 7.0
Listing I
(* This simple program is designed to illustrate basic communication
(* with the PC Interface Board.
(* Routines such as XilinxWrite can be used to create a more elaborate
(* software program.
(* Turbo Pascal can only allocate memory in 64K byte chunks. With
(* longint variables used to store DDC112 data, this limits the number
(* of data points that can be stored to 64K/4 = 16K. To retrieve the
(* full 32K of data points that can be stored on the PC Interface Board
(* you will need to create some sort of array structure to avoid the
(* 64K limit
(*
*)
*)
*)
*)
*)
*)
*)
*)
*)
*)
*)
(*
*)
program DDCExample;
uses Dos,CRT,Strings;
var
pPrintPort
PCPort
readdr, wraddr, strbaddr
pData
Nt
NumChan
DataCkCode
SysCkCode
IntCountCode
Ctrl1Code, Ctrl2Code
DXmitDelayCode
NumChanCode
TestPulseCode
:
:
:
:
:
:
:
:
:
:
:
:
:
^word;
string[4];
word;
^longint;
longint;
byte;
word;
word;
longint;
word;
word;
word;
word;
{***************************************************************************************}
procedure XilinxRefresh; {load all the registers on the PC Interface board}
{***************************************************************************************}
var
i : byte;
begin
for i := 1 to 2 do
begin
PORT[strbaddr] := 0;
Delay(1);
{initialize port strobe high}
Ctrl2Code := Ctrl2Code AND $7E; {hold CONV}
XilinxWrite(7, Ctrl2Code);
Delay(100);
XilinxWrite(0, DataCkCode);
XilinxWrite(1, SysCkCode);
XilinxWrite(2, ((IntCountCode SHR 21) AND $07));
XilinxWrite(3, ((IntCountCode SHR 14) AND $7F));
XilinxWrite(4, ((IntCountCode SHR 7) AND $7F));
XilinxWrite(5, ((IntCountCode AND $7F)));
XilinxWrite(6, (Ctrl1Code));
XilinxWrite(8, ((DXmitDelayCode AND $180) SHR 7));
XilinxWrite(9, ((DXmitDelayCode AND $7F)));
XilinxWrite(10, NumChanCode);
XilinxWrite(11, TestPulseCode);
Delay(100);
Ctrl2Code := Ctrl2Code OR $1;
XilinxWrite(7, Ctrl2Code);
end;
end;
{***************************************************************************************}
procedure InitializeLPT;
{***************************************************************************************}
begin
if PCPort = ‘LPT1’ then pPrintPort := Ptr($40,$08);
if PCPort = ‘LPT2’ then pPrintPort := Ptr($40,$0A);
wraddr := pPrintPort^; {parallel port WRITE address}
readdr := wraddr + 1; { “
“ READ
“ }
strbaddr := wraddr + 2; { “
“ STROBE “ }
Port[strbaddr] := 0;
{init strobe hi}
end;
{***************************************************************************************}
procedure XilinxWrite(XilinxAddr, XilinxData : Byte);
{writes to the register on the PC Interface Board}
{***************************************************************************************}
begin
PORT[wraddr] := $7F AND XilinxAddr;
Delay(2);
PORT[strbaddr] := 1;
Delay(1);
PORT[strbaddr] := 0;
Delay(1);
PORT[wraddr] := $80 OR XilinxData;
Delay(2);
PORT[strbaddr] := 1;
Delay(1);
PORT[strbaddr] := 0;
Delay(1);
end;
4
{release CONV}
(***************************************************************************************)
procedure getDataMem(Nsize: Word); {allocate memory for data storage}
{*************************************************************************************}
var
memget : word;
begin
memget := Nsize*sizeof(Longint);
if MaxAvail >= memget then getmem(pData, memget)
else
begin
writeln(‘Non-Recoverable Memory Shortage - Program Halt’);
halt;
end;
end;
{**************************************************************************************}
procedure freeDataMem(Nsize: Word);
{free data storage memory}
{**************************************************************************************}
var
memfree : word;
begin
memfree := Nsize*sizeof(longint);
freemem(pData,memfree);
end;
if FirstTime then {make sure 1st pt was from side A...}
begin
if SideRd = 0 then FirstTime := False {SideRd=0 —> side A; 1st pt ok}
else {1st pt side B, throw it away}
begin
FirstTime := False;
for j := 1 to (NumChan-1) do {read & throw away sideB data}
begin
PortDataRd := $6F; {decrement Xilinx RAM Memory Address}
PORT[wraddr] := PortDataRd;
PORT[strbaddr] := 1;
PORT[strbaddr] := 0;
PORT[strbaddr] := 1;
PORT[strbaddr] := 0;
for iRd := 1 to 6 do
{get 6 nibbles from RAM}
begin
PortDataRd := PortDataRd - $10; {MSB, MSB-1,...,LSB nibble}
PORT[wraddr] := PortDataRd;
PORT[strbaddr] := 1;
PORT[strbaddr] := 0;
k := 0;
{Wait For PC Interface Board Data Valid}
BusyBit3 := (PORT[readdr] AND $08) SHR 3; {init bit 3}
while (BusyBit3 <> 1) AND (K <= 20000) do
begin
BusyBit3 := (PORT[readdr] AND $08) SHR 3;
inc(k);
if (k mod 40) = 0 then delay(1);
if k = 20000 then
begin
XilinxWrite(6,Ctrl1Code OR $20); {enable write to RAM}
Exit;
{with readback error}
end;
end;
end;
end;
{***************************************************************************************}
procedure ReadData(var ReadErr: Boolean);
{
{ this procedure retrieves data from the PC Int. Bd. It checks to make sure
}
{ the 1st pt read back is from side A. If it’s not, it throws side B data
}
{ away and so that it starts with side A.
}
{**************************************************************************************}
var
Fnum, N
: longint;
BusyBit3
: integer; {data ready bit}
Nib, C, SideRd
: byte;
PortDataRd
: byte;
iRd, TRd, k, j
: word;
FirstTime
: boolean;
begin
FirstTime := true; {flag to enable check for side A or B on 1st data pt}
ReadErr := true;
XilinxWrite(6, Ctrl1Code AND $5F); {enable readback}
k := 0; {wait For PC Interface Board Data Valid...}
BusyBit3 := (PORT[readdr] AND $08) SHR 3; {init bit 3}
while (BusyBit3 <> 1) AND (K <= 20000) do
begin
BusyBit3 := (PORT[readdr] AND $08) SHR 3;
inc(k);
if (k mod 40) = 0 then delay(1);
if k = 20000 then
begin
XilinxWrite(6,Ctrl1Code OR $20); {enable write to RAM}
Exit;
{with readback error}
end;
end;
for N := Nt-1 downto 0 do
{retrieve most recent pts. first...}
begin
for C := 1 to NumChan do
begin
TRd := N + Nt*(C-1);
Fnum := 0;
PortDataRd := $6F;
{decrement Xilinx RAM Memory Address}
PORT[wraddr] := PortDataRd;
PORT[strbaddr] := 1;
PORT[strbaddr] := 0;
PORT[strbaddr] := 1;
PORT[strbaddr] := 0;
for iRd := 1 to 6 do
{get 6 nibbles from RAM}
begin
PortDataRd :PortDataRd - $10; {MSB, MSB-1,...,LSB nibble}
PORT[wraddr] := PortDataRd;
PORT[strbaddr] := 1;
PORT[strbaddr] := 0;
k := 0;
{wait For PC Interface Board Data Valid}
BusyBit3 := (PORT[readdr] AND $08) SHR 3; {init bit 3}
while (BusyBit3 <> 1) AND (K <= 20000) do
begin
BusyBit3 := (PORT[readdr] AND $08) SHR 3;
inc(k);
if (k mod 40) = 0 then delay(1);
if k = 20000 then
begin
XilinxWrite(6,Ctrl1Code OR $20); {enable write to RAM}
Exit;
{with readback error}
end;
end;
nib := ((PORT[readdr] XOR $80) AND $F0) SHR 4;
{XOR inverts bit 7 (-busy), AND F0 gets rid of 4 lower bits,
SHR puts the data bits in lower nibble}
if iRd = 1 then SideRd := ((nib AND $4) Xor $4) SHR 2; {bit3 lo—> sideA}
Fnum := Fnum SHL 4;
Fnum := Fnum OR nib; {add nibble to final number}
end;
Fnum := 0;
{reset and get new 1st data pt}
PortDataRd := $6F; {decrement Xilinx RAM Memory Address}
PORT[wraddr] := PortDataRd;
PORT[strbaddr] := 1;
PORT[strbaddr] := 0;
PORT[strbaddr] := 1;
PORT[strbaddr] := 0;
for iRd := 1 to 6 do
{get 6 nibbles}
begin
PortDataRd := PortDataRd - $10; {MSB, MSB-1,...,LSB nibble}
PORT[wraddr] := PortDataRd;
PORT[strbaddr] := 1;
PORT[strbaddr] := 0;
k := 0;
{wait For PC Interface Board Data Valid}
BusyBit3 := (PORT[readdr] AND $08) SHR 3; {init bit 3}
while (BusyBit3 <> 1) AND (K <= 20000) do
begin
BusyBit3 := (PORT[readdr] AND $08) SHR 3;
inc(k);
if (k mod 40) = 0 then delay(1);
if k = 20000 then
begin
XilinxWrite(6,Ctrl1Code OR $20); {enable write to RAM}
Exit;
{with readback error}
end;
end;
nib := ((PORT[readdr] XOR $80) AND $F0) SHR 4;
{XOR inverts bit 7 (-busy), AND F0 gets rid of 4 lower bits,
SHR puts the data bits in lower nibble}
Fnum := Fnum SHL 4;
Fnum := Fnum OR nib; {add nibble to final number}
end;
end;
end;
5
Fnum := (Fnum AND $000FFFFF); {set bits 31-21 := 0}
pData^ := Fnum;
dec(pData);
end;
end;
ReadErr := false;
{read was ok}
XilinxWrite(6,Ctrl1Code OR $20); {enable write to RAM}
end;
{**************************************************************************************}
{Main}
{***************************************************************************************}
var
Err : boolean;
N : longint;
C : byte;
begin
PCPort := ‘LPT1’;
InitializeLPT;
DataCkCode := 1; {DCLK = 20Mhz/(2*(DataCkCode+1)), if DataCkCode = 7x, DCLK=20Mhz}
SysCkCode := 0; {DCLK = 20Mhz/(2*(SysCkCode+1)), if SysCkCode = 7x, SCLK=20Mhz}
IntCountCode := 5999;
{Tint = (IntCountCode+1) * .1us}
Ctrl1Code := $25;
{gain=5, test off, write to RAM, int. DCLK}
Ctrl2Code := $01;
{initially hold conv}
DXmitDelayCode := 1;
{1 < DXmitDelayCode < 4095}
NumChanCode := 2; {NumChanCode = 2 * # of DDC112s (2 chan/part)}
NumChan := NumChanCode * 2; {“A” and “B” for each channel}
TestPulseCode := 0; {# of packets = TestPulseCode + 2; 127 for 1 packet}
XilinxRefresh;
writeln(chr(10),’Enter the number of points to retrieve from the DDC112 PC Interface Board’);
readln(Nt);
writeln(chr(10),’ Allowing data to fill RAM on Demo Board’,chr(10));
delay(round(IntCountCode/5000*(Nt+10)*1.1)); {give time for RAM to fill}
getDataMem(Nt*NumChan);
{allow extra for safety margin}
ReadData(Err);
if Err = True then
begin
writeln(‘Data Retrieval Error’);
writeln;
writeln(‘Make sure cables are connected,’);
writeln(‘and the power supply is on.’);
end
else
begin
for N := 1 to Nt do
begin
inc(pData);
write(‘Data Point ‘,N:3,’) ‘);
write(‘ 1A: ‘,pData^:7);
inc(pData);
write(‘ 2A: ‘,pData^:7);
inc(pData);
write(‘ 1B: ‘,pData^:7);
inc(pData);
write(‘ 2B: ‘,pData^:7);
writeln;
end;
end;
freeDataMem(Nt*NumChan);
end.
6
7
FIGURE 2. DDC112 Circuit Diagram of PC Interface.
P24
MCLK
P6
BNC
P75
STRB
P76
0
P77
1
MCLK
P78
2
DCK_SOURCE
BNC
SETDCLK
P79
3
P80
4
P81
5
P82
6
P58
GND
DDCCKC
P44
SETSCLK
I_BUS
P83
SETSCLK
CONV
Bit_7
STRB
G1
BIT_7
G0
SCLK
SETDCLK
DCLK
BNC
DCK_SOURCE
P30
CONV
P63
G1
P62
G0
P59
G2
P60
CONV_HOLD
P35
TEST
P56
RDLY_LSB
P37
RDLY_MSB
P38
NUM_DDCS
P39
W/RB
P40
CONV _LO
P41
SCLK
P47
DCLK
P48
DECMEM
P42
READ_LSB
P49
READ_MID
P50
READ_MSB
P51
G2
I_BUS<0: 6>
I_BUS
CONV_HOLD
DDCDIN
READADD2
TEST
READADD1
RDLY_LSB
READADD0
RDLY_MSB
NUM_DDCS
W/RB
SCLK
DCLK
STRB
READADD0
Bit 6
READADD1
P84
READADD2
CONV_LO
W/RB
P2
Bit 7
P3
Bit 5
DECMEM
READ_D2
READ_LSB
READ_D3
READ_D1
DDCODC
READ_D0
P4
READ_MSB
RAM_DE
READ_DV
Bit 4
READ_MID
DV
Bit 3
DIN_BUS
P5
DIN BUS<0: 7>
P14
7
P15
6
P16
5
P17
4
P18
3
Dedicated Pins
Do Not Change
P34
0
P19
P21
0
P52
RAM_OE
HDC
+5
1
DV
GND
2
P20
P46
Input P45 Not Used
P36
LDC
FIGURE 3. DDC112 PC Interface Xilinx Setup PROM U5.
8
RAM BYTE SELECT AND ADDRESS CONTROL
READADD1
READADD2
A0
00
A1
01
D2-4
READ_LSB
READ_MID
02
READ_MSB
03
D
FD
C
STRB
Q
DECMEM
NIB SELECT OF RAM BYTE
DIN_BUS
HX257
0
4
1
5
2
6
3
7
READADD0
(MSNIB/LSNIB)
2
3
5
6
11
10
14
13
1
15
A1
B1
A2
B2
A3
B3
A4
B4
AB
GB
Y1
Y2
Y3
Y4
4
READ_D0
7
READ_D1
9
READ_D2
12
READ_D3
GND
UXX
PC READBACK DATA VALID GENERATOR
STRB
RAM_OE
(READ_EN)
+5
DATA VALID SETUP DELAY
D
DV
C
AND
Q
FDRD
AND
D
C
FDRD
D
C
FD
Q D
C
FD
Q
AND
D
C
RD
W/RB
Q
Block READ_DV
Unless DV Transitions
During Data Write
Operation.
DCLK
FIGURE 4. DDC112 Setup PROM U5, Output Data Control (DDCODC).
9
FDRD
RD
RD
Q
READ_DV
C
FD
OR
FD
Q
Q
AND
D1
D0
1
0
D5
D4
D3
D2
D1
D0
5
4
3
2
1
0
D5
D4
D3
D2
D1
D0
5
4
3
2
1
0
D5
D4
D3
D2
D1
D0
5
4
3
2
1
0
SCLK
C
D6
6
C
D6
6
C
D6
6
C
D2
2
D3
D4
D5
D6
MSB
MID2
MID1
LSB
READADD0
+5
D3
Q3
TC
C
CE
Q1
Q0
D2
D3
UD
PE
C
CE
Q5
Q4
Q3
Q2
Q1
Q0
ACLK
Q0
Q1
Q2
GND
D3
Q4
CE
RD
TC
Q3
Q2
Q1
C
PE
Q0
TC
Q3
Q2
Q1
Q0
TC
Q3
Q2
Q1
D3
C16BUDRD
RD
C16BUDRD
RD
C16BUDRD
UD
D2
D1
D0
CE
C
PE
UD
Q5
Q3
D2
Q6
D1
D0
D1
Q6
Q0
Q2
D0
Q1
RD
Q0
C16BUDRD
D3
PE
D2
UD
Q2
TC
Q3
Q2
Q1
Q0
Q3
Q5
RD
C16BUDRD
Q4
D1
Q6
D0
C
CE
Q1
Q0
Q2
PE
D2
UD
Q4
D1
RD
TC
CE
D0
Q3
Q1
Q2
Q0
C16BUDRD
C
D3
PE
UD
D2
D1
D0
Q5
PLATCH7
Q3
RDLY_MSB 00
CONV GENERATOR
CTRL_2 07
Q6
Q0
Q1
Q2
INV
REGISTER SELECT
GND
C
D
FD
INV
INV
BNC
C
D
FD
CONV_NEGSYNC
SCLK
07
FIGURE 5. DDC112 Setup PROM U5, Data In Subsection (DDCDIN).
SLCK
SLCK
C
CONV
D
D
CONV_HOLD
Wait Until CONV
is HIGH Before
Stopping CONV Gen
I BUS
NOR
D0
0
STRB
D1
1
C
D2
2
READADD1
SETDCLK 00
READADD2
Q3
A0
SETSCLK 01
Q4
A1
CONV_MSB 02
Q5
Q
Q
CONV_XSYNC
CONV_LO
C
D
FD
D5
D4
D3
D2
D1
D0
5
4
3
2
1
0
Q
C
D6
6
CONTROL
REGISTER 1
Q0
Q1
Q2
INV
0
+5
G0
G1
G2
C
D
C
D
RD
FDRD
RD
FDRD
Q
Q
D1
D0
1
0
D4
D3
D2
D1
4
3
2
1
OR
Q
CONV
C
D0
D5
5
0
D6
6
C
D2
2
D4
D3
D5
4
3
5
Q3
TEST_EN
W/RB
Q5
Q4
D6
6
DCK_SOURCE
Q6
CONV_X
PLATCH7
Q6
E1
74-138
D3
E3
CTRL_1 06
D4
A2
CONV_MID2 03
3
E2
CONV_LSB 05
CONV_MID1 04
4
AND
A0
RDLY_LSB 01
D5
A1
NUM_DDCS 02
D6
E2
05
5
E1
74-138
04
E3
06
6
A2
TST_PULSES 03
DATA/ADD
FD
TEST
PULSES
D
C
GND
CONV_X
INV
CONV_XSYNC
Q4
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q0
Q1
Q2
Q1
Q3
TC
Q2
C
CE
PE
RD
Q0
TC
Q3
D3
C16BUDRD
RD
Q2
Q1
Q0
UD
D2
D1
D0
CE
C
PE
UD
D3
D2
D1
C16BUDRD
TC
D0
Q3
RD
C
CE
Q1
Q2
Q0
D3
PE
UD
D2
D1
C16BUDRD
TC
CE
D0
Q3
C
RD
Q1
Q2
Q0
C16BUDRD
D3
PE
UD
D2
D1
D0
AND
AND
All 1's Hold Test HIGH
CONV_HOLD
CONV_HOLD
CONV_LO
CONV_NEGSYNC
Q5
Q3
Q6
+5
CONTROL
REGISTER 2
PLATCH7
PLATCH7
Bit 7
PLATCH7
PLATCH7
PLATCH7
PLATCH7
10
AND
INV
OR
C
D
TEST_EN
AND
FD
Q
TEST
I_BUS
D_CLK RATE CONTROL
AND
6
5
4
3
2
1
0
SETDCLK
MCLK
Q6
D6
Q5
D5
Q4
D4
Q3
D3
D2 PLATCH7 Q2
Q1
D1
Q0
D0
C
CE
C
D0
D1
D2
Q0
D3
UD C16BUDRD Q1
Q2
PE
Q3
C
TC
CE
CCLK
Q
FDC
D
INV
AND
RD
INV
OR
+5
GND
DCLK
DCK_SOURCE
BNC
AND
S_CLK RATE CONTROL
AND
6
5
4
3
2
1
0
SETSCLK
Q6
D6
Q5
D5
Q4
D4
Q3
D3
D2 PLATCH7 Q2
Q1
D1
Q0
D0
C
SCLK
CE
C
Q
FDC
D0
D1
D2
Q0
D3
UD C16BUDRD Q1
Q2
PE
Q3
C
TC
CE
D
INV
RD
GND
+5
FIGURE 6. DDC112 Setup PROM U5, Clock Control Subsection (DDCCKC).
11
READ_MSB
RAM_WE
P66
P6
I_BUS<0: 6>
W/RB
DECMEM
RAM_WE
READ_MSB
READ_MID
READ_LSB
DDCMEM
CE_MSB
CE_MID
CE_LSB
CONV_HOLD
CONV_LO
NUM_DDCS
RDLY_MSB
RDLY_LSB
I_BUS
P9
P8
CE_LSB
CE_MID
CE_MSB
P53
P7
P10
RAM_OE
DOUT_BUS<0:7>
DDCCDC
DCLK
ADD_BUS<0:14>
CS1
CS1
RAM_OE
DXo
CS0
CS0
GND
L_DATAo
DXo
L_DATAo
Input P48 Not Used
Input P11 Not Used
Input P46 Not Used
Input P61 Not Used
FIGURE 7. DDC112 PC Interface Xilinx Setup PROM U6.
READ_MID
DCLK
P69
P67
SCLK
P70
READ_LSB
NUM_DDCS
P77
P68
CONV_LO
P75
DECMEM
CONV_HOLD
P81
W/RB
6
P5
P78
5
P4
P76
4
P3
RDLY_LSB
3
P2
P79
2
P84
RDLY_MSB
1
P83
P80
0
P82
DCLK
ADD BUS
SCLK
DOUT_BUS
12
INV
SDATA
DCLKOUT
DX
DV
P52
P49
P50
SDATA
DX
+5
10
P59
P51
DV
11
P58
P63
12
P57
GND
0
1
2
3
4
5
6
7
8
9
13
P62
DCLKOUT
GND
14
P60
A00
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
P36
P34
Dedicated Pins
Do Not Change
P14
P15
P16
P17
P18
P19
P20
P21
P23
P24
P25
P26
P27
P28
P29
LDC
HDC
0
1
2
3
4
5
6
7
when Control Bit is "1".
I/O Buffers are Tri-State
P35
P37
P38
P39
P40
P41
P44
P45
13
RD
FDRD
Q
INV
AND
NOR
NOR
Block W/RB Status Change
While Transmitting Data From
DDCLK or Writing Data Into
RAM.
C
D
AND
RAMCLK1
NOR
C
D
C
D
C
D
C
D
Q
RD
U9
FDRD
RD
U4
FDRD
Q
Q
RD
Q
CNT_U/DB
NAND
RD
U6
FDRD
WRITE MID
C
D
OUTPUT BYTE SELECT
U5
FDRD
Q
WRITE LSBYTE
C
D
RD
FDRD
RAMCLK2
C
D
NOR
Q
FD
RD
FDRD
NOR
FIGURE 8. DDC112 Setup PROM U6, Memory Control (DDCMEM).
W/RB
DCLK
Delay WR_DONE 1/2
DCLK Cycle to Ensure
MEMCLK Pulse.
DX o
L_DATAo
0
+5
Q
RD
U7
FDRD
Q
C
D
RAM_OE
RAM_WE
WRITE MSBYTE
C
D
CS0
CS1
FD
Q
GND
DECMEM
READ_LSB
READ_MID
READ_MSB
WR_DONE
2
3
5
6
11
10
14
13
1
15
Y4B
Y3B
Y2B
Y1B
U01
A1
B1
A2
B2
A3
B3
A4
B4
AB
GB
HX158
12
9
7
4
RAM CHIP SELECT
INV
RAM FUNCTION SELECT
CE_LSB
CE_MID
CE_MSB
+5
MEMCLK
GND
RD
D0
D1
D2
Q0
D3
UD C16BUDRD Q1
Q2
PE
Q3
C
TC
CE
RD
D0
D1
D2
Q0
D3
UD C16BUDRD Q1
Q2
PE
Q3
C
TC
CE
RD
D0
D1
D2
Q0
D3
UD C16BUDRD Q1
Q2
PE
Q3
C
TC
CE
RD
D0
D1
D2
Q0
D3
UD C16BUDRD Q1
Q2
PE
Q3
C
TC
CE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ADD_BUS<0: 14>
MEMORY ADDRESS COUNTER
INV
RD
FDRD
INV
Q
Q6
D6
Q5
D5
Q4
D4
Q3
D3
D2 PLATCH7 Q2
Q1
D1
Q0
D0
C
SIDE B "0"
SIDE INDICATOR BIT
SIDE A "1"
INV
C
D
6
5
4
3
2
1
0
4
3
2
1
0
RD
Q6
D6
Q5
D5
Q4
D4
Q3
D3
D2 PLATCH7 Q2
Q1
D1
Q0
D0
C
INV SCLK
INV
LDV
GND
SCLK
+5
RD
MIDDLE
DLY_TC
READ DELAY
COUNTER
D0
D1
D2
Q0
D3
UD C16BUDRD Q1
Q2
PE
Q3
C
TC
CE
RD
D0
D1
D2
Q0
D3
UD C16BUDRD Q1
Q2
PE
Q3
C
TC
CE
RD
D0
D1
D2
Q0
D3
UD C16BUDRD Q1
Q2
PE
Q3
C
TC
CE
SCLK C
D
OR
FIGURE 9. DDC112 Setpup PROM U6, Collect Data Control (DDCCDC).
DOUT_BUS
CS1
CS0
CONV_LO
CONV_HOLD
DV
I_BUS
RDLY_LSB
RDLY_MSB
END_DATA
SCLK
GND
Q
D
FDRD
RD8
C
LDV
Side
D
C
S1
S0
D2
D1
D0
0
M3-1
7
S1
S0
D2
D1
D0
0
M3-1
0
M3-1
6
RS4
Q3
Q2
Q1
Q0
C
D7
D6
D5
D4
D3
D2
D1
D0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
D20
D19
D18
D17
D16
S1
S0
D2
D1
D0
5
AND
S1
S0
D2
D1
D0
0
RD8
0
M3-1
3
M3-1
4
RS8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
C
D7
D6
D5
D4
D3
D2
D1
D0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
D15
D14
D13
D12
D11
D10
D9
D8
S1
S0
D2
D1
D0
RD
FDRD
LSB
DXo
OR
SDATA
DCLK
INV
END_DATA
DCLK
Q
C
D
0
RS8
OR
2
M3-1
S1
S0
D2
D1
D0
RD8
C
D
Q
SDCK
ACQUIRE DATA ON
DCLK FALLING EDGE
RD
FDRD
DX
+5
INV
DCLK
GND
DX
INV
OR
DV
0
M3-1
S1
S0
D2
D1
D0
1
D
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
C
D7
D6
D5
D4
D3
D2
D1
D0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
D7
D6
D5
D4
D3
D2
D1
D0
S1
S0
D2
D1
D0
0
M3-1
0
14
D
FTP
Q
AND
+5
DCLKOUT
RD
D0
D1
D2
Q0
D3
UD C16BUDRD Q1
Q2
PE
Q3
C
TC
CE
C
T
PE
AND
20-BIT
COUNTER
DCLK
C
D
C
D
RD
FD
DCLK
Q6
D6
Q5
D5
Q4
D4
Q3
D3
D2 PLATCH7 Q2
Q1
D1
Q0
D0
C
NUM_DDCS
6
5
4
3
2
1
0
NUMBER OF DDC
CHANNELS COUNTER
BC_TC
DCLK
Q
C
D
GND
FDRD
D
C
FDRD
FD
AND
Q
RD
Q
DCLK
DDC_TC
END_DATA
L_DATAo
D0
D1
D2
Q0
D3
UD C16BUDRD Q1
Q2
PE
Q3
C
TC
CE
RD
D0
D1
D2
Q0
D3
UD C16BUDRD Q1
Q2
PE
Q3
C
TC
CE
Q