ETC ACS8526

ACS8526 LC/P LITE
Line Card Protection Switch for PDH,
SONET or SDH Systems
ADVANCED COMMUNICATIONS
COMMUNICATION
Description
FINAL
Features
The ACS8526 is a highly integrated single-chip solution
for protection switching between two SECs (SDH/SONET
Equipment Clocks) from Master and Slave SETS clock
cards, for line cards in a PDH, SONET or SDH Network
Element. The ACS8526 has fast activity monitors on the
inputs and will raise a flag on a pin if there is a loss of
activity on the currently selected input. The protection
switching between the input reference clock sources is
controlled by an external pin.
The ACS8526 has two SEC reference clock input ports,
configured for expected frequency by setting hardware
pins or by writing to registers via the serial interface.
The ACS8526 can perform frequency translation,
converting, for example, an 8 kHz SEC input clock from a
backplane into a 155.52 MHz clock for local line cards.
The ACS8526 generates two independent SEC clock
outputs, one on a PECL/LVDS port and one on a
TTL/CMOS port, at spot frequencies configured by
hardware pins, or by writing to registers via the serial
interface. The hardware selectable spot frequencies
range from 1.544 MHz up to 155.52 MHz, with further
options for N x E1/DS1 and 311.04 MHz via register
selection. The ACS8526 also provides an 8 kHz Frame
Sync output and 2 kHz Multi-Frame Sync output, both with
programmable pulse width and polarity.
Advanced configuration possibilities are available via the
serial port (which can be SPI compatible), however the
basic configuration of I/O frequencies and SONET/SDH
selection by hardware make the device suitable for
standalone operation, i.e., no need for a microprocessor.
Block Diagram
Figure 1
‹ Line card protection switch - partners Semtech SETS
devices for Stratum 3E/3/4E/4 PDH, SONET/SDH
applications
‹ High performance DPLL/APLL solution
‹ Output jitter compliant to STM-1
‹ Two independent SEC inputs ports (TTL)
‹ Four independent output ports:
‹ Two clock ports: one PECL/LVDS, one TTL
‹ Two Syncs (TTL): 8 kHz FrSync & 2 KHz MFrSync
‹ TTL I/O ports: spot frequencies 2 kHz to 77.76 MHz
‹ PECL/LVDS port: spot frequencies 2 kHz to 311 MHz
‹ N x E1/DS1 mode
‹ Programmable pulse width and polarity on Syncs
‹ SONET/SDH frequency translation
‹ Digital Holdover mode on input failure
‹ Separate activity monitors and register alarms on
each input.
‹ “Loss of activity” on selected input flagged on
dedicated pin
‹ Source switch under external hardware control
‹ PLL “Locked” and “Acquisition” bandwidth selectable
from 18, 35 or 70 Hz
‹ Configurable via serial interface or hardware pins
‹ Output clock phase continuity to GR-1244-CORE[13]
‹ Single 3.3 V operation, 5 V I/O compatible
‹ IEEE 1149.1 JTAG Boundary Scan is supported
‹ Operating temperature (ambient) of -40 to +85 °C
‹ Available in LQFP 64 package
Block Diagram of the ACS8526 LC/P LITE
LOS_ALARM
IP_FREQ
SONSDHB
MUX
2
2 x SEC TTL inputs
SEC1
SEC Inputs:
Programmable
Frequencies
N x 8 kHz
SEC2
1.544 MHz
2.048 MHz
6.48 MHz
19.44 MHz
SRCSW
25.92 MHz
38.88 MHz
TCK
51.84 MHz
TDI
77.76 MHz
TMS
TRST
TDO
Input
SEC Port
Selector
APLL2
Digital Feedback
E1/DS1
Synthesis
APLL3
IEEE
1149.1
JTAG
SEC Outputs:
01 (LVDS/PECL)
DPLL2
DPLL1
Chip
Clock
Generator
TCXO or
XO
Revision 3.00/January 2003 © Semtech Corp.
Priority Register Set
Table
F8526D_001BLOCKDIA_03
Page 1
MUX
1
Output
Port
Frequency
Selection
02 (TTL)
Sync Outputs:
MFrSync 2 kHz (TTL)
APLL 1
FrSync 8 kHz (TTL)
SPI Compatible
Serial Interface
Port
OP_FREQ1
OP_FREQ2
Output Frequencies/MHz
01 Output:
02 Output:
19.44
1.544
25.92
2.048
34.368 (E3) 3.088
38.88
19.44
44.736 (DS3) 25.92
51.84
34.368 (E3)
77.76
38.88
155.52
44.736 (DS3)
51.84
77.76
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Table of Contents
ADVANCED COMMUNICATION
Table of Contents
ACS8526 LC/P LITE
FINAL
Section
Page
Description ................................................................................................................................................................................................. 1
Block Diagram............................................................................................................................................................................................ 1
Features ..................................................................................................................................................................................................... 1
Table of Contents ...................................................................................................................................................................................... 2
Pin Diagram ............................................................................................................................................................................................... 3
Pin Description........................................................................................................................................................................................... 4
Introduction................................................................................................................................................................................................ 6
General Description................................................................................................................................................................................... 6
Inputs ..................................................................................................................................................................................................6
Preconfiguring Inputs - Expected Input Frequency ................................................................................................................ 7
Preconfiguring Inputs- SONET/SDH ........................................................................................................................................ 7
Input Locking Frequency Modes ............................................................................................................................................. 7
Selection of Input SECs .....................................................................................................................................................................8
Initialization .............................................................................................................................................................................. 8
SEC Selection - SRCSW pin...................................................................................................................................................... 8
Output Clock Phase Continuity on Source Switchover .......................................................................................................... 8
Activity Monitors.................................................................................................................................................................................9
SEC Activity Monitors ............................................................................................................................................................... 9
Fast Activity Monitor.............................................................................................................................................................. 10
Phase Locked Loops (PLLs) ........................................................................................................................................................... 10
PLL Overview ......................................................................................................................................................................... 10
PLL Architecture .................................................................................................................................................................... 11
PLL Operational Controls ...................................................................................................................................................... 14
DPLL Feature Summary ........................................................................................................................................................ 16
Outputs ............................................................................................................................................................................................ 17
Output Frequency Selection by Hardware ........................................................................................................................... 17
Output Frequency Selection by Register Programming...................................................................................................... 17
Local Oscillator Clock...................................................................................................................................................................... 27
Crystal Frequency Calibration............................................................................................................................................... 27
Power-On Reset............................................................................................................................................................................... 27
Status Reporting ............................................................................................................................................................................. 27
Loss of Input Signal - LOS Flag............................................................................................................................................. 27
Status Information ................................................................................................................................................................ 27
Serial Interface................................................................................................................................................................................ 27
Register Map........................................................................................................................................................................................... 30
Register Organisation ..................................................................................................................................................................... 30
Multi-word Registers ............................................................................................................................................................. 30
Register Access ..................................................................................................................................................................... 30
Flags ....................................................................................................................................................................................... 30
Defaults.................................................................................................................................................................................. 30
Register Descriptions ............................................................................................................................................................................. 32
Electrical Specifications ......................................................................................................................................................................... 61
JTAG ................................................................................................................................................................................................. 61
Over-voltage Protection .................................................................................................................................................................. 61
Maximum Ratings ........................................................................................................................................................................... 62
Operating Conditions ...................................................................................................................................................................... 62
Jitter Performance .......................................................................................................................................................................... 65
Input/Output Timing ....................................................................................................................................................................... 67
Package Information .............................................................................................................................................................................. 68
Thermal Conditions......................................................................................................................................................................... 69
Application Information .......................................................................................................................................................................... 70
References .............................................................................................................................................................................................. 71
Abbreviations .......................................................................................................................................................................................... 71
Notes ....................................................................................................................................................................................................... 72
Trademark Acknowledgements ............................................................................................................................................................. 72
Revision Status/History ......................................................................................................................................................................... 73
Ordering Information .............................................................................................................................................................................. 74
Disclaimers...................................................................................................................................................................................... 74
Contacts........................................................................................................................................................................................... 74
Revision 3.00/January 2003 © Semtech Corp.
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ACS8526 LC/P LITE
ADVANCED COMMUNICATION
Pin Diagram
ACS8526 Pin Diagram
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
SONSDHB
O1_FREQ2
IC9
IC8
IC7
NC2
AGND4
VA3+
O2
NC1
VDD3
DGND6
SDO
TDI
TDO
TCK
Figure 2
FINAL
AGND1
IC1
AGND2
VA1+
LOS_ALARM
REFCLK
DGND1
VD1+
VD2+
DGND2
DGND3
VD3+
SRCSW
VA2+
AGND3
IC2
ACS8526
LC/P LITE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PORB
SCLK
O1_FREQ1
O1_FREQ0
CSB
SDI
CLKE
TMS
DGND5
VDD2
O2_FREQ1
TRST
O2_FREQ2
O2_FREQ0
IP_FREQ2
IP_FREQ1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
FrSync
MFrSync
O1POS
O1NEG
GND_DIFF
VDD_DIFF
IC3
IC4
IC5
IC6
VDD5V
IP_FREQ0
SEC1
SEC2
DGND4
VDD1
1
2
3
4
5
6
7
8
9
10
11
1
12
13
14
15
16
F8526D_002PINDIAG_01
Revision 3.00/January 2003 © Semtech Corp.
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ACS8526 LC/P LITE
ADVANCED COMMUNICATION
Pin Description
FINAL
Table 1 Power Pins
Pin Number
Symbol
I/O
Type
Description
8, 9,
12
VD1+, VD2+,
VD3+
P
-
Supply Voltage: Digital supply to gates in analog section, +3.3 Volts ± 10%.
22
VDD_DIFF
P
-
Supply Voltage: Digital supply for differential output pins 19 and 20, +3.3 Volts
± 10%.
27
VDD5V
P
-
Digital Supply for +5 Volts tolerance to input pins. Connect to +5 Volts (± 10%)
for clamping to +5 Volts. Connect to VDD for clamping to +3.3 Volts. Leave
floating for no clamping, input pins tolerant up to +5.5 Volts.
32, 39,
54
VDD1, VDD2,
VDD3,
P
-
Supply Voltage: Digital supply to logic, +3.3 Volts ± 10%.
4
VA1+
P
-
Supply Voltage: Analog supply to clock multiplying PLL, +3.3 Volts ± 10%.
14, 57
VA2+, VA3+
P
-
Supply Voltage: Analog supply to output PLLs APLL2 and APLL1, +3.3 Volts
± 10%.
15, 58
AGND3, AGND4
-
Supply Ground: Analog ground for output PLLs APLL2 and APLL1.
7, 10,
11
DGND1, DGND2,
DGND3
P
-
Supply Ground: Digital ground for components in PLLs.
31, 40,
53
DGND4, DGND5,
DGND6
P
-
Supply Ground: Digital ground for logic.
21
GND_DIFF
P
-
Supply Ground: Digital ground for differential output pins 19 and 20.
1, 3
AGND1, AGND2
P
-
Supply Ground: Analog grounds.
Note...I = Input, O = Output, P = Power, TTLU = TTL input with pull-up resistor, TTLD = TTL input with pull-down resistor.
Table 2 Internally Connected
Pin Number
Symbol
I/O
Type
Description
2, 16, 23, 24,
25, 26, 60,
61, 62
IC1, IC2, IC3, IC4,
IC5, IC6, IC7,
IC8 IC9
-
-
Internally Connected: Leave to float.
55, 59
NC1, NC2
-
-
Not Connected: Leave to float.
I/O
Type
Table 3 Other Pins
Pin Number
Symbol
Description
5
LOS_ALARM
O
TTL/CMOS
6
REFCLK
I
TTL
Reference Clock: 12.800 MHz (refer to section headed Local Oscillator Clock).
13
SRCSW
I
TTLD
Source Switching: Controls switchover between SEC1 and SEC2 inputs as the
selected reference. SRCSW must be held High on power-up or reset, and for a
further 251 ms after PORB has gone High. See ‘‘Initialization’’ on page 8.
17
FrSync
O
TTL/CMOS
Revision 3.00/January 2003 © Semtech Corp.
LOS_Alarm: Flag to indicate loss of activity of currently selected reference
source.
Output Reference: 8 kHz Frame Sync output.
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ACS8526 LC/P LITE
ADVANCED COMMUNICATION
FINAL
Table 3 Other Pins (cont...)
Pin Number
Symbol
I/O
Type
Description
18
MFrSync
O
TTL/CMOS
Output Reference: 2 kHz Multi-Frame Sync output.
19,
20
O1POS,
O1NEG
O
LVDS/PECL
Output Reference 1: Differential output., default LVDS.
28
IP_FREQ0
I
TTL
Input Reference Frequency Select: Frequency select for input SEC1 and SEC2.
29
SEC1
I
TTLD
Input Reference 1: Primary input.
30
SEC2
I
TTLD
Input Reference 2: Secondary input.
33
IP_FREQ1
I
TTL
Input Reference Frequency Select: Frequency select for input SEC1 and SEC2.
34
IP_FREQ2
I
TTL
Input Reference Frequency Select: Frequency select for input SEC1 and SEC2.
35
O2_FREQ0
I
TTL
Output O2 Frequency Select: Frequency select for output O2.
36
O2_FREQ2
I
TTL
Output O2 Frequency Select: Frequency select for output O2.
37
TRST
I
TTLD
JTAG Control Reset Input: TRST = 1 to enable JTAG Boundary Scan mode.
TRST = 0 for normal device operation (JTAG logic transparent). NC if not used.
38
O2_FREQ1
I
TTL
Output O2 Frequency Select: Frequency select for output O2.
41
TMS
I
TTLU
JTAG Test Mode Select: Boundary Scan enable. Sampled on rising edge of TCK.
NC if not used.
42
CLKE
I
TTLD
SCLK Edge Select: SCLK active edge select, CLKE = 1, selects falling edge of
SCLK to be active.
43
SDI
I
TTLD
Interface Address: SPI compatible Serial Data Input.
44
CSB
I
TTLU
Chip Select (Active Low): This pin is asserted Low by the external device
(microprocessor) to enable the Serial interface.
45
O1_FREQ0
I
TTL
Output O1 Frequency Select: Frequency select for output O1.
46
O1_FREQ1
I
TTL
Output O1 Frequency Select: Frequency select for output O1.
47
SCLK
I
TTLD
Serial Data Clock: The Low to High transition on this input latches the data on the
SDI input into the internal registers. The active clock edge (defined by CLKE)
latches the data out of the internal registers onto the SDO output.
48
PORB
I
TTLU
Power-On Reset: Master reset. If PORB is forced Low, all internal states are reset
back to default values.
49
TCK
I
TTLD
JTAG Clock: Boundary Scan clock input.
50
TDO
O
TTL/CMOS
U
JTAG Output: Serial test data output. Updated on falling edge of TCK.
51
TDI
I
TTL
JTAG Input: Serial test data Input. Sampled on rising edge of TCK. NC if not used.
52
SDO
O
TTLD
Interface Address: SPI compatible Serial Data Output.
56
O2
O
TTL/CMOS
Output Reference: Programmable, default 19.44 MHz.
63
O1_FREQ2
I
TTL
Output O1 Frequency Select: Frequency select for output O1.
64
SONSDHB
I
TTLD
SONET or SDH frequency select: Sets the initial power up state (or state after a
PORB) of the SONET/SDH frequency selection registers, Reg. 34, Bit 2 and
Reg. 38, Bit 5, Bit 6 and Reg. 64 Bit 4. The register states can be changed after
power up by software.
Revision 3.00/January 2003 © Semtech Corp.
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ACS8526 LC/P LITE
ADVANCED COMMUNICATION
Introduction
FINAL
The ACS8526 is a highly integrated, single-chip solution
for protection switching of two SEC inputs from, for
example, Master and Slave SETS clock cards sources, for
Line Cards in a SONET or SDH Network Element. The
ACS8526 has fast activity monitors on the SEC clock
inputs.
The ACS8526 can be used as a standalone part without
the serial interface where all input and output frequencies
are set by external control using the IP_FREQ and
OP_FREQ pins. These pins determine the default
power-up or reset state of internal registers, that in turn
determine the I/O frequencies.
If more detailed control is required, then the registers
within the device can be re-configured, after an
initialization period, by writes through the serial interface.
The SRCSW pin is used to select one of the two SEC inputs
to lock to. The SRCSW pin must remain High for at least
251 ms following power-up or reset (251 ms after the
PORB signal has gone High). SRCSW Low following a
power-up or reset is not supported.
The ACS8526 has two SEC inputs from which it can
generate independent clocks on outputs 01 and 02 with
a total of 53 possible output frequencies. In addition,
there are two Sync outputs; 8 kHz Frame Synchronization
(FrSync) signal and a 2 kHz Multi-Frame Synchronization
(MFrSync) signal.
APLL bandwidth is set four orders of magnitude higher
than the DPLL bandwidth. This ensures that the overall
system performance still maintains the advantage of
consistent behaviour provided by the digital approach.
The DPLLs are clocked by the external oscillator module
(TCXO or XO) so that prior to initial lock (with no input
reference) or in Digital Holdover, the frequency stability is
only determined by the stability of the external oscillator
module. This gives the key advantage of confining all
temperature critical components to one well defined and
pre-calibrated oscillator module, whose performance can
be chosen to match the application. All performance
parameters of the DPLLs are programmable without the
need to understand detailed PLL equations. Bandwidth,
damping factor and lock range can all be configured
under software control.
The hardware set-up configures a subset of the registers
in the register block, with the remainder adopting their
default settings. If hardware set-up alone is insufficient
for configuring, controlling and monitoring the device for a
particular application, then access to the full set of
registers for these purposes is provided by an SPI
compatible serial interface port.
Each register (8-bit wide data field) is identified by and
referred to by its hexadecimal address and name, e.g.
Reg. 7D cnfg_LOS_alarm. The ‘‘Register Map’’ on
page 30 summarizes the content of all of the registers,
and each register is individually described in the
subsequent Register Tables, organised in order of
ascending Address (hexadecimal), in the “Register
Descriptions” from page 32 onwards.
Initially the ACS8526 generates a stable, low-noise clock
signal at a frequency to the same accuracy as the external
oscillator, or it can be made more accurate via software
calibration to within ± 0.02 ppm. The device always
attempts to lock to one of its inputs (according to the
value on the SRCSW pin). Once locked to a reference the
accuracy of the output clock is determined directly by the
accuracy of the input reference. In the absence of any
input references the device simply maintains its most
recent frequency in a Digital Holdover mode. However, as
soon as the DPLL detects an input presence, it will
attempt to lock to it and will not “qualify” it first. As soon
as the DPLL detects a failure on the input, the DPLL
freezes its operating frequency and raises the LOS alarm
on device pin LOS_ALARM.
Inputs
The overall PLL loop bandwidth, damping, pull-in range
and frequency accuracy are all determined by digital
parameters that provide a consistent level of
performance. An Analog PLL (APLL) takes the signal from
the DPLL output and provides a lower jitter output. The
The ACS8526 SETS device has two TTL/CMOS compatible
SEC input ports. They are 3 V and 5 V compatible (with
clamping if required by connecting the VDD5V pin). Refer
to the ‘‘Electrical Specifications’’ on page 61 for more
information on electrical compatibility.
Revision 3.00/January 2003 © Semtech Corp.
An Evaluation board and intuitive GUI-based software
package is available for device introduction. This has its
own documentation “ACS8526-EVB”.
General Description
The following description refers to the Block Diagram
(Figure 1 on page 1).
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ACS8526 LC/P LITE
ADVANCED COMMUNICATION
FINAL
Input frequencies supported range from 2 kHz to
155.52 MHz. Common E1, DS1, OC-3 and sub-divisions
are supported as spot frequencies that the DPLLs will
directly lock to. Any input frequency, up to 100 MHz, that
is a multiple of 8 kHz can also be locked to via an inbuilt
programmable divider.
In addition to the SEC inputs, there are four configuration
pins IP_FREQ [2:0] and SONSDHB used to configure the
input to expect a particular input frequency (same value
applies to both inputs), and a control pin SRCSW for
switching between SEC1 and SEC2 as the selected input
reference to which the device tries to lock.
inputs will be configured to expect the same input frequency.
After a reset and initialization period, any change of state on
IP_FREQ [2:0] or SONSDHB will have no effect on the device
configuration, as these are only read during the reset period.
The register programming approach provides a greater
range of frequencies than the hardware selection
method: more spot frequencies, plus frequencies derived
using DivN Mode up to 100 MHz (TTL technology limit).
Table 4 Hardware Configuration for Selecting Expected
Input Frequency on SEC1 and SEC2
IP_FREQ Pins
Preconfiguring Inputs - Expected Input Frequency
The inputs SEC1 and SEC2 must be preconfigured to
expect a particular input frequency.
The expected input frequencies can be selected from a
range of spot frequencies by either:
z
Hardware selection: configuring the hardware pins
IP_FREQ [2:0] and SONSDHB, which are read on reset
z
Register programming: writing to the
cnfg_ref_source_frequency and cnfg_input_mode
registers.
Hardware Selection of Expected I/P Frequency
The combined pin states of IP_FREQ [2:0] and SONSDHB
represent a 4-bit word which addresses a particular
frequency value as given in Table 4.
The frequency selected by the hardware configuration is
always applied to both inputs on Power-up or Reset, so
both will be preconfigured to expect the same frequency.
If SEC1 and SEC2 are required to expect different
frequencies, then these inputs must be subsequently
reconfigured by programming the appropriate registers.
2
1
0
0
0
0
0
0
1
0
1
0
SONSDHB
Pin
Input frequency
X
8 kHz
0
2.048 MHz
1
1.544 MHz
0
X
6.48 MHz
1
1
X
19.44 MHz
1
0
0
X
25.92 MHz
1
0
1
X
38.88 MHz
1
1
0
X
51.84 MHz
1
1
1
X
77.76 MHz
Preconfiguring Inputs- SONET/SDH
The register ip_sonsdhb is used to select SDH or SONET
mode for the entire device and its setting affects
parameters other than just the expected input frequency
selection, e.g. output frequency. To set the device for use
in a SONET network, set ip_sonsdhb = 1. For SDH, set
ip_sonsdhb = 0.
Input Locking Frequency Modes
Register Programming of Expected I/P Frequency
The expected input frequencies can be programmed by
writing to the cnfg_ref_source_frequency registers
(Reg. 22 and 23) and ip_sonsdhb (Bit 2 of
cnfg_input_mode,Reg. 34), via the serial interface. This
must not be done until after the end of the initialization
period (see ‘‘Initialization’’ on page 8).
Each input port has to be configured to receive the
expected input frequency. To achieve this, three input
locking frequency modes are provided: Direct Lock,
Lock8K and DivN.
Note...Any subsequent reset will cause these registers to be
overwritten by values that equate to the single hardware
selected frequency on the pins at the time of reset, i.e both
In Direct Lock mode, DPLL1 can lock to the selected input
at the spot frequency of the input, for example 19.44 MHz
performs the DPLL phase comparisons at 19.44 MHz.
Revision 3.00/January 2003 © Semtech Corp.
Direct Lock Mode
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FINAL
(b) To lock to 10.000 MHz:
In Lock8K and DivN modes an internal divider is used
prior to DPLL1 to divide the input frequency before it is
used for phase comparisons.
(i)
Lock8K Mode
Lock8K mode automatically sets the divider parameters
to divide the input frequency down to 8 kHz. Lock8K can
only be used on the supported spot frequencies. See
divn_SEC1 and 2 descriptions (Bit 7 of Reg. 22 and 23,
cnfg_ref_source_frequency). Lock8k mode is enabled by
setting the Lock8k bit (Bit 6) in the appropriate
cnfg_ref_source_frequency register. Using lower
frequencies for phase comparisons in the DPLL results in
a greater tolerance to input jitter. It is possible to choose
which edge of the input reference clock to lock to, by
setting 8K Edge Polarity, (Bit 2 of Reg. 03, test_register1).
DivN Mode
In DivN mode, the divider parameters are set manually by
configuration (Bit 7 of the cnfg_ref_source_frequency
register), but must be set so that the frequency after
division is exactly 8 kHz.
The DivN function is defined as:
DivN = “Divide by N+ 1”, i.e. it is the dividing factor used
for the division of the input frequency, and has a value of
(N+1) where N is an integer from 1 to 12499 inclusive.
Therefore, in DivN mode the input frequency can be
divided by any integer value between 2 to 12499.
Consequently, any input frequency which is a multiple of
8 kHz, between 8 kHz to 125 MHz, can be supported by
using DivN mode.
Note...Both reference inputs can be set to use DivN
independently of the frequency and configuration of the other
input. However only one value of N is allowed, so if both inputs
have DivN selected, they must be running at the same
frequency.
DivN Examples
(a) To lock to 2.000 MHz:
(i)
Set the cnfg_ref_source_frequency register to
10XX0000 (binary) to enable DivN, and set the
frequency to 8 kHz - the frequency required after
division. (XX = “Leaky Bucket” ID for this input).
(ii) To achieve 8 kHz, the 2 MHz input must be
divided by 250. So, if DivN = 250 = (N + 1)
then N must be set to 249. This is done by writing
F9 hex (249 decimal) to the DivN register pair
Reg. 46/47.
Revision 3.00/January 2003 © Semtech Corp.
The cnfg_ref_source_frequency register is set to
10XX0000 (binary) to set the DivN and the
frequency to 8 kHz, the post-division frequency.
(XX = “Leaky Bucket” ID for this input).
(ii) To achieve 8 kHz, the 10 MHz input must be
divided by 1,250. So, if DivN, = 250 = (N+1)
then N must be set to 1,249. This is done by
writing 4E1 hex (1,249 decimal) to the DivN
register pair Reg. 46/47.
Selection of Input SECs
Initialization
Switching between inputs SEC1 and SEC2 is triggered
directly from a dedicated pin (SRCSW), though for the
device to operate properly, the device must first be
initialized by holding the pin High during reset and for at
least a further 251 ms after PORB has gone High (250 ms
allowance for the internal reset to be removed plus 1 ms
allowance for APLLs to start-up and become stable). A
simple external circuit to set SCRSW high for the required
period is shown in the ‘‘Simplified Application Schematic’’
on page 70. If SCRSW is held Low at any time during the
251 ms initialization period, this will result in incorrect
device operation.
SEC Selection - SRCSW pin
After the ACS8526 has been initialized (see previous
“Initialization” section), then the value of SRCSW pin
directly selects either SEC1 (SRCSW High) or SEC2
(SRCSW Low). The default frequency tolerance of SEC1
and SEC2 is ± 80 ppm (Reg. 41 and Reg. 42) with respect
to the local (calibrated) oscillator clock. These registers
can be subsequently set by external software, if required.
After initialization, the output clocks are stable and the
device will operate as a simple switch, with the DPLL
trying to lock on to the selected reference source.
Output Clock Phase Continuity on Source
Switchover
A phase offset between SEC inputs will be seen as a
phase shift on the output on source switchover equal to
the input phase offset. (Note...The ACS8526 has no
Phase Build-out function to accommodate this. If this
function is required, it is available on the AS8525 LC/P
device).
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The rate of change of phase on the output, during the time
between input switchover and the output settling to a
steady state, is dependent on factors of: input frequency,
input phase change, DPLL bandwidth, DPLL frequency
limit, and phase detector capture range. The ACS8526
always complies with GR-1244-CORE[13] spec for Stratum
3 (max rate of phase change of 81 ns/1.326 ms), for
input frequencies at 6.48 MHz or higher, with the default
1UI phase detector capture range.
For inputs at a lower frequency than 6.48 MHz (e.g. 8 kHz)
with the DPLL frequency limit set to greater than ± 30
ppm (note default is ± 80 ppm), then to ensure
compliance with GR-1244-CORE[13] at DPLL bandwidth
settings of 18, 35 or 70 Hz, the input phase difference
between the Master and Slave inputs to the line card PLL
should be limited to less than 600, 330 ns or 190 ns
respectively. Alternatively, the DPLL frequency range
should be set < ± 30 ppm. A well designed system would
have Master and Slave clock from the clock sync cards
aligned to within a few nanoseconds. In which case a
complete system using the Semtech SETS clock card
parts (ACS8530, ACS8520 or ACS8510) and this line card
part would be fully compliant to GR-1244-CORE[13]
specifications under all conditions due to the lower
frequency range and bandwidth set at the clock card end.
Activity Monitors
Two types of Activity monitors are incorporated in the
ACS8526:
z
SEC Activity Monitors, which raise flags in Reg. 11,
sts_reference_sources for each SEC in event of no
input activity, as defined by the configuration of Leaky
Bucket accumulator.
z
Fast Activity Monitor (part of DPLL), which raises LOS
alarm on pin LOS_ALARM in event of 2 missing cycles
of input activity on the selected source.
SEC Activity Monitors
There is a SEC activity monitor assigned to each SEC
input. Each has a programmable Leaky Bucket
Accumulator which is used to determine at what point the
period of inactivity is deemed sufficient to raise or clear an
alarm. Each SEC has its own no activity alarm bit in
Reg. 11, sts_reference_sources,. The monitors operate
continuously such that at all times the activity status of
each SEC input is known.
Leaky Bucket Accumulator
Anomalies detected by the Activity Monitor are integrated
in a Leaky Bucket Accumulator. There is one Leaky Bucket
Revision 3.00/January 2003 © Semtech Corp.
Accumulator per SEC input. The accumulators share a set
of configuration parameters which can be programmed
via Reg. 50 to Reg. 53. They are:
z
Bucket size
z
Alarm trigger (set threshold)
z
Alarm clear (reset threshold)
z
Leak rate (decay rate)
There are occasional anomalies that do not cause the
Accumulator to cross the alarm setting threshold, but if
the Bucket fills faster than it leaks it will eventually cross
the alarm setting threshold and the associated SEC Input
Activity Alarm bit in Reg. 11, sts_reference_sources, will
change to 1 (Alarm active).
Each Leaky Bucket Accumulator is a digital circuit which
mimics the operation of an analog integrator. If several
events occur close together, each event adds to the
amplitude and the alarm will be triggered quickly; if events
occur over a greater time period but still sufficiently close
together to overcome the decay, the alarm will be
triggered eventually. If events occur at a rate which is not
sufficient to overcome the decay, the alarm will not be
triggered. Similarly, if no defect events occur for a
sufficient time, the amplitude will decay gradually and the
alarm will be cleared when the amplitude falls below the
alarm clearing threshold. The ability to decay the
amplitude over time allows the importance of defect
events to be reduced as time passes by. This means that,
in the case of isolated events, the alarm will not be set,
whereas, once the alarm becomes set, it will be held on
until normal operation has persisted for a suitable time
(but if the operation is still erratic, the alarm will remain
set). Figure 3 illustrates the behavior of the Leaky Bucket
Accumulator.
Each SEC input is monitored over a 128 ms period. If,
within a 128 ms period, an irregularity occurs that is not
deemed to be due to allowable jitter/wander, then the
Accumulator is incremented.
The Accumulator continues to increment up to the point
that it reaches the programmed Bucket size. The “fill rate”
of the Leaky Bucket is, therefore, 8 units/second. The
“leak rate” of the Leaky Bucket is programmable to be in
multiples of the fill rate (x 1, x 0.5, x 0.25 and x 0.125) to
give a programmable leak rate from 8 units/sec down to
1 unit/sec. A conflict between trying to “leak” at the same
time as a “fill” is avoided by preventing a leak when a fill
event occurs.
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Figure 3
FINAL
Inactivity and Irregularity Monitoring
Inactivities/Irregularities
Reference
Source
bucket_size
Leaky
Bucket
Response
upper_threshold
lower_threshold
Programmable Fall Slopes
(all programmable)
Alarm
F8530D_026Inact_Irreg_Mon_02
Leaky Bucket Timing
The time taken (in seconds) to raise an inactivity alarm on
an SEC that has previously been fully active (Leaky Bucket
empty) will be:
(cnfg_upper_threshold) / 8
If an input is intermittently inactive then this time can be
longer. The default setting of cnfg_upper_threshold is 6,
therefore the default time is 0.75 s.
The time taken (in seconds) to cancel the activity alarm on
a previously completely inactive SEC is calculated, for a
particular Leaky Bucket, as:
[2
(a)
x (b - c)]/ 8
where:
a = cnfg_decay_rate
b = cnfg_bucket_size
c = cnfg_lower_threshold
The default setting is shown in the following:
1
[2 x (8 - 4)] /8 = 1.0 secs
With the DPLL in Digital Holdover mode it is isolated from
further disturbances. If the input becomes active again
then the DPLL will continue to lock to the input, with little
disturbance.
Phase Locked Loops (PLLs)
This section is in four parts;
z
Overview description of the PLLs
z
Architectural description, introducing the sub-blocks
and their interconnection options for different
frequency selection and jitter filtering
z
Description of PLL controls- phase error detector
options, Loop bandwidth and damping selection
z
DPLL summary feature list.
PLL Overview
Fast Activity Monitor
Anomalies on the selected clock have to be detected as
they occur and the PLL must be temporarily isolated until
the clock is once again pure. The SEC activity monitor
cannot be used for this because the high degree of
accuracy required dictates that the process be slow. To
achieve the immediacy required, the PLL uses an
alternative mechanism. The phase locked loop itself
Revision 3.00/January 2003 © Semtech Corp.
contains an additional fast activity monitor such that
within approximately two missing input clock cycles, a
no-activity flag is raised and the DPLL is frozen in Digital
Holdover mode. This flag generates LOS (Loss of Signal)
alarm on pin LOS_ALARM.
The PLL circuitry comprises the following blocks shown in
Figure 1: Two Digital PLLs (DPLL1 and DPLL2), two output
multiplying and filtering Analog PLLs (APLL1 and APLL2),
output frequency dividers in an Output Port Frequency
Selection block, a synthesis block, multiplexers MUX1 and
MUX2, and a feedback Analog PLL (APLL3).
These functional blocks, and their interconnections, are
highly configurable, via register control, which provides a
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FINAL
range of output frequencies and levels of jitter
performance. However if the device is configured by
hardware alone, then the PLLs are configured as shown in
Table 7 and 8.
Digital Synthesis is used to generate all required
SONET/SDH output frequencies. The digital logic
operates at 204.8 MHz that is multiplied up from the
external 12.800 MHz oscillator module. Hence the best
resolution of the output signals from the DPLLs is one
204.8 MHz cycle or 4.9 ns.
Additional resolution and lower final output jitter is
provided by a de-jittering APLL that reduces the
4.9 ns pk-pk jitter from the digital down to 500 ps pk-pk
and 60 ps RMS as typical final outputs measured
broadband (from 10 Hz to 1 GHz). This arrangement
combines the advantages of the flexibility and
repeatability of a DPLL with the low jitter of an APLL.
The DPLLs in the ACS8526 are programmable for
parameters of bandwidth (18, 35 and 70 Hz) and
damping factor (from 1.2 to 20). See Sections ‘‘DPLL1
Jitter Transfer Characteristic, (Freq. = 1.544 MHz, Jitter =
0.2 UI pk-pk, Damping Factor = 5)’’ on page 14, and
‘‘Damping Factor Programmability’’ on page 15.
DPLL1 input frequency is programmable with 12 common
SONET/SDH spot frequencies. See
cnfg_nominal_frequency Reg. 3C and Reg. 3D
The DPLL has programmable frequency acceptance and
output range (from 0 to 80 ppm) set by the allowable
offset between the expected input frequency and the
calibrated external frequency, Reg. 41 and Reg. 42).
There is no requirement to understand the loop filter
equations or detailed gain parameters since all high level
factors such as overall bandwidth can be set directly in
registers via the microprocessor interface. No external
critical components are required for either the internal
DPLLs or APLLs, providing another key advantage over
traditional discrete designs.
DPLL1 always produces an output at 77.76 MHz to feed
the APLL, regardless of the frequency selected at the
output pins or the locking frequency (frequency at the
input of the Phase and Frequency Detector- PFD).
Revision 3.00/January 2003 © Semtech Corp.
DPLL2 can be operated at a number of frequencies. This
is to enable the generation of extra output frequencies,
which cannot be easily related to 77.76 MHz. If DPLL2 is
enabled, it locks to the 8 kHz from DPLL1. This is because
all of the frequencies of operation of DPLL2 can be
divided to 8 kHz and this will ensure synchronization of
frequencies, from 8kHz upwards, within the two DPLLs.
Both of the DPLLs’ outputs can be connected to
multiplying and filtering APLLs. The outputs of these
APLLs are divided making a number of frequencies
simultaneously available for selection at the output clock
ports. The various combinations of DPLL, APLL and divider
configurations allow for generation of a comprehensive
set of frequencies, as listed in Table 9, “Output Frequency
Selection,” on page 19.
A function is provided to synchronise the lower output
frequencies when DPLL1 is locked to a high frequency
reference input. The dividers that generate the 2 kHz and
8 kHz outputs are reset such that the output 2/8 kHz
clocks are lined up with the input 2 kHz.
The PLL configurations required for particular output
frequencies are described in ‘‘Output Frequency
Selection by Hardware’’ on page 17, and ‘‘Output
Frequency Selection by Register Programming’’ on
page 17.
An advanced feature of the device is its ability to control
the amount of jitter and wander that is tolerated on the
input. This is achieved by the configuration of the Phase
and Frequency detectors within the DPLLs, which
determines the phase error input to the Digital Loop Filter.
For basic operation, the configuration should not be
changed from the default settings.
PLL Architecture
Figure 4 shows the PLL arrangement in more detail. Each
DPLL comprises a generic Phase and Frequency Detector
(PFD) with a Digital Loop filter, together with Forward,
Feedback, and Low Frequency (LF) (DPLL1 only) Digital
Frequency Synthesis (DFS) blocks. The Forward DFS block
represents a Digital Timed Oscillator (DTO).
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Figure 4
FINAL
PLL Block Diagram
sts_current_phase
DPLL2_frequency
DPLL1_freq_to_APLL2
DPLL2
0
Forward
DFS
PFD and
Loop Filter
8 kHz
MUX
2
DPLL2_dig_
feedback
APLL2
APLL2
Output
Dividers
01 and 02
APLL1
APLL1
Output
Dividers
01 and 02
1
1
Feedback
DFS
0
8 kHz
DPLL1_frequency
0
DPLL1
1
DPLL1
Reference
Input
PFD and
Loop Filter
LF
Output
DFS
0
sts_current_phase
MUX
X
1
1
FrSync
MFrSync
O1 and O2
DPLL1_frequency
77M
Forward
DFS
APLL3
1
Locking
Frequency
Feedback
DFS
0
Analog
F8526D_017BLOCKDIA_01
The DPLL architecture for DPLL1 is more complex than
that of DPLL2. See “DPLL Feature Summary” on page 16.
The selected SEC input is always supplied to DPLL1.
DPLL1 may use either digital feedback or analog
feedback (via APLL3).
DPLL2 always takes its feed from DPLL1 and cannot be
used to select a different input to that of DPLL1.
DFS is a technique for generating an output frequency
using a higher frequency system clock (204.8 MHz in the
case of the 77.76 MHz synthesis). However, the edges of
the output clock are not ideally placed in time, since all
edges of the output clock will be aligned to the active edge
of the system clock. This means that the generated clock
will inherently have jitter on it equivalent to one period of
the system clock.
DPLL1 and APLLs
DPLL1 always produces 77.76 MHz. The input reference
is either passed directly to the PFD or via a pre-divider (not
shown) to produce the reference input. The feedback
77.76 MHz is either divided or synthesized to generate
the locking frequency.
The DPLL1 77M Forward DFS block uses DFS clocked by
the 204.8 MHz system clock to synthesize the 77.76 MHz
Revision 3.00/January 2003 © Semtech Corp.
and, therefore, has an inherent 4.9 ns of pk-pk jitter.
There is an option to use a feedback APLL (APLL3) to filter
out this jitter before the 77.76 MHz is used to generate
the feedback locking frequency in the DPLL1 feedback
DFS block. This analog feedback option allows a lower
jitter (<1 ns) feedback signal to give maximum
performance.
The 77.76 MHz is fed to DPLL1 LF Output DFS block and
to APLL1. The low frequency DPLL1 LF Output DFS block
is used to produce three frequencies; two of them,
Digital1 and Digital2, are available for selection to be
produced at outputs O1 and O2, and the third frequency
can produce multiple E1/DS1 rates via the filtering APLLs.
The input clock to the DPLL1 LF Output DFS block is
77.76 MHz from APLL1 (post jitter filtering) or 77.76 MHz
direct from the DPLL1 77M Forward DFS. Utilizing the
clock from APLL1 will result in lower jitter outputs from the
DPLL1 LF Output DFS block.
However, when the input to the APLL1 is taken from the
DPLL1 LF Output DFS block, the input to that block comes
directly from the DPLL1 77M Forward DFS block so that a
“loop” is not created.
APLL1 is for multiplying and filtering. The input to APLL1 is
controlled by MUX 1 (see ‘‘Multiplexers’’ on page 13). The
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frequency from APLL1 is four times its input frequency i.e.
311.04 MHz when used with a 77.76 MHz input. APLL1 is
subsequently divided by 1, 2, 4, 6, 8, 12, 16 and 48 and
these are available at the O1 and O2 Outputs.
DPLL2 & APLLs
DPLL2 is simpler than DPLL1. DPLL2 offers no low
frequency output. The DPLL2 input can only be used to
lock to DPLL1. Unlike DPLL1, the DPLL2 Forward DFS
block does not always generate 77.76 MHz. The possible
frequencies are listed in Table 12, “APLL2 Frequencies,”
on page 24. Similarly to DPLL1, the output of the DPLL2
Forward DFS block is generated using DFS clocked by the
204.8 MHz system clock and will have an inherent jitter of
4.9 ns.
The DPLL2 feedback DFS also has the facility to be able
to use the post APLL2 (jitter-filtered) clock to generate the
feedback locking frequency. Again, this will give the
maximum performance by using a low jitter feedback.
FrSync, MFrSync, 2 kHz and 8 kHz Clock Outputs
Whilst the FrSync and MFrSync Outputs are always
supplied from DPLL1, the 2 kHz and 8 kHz options
available from the O1 and O2 Outputs can be supplied
from either DPLL1 or DPLL2 (Reg. 7A Bit 7).
Multiplexers
Multiplexers MUX1 and MUX2 are used to select the
appropriate inputs to the Analog PLLs. The function they
represent is controlled by cnfg_DPLL1_frequency
Reg. 65.
APLL1 Input Selection using MUX 1
z
DPLL1 77M Forward DFS block (77.76 MHz) with
analog feedback (no synthesis) selected for input to
APLL1 (Reg. 65 Bit [2:0]) set to 000
z
DPLL1 77M Forward DFS block (77.76 MHz) with
digital feedback (no synthesis) selected for input to
APLL1 (Reg. 65 Bit [2:0]) set to 001
z
DPLL1 LF Output DFS block selected for input to
APLL1
APLL2 block is also for multiplying and filtering. The input
to APLL2 is controlled by MUX 2 (see ‘‘Multiplexers’’ on
page 13) and can come either from the DPLL2 Forward
DFS block or from DPLL1.
The frequency generated from the APLL2 is four times its
input frequency i.e. 311.04 MHz when used with a
77.76 MHz input. APLL2 is subsequently divided by 2, 4,
8, 12, 16, 48 and 64 and these are available at the O1
and 02 Outputs.
“Digital” Frequencies
DFS is also carried out by DPLL1 LF Output DFS block in
Figure 4 (E1/DS1 Synthesis block in Figure 1). This block
is clocked either by the DPLL1 77M Forward DFS block or
via the APLL1, and generates the single frequencies
Digital1 and Digital2 (see Table 13 and Table 14). The
input clock frequency of the DFS is always 77.76 MHz and
as such has a period of approximately 12 ns. The jitter
generated on the Digital outputs is relatively high,
because they do not pass through an APLL for jitter
filtering. The minimum level of jitter is when DPLL1 is in
analog feedback mode, when the pk-pk jitter will be
approximately 13 ns (equivalent to a period of the DFS
clock). The maximum jitter is generated when in digital
feedback mode, when the total is approximately 18 ns.
The E1/DS1 Synthesis block generates the E1/DS1 rates
for the APLLs, using the output from DPLL1. It generates
12E1, 16E1, 16DS1 or 24DS1, for selection by MUX1.
Revision 3.00/January 2003 © Semtech Corp.
•
•
•
•
12E1 (Reg. 65 Bit [2:0] set to 010)
16E1 (Reg. 65 Bit [2:0] set to 011)
24DS1 (Reg. 65 Bit [2:0] set to 100)
16DS1 (Reg. 65 Bit [2:0] set to 101).
APLL2 Input Selection using MUX 2
z
DPLL2 Forward DFS block selected for input to APLL2
(Reg. 65 Bit 6 = 1). The input frequency is selected
from the operating frequency of DPLL2 (Reg. 64 Bits
[2:0]) i.e 12E1, 24DS1, 16E1, 16DS1, E3, DS3, OC-N
z
DPLL1 + Synthesis selected for input to APLL2
•
•
•
•
12E1 (Reg. 65 Bit 6 = 0 and Bit [5:4] set to 00)
16E1 (Reg. 65 Bit 6 = 0 and Bit [5:4] set to 01)
24DS1 (Reg. 65 Bit 6 = 0 and Bit [5:4] set to 10)
16DS1 (Reg. 65 Bit 6 = 0 and Bit [5:4] set to 11).
Notes: (i) DPLL2 output cannot be selected for input to APLL1
(ii) If both multiplexers select digital synthesis, the
same frequency value must be selected in Reg. 65
Bit [2:0] and Reg. 65 Bit [5:4].
APLLs
There are three main APLLs. APLL1 and APLL2 provide a
lower final output jitter reducing the 4.9 ns pk-pk jitter
from the digital down to 500 ps pk-pk and 60 ps RMS as
typical final outputs measured broadband (from 10 Hz to
1 GHz). The feedback APLL (APLL3) is selected by default;
it provides improved performance over the digital
feedback.
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APLL Output Dividers
PLL Operational Controls
Each APLL has its own divider. Each divider
simultaneously outputs a series of fixed ratios of its APLL
input. Any of these divided outputs may be selected as the
output on Outputs O1 or O2 by configuring Reg. 61 and
Reg. 62, with the following exceptions: (APLL1)/2 and
(APLL1)/1 only available for Output 01 (differential port),
and (APLL1)/48 only available for Output 02.
The main factors controlling the operation of the PLL are:
PFD and Loop Filters
The PFD compares the input reference with that of the
locking frequency (feedback) giving a phase error which is
then filtered by a 100Hz low pass filter, to give the
average phase error for input into a loop filter. The PFD is
quite complex and has several programmable options to
determine what phase error value is fed to the loop (See
“Phase and Frequency Detectors” on page 15”)
depending on the type of jitter/wander expected.
The loop filter bandwidth and damping is programmable
to optimize the locking time/ability to track the input. See
“DPLL1 Jitter Transfer Characteristic, (Freq. = 1.544 MHz,
Jitter = 0.2 UI pk-pk, Damping Factor = 5)” on page 14
and “Damping Factor Programmability” on page 15.
Figure 5
1. Input reference and feedback frequency selection See “PLL Architecture” on page 11, and ‘‘Input
Locking Frequency Modes’’ on page 7.
2. Loop Bandwidth and Damping factor of the DPLLs these determine how fast the device can to lock to the
selected input, or how tightly it can track the input.
3. PFD settings - these affect the input phase error to the
Loop filter and relate to jitter and wander tolerance See “Phase/Frequency/Lock Detection” on page 15.
DPLL1 initially tries to lock to the input frequency of the
selected input SEC. By default, it uses a wide “acquisition”
bandwidth setting until it has achieved frequency lock,
then DPLL1 switches to using a narrower “Locked”
bandwidth setting as it locks to the phase of the input.
Input Acquisition Bandwidth
DPLL1 has programmable acquisition bandwidth of 18,
35 or 70 Hz. The default is set to 70 Hz.
DPLL1 Jitter Transfer Characteristic, (Freq. = 1.544 MHz, Jitter = 0.2 UI pk-pk, Damping Factor = 5)
Revision 3.00/January 2003 © Semtech Corp.
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Input Locked Bandwidth
Phase/Frequency/Lock Detection
The ACS8526 has programmable “Locked” bandwidth of
18, 35 or 70 Hz. These bandwidth settings correspond to
the -3 dB jitter attenuation point on the ACS8526’s jitter
transfer characteristic shown in Figure 5.
Two main types of detector are available in the ACS8526:
The DPLL damping factor is set by default to provide a
maximum wander gain peak of around 0.1 dB. Many of
the specifications (e.g. GR-1244-CORE [13], G.812[7] and
G.813[8]) specify a wander transfer gain of less than
0.2 dB. GR-253[11] specifies jitter (not wander) transfer of
less than 0.1 dB. To accommodate the required levels of
transfer gain, the ACS8526 provides a choice of damping
factors, with more choice given as the bandwidth setting
increases into the frequency regions classified as jitter.
Table 5 shows which damping factors are available for
selection at the different bandwidth settings, and the
corresponding jitter transfer approximate gain peak.
Table 5 Available Damping Factors for different DPLL
Bandwidths, and Associated Gain Peak Values
18
35
70
Damping
Factor selected
Gain Peak/dB
1
1.2
0.4
2
2.5
0.2
3, 4, 5
5
0.1
1
1.2
0.4
2
2.5
0.2
3
5
0.1
4, 5
10
0.06
1
1.2
0.4
2
2.5
0.2
3
5
0.1
4
10
0.06
5
20
0.03
Revision 3.00/January 2003 © Semtech Corp.
z
Phase Loss/Lock detectors.
There are two multi-phase and frequency detectors, one
for each DPLL. The multi-phase and frequency detectors
are used to compare input and feedback clocks. They
operate at input frequencies up to 77.76 MHz
(155.52 MHz is internally divided down to 77.76 MHz).
Damping Factor Programmability
Reg. 6B [2:0]
Phase and frequency detectors, and
Phase and Frequency Detectors
If the ACS8526 is used with only DPLL1, the highest
bandwidth setting is recommended to ensure the best
tracking of the input SEC. If DPLL2 is also to be used,
DPLL1 should be set to a lower bandwidth setting than
DPLL2. The lowest bandwidth setting will provide the
highest jitter attenuation, although this is not the main
function of the ACS8526 device.
Bandwidth/Hz
z
A common arrangement however is to use Lock8k mode
(See Bit 6 of Reg. 22 and 23), where all input frequencies
are divided down to 8 kHz internally. Marginally better
MTIE figures may be possible in direct lock mode due to
more regular phase updates. This direct locking capability
is one of the unique features of the ACS8526.
A multi-phase detector (patent pending) approach is used
in order to give an infinitesimally small input phase
resolution combined with large jitter tolerance. A
multi-phase detector comprises the following phase
detectors:
z
Phase and frequency detector (± 360°, or ± 180°
range).
z
An Early/Late phase detector for fine resolution.
z
A multi-cycle phase detector for large input jitter
tolerance (up to 8191 UI), which captures and
remembers phase differences of many cycles
between input and feedback clocks.
The phase detectors can be configured to be immune to
occasional missing input clock pulses by using nearest
edge detection (± 180°capture) or the normal
± 360° phase capture range which gives frequency
locking. The device will automatically switch to nearest
edge locking when it has detected that phase lock has
been achieved. It is possible to disable the selection of
nearest edge locking via Reg. 03 Bit 6 (set to 1). In this
setting, frequency locking will always be enabled.
The balance between the first two types of phase detector
employed can be adjusted via Reg. 6A, 6C and 6D. The
default settings should be sufficient for all modes.
Adjustment of these settings affects only small signal
overshoot and bandwidth.
The multi-cycle phase detector (wide-range) is enabled via
Reg. 74, Bit 6 set to 1 and the range is set in exponentially
increasing steps from ± 1 UI up to 8191 UI via Reg. 74,
Bits [3:0].
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When this detector is enabled it keeps a track of the
correct phase position over many cycles of phase
difference to give excellent jitter tolerance. This provides
an alternative to switching to Lock8k mode as a method
of achieving high jitter tolerance.
DPLL Feature Summary
z
Multiple E1 and DS1 outputs supported
An additional control (Reg. 74 Bit 5) enables the
multi-phase detector value to be used in the final phase
value as part of the DPLL loop. When enabled by setting
High, the multi cycle phase value will be used in the loop
and gives faster pull-in (but more overshoot). The
characteristics of the loop will be similar to Lock8k mode
where again large input phase differences contribute to
the loop dynamics. Setting the bit Low only uses a max
figure of 360° in the loop and will give slower pull-in but
gives less overshoot. The final phase position that the
loop has to pull in to is still tracked and remembered by
the multi-cycle phase detector in either case.
z
Low jitter MFrSync (2 kHz) and FrSync (8 kHz) outputs
z
Multiple phase loss and multiple phase detectors (see
“DPLL1 Advanced Features”)
z
Direct PLL locking to common SONET/SDH input
frequencies or any multiple of 8 kHz
z
Fast detection on input failure and entry into Digital
Holdover mode (holds at the current frequency value)
z
Frequency translation between input and output rates
via direct digital synthesis
z
High accuracy digital architecture for stable PLL
dynamics combined with an APLL for low jitter final
output clocks
Phase Lock/Loss Detectors
z
Selectable Automatic DPLL bandwidth control (auto*
selects either Locked bandwidth, or Acquisition
bandwidth), or Locked DPLL bandwidth (Reg. 3B
Bit 7).
z
Programmable bandwidth controls:
(* = hardware default selection)
DPLL1 Main Features
Phase lock/loss detection is handled in several ways.
Phase loss can be triggered from:
z
The fine phase lock detector, which measures the
phase between input and feedback clock
z
The coarse phase lock detector, which monitors whole
cycle slips
z
Detection that the DPLL is at min. or max. frequency
z
Detection of no activity on the input
z
Each of these sources of phase loss indication is
individually enabled via registers bits (see Reg. 73 and
74). Phase lock or loss is used to determine whether to
switch to nearest edge locking and whether to use
acquisition or normal bandwidth settings for the DPLL.
Acquisition bandwidth is used for faster pull-in from an
unlocked state.
The coarse phase lock detector detects phase differences
of n cycles between input and feedback clocks, where n is
set by Reg. 74, Bits [3:0]; the same register that is used
for the coarse phase detector range, since these
functions go hand in hand. This detector may be used in
the case where it is required that a phase loss indication
is not given for reasonable amounts of input jitter and so
the fine phase loss detector is disabled and the coarse
detector is used instead.
Revision 3.00/January 2003 © Semtech Corp.
• Locked bandwidth: 18, 35* or 70 Hz (Reg. 67)
• Acquisition bandwidth: 18, 35 or 70* Hz
(Reg. 69)
• Damping factor, (For optional faster locking and
peaking control) Factors = 1.2, 2.5, 5, 10* or 20
(Reg. 6B, Bits [2:0])
Programmable DPLL pull-in frequency range (Reg. 41,
Reg. 42).
DPLL1 Advanced Features
Phase Loss Indicators
z
Phase loss fine limit. on*/off (Reg. 73 Bit 7) and
programmable range 0 to 7 Dec. (Reg. 73 Bits [2:0])
z
Multi-cycle phase loss course limit, on*/off (Reg. 74
Bit 7) and selectable range from ±(1 to 8191) UI in 13
steps (Reg. 74 Bits [3:0]).
Phase Detector Controls
z
Multi-cycle phase detector - Course phase detector &
capture range on*/off (Reg. 74 Bit 6) and selectable
range from ± (1 to 8191) UI in 13 steps (Reg. 74 Bits
[3:0]). If selected, this feature increases jitter and
wander tolerance to a maximum of 8192 UI (normally
limited to ±0.5 UI)
z
Use of coarse phase detector result in DPLL algorithm,
on*/off (Reg. 74 Bit 5) - speeds up phase locking
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ADVANCED COMMUNICATION
z
z
FINAL
Limit DPLL1 Integral when at DPLL frequency limit,
on*/off (Reg. 3B Bit 3) - reduces overshoot
Advanced Phase Detector Controls
z
PD2 gain control enable, on*/off (Reg. 6C Bit 7)
If on, this allows automatic gain selection according to
the type of feedback to the DPLL (For the digital
feedback setting, the gain used for PD2 is given by
(Reg. 6C Bits [2:0]). If off, PD2 is not used
z
Adjustable gain settings for PD2 (with auto switching
enabled), for the following feedback cases:
Anti-noise filter for low frequency inputs, on/off*
(Reg. 76 Bit 7).
Advanced Phase Detector Controls
z
z
DPLL1 PD2 gain enable, on*/off (Reg. 6D
Bit 7)
If on, this allows automatic gain selection according to
the type of feedback to the DPLL (For the digital
feedback setting, the gain used for PD2 is given by
Reg. 6D Bits [2:0]). If off, PD2 is not used.
Adjustable gain settings for PD2 (when enabled), for
the following feedback cases:
• Digital feedback (Reg. 6D Bits [2:0])
• Analog feedback (all frequencies above 8 kHz)
(Reg. 6D Bits [6:4])
• Analog 8k (or less) feedback (Reg. 6B Bits [2:0]).
DPLL2 Main Features
z
Always locked to DPLL1
z
Programmable controls
• Damping factor, (For optional faster locking and
peaking control) Factors = 1.2, 2.5, 5*, 10 or 20.
Digital feedback, on*/off (Reg. 35 Bit 6)
z
Output frequency selection (Reg. 64)
• DS3/E3 support (44.736 MHz / 34.368 MHz)
independent of rates from DPLL1
• Low jitter E1/DS1 options independent of rates
from DPLL1
• Frequencies of n x E1/DS1 including 16 and 12 x
E1, and 16 and 24 x DS1 supported
• Squelched (clock off)
z
Can provide the source for the 2 kHz and 8 kHz
outputs available at Outputs 01 and 02 (Reg. 7A Bit
7).
The ACS8526 delivers four output signals on the following
ports: Two clocks, one each on Output O1 and O2, and two
Sync signals, one each on output ports FrSync and
MFrSync. Outputs O1 and O2 are independent of each
other and are individually selectable. Output 01 is a
differential port (pins O1POS and O1NEG), and can be
selected to be PECL or LVDS via Reg. 3A
cnfg_differential_output. Output O2 (pin O2) and the Sync
outputs are TTL/CMOS compatible.
The frequencies available on the outputs can be selected
from a range of spot frequencies by either:
z
Hardware selection: configuring the hardware pins
OP_FREQ1 [2:0], OP_FREQ2[2:0] and SONSDH, which
are read on reset, or
z
Register programming: writing to the registers after
the end of the initialization period.
Output Frequency Selection by Hardware
Tables 6 and 7 show the hardware settings for selecting
particular output frequencies on Outputs 01 and 02. Note
that the hardware frequency selection method provides
only a subset (11) of the total number of frequencies (55)
available when selecting by register programming.
Output Frequency Selection by Register
Programming
DPLL2 Advanced Features
The advanced features are the same as those for DPLL1,
with DPLL2 using the configuration values for DPLL1, with
the following exceptions:
Revision 3.00/January 2003 © Semtech Corp.
Outputs
The two Sync outputs, FrSync (8 kHz) and MFrSync
(2 kHz), are derived from DPLL1.
• Locked bandwidth: 18*, 35 or 70 Hz
z
• Digital feedback (Reg. 6C Bits [2:0])
• Analog feedback (all frequencies above 8K)
(Reg. 6C Bits [6:4])
• Analog 8k (or less) feedback (Reg. 6A Bits [2:0]).
The output frequencies on O1 and O2 are controlled by a
number of interdependent parameters (refer to ‘‘PLL
Architecture’’ on page 11). The frequencies of the output
clocks are selectable from a range of pre-defined spot
frequencies/port technologies, as defined in Table 8.
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FINAL
Table 6 Output 01 Frequency Selection by Hardware Configuration
O1_FREQ
2
1
0
0
0
0
0
0
1
0
1
0
SONSDHB
Pin
Output
Frequency/
MHz
DPLL Selected
X
0
-
DPLL Mode
Jitter Level (typ)
rms (ps)
pk-pk (ns)
-
-
-
0
34.368
DPLL2
E3
120
1
1
44.736
DPLL2
DS3
110
1
0
X
19.44
DPLL1
Analog feedback
60
0.6
1
1
X
25.92
DPLL1
Analog feedback
60
0.6
1
0
0
X
38.88
DPLL1
Analog feedback
60
0.6
1
0
1
X
51.84
DPLL1
Analog feedback
60
0.6
1
1
0
X
77.76
DPLL1
Analog feedback
60
0.6
1
1
1
X
155.52
DPLL1
Analog feedback
60
0.6
Output
Frequency/
MHz
DPLL Selected
DPLL Mode
0
-
2.048
Table 7 Output 02 Frequency Selection by Hardware Configuration
O2_FREQ
2
1
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
1
SONSDHB O1_FREQ
Pin
=
“001”
X
0
1
0
1
X
FALSE
TRUE
Jitter Level (typ)
rms (ps)
pk-pk (ns)
-
-
-
DPLL2
16E1
400
2
1.544
DPLL2
16DS1
200
1.2
2.048
DPLL1
12E1
900
0.45
3.088
DPLL1
24DS1
110
0.75
0
X
34.368
DPLL2
E3
120
1
1
X
44.736
DPLL2
DS3
110
1
1
X
X
19.44
DPLL1
Analog feedback
60
0.6
0
0
X
X
25.92
DPLL1
Analog feedback
60
0.6
1
0
1
X
X
38.88
DPLL1
Analog feedback
60
0.6
1
1
0
X
X
51.84
DPLL1
Analog feedback
60
0.6
1
1
1
X
X
77.76
DPLL1
Analog feedback
60
0.6
Revision 3.00/January 2003 © Semtech Corp.
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ADVANCED COMMUNICATION
FINAL
3. Refer to Table 11, APLL1 Frequencies, and Table 12,
APLL2 Frequencies, to determine in what mode
DPLL1 and DPLL2 need to be configured, considering
the output jitter level.
Outputs O1 & O2 Frequency Configuration Steps
The output frequency selection is performed in the
following steps:
1. Refer to Table 10, Frequency Divider Look-up, to
choose a set of output frequencies.
2. Refer to the Table 10 to determine the required APLL
frequency to support the frequency set.
4. Refer to Table 13, O1 and O2 Output Frequency
Selection, and the column headings in Table 10,
Frequency Divider Look-up, to select the appropriate
frequency from either of the APLLs on each output as
required.
Table 8 Output Reference Source Selection Table
Port
Name
Output Port
Technology
Frequencies Supported
Output
O1
LVDS/PECL
(LVDS default)
Output
O2
TTL/CMOS
FrSync
TTL/CMOS
FrSync, 8 kHz programmable pulse width and polarity, see Reg. 7A.
MFrSync
TTL/CMOS
MFrSync, 2 kHz programmable pulse width and polarity, see Reg. 7A.
Frequency selection as per Table 9 and Table 13
Note...1.544 MHz/2.048 MHz are shown for SONET/SDH respectively. Pin SONSDHB controls default. When High, SONET is default.
Table 9 Output Frequency Selection
Frequency (MHz, unless stated otherwise)
DPLL1 Mode
DPLL2 Mode
APLL2 Input Mux
Jitter Level (typ)
rms
(ps)
pk-pk
(ns)
2 kHz
77.76 MHz Analog
-
-
60
0.6
2 kHz
Any digital feedback
mode
-
-
1400
5
8 kHz
77.76 MHz Analog
-
-
60
0.6
8 kHz
Any digital feedback
mode
-
-
1400
5
Select DPLL2
500
2.3
Select DPLL1 12E1
250
1.5
Select DPLL2
200
1.2
Select DPLL1 16DS1
150
1.0
1.536
-
12E1 mode
1.536
-
-
1.544
-
1.544
-
16DS1 mode
-
1.544
via Digital1 or Digital2 (not Output O1)
77.76 MHz Analog
-
-
3800
13
1.544
via Digital1 or Digital2 (not Output O1)
Any digital feedback
mode
-
-
3800
18
Select DPLL2
500
2.3
Select DPLL1 12E1
250
1.5
Select DPLL2
400
2.0
2.048
-
12E1 mode
2.048
-
-
2.048
-
16E1 mode
Revision 3.00/January 2003 © Semtech Corp.
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Table 9 Output Frequency Selection (cont...)
Frequency (MHz, unless stated otherwise)
DPLL1 Mode
2.048
DPLL2 Mode
-
-
APLL2 Input Mux
Select DPLL1 16E1
Jitter Level (typ)
rms
(ps)
pk-pk
(ns)
220
1.2
2.048
(not Output O1)
12E1 mode
-
-
900
4.5
2.048
via Digital1 or Digital2 (not Output O1)
77.76 MHz Analog
-
-
3800
13
2.048
via Digital1 or Digital2 (not Output O1)
Any digital feedback
mode
-
-
3800
18
Select DPLL2
200
1.2
Select DPLL1 16DS1
150
1.0
760
2.6
2.059
-
2.059
-
-
16DS1 mode
-
2.059
(not Output O1)
16DS1 mode
-
2.316
-
24DS1 mode
Select DPLL2
110
0.75
2.316
-
-
Select DPLL1 24DS1
110
0.75
2.731
-
16E1 mode
Select DPLL2
400
1.5
2.731
-
-
Select DPLL1 16E1
220
1.2
250
1.6
2.731
(not Output O1)
16E1 mode
-
-
2.796
-
DS3 mode
Select DPLL2
110
1.0
3.088
-
24DS1 mode
Select DPLL2
110
0.75
3.088
-
-
Select DPLL1 24DS1
110
0.75
3.088
(not Output O1)
24DS1 mode
-
-
110
0.75
3.088
via Digital1 or Digital2 (not Output O1)
77.76 MHz Analog
-
-
3800
13
3.088
via Digital1 or Digital2 (not Output O1)
Any digital feedback
mode
-
-
3800
18
110
1.0
3.728
-
DS3 mode
Select DPLL2
4.096
via Digital1 or Digital2 (not Output O1)
77.76 MHz Analog
-
-
3800
13
4.096
via Digital1 or Digital2 (not Output O1)
Any digital feedback
mode
-
-
3800
18
4.296
-
E3 mode
Select DPLL2
120
1.0
4.86
-
77.76 MHz mode
Select DPLL2
60
0.6
5.728
-
E3 mode
Select DPLL2
120
1.0
900
4.5
Select DPLL2
500
2.3
Select DPLL1 12E1
250
1.5
760
2.6
200
1.2
6.144
12E1 mode
-
6.144
-
12E1 mode
6.144
-
-
6.176
16DS1 mode
-
6.176
-
Revision 3.00/January 2003 © Semtech Corp.
16DS1 mode
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-
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Table 9 Output Frequency Selection (cont...)
Frequency (MHz, unless stated otherwise)
DPLL1 Mode
6.176
DPLL2 Mode
-
-
APLL2 Input Mux
Select DPLL1 16DS1
Jitter Level (typ)
rms
(ps)
pk-pk
(ns)
150
1.0
6.176
via Digital1 or Digital2 (not Output O1)
77.76 MHz Analog
-
-
3800
13
6.176
via Digital1 or Digital2 (not Output O1)
Any digital feedback
mode
-
-
3800
18
60
0.6
6.48
-
77.76 MHz mode
Select DPLL2
6.48
(not Output O1)
77.76 MHz analog
-
-
60
0.6
6.48
(not Output O1)
77.76 MHz digital
-
-
60
0.6
8.192
12E1 mode
-
-
900
4.5
8.192
16E1 mode
-
-
250
1.6
Select DPLL2
400
2.0
Select DPLL1 16E1
220
1.2
8.192
-
16E1 mode
8.192
-
-
8.192
via Digital1 or Digital2 (not Output O1)
77.76 MHz Analog
-
-
3800
13
8.192
via Digital1 or Digital2 (not Output O1)
Any digital feedback
mode
-
-
3800
18
8.235
16DS1 mode
-
-
760
2.6
9.264
24DS1 mode
-
-
110
0.75
9.264
-
Select DPLL2
110
0.75
9.264
-
Select DPLL1 24DS1
110
0.75
250
1.6
110
1.0
900
4.5
Select DPLL2
500
2.3
Select DPLL1 12E1
250
1.5
10.923
16E1 mode
11.184
-
12.288
12E1 mode
24DS1 mode
DS3 mode
Select DPLL2
-
-
12.288
-
12E1 mode
12.288
-
-
12.352
24DS1 mode
-
-
110
0.75
12.352
16DS1 mode
-
-
760
2.6
12.352
-
Select DPLL2
200
1.2
12.352
-
Select DPLL1 16DS1
150
1.0
16DS1 mode
-
12.352 via Digital1 or Digital2 (not Output O1)
77.76 MHz Analog
-
-
3800
13
12.352 via Digital1 or Digital2 (not Output O1)
Any digital feedback
mode
-
-
3800
18
16.384
12E1 mode
-
-
900
4.5
16.384
16E1 mode
-
-
250
1.6
Revision 3.00/January 2003 © Semtech Corp.
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ADVANCED COMMUNICATION
FINAL
Table 9 Output Frequency Selection (cont...)
Frequency (MHz, unless stated otherwise)
DPLL1 Mode
DPLL2 Mode
16.384
-
16E1 mode
16.384
-
-
APLL2 Input Mux
Jitter Level (typ)
rms
(ps)
pk-pk
(ns)
Select DPLL2
400
2.0
Select DPLL1 16E1
220
1.2
16.384 via Digital1 or Digital2 (not Output O1)
77.76 MHz Analog
-
-
3800
13
16.384 via Digital1 or Digital2 (not Output O1)
Any digital feedback
mode
-
-
3800
18
16.469
16DS1 mode
-
-
760
2.6
17.184
-
120
1.0
18.528
24DS1 mode
110
0.75
18.528
-
Select DPLL2
110
0.75
18.528
-
Select DPLL1 24DS1
110
0.75
E3 mode
Select DPLL2
-
24DS1 mode
-
-
19.44
77.76 MHz analog
-
-
60
0.6
19.44
77.76 MHz digital
-
-
60
0.6
60
0.6
250
1.6
110
1.0
900
4.5
Select DPLL2
500
2.3
Select DPLL1 12E1
250
1.5
19.44
21.845
16E1 mode
22.368
24.576
77.76MHz mode
-
-
DS3 mode
12E1 mode
Select DPLL2
Select DPLL2
-
-
24.576
-
12E1 mode
24.576
-
-
24.704
24DS1 mode
-
-
110
0.75
24.704
16DS1 mode
-
-
760
2.6
24.704
-
Select DPLL2
200
1.2
24.704
-
-
Select DPLL1 16DS1
150
1.0
16DS1 mode
25.92
77.76 MHz analog
-
-
60
0.6
25.92
77.76 MHz digital
-
-
60
0.6
32.768
16E1 mode
-
-
250
1.6
Select DPLL2
400
2.0
Select DPLL1 16E1
220
1.2
Select DPLL2
120
1.0
110
0.75
Select DPLL2
110
0.75
Select DPLL1 24DS1
110
0.75
32.768
-
16E1 mode
32.768
-
-
34.368
-
37.056
24DS1 mode
37.056
-
37.056
-
Revision 3.00/January 2003 © Semtech Corp.
E3 mode
24DS1 mode
-
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FINAL
Table 9 Output Frequency Selection (cont...)
Frequency (MHz, unless stated otherwise)
DPLL1 Mode
DPLL2 Mode
APLL2 Input Mux
Jitter Level (typ)
rms
(ps)
pk-pk
(ns)
38.88
77.76 MHz analog
-
-
60
0.6
38.88
77.76 MHz digital
-
-
60
0.6
38.88
-
77.76 MHz mode
Select DPLL2
60
0.6
44.736
-
DS3 mode
Select DPLL2
110
1.0
49.152 (Output O1 only)
12E1 mode
-
-
900
4.5
49.408 (Output O1 only)
16DS1 mode
-
-
760
2.6
51.84
77.76 MHz analog
-
-
60
0.6
51.84
77.76 MHz digital
-
-
60
0.6
65.536 (Output O1 only)
16E1 mode
-
-
250
1.6
120
1.0
68.736
74.112
(Output O1 only)
E3 mode
Select DPLL2
24DS1 mode
-
-
110
0.75
77.76
77.76 MHz analog
-
-
60
0.6
77.76
77.76 MHz digital
-
-
60
0.6
60
0.6
77.76
-
77.76 MHz mode
Select DPLL2
98.304 (Output O1 only)
12E1 mode
-
-
900
4.5
98.816 (Output O1 only)
16DS1 mode
-
-
760
2.6
131.07
16E1 mode
-
-
250
1.6
148.22 (Output O1 only)
24DS1 mode
-
-
110
0.75
155.52 (Output O1 only)
77.76 MHz analog
-
-
60
0.6
155.52 (Output O1 only)
77.76 MHz digital
-
-
60
0.6
311.04 (Output O1 only)
77.76 MHz analog
-
-
60
0.6
311.04 (Output O1 only)
77.76 MHz digital
-
-
60
0.6
(Output O1 only)
Revision 3.00/January 2003 © Semtech Corp.
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Table 10 Frequency Divider Look-up
Transmission Rate
APLL Frequency
APLL/2
APLL/4
APLL/6
51.84
APLL/8
OC-N Rates
311.04
155.52
77.76
38.88
E3
274.944
137.472
68.376
-
34.368
DS3
178.944
89.472
44.736
-
22.368
24DS1
148.224
74.112
37.056
24,704
18.528
16E1
131.072
65.536
32.768
21.84533
16DS1
98.816
49.408
24.704
12E1
98.304
49.152
24.576
APLL/12
25.92
APLL/16
APLL/48
APLL/64
19.44
6.48
4.86
-
17.184
5.728
4.296
-
11.184
3.728
2.796
12.352
9.264
3.088
2.316
16.384
10.92267
8.192
2.730667
2.048
16.46933
12.352
8.234667
6.176
2.058667
1.544
16.384
12.288
8.192
6.144
2.048
1.536
Note...All frequencies in MHz.
Table 11 APLL1 Frequencies
APLL1 Frequency
Synthesis/MUX setting for APLL1
input
DPLL1 Frequency Control
Reg. 65 Bits[2:0]
Output Jitter Level
ns (pk-pk)
311.04
Normal (digital feedback)
000
<0.5
311.04 MHz
Normal (analog feedback)
001
<0.5
98.304 MHz
12E1 (digital feedback)
010
<2
131.072 MHz
16E1 (digital feedback)
011
<2
148.224 MHz
24DS1 (digital feedback)
100
<2
98.816 MHz
16DS1 (digital feedback)
101
<2
-
Do not use
110
-
-
Do not use
111
-
Table 12 APLL2 Frequencies
APLL2
Frequency
DPLL Mode
DPLL2 Forward DFS
Frequency (MHz)
DPLL2 Freq Control
Register Bits
Reg. 64 Bits [2:0]
APLL2 Input from
DPLL1 or 2.
Reg. 65 Bit 6
DPLL1 + Synthesis
Freq to APLL2
Register Bits
Reg. 65 Bits [5:4]
Output
Jitter Level
ns (pk-pk)
311.04 MHz
DPLL2-Squelch 77.76
ed
000
0 (DPLL2 selected)
XX
<0.5
311.04 MHz
DPLL2-Normal
77.76
001
0 (DPLL2 selected)
XX
<0.5
98.304 MHz
DPLL2-12E1
24.576
010
0 (DPLL2 selected)
XX
<0.5
131.072 MHz
DPLL2-16E1
32.768
011
0 (DPLL2 selected)
XX
<0.5
148.224 MHz
DPLL2-24DS1
37.056 (2*18.528)
100
0 (DPLL2 selected)
XX
<0.5
98.816 MHz
DPLL2-16DS1
24.704
101
0 (DPLL2 selected)
XX
<0.5
Revision 3.00/January 2003 © Semtech Corp.
Page 24
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ACS8526 LC/P LITE
ADVANCED COMMUNICATION
FINAL
Table 12 APLL2 Frequencies (cont...)
APLL2
Frequency
DPLL Mode
DPLL2 Forward DFS
Frequency (MHz)
DPLL2 Freq Control
Register Bits
Reg. 64 Bits [2:0]
APLL2 Input from
DPLL1 or 2.
Reg. 65 Bit 6
DPLL1 + Synthesis
Freq to APLL2
Register Bits
Reg. 65 Bits [5:4]
Output
Jitter Level
ns (pk-pk)
274.944 MHz
DPLL2-E3
68.736 (2*34.368)
110
0 (DPLL2 selected)
XX
<0.5
178.944 MHz
DPLL2-DS3
44.736
111
0 (DPLL2 selected)
XX
<0.5
98.304 MHz
DPLL1-12E1
-
XXX
1 (DPLL1 selected)
00
<2
131.072 MHz
DPLL1-16E1
-
XXX
1 (DPLL1 selected)
01
<2
148.224 MHz
DPLL1-24DS1
-
XXX
1 (DPLL1 selected)
10
<2
98.816 MHz
DPLL1-16DS1
-
XXX
1 (DPLL1 selected)
11
<2
Note...If using Synthesis for inputs to both APLL1 and APLL2, then they must both use the same synthesis settings
“Digital” Frequencies
Table 13, “O1 and O2 Output Frequency Selection,” lists
Digital1 and Digital2 as available for selection. Digital1 is
a single frequency selected from the range shown in
Table 14. Digital2 is another single frequency selected
from the same range.
Table 13 O1 and O2 Output Frequency Selection
Value
Output O2
Reg. 61 Bits [3:0]
Output O1
Reg. 62 Bits [7:4]
0000
Off
Off
0001
2 kHz
2 kHz
0010
8 kHz
8 kHz
0011
Digital2
APLL1/2
0100
Digital1
Digital1
0101
APLL1/48
APLL1/1
0110
APLL1/16
APLL1/16
0111
APLL1/12
APLL1/12
1000
APLL1/8
APLL1/8
1001
APLL1/6
APLL1/6
1010
APLL1/4
APLL1/4
1011
APLL2/64
APLL2/64
1100
APLL2/48
APLL2/48
1101
APLL2/16
APLL2/16
1110
APLL2/8
APLL2/8
1111
APLL2/4
APLL2/4
Revision 3.00/January 2003 © Semtech Corp.
Using Output O2 to Control Pulse Width of 2/8 kHz on FrSync,
MFrSync and 01 Outputs
It can be seen from Table 13 (01 and 02 Output
Frequency Selection) that frequencies listed as 2 kHz and
8 kHz can be selected. Whilst the FrSync and MFrSync
outputs are always supplied from DPLL1, the 2 kHz and
8 kHz options available from the O1 and O2 outputs are
all supplied via DPLL1 or DPLL2 (Reg. 7A Bit 7).
The outputs can be either clocks (50:50 mark-space) or
pulses, and can be inverted. When pulse configuration is
used, the pulse width will be one cycle of the rate selected
on Output O2 (Output O2 must be configured to generate
at least 1,544 kHz to ensure that pulses are generated
correctly). Figure 6 shows the various options with the
8 kHz controls in Reg. 7A. There is an identical
arrangement with Reg. 7A Bits [1:0] for the 2 kHz 01 and
MFrSync outputs. Outputs FrSync and MFrSync can be
disabled via Reg. 63 Bits [7:6].
Page 25
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ACS8526 LC/P LITE
ADVANCED COMMUNICATION
Figure 6
FINAL
Control of 8k Options.
02 Output
02 Output
FrSync at 8 kHz, or
Output 01 at 8kHz
FrSync at 8 kHz, or
Output 01 at 8kHz
a) Clock non-inverted, Reg.7A[3:2] = 00
c) Clock inverted, Reg.7A[3:2] = 10
02 Output
02 Output
FrSync at 8 kHz, or
Output 01 at 8kHz
FrSync at 8 kHz, or
Output 01 at 8kHz
b) Pulse non-inverted, Reg.7A[3:2] = 01
d) Pulse inverted, Reg.7A[3:2] = 11
F8525_016outputoptions8k_01
Table 14 Digital Frequency Selections
Digital1 Control
Reg.39 Bits [5:4]
Digital1 SONET/
SDH Reg. 38 Bit5
Digital1 Freq. (MHz)
Digital2 Control
Reg. 39 Bits[7:6]
Digital2 SONET/SDH
Reg.38 Bit6
Digital2 Freq. (MHz)
00
0
2.048
00
0
2.048
01
0
4.096
01
0
4.096
10
0
8.192
10
0
8.192
11
0
16.384
11
0
16.384
00
1
1.544
00
1
1.544
01
1
3.088
01
1
3.088
10
1
6.176
10
1
6.176
11
1
12.352
11
1
12.352
Revision 3.00/January 2003 © Semtech Corp.
Page 26
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ACS8526 LC/P LITE
ADVANCED COMMUNICATION
Local Oscillator Clock
FINAL
Status Reporting
The Master system clock on the ACS8526 should be
provided by an external clock oscillator of frequency
12.800 MHz. Wander on the local oscillator clock will not
have a significant effect on the output clock whilst in
Locked mode. In Free-Run or Holdover mode wander on
the crystal is more significant. Variation in crystal
temperature or supply voltage both cause drifts in
operating frequency, as does ageing. These effects must
be limited by careful selection of a suitable component for
the local oscillator. Please contact Semtech for
information on crystal oscillator suppliers.
Crystal Frequency Calibration
The absolute crystal frequency accuracy is less important
than the stability since any frequency offset can be
compensated by adjustment of register values in the IC.
This allows for calibration and compensation of any
crystal frequency variation away from its nominal value.
An adjustment of ± 50 ppm would be sufficient to cope
with most crystals, in fact the range is an order of
magnitude larger due to the use of two 8-bit register
locations. The setting of the conf_nominal_frequency
register allows for this adjustment. An increase in the
register value increases the output frequencies by
0.0196229 ppm for each LSB step.
Note...The default register value (in decimal) = 39321
(9999 hex) = 0 ppm offset. The minimum to maximum offset
range of the register is 0 to 65535 (dec), giving an adjustment
range of -770 ppm to +514 ppm of the output frequencies, in
0.0196229 ppm steps.
Example: If the crystal was oscillating at 12.800 MHz + 5 ppm,
then the calibration value in the register to give a - 5 ppm
adjustment in output frequencies to compensate for the crystal
inaccuracy, would be:
39321 - (5 / 0.0196) = 39066 (dec) = 989A (hex).
Power-On Reset
The Power-On Reset (PORB) pin resets the device if forced
Low. The reset is asynchronous, the minimum Low pulse
width is 5 ns. Reset is needed to initialize all of the
register values to their defaults. Reset must be asserted
at power on, and may be re-asserted at any time to restore
defaults. This is implemented simply using an external
capacitor to GND along with the internal pull-up resistor.
The ACS8526 is held in a reset state for 250 ms after the
PORB pin has been pulled High. In normal operation PORB
should be held High.
Revision 3.00/January 2003 © Semtech Corp.
Loss of Input Signal - LOS Flag
In the event of loss of SEC input signal, LOS flag is raised
on the LOS_ALARM pin.
Status Information
Status information can be read from the following Status
Registers:
z
sts_current_DPLL_frequency (Reg. 0C, 0D, and 07)
z
sts_reference_sources (Reg. 11).
The registers sts_current_DPLL_frequency report the
frequency of DPLL1 or DPLL2 with respect to the external
crystal XO frequency (after calibration via Reg. 3C, 3D if
used). The selection of DPLL2 or DPLL1 reporting is made
via Reg. 4B, Bit 4. The value is a 19-bit signed number
with one LSB representing 0.0003068 ppm (range of ±
80 ppm). This value is actually the integral path value in
the DPLL, and as such corresponds to an averaged
measurement of the input frequency, with an averaging
time inversely proportional to the DPLL bandwidth setting.
Reading this regularly can show how the currently locked
source is varying in value e.g. due to frequency wander on
its input.
Serial Interface
The ACS8526 device has a serial interface which can be
SPI compatible.
The Motorola SPI convention is such that address and
data is transmitted and received MSB first. On the
ACS8526, device address and data are transmitted and
received LSB first. Address, read/write control and data
on the SDI pin is latched into the device on the rising edge
of the SCLK. During a read operation, serial data output
on the SDO pin can be read out of the device on either the
rising or falling edge of the SCLK depending on the logic
level of CLKE. For standard Motorola SPI compliance,
data should be clocked out of the SDO pin on the rising
edge of the SCLK so that it may be latched into the
microprocessor on the falling edge of the SCLK. Figure 7
and 8 show the timing diagrams of write and read
accesses for this interface.
The serial interface clock (SCLK) is not required to run
between accesses (i.e., when CSB = 1).
Page 27
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ACS8526 LC/P LITE
ADVANCED COMMUNICATION
Figure 7
FINAL
Write Access Timing for SERIAL Interface
CSB
tsu2
tpw2
th2
SCLK
th1
tsu1
_
SDI
SDO
R/W
tpw1
A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7
Output not driven, pulled low by internal resistor
F8525D_014WriteAccSerial_01
Table 15 Write Access Timing for SERIAL Interface (For use with Figure 7)
Symbol
Parameter
MIN
TYP
MAX
tSU1
Setup SDI valid to SCLKrising edge
4 ns
-
-
tSU2
Setup CSBfalling edge to SCLKrising edge
14 ns
-
-
tpw1
SCLK Low time
22 ns
-
-
tpw2
SCLK High time
22 ns
-
-
th1
Hold SDI valid after SCLKrising edge
6 ns
-
-
th2
Hold CSB Low after SCLKrising edge
5 ns
-
-
tp
Time between consecutive accesses (CSBrising edge to CSBfalling edge)
10 ns
-
-
Revision 3.00/January 2003 © Semtech Corp.
Page 28
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ACS8526 LC/P LITE
ADVANCED COMMUNICATION
Figure 8
FINAL
Read Access Timing for SERIAL Interface
CLKE = 0; SDO data is clocked out on the rising edge of SCLK
CSB
tsu2
tpw2
th2
SCLK
th1
tsu1
_
R/W
SDI
tpw1
A0 A1 A2 A3 A4 A5 A6
td1
Output not driven, pulled low by internal resistor
SDO
td2
D0 D1 D2 D3 D4 D5 D6 D7
CLKE = 1; SDO data is clocked out on the falling edge of SCLK
CSB
th2
SCLK
_
SDI
R/W
A0 A1 A2 A3 A4 A5 A6
td1
SDO
Output not driven, pulled low by internal resistor
td2
D0 D1 D2 D3 D4 D5 D6 D7
F8526D_013ReadAccSerial_01
Table 16 Read Access Timing for SERIAL Interface (For use with Figure 8)
Symbol
Parameter
MIN
TYP
MAX
tSU1
Setup SDI valid to SCLKrising edge
4 ns
-
-
tSU2
Setup CSBfalling edge to SCLKrising edge
14 ns
-
-
td1
Delay SCLKrising edge (SCLKfalling edge for CLKE = 1) to SDO valid
-
-
18 ns
td2
Delay CSBrising edge to SDO High-Z
-
-
16 ns
tpw1
SCLK Low time
22 ns
-
-
tpw2
SCLK High time
22 ns
-
-
th1
Hold SDI valid after SCLKrising edge
6 ns
-
-
th2
Hold CSB Low after SCLKrising edge, for CLKE = 0
Hold CSB Low after SCLKfalling edge, for CLKE = 1
5 ns
-
-
tp
Time between consecutive accesses (CSBrising edge to CSBfalling edge)
10 ns
-
-
Revision 3.00/January 2003 © Semtech Corp.
Page 29
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ACS8526 LC/P LITE
ADVANCED COMMUNICATION
Register Map
FINAL
Register Access
Each Register, or register group, is described in the
following Register Map (Table 17) and subsequent
Register Description Tables.
Register Organisation
The ACS8526 LC/P LITE uses a total of 45 eight-bit
registers, identified by a Register Name and
corresponding hexadecimal Register Address. They are
presented here in ascending order of Reg. address and
each Register is organised with the most-significant bit
positioned in the left-most bit, with bit significance
decreasing towards the right-most bit. Some registers
carry several individual data fields of various sizes, from
single-bit values (e.g. flags) upwards. Several data fields
are spread across multiple registers, as shown in the
Register Map, Table 17.
Shaded areas in the map are “don’t care” and writing
either 0 or 1 to them will not affect any function of the
device.
Bits labelled “Set to 0” or “Set to 1” must be set as stated
during initialisation of the device, either following powerup, or after a power-on reset (POR). Failure to correctly set
these bits may result in the device operating in an
unexpected way.
CAUTION! Do not write to any undefined register
addresses as this may cause the device to operate in a
test mode. If an undefined register has been
inadvertently addressed, the device should be reset to
ensure the undefined registers are at default values.
Multi-word Registers
For multi-word registers (e.g. Reg. 0C and 0D), all the
words have to be written to their separate addresses in
order, and without any other access taking place, before
their combined value can take effect. If the sequence is
interrupted, or the addresses are written to in the wrong
order, the sequence of writes will be ignored.
Revision 3.00/January 2003 © Semtech Corp.
Most registers are either configuration registers or status
registers, the exceptions being the chip_id and
chip_revision registers. Configuration registers may be
written to or read from at any time (the complete 8-bit
register must be written, even if only one bit is being
modified). All status registers may be read at any time. A
description of each register is given in the Register Map,
and Register Map Description.
Configuration Registers
Each configuration register reverts to a default value on
power-up or following a reset. Most default values are
fixed, but some will be pin-settable. All configuration
registers can be read out over the serial port.
Status Registers
The Status Registers contain readable registers. They may
all be read from outside the chip but are not writeable
from outside the chip (except for a clearing operation). All
status registers are read via shadow registers to avoid
data hits due to dynamic operation. Each individual status
register has a unique location.
Flags
In the event of loss of the currently selected input a
no-activity flag is raised on pin LOS_ALARM indicating that
the input to DPLL1 has failed. The active state (High or
Low) of the LOS_ALARM pin is programmable and the pin
can either be driven, or set to high impedance when nonactive (Reg 7D refers).
Defaults
Each Register is given a defined default value at reset and
these are listed in the Map and Description Tables.
However, some read-only status registers may not
necessarily show the same default values after reset as
those given in the tables. This is because they reflect the
status of the device which may have changed in the time
it takes to carry out the read, or through reasons of pin
configuration. In the same way, the default values given
for shaded areas could also take different values to those
stated.
Page 30
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ACS8526 LC/P LITE
ADVANCED COMMUNICATION
FINAL
Table 17 Register Map
Address
(hex)
Default
(hex)
Register Name
RO = Read Only
R/W = Read/Write
chip_id (RO)
00
chip_revision (RO)
test_register1 (R/W)
03
14
sts_current_DPLL_frequency [7:0] 0C
00
(RO)
Data Bit
7 (msb)
6
5
01
21
chip_id[15:8], 8 MSBs of Chip ID
02
00
[18:16] 07
11
22
cnfg_ref_source_frequency SEC1
Disable_180
Resync_
analog
lock8k_SEC1
divn_SEC2
lock8k_SEC2
34
C2
auto_extsync_
en
35
40
cnfg_dig_outputs_sonsdh (R/W)
38
14
cnfg_digtial_frequencies (R/W)
39
08
cnfg_differential_output (R/W)
3A
C2
cnfg_auto_bw_sel
3B
98
[7:0] 3C
99
FF
cnfg_DPLL_freq_limit (R/W) [9:8]
42
03
[7:0]. 46
FF
[13:8] 47
3F
No Activity
SEC1
reference_source_frequency_SEC1
reference_source_frequency_SEC2
XO_ edge
dig2_sonsdh
ip_sonsdhb
dig1_sonsdh
digital2_frequency
digital1_frequency
Output O1 _LVDS_PECL
auto_BW_sel
DPLL1_lim_int
Bits[7:0] of cnfg_nominal_frequency
[15:8] 3D 99
cnfg_DPLL_freq_limit (R/W) [7:0] 41
Bits[15:8] of cnfg_nominal_frequency
Bits[7:0] of cnfg_DPLL_freq_limit
Bits[9:8] cnfg_DPLL_freq_limit
divn_value [7:0] (divide Input frequency by n)
divn_value [13:8] (divide Input frequency by n)
DPLL1_DPLL2
_select
00
cnfg_upper_threshold (R/W)
50
06
upper_threshold_value (Activity alarm, Leaky Bucket - set threshold)
cnfg_lower_threshold (R/W)
51
04
lower_threshold_value (Activity alarm, Leaky Bucket - reset threshold)
cnfg_bucket_size (R/W)
52
08
bucket_size_value (Activity alarm, Leaky Bucket - size)
cnfg_decay_rate (R/W)
53
01
cnfg_output_frequency(R/W) (O2) 61
0A
(O1) 62
00
(MFrSync/FrSync) 63
C0
cnfg_DPLL2_frequency (R/W)
64
00
cnfg_DPLL1_frequency (R/W)
65
01
Set to 0
Bits [18:16] of sts_current_DPLL_frequency
divn_SEC1
4B
Set to 0
No Activity
SEC2
00
cnfg_registers_source_select
(R/W)
Set to 0
Bits [7:0] of sts_current_DPLL_frequency
00
cnfg_freq_divn (R/W)
8K Edge
Polarity
0 (lsb)
Bits [15:8] of sts_current_DPLL_frequencyy
22
cnfg_DPLL2_path (R/W)
(R/W)
1
chip_revision[7:0]
Phase_alarm
(RO)
SEC2 23
cnfg_nominal_frequency
2
00
sts_reference_sources (RO)
Alarm Status on inputs:SEC1 & 2
cnfg_input_mode (R/W)
3
chip_id[7:0], 8 LSBs of Chip ID
[15:8] 0D 00
(R/W)
4
4E
decay_rate_value (Activity
alarm, Leaky Bucket - leak rate)
output_freq_O2
output_freq_O1
MFrSync_en
FrSync_en
DPLL2_frequency
APLL2_for_
DPLL1_E1/
DS1
DPLL1_freq_to_APLL2
DPLL1_frequency
cnfg_DPLL2_bw (R/W)
66
00
DPLL2_bandwidth
cnfg_DPLL1_locked_bw (R/W)
67
10
DPLL1_locked_bandwidth
cnfg_DPLL1_acq_bw (R/W)
69
11
cnfg_DPLL2_damping (R/W)
6A
13
DPLL1_acquisition_bandwidth
DPLL2_PD2_gain_alog
DPLL2_damping
DPLL1_PD2_gain_alog_8k
cnfg_DPLL1_damping (R/W)
6B
14
cnfg_DPLL2_PD2_gain (R/W)
6C
C2
DPLL2_PD2_
gain_enable
cnfg_DPLL1_PD2_gain (R/W)
6D C2
DPLL1_PD2_
gain_enable
DPLL1_PD2_gain_alog
cnfg_phase_loss_fine_limit (R/W) 73
A2
fine_limit_en
noact_ph_loss
narrow_en
cnfg_phase_loss_coarse_limit
(R/W)
74
E5
coarse_lim_
phaseloss_en
wide_range_
en
multi_ph_resp
cnfg_ip_noise_window (R/W)
76
06
ip_noise_
window_en
cnfg_sync_pulses (R/W)
7A
00
2k_8k_from_
DPLL2
cnfg_LOS_alarm (R/W)
7D 02
cnfg_protection (R/W)
7E
DPLL1_PD2_gain_digital
phase_loss_fine_limit
phase_loss_coarse_limit
8k_invert
85
Revision 3.00/January 2003 © Semtech Corp.
DPLL1_damping
DPLL2_PD2_gain_digital
8k_pulse
2k_invert
2k_pulse
LOS_GPO_en
LOS_tristate_
en
LOS_
polarity
protection_value
Page 31
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ACS8526 LC/P LITE
ADVANCED COMMUNICATION
Register Descriptions
FINAL
Address (hex): 00
Register Name
chip_id
Bit 7
Bit 6
Description
Bit 5
(RO) 8 least significant bits of the Default Value
chip ID.
Bit 4
Bit 3
Bit 2
Bit 1
0100 1110
Bit 0
chip_id[7:0], 8 LSBs of Chip ID
Bit No.
[7:0]
Description
Bit Value
chip_id
Least significant byte of the 2-byte device ID.
4E (hex)
Value Description
Address (hex): 01
Register Name
chip_id
Bit 7
Bit 6
Description
Bit 5
(RO) 8 most significant bits of the Default Value
chip ID.
Bit 4
Bit 3
Bit 2
Bit 1
0010 0001
Bit 0
chip_id[15:8], 8 MSBs of Chip ID
Bit No.
[7:0]
Description
Bit Value
chip_id
Most significant byte of the 2-byte device ID.
21 (hex)
Value Description
Address (hex): 02
Register Name
Bit 7
chip_revision
Bit 6
Description
Bit 5
(RO) Silicon revision of the device. Default Value
Bit 4
Bit 3
Bit 2
Bit 1
0000 0000
Bit 0
chip_revision[7:0]
Bit No.
[7:0]
Description
Bit Value
chip_revision
Silicon revision of the device.
00 (hex)
Revision 3.00/January 2003 © Semtech Corp.
Page 32
Value Description
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ACS8526 LC/P LITE
ADVANCED COMMUNICATION
Address (hex): 03
Register Name
Bit 7
phase_alarm
Bit No.
test_register1
Bit 6
FINAL
Description
Bit 5
disable_180
(R/W) Register containing various Default Value
test controls (not normally used).
Bit 4
Bit 3
resync_analog
Set to 0
Description
Bit 2
Bit 1
8k Edge Polarity Set to 0
Bit Value
00X1 0100
Bit 0
Set to 0
Value Description
7
phase_alarm (phase alarm (R/O))
Instantaneous result from DPLL1.
0
1
DPLL1 reporting phase locked.
DPLL1 reporting phase lost.
6
disable_180
Normally the DPLL will try to lock to the nearest
edge (± 180°) for the first 2 seconds when locking
to a new reference. If the DPLL does not determine
that it is phase locked after this time, then the
capture range reverts to ± 360°, which corresponds
to frequency and phase locking. Forcing the DPLL
into frequency locking mode may reduce the time to
frequency lock to a new reference by up to two
seconds. However, this may cause an unnecessary
phase shift of up to 360° when the new and old
references are very close in frequency and phase.
0
1
DPLL1 automatically determines frequency lock
enable.
DPLL1 forced to always frequency and phase lock.
5
Not used.
-
-
4
resync_analog (analog dividers re-synchronization)
The analog output dividers include a
synchronization mechanism to ensure phase lock at
low frequencies between the input and the output.
0
Analog divider only synchronized during first 2
seconds after power-up.
Analog dividers always synchronized.This keeps the
clocks divided down from the APLL output, in sync
with equivalent frequency digital clocks in the DPLL.
Hence ensuring that 6.48 MHz output clocks, and
above, are in sync with the DPLL even though only a
77.76 MHz clock drives the APLL.
3
Set to 0
Test Control. Leave unchanged or set to 0.
0
-
2
8k Edge Polarity
When Lock8k or DivN mode is selected for the
current input SEC, this bit allows the system to lock
on either the rising or the falling edge of the input
clock.
0
1
Lock to falling clock edge.
Lock to rising clock edge.
1
Set to 0
Test Control. Leave unchanged or set to 0.
0
-
0
Set to 0
Test Control. Leave unchanged or set to 0.
0
-
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Address (hex): 07
Register Name
sts_current_DPLL_frequency
[18:16]
Bit 7
Bit 6
Bit 5
FINAL
Description
(RO) Bits [18:16] of the current
DPLL frequency.
Bit 4
Bit 3
Bit 2
Default Value
0000 0000
Bit 1
Bit 0
Bits [18:16] of sts_current_DPLL_frequency
Bit No.
Description
Bit Value
Value Description
[7:3]
Not used.
-
-
[2:0]
Bits [18:16] of sts_current_DPLL_frequency
When Bit 4 (DPLL1_DPLL2_select) of Reg. 4B
(cnfg_registers_source_select) = 0 the frequency
for DPLL1 is reported.
When this Bit 4 = 1 the frequency for DPLL2 is
reported.
-
See register description of
sts_current_DPLL_frequency at Reg. 0D.
Address (hex): 0C
Register Name
Bit 7
sts_current_DPLL_frequency
[7:0]
Bit 6
Bit 5
Description
(RO) Bits [7:0] of the current DPLL Default Value
frequency.
Bit 4
Bit 3
Bit 2
0000 0000
Bit 1
Bit 0
Bits [7:0] of sts_current_DPLL_frequency
Bit No.
[7:0]
Description
Bit Value
Bits [7:0] of sts_current_DPLL_frequency
When Bit 4 (DPLL1_DPLL2_select) of Reg. 4B
(cnfg_registers_source_select) = 0 the frequency
for DPLL1 is reported.
When this Bit 4 = 1 the frequency for DPLL2 is
reported.
Revision 3.00/January 2003 © Semtech Corp.
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-
Value Description
See register description of
sts_current_DPLL_frequency at Reg. 0D.
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Address (hex): 0D
Register Name
sts_current_DPLL_frequency
[15:8]
Bit 7
Bit 6
Bit 5
FINAL
Description
(RO) Bits [15:8] of the current
DPLL frequency.
Bit 4
Bit 3
Bit 2
Default Value
0000 0000
Bit 1
Bit 0
Bits [15:8] of sts_current_DPLL_frequency
Bit No.
[7:0]
Description
Bit Value
Bits [15:8] of sts_current_DPLL_frequency
The value in this register is combined with the value
in Reg. 0C and Reg. 07 to represent the current
frequency offset of the DPLL.
When Bit 4 (DPLL1_DPLL2_select) of Reg. 4B
(cnfg_registers_source_select) = 0 the frequency
for DPLL1 is reported.
When this Bit 4 = 1 the frequency for DPLL2 is
reported.
-
Value Description
In order to calculate the ppm offset of the DPLL with
respect to the crystal oscillator frequency, the value
in Reg. 07, Reg. 0D and Reg. 0C need to be
concatenated. This value is a 2’s complement
signed integer. The value multiplied by
0.0003068 dec. will give the value in ppm offset
with respect to the XO frequency, allowing for any
crystal calibration that has been performed, via
cnfg_nominal_frequency, Reg. 3C and 3D. The
value is actually the DPLL integral path value so it
can be viewed as an average frequency, where the
rate of change is related to the DPLL bandwidth. If
Bit 3 of Reg. 3B is High then this value will freeze if
the DPLL has been pulled to its min or max
frequency.
Address (hex): 11
Register Name
Bit 7
sts_reference_sources
SEC1 & SEC2
Bit 6
Description
Bit 5
(RO except for test when R/W)
Reports any alarms active on
inputs.
Bit 4
Bit 3
Bit 2
No Activity
SEC2 Input
Bit No.
[7:6]
Default Value
0010 0010
Bit 1
Bit 0
No Activity
SEC1 Input
Description
Bit Value
Value Description
Not Used
-
-
SEC2 Input Activity Alarm
Alarm indication from the activity monitors.
0
1
No alarm (input valid).
Input has an active “no activity” alarm.
Not Used
-
-
1
SEC1 Input Activity Alarm
Alarm indication from the activity monitors.
0
1
No alarm (input valid).
Input has an active “no activity” alarm.
0
Not Used
-
-
5
[3:2]
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Address (hex): 22
Register Name
cnfg_ref_source_frequency
SEC1
Bit 7
divn_SEC<n>
Bit No.
Bit 6
Bit 5
FINAL
Description
(R/W) Configuration of the
frequency and input monitoring
for input SEC<n>. For Reg. 22,
<n> = 1.
Bit 4
Bit 3
Bit 2
Default Value
0000 XXXX
Where XXXX is set by values on
Pins IP_FREQ[2:0] and SONSDHB
See Note in Description [3:0].
Bit 1
Bit 0
reference_source_frequency_SEC<n>
lock8k_SEC<n>
Description
Bit Value
Value Description
7
divn_SEC<n>
This bit selects whether or not input SEC<n> is
divided in the programmable pre-divider prior to
being input to the DPLL and frequency monitor- see
Reg. 46 and Reg. 47 (cnfg_freq_divn).
0
1
Input SEC<n> fed directly to DPLL and monitor.
Input SEC<n> fed to DPLL and monitor via predivider.
6
lock8k_SEC<n>
This bit selects whether or not input SEC<n> is
divided in the preset pre-divider prior to being input
to the DPLL. This results in the DPLL locking to the
reference after it has been divided to 8 kHz. This bit
is ignored when divn_SEC<n> is set (bit = 1).
0
1
Input SEC<n> fed directly to DPLL.
Input SEC<n> fed to DPLL via preset pre-divider.
[5:4]
Not used.
-
-
[3:0]
reference_source_frequency_SEC<n>
Programs the frequency of the SEC connected to
input SEC<n>. If divn_SEC<n> is set then this value
should be set to 0000 (8 kHz).
Note...The value on the pins IP_FREQ [2:0] and
SONSDHB determines the default expected input
frequency which, at power-up/reset is written to
both cnfg_ref_source_frequency registers, giving
each the same default value. The values in each
register can, after the initialization period (251 ms
after PORB goes High), be changed on an individual
basis by writing to each register separately via the
serial interface, however any subsequent reset will
cause these registers’ values to be overwritten by
whatever value is on the pins at the time of the
reset. See “Preconfiguring Inputs - Expected Input
Frequency” and Table 4 on page 7.
Address (hex): 23
cnfg_ref_source_frequency
Revision 3.00/January 2003 © Semtech Corp.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011-1111
SEC2
Page 36
8 kHz.
1544/2048 kHz (dependant on Bit 2 (ip_sonsdhb)
in Reg. 34).
6.48 MHz.
19.44 MHz.
25.92 MHz.
38.88 MHz.
51.84 MHz.
77.76 MHz.
Not used.
2 kHz.
4 kHz.
Not used.
As Reg. 22, but for SEC2, i.e. <n> = 2
Default = 0000 0000
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Address (hex): 34
Register Name
cnfg_input_mode
Bit 7
Bit 6
FINAL
Description
Bit 5
(R/W) Register controlling various Default Value
input modes of the device.
Bit 4
Bit 3
XO_edge
Bit No.
[7:6]
5
[4:3]
2
Bit 2
Bit 1
1100 0010*
Bit 0
ip_sonsdhb
Description
Bit Value
Value Description
Not used.
-
-
XO_edge
If the 12.8 MHz oscillator module connected to
REFCLK has one edge faster than the other, then for
jitter performance reasons, the faster edge should
be selected. This bit allows either the rising edge or
the falling edge to be selected.
0
Device uses the rising edge of the external
oscillator.
Device uses the falling edge of the external
oscillator.
Not used.
-
-
ip_sonsdhb
Bit to configure input frequencies to be either
SONET or SDH derived. This applies only to
selections of 0001 (bin) in the
cnfg_ref_source_frequency registers when the input
frequency is either 1544 kHz or 2048 kHz.
0
1
SDH- inputs set to 0001 expected to be 2048 kHz.
SONET- inputs set to 0001 expected to be
1544 kHz.
-
-
1
*The default value of Bit 2 is taken from the value of
the SONSDHB pin at power-up.
[1:0]
Not used.
Address (hex): 35
Register Name
Bit 7
cnfg_DPLL2_path
Bit 6
Description
Bit 5
(R/W) Register to configure the
feedback mode of DPLL2.
Bit 4
Bit 3
Bit 2
Default Value
Bit 1
0100 0000
Bit 0
DPLL2_dig_
feedback
Bit No.
Description
Bit Value
Value Description
7
Not used.
-
-
6
DPLL2_dig_feedback
Bit to select digital feedback mode for DPLL2.
0
1
DPLL2 in analog feedback mode.
DPLL2 in digital feedback mode.
Not used.
-
-
[5:0]
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Address (hex): 38
Register Name
cnfg_dig_outputs_sonsdh
Bit 7
Bit 6
dig2_sonsdh
Bit No.
Bit 5
FINAL
Description
Configures Digital1 and Digital2
output frequencies to be SONET
or SDH compatible frequencies.
Bit 4
Bit 3
Bit 2
Default Value
Bit 1
0001 0100
Bit 0
dig1_sonsdh
Description
Bit Value
Value Description
7
Not used.
-
-
6
dig2_sonsdh
Selects whether the frequencies generated by the
Digital2 frequency generator are SONET derived or
SDH.
Default value of this bit is set by the SONSDHB pin
at power-up.
0
Digital2 can be selected from 1,544/3,088/6,176/
12,352 kHz.
Digital2 can be selected from 2,048/4,096/8,192/
16,384 kHz.
dig1_sonsdh
Selects whether the frequencies generated by the
Digital1 frequency generator are SONET derived or
SDH.
Default value of this bit is set by the SONSDHB pin
at power-up.
0
Not used.
-
5
[4:0]
1
1
Digital1 can be selected from 1,544/3,088/6,176/
12,352 kHz.
Digital1 can be selected from 2,048/4,096/8,192/
16,384 kHz.
-
Address (hex): 39
Register Name
Bit 7
cnfg_digtial_frequencies
Bit 6
digital2_frequency
Bit No.
Description
Bit 5
(R/W) Configures the actual
Default Value
frequencies of Digital1 & Digital2.
Bit 4
Bit 3
Bit 2
Bit 1
0000 1000
Bit 0
digital1_frequency
Description
Bit Value
Value Description
[7:6]
digital2_frequency
Configures the frequency of Digital2. Whether this is
SONET or SDH based is configured by Bit 6
(dig2_sonsdh) of Reg. 38.
00
01
10
11
Digital2 set to 1,544 kHz or 2,048 kHz.
Digital2 set to 3,088 kHz or 4,096 kHz.
Digital2 set to 6,176 kHz or 8,192 kHz.
Digital2 set to 12,353 kHz or 16,384 kHz.
[5:4]
digital1_frequency
Configures the frequency of Digital1. Whether this is
SONET or SDH based is configured by Bit 5
(dig1_sonsdh) of Reg. 38.
00
01
10
11
Digital1 set to 1,544 kHz or 2,048 kHz.
Digital1 set to 3,088 kHz or 4,096 kHz.
Digital1 set to 6,176 kHz or 8,192 kHz.
Digital1 set to 12,353 kHz or 16,384 kHz.
[3:0]
Not used.
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Address (hex): 3A
Register Name
cnfg_differential_output
Bit 7
Bit 6
Bit 5
FINAL
Description
(R/W) Configures the electrical
Default Value
compatibility of the differential
output driver to be 3 V PECL or 3 V
LVDS.
Bit 4
Bit 3
Bit 2
Bit 1
1100 0010
Bit 0
Output O1_LVDS_PECL
Bit No.
Description
Bit Value
[7:2]
Not used.
-
[1:0]
Output O1_LVDS_PECL
Selection of the electrical compatibility of Output O1
between 3 V PECL and 3 V LVDS.
00
01
10
11
Value Description
Output O1 disabled.
Output O1 3 V PECL compatible.
Output O1 3 V LVDS compatible.
Not used.
Address (hex): 3B
Register Name
Bit 7
cnfg_auto_bw_sel
Bit 6
Description
Bit 5
(R/W) Register to select
Default Value
automatic bandwidth selection for
DPLL1 path
Bit 4
Bit 3
7
[6:4]
3
[2:0]
Bit 1
Bit 0
DPLL1_lim_int
auto_BW_sel
Bit No.
Bit 2
1001 1000
Description
Bit Value
Value Description
auto_BW_sel
Bit to select locked bandwidth (Reg. 67) or
acquisition bandwidth (Reg. 69) for DPLL1.
1
0
Automatically selects either locked or acquisition
bandwidth as appropriate.
Always selects locked bandwidth.
Not used.
-
-
DPLL1_lim_int
When set to 1 the integral path value of DPLL1 is
limited or frozen when DPLL1 reaches either min. or
max. frequency. This can be used to minimise
subsequent overshoot when the DPLL is pulling in.
Note that when this bit is enabled, the reported
frequency value, via current_DPLL_freq (Reg. 0C,
0D and 07), is also frozen.
1
0
DPLL value frozen.
DPLL not frozen.
Not used.
-
-
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Address (hex): 3C
Register Name
cnfg_nominal_frequency
[7:0]
Bit 7
Bit 6
FINAL
Description
Bit 5
(R/W) Bits [7:0] of the register
Default Value
used to calibrate the crystal
oscillator used to clock the device.
Bit 4
Bit 3
Bit 2
1001 1001
Bit 1
Bit 0
cnfg_nominal_frequency_value[7:0]
Bit No.
[7:0]
Description
Bit Value
cnfg_nominal_frequency_value[7:0].
-
Value Description
See register description of Reg. 3D
(cnfg_nominal_frequency_value[15:8]).
Address (hex): 3D
Register Name
Bit 7
cnfg_nominal_frequency
[15:8]
Bit 6
Bit 5
Description
(R/W) Bits [15:8] of the register
Default Value
used to calibrate the crystal
oscillator used to clock the device.
Bit 4
Bit 3
Bit 2
Bit 1
1001 1001
Bit 0
cnfg_nominal_frequency_value[15:8]
Bit No.
[7:0]
Description
Bit Value
cnfg_nominal_frequency_value[15:8]
This register is used in conjunction with Reg. 3C
(cnfg_nominal_frequency_value[7:0].) to be able to
offset the frequency of the crystal oscillator by up to
+514 ppm and –770 ppm. The default value
represents 0 ppm offset from 12.80 MHz.
This value is a 2s-complement signed integer.
Revision 3.00/January 2003 © Semtech Corp.
Page 40
-
Value Description
In order to program the ppm offset of the crystal
oscillator frequency, the value in Reg. 3C and
Reg. 3D need to be concatenated. This value is an
unsigned integer. The value multiplied by
0.0196229 dec. will give the value in ppm. To
calculate the absolute value, the default 39321
(9999 hex) needs to be subtracted.
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Address (hex): 41
Register Name
cnfg_DPLL_freq_limit
[7:0]
Bit 7
Bit 6
FINAL
Description
Bit 5
(R/W) Bits [7:0] of the DPLL
frequency limit register.
Bit 4
Bit 3
Bit 2
Default Value
Bit 1
1111 1111
Bit 0
Bits[7:0] of cnfg_DPLL_freq_limit
Bit No.
[7:0]
Description
Bit Value
Bits [7:0] of cnfg_DPLL_freq_limit
This register defines the extent of frequency offset
to which DPLL1 will track a source before limitingi.e. it represents the pull-in range of the DPLLs. The
offset of the device is determined by the frequency
offset of the DPLL when compared to the offset of
the external crystal oscillator clocking the device. If
the oscillator is calibrated using
cnfg_nominal_frequency Reg. 3C and 3D, then this
calibration is automatically taken into account. The
DPLL frequency limit limits the offset of the DPLL
when compared to the calibrated oscillator
frequency.
-
Value Description
In order to calculate the frequency limit in ppm,
Bit 1 of Reg. 42 and Reg. 41 need to be
concatenated. This value is a unsigned integer and
represents limit both positive and negative in ppm.
The value multiplied by 0.078 will give the value in
ppm.
Address (hex): 42
Register Name
Bit 7
cnfg_DPLL_freq_limit
[9:8]
Bit 6
Description
Bit 5
(R/W) Bits [9:8] of the DPLL
frequency limit register.
Bit 4
Bit 3
Bit 2
Default Value
Bit 1
0000 0011
Bit 0
Bits [9:8] of cnfg_DPLL_freq_limit
Bit No.
Description
Bit Value
Value Description
[7:2]
Not used.
-
-
[1:0]
Bits [9:8] of cnfg_DPLL_freq_limit.
-
See Reg. 41 (cnfg_DPLL_freq_limit) for details.
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Address (hex): 46
Register Name
cnfg_freq_divn
[7:0].
Bit 7
Bit 6
FINAL
Description
Bit 5
(R/W) Bits [7:0] of the division
factor for inputs using the DivN
feature.
Bit 4
Bit 3
Default Value
Bit 2
Bit 1
1111 1111
Bit 0
divn_value [7:0] (divide input frequency by n)
Bit No.
[7:0]
Description
Bit Value
divn_value[7:0].
-
Value Description
See Reg. 47 (cnfg_freq_divn {13:8]) for details.
Address (hex): 47
Register Name
cnfg_freq_divn
[13:8]
Bit 7
Bit 6
Description
Bit 5
(R/W) Bits [13:8] of the division
factor for inputs using the DivN
feature.
Bit 4
Bit 3
Default Value
Bit 2
Bit 1
0011 1111
Bit 0
divn_value [13:8] (divide input frequency by n)
Bit No.
Description
Bit Value
Value Description
[7:6]
Not used.
-
-
[5:0]
divn_value[13:8]
This register, in conjunction with Reg. 46
(cnfg_freq_divn) represents the integer value by
which to divide inputs that use the DivN pre-divider.
The DivN feature supports input frequencies up to a
maximum of 100 MHz; therefore, the maximum
value that should be written to this register is 30D3
hex (12499 dec). Use of higher DivN values may
result in unreliable behaviour.
-
The input frequency will be divided by the value in
this register plus 1. i.e. to divide by 8, program a
value of 7.
Address (hex): 4B
Register Name
Bit 7
cnfg_registers_source_select
Bit 6
Bit 5
Description
(R/W) Register to select the
source of many of the registers.
Bit 4
Bit 3
Bit 2
Default Value
Bit 1
0000 0000
Bit 0
DPLL1_DPLL2_
select
Bit No.
[7:5]
Description
Bit Value
Not used.
Revision 3.00/January 2003 © Semtech Corp.
-
Page 42
Value Description
-
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Address (hex): 4B (cont...)
Register Name
cnfg_registers_source_select
Bit 7
Bit 6
Bit 5
FINAL
Description
(R/W) Register to select the
source of many of the registers.
Bit 4
Bit 3
Bit 2
Default Value
Bit 1
0000 0000
Bit 0
DPLL1_DPLL2_
select
Bit No.
4
[3:0]
Description
Bit Value
Value Description
DPLL1_DPLL2_select
Bit to select between many of the registers
associated with DPLL1 or DPLL2 e.g. frequency
registers.
0
1
DPLL1 registers selected.
DPLL2 registers selected.
Not used.
-
-
Address (hex): 50
Register Name
Bit 7
cnfg_upper_threshold
Bit 6
Description
Bit 5
(R/W) Register to program the
activity alarm setting limit for the
Leaky Bucket Configuration.
Bit 4
Bit 3
Bit 2
Default Value
Bit 1
0000 0110
Bit 0
upper_threshold_value (Activity alarm, Leaky Bucket - set threshold)
Bit No.
[7:0]
Description
Bit Value
upper_threshold_value
The Leaky Bucket operates on a 128 ms cycle. If,
during a cycle, it detects that an input has either
failed or has been erratic, then for each cycle in
which this occurs, the accumulator is incremented
by 1, and for each period of 1, 2, 4, or 8 cycles, as
programmed in Reg. 53 (cnfg_decay_rate), in which
this does not occur, the accumulator is
decremented by 1.
-
Value Description
Value at which the Leaky Bucket will raise an
inactivity alarm.
When the accumulator count reaches the value
programmed as the upper_threshold_value, the
Leaky Bucket raises an input inactivity alarm.
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Address (hex): 51
Register Name
cnfg_lower_threshold
Bit 7
Bit 6
FINAL
Description
Bit 5
(R/W) Register to program the
activity alarm resetting limit for
the Leaky Bucket Configuration.
Bit 4
Bit 3
Bit 2
Default Value
Bit 1
0000 0100
Bit 0
lower_threshold_value (Activity alarm, Leaky Bucket - reset threshold)
Bit No.
[7:0]
Description
Bit Value
lower_threshold_value
The Leaky Bucket operates on a 128 ms cycle. If,
during a cycle, it detects that an input has either
failed or has been erratic, then for each cycle in
which this occurs, the accumulator is incremented
by 1, and for each period of 1, 2, 4, or 8 cycles, as
programmed in Reg. 53 (cnfg_decay_rate), in which
this does not occur, the accumulator is
decremented by 1.
-
Value Description
Value at which the Leaky Bucket will reset an
inactivity alarm.
The lower_threshold_value is the value at which the
Leaky Bucket will reset an inactivity alarm.
Address (hex): 52
Register Name
cnfg_bucket_size
Bit 7
Bit 6
Description
Bit 5
(R/W) Register to program the
maximum size limit for the Leaky
Bucket Configuration.
Bit 4
Bit 3
Bit 2
Default Value
Bit 1
0000 1000
Bit 0
bucket_size_value (Activity alarm, Leaky Bucket - size)
Bit No.
[7:0]
Description
Bit Value
bucket_size_value
The Leaky Bucket operates on a 128 ms cycle. If,
during a cycle, it detects that an input has either
failed or has been erratic, then for each cycle in
which this occurs, the accumulator is incremented
by 1, and for each period of 1, 2, 4, or 8 cycles, as
programmed in Reg. 53 (cnfg_decay_rate), in which
this does not occur, the accumulator is
decremented by 1.
-
Value Description
Value at which the Leaky Bucket will stop
incrementing, even with further inactive periods.
The number in the Bucket cannot exceed the value
programmed into this register.
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Address (hex): 53
Register Name
cnfg_decay_rate
Bit 7
Bit 6
FINAL
Description
Bit 5
(R/W) Register to program the
“decay” or “leak” rate for the
Leaky Bucket Configuration.
Bit 4
Bit 3
Bit 2
Default Value
0000 0001
Bit 1
Bit 0
decay_rate_value (Activity alarm,
Leaky Bucket - leak rate)
Bit No.
Description
Bit Value
[7:2]
Not used.
-
[1:0]
decay_rate_value
The Leaky Bucket operates on a 128 ms cycle. If,
during a cycle, it detects that an input has either
failed or has been erratic, then for each cycle in
which this occurs, the accumulator is incremented
by 1, and for each period of 1, 2, 4, or 8 cycles, as
programmed in this register, in which this does not
occur, the accumulator is decremented by 1.
00
01
10
11
Value Description
Bucket decay rate of 1 every 128 ms.
Bucket decay rate of 1 every 256 ms.
Bucket decay rate of 1 every 512 ms.
Bucket decay rate of 1 every 1,024 ms.
The Leaky Bucket can be programmed to “leak” or
“decay” at the same rate as the “fill” cycle, or
effectively at one half, one quarter, or one eighth of
the fill rate.
Address (hex): 61
Register Name
Bit 7
cnfg_output_frequency
(Output O2)
Bit 6
Description
Bit 5
(R/W) Register to configure and
enable the frequencies available
on Output O2.
Bit 4
Bit 3
Bit 2
Default Value
0000 XXXX
Where XXXX is set by values on
Pins O2_FREQ[2:0], SONSDHB
and O1_FREQ[2:0]. See Note in
[3:0] description.
Bit 1
Bit 0
output_freq_O2
Bit No.
[7:4]
Description
Bit Value
Not used.
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Value Description
-
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Address (hex): 61 (cont...)
Register Name
Bit 7
cnfg_output_frequency
(Output O2)
Bit 6
FINAL
Description
Bit 5
(R/W) Register to configure and
enable the frequencies available
on Output O2.
Bit 4
Bit 3
Bit 2
Default Value
0000 XXXX
Where XXXX is set by values on
Pins O2_FREQ[2:0], SONSDHB
and O1_FREQ[2:0]. See Note in
[3:0] description.
Bit 1
Bit 0
output_freq_O2
Bit No.
[3:0]
Description
Bit Value
output_freq_O2
Configuration of the output frequency available at
Output O2. Many of the frequencies available are
dependent on the frequencies of the APLL1 and the
APLL2. These are configured in Reg. 64 and
Reg. 65. See “Output Frequency Selection by
Register Programming” on page 17.
Note...The values on the pins O2_FREQ [2:0],
SONSDHB and 01_FREQ[2:0] determine the default
output frequency for Output O2, which, at power-up/
reset is written to the cnfg_output_frequency
register. The value in this register can, after the
initialization period (251 ms after PORB goes High),
be changed by writing to it via the serial interface,
however any subsequent reset will cause this
register’s value to be overwritten by whatever value
is on the pins at the time of the reset. See “Output
Frequency Selection by Hardware” and Table 7 on
page 18.
Revision 3.00/January 2003 © Semtech Corp.
Page 46
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Value Description
Output disabled.
2 kHz.
8 kHz.
Digital2 (Reg. 39 cnfg_digital_frequencies).
Digital1 (Reg. 39 cnfg_digital_frequencies).
APLL1 frequency/48.
APLL1 frequency/16.
APLL1 frequency/12.
APLL1 frequency/8.
APLL1 frequency/6.
APLL1 frequency/4.
APLL2 frequency/64.
APLL2 frequency/48.
APLL2 frequency/16.
APLL2 frequency/8.
APLL2 frequency/4.
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Address (hex): 62
Register Name
cnfg_output_frequency
(Output O1)
Bit 7
Bit 6
FINAL
Description
Bit 5
(R/W) Register to configure and
enable the frequencies available
on Output O1.
Bit 4
Bit 3
Bit 2
Default Value
0000 XXXX
Where XXXX is set by values on
Pins O2_FREQ[2:0] and
SONSDHB, See Note in [3:0]
description.
Bit 1
Bit 0
output_freq_O1
Bit No.
[7:4]
Description
Bit Value
output_freq_O1
Configuration of the output frequency available at
Output O1. Many of the frequencies available are
dependent on the frequencies of the APLL1 and the
APLL2. These are configured in Reg. 64 and
Reg. 65. See “Output Frequency Selection by
Register Programming” on page 17.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Note...The values on the pins O1_FREQ [2:0] and
SONSDHB determine the default output frequency
for Output O1, which, at power-up/reset is written to
the cnfg_output_frequency register. The value in
this register can, after the initialization period
(251 ms after PORB goes High), be changed by
writing to it via the serial interface, however any
subsequent reset will cause this register’s value to
be overwritten by whatever value is on the pins at
the time of the reset. See “Output Frequency
Selection by Hardware” and Table 6 on page 18.
[3:0]
Not used.
-
Value Description
Output disabled.
2 kHz.
8 kHz.
APLL1 frequency/2.
Digital1 (Reg. 39 cnfg_digital_frequencies).
APLL1 frequency.
APLL1 frequency/16.
APLL1 frequency/12.
APLL1 frequency/8.
APLL1 frequency/6.
APLL1 frequency/4.
APLL2 frequency/64.
APLL2 frequency/48.
APLL2 frequency/16.
APLL2 frequency/8.
APLL2 frequency/4.
-
Address (hex): 63
Register Name
Bit 7
MFrSync_en
Bit No.
7
cnfg_output_frequency
(MFrSync/FrSync)
Bit 6
Description
Bit 5
(R/W) Register to configure and
enable the frequencies available
on outputs MFrSync and FrSync.
Bit 4
Bit 3
Bit 2
Default Value
Bit 1
1100 0000
Bit 0
FrSync_en
Description
Bit Value
MFrSync_en
Register bit to enable the 2 kHz Sync output
(MFrSync).
Revision 3.00/January 2003 © Semtech Corp.
0
1
Page 47
Value Description
Output MFrSync disabled.
Output MFrSync enabled.
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Address (hex): 63 (cont...)
Register Name
cnfg_output_frequency
(MFrSync/FrSync)
Bit 7
MFrSync_en
Bit No.
6
[5:0]
Bit 6
FINAL
Description
Bit 5
(R/W) Register to configure and
enable the frequencies available
on outputs MFrSync and FrSync.
Bit 4
Bit 3
Default Value
Bit 2
1100 0000
Bit 1
Bit 0
FrSync_en
Description
Bit Value
Value Description
FrSync_en
Register bit to enable the 8 kHz Sync output
(FrSync).
0
1
Output FrSync disabled.
Output FrSync enabled.
Not used.
-
-
Address (hex): 64
Register Name
Bit 7
cnfg_DPLL2_frequency
Bit 6
Description
Bit 5
(R/W) Register to configure DPLL2 Default Value
Frequency
Bit 4
Bit 3
Bit 2
0000 0000
Bit 1
Bit 0
DPLL2_frequency
Bit No.
Description
Bit Value
[7:4]
Not used.
[2:0]
DPLL2_frequency
Register to configure the frequency of operation of
DPLL2. The frequency of DPLL2 will also affect the
frequency of the APLL2 which, in turn, affects the
frequencies available at outputs O1 and O2 see
Reg. 61 and Reg. 62. It is also possible to not use
DPLL2 at all, but use the APLL2 to run directly from
DPLL1 output, see Reg. 65
(cnfg_DPLL1_frequency). If any frequencies are
required from the APLL2 then DPLL2 should not be
squelched, as the APLL2 input is squelched and the
APLL2 will free run.
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Page 48
000
001
010
011
100
101
110
111
Value Description
DPLL2 squelched (clock off).
77.76 MHz (OC-N rates),
APLL2 frequency = 311.04 MHz.
12E1, APLL2 frequency = 98.304 MHz.
16E1, APLL2 frequency = 131.072 MHz.
24DS1, APLL2 frequency = 148.224 MHz.
16DS1, APLL2 frequency = 98.816 MHz.
E3, APLL2 frequency = 274.944 MHz.
DS3, APLL2 frequency = 178.944 MHz.
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Address (hex): 65
Register Name
cnfg_DPLL1_frequency
Bit 7
Bit 6
APLL2_for_
DPLL1_E1/DS1
Bit No.
FINAL
Description
Bit 5
(R/W) Register to configure DPLL1 Default Value
and MUX2 parameters.
Bit 4
Bit 3
Bit 2
DPLL1_freq_to_APLL2
0000 0001
Bit 1
Bit 0
DPLL1_frequency
Description
Bit Value
Value Description
7
Not used.
-
-
6
APLL2_for_DPLL1_E1/DS1
Register bit to control MUX2 which selects whether
the APLL2 takes its input from DPLL2 or DPLL1. If
DPLL1 is selected then the frequency is controlled
by Bits [5:4], DPLL1_freq_to_APLL2.
0
1
APLL2 takes its input from DPLL2.
APLL2 takes its input from DPLL1.
[5:4]
DPLL1_freq_to_APLL2
Register to select the frequency/mode of DPLL1
which is driven to the APLL2 when selected by Bit 6,
APLL2_for_DPLL1_E1/DS1.
00
01
10
11
12E1, APLL2 frequency = 98.304 MHz.
16E1, APLL2 frequency = 131.072 MHz.
24DS1, APLL2 frequency = 148.224 MHz.
16DS1, APLL2 frequency = 98.816 MHz.
3
[2:0]
Not used.
-
DPLL1_frequency
Register to configure the frequency of operation of
DPLL1/APLL1. This register affects the frequencies
available at outputs O1 and O2, see Reg. 61 and
Reg. 62.
000
001
010
011
100
101
110
111
77.76 MHz, digital feedback,
APLL1 frequency = 311.04 MHz.
77.76 MHz, analog feedback, (via APLL3)
APLL1 frequency = 311.04 MHz.
12E1, APLL1 frequency = 98.304 MHz.
16E1, APLL1 frequency = 131.072 MHz.
24DS1, APLL1 frequency = 148.224 MHz.
16DS1, APLL1 frequency = 98.816 MHz.
Not used.
Not used.
Note...001 is the only selection that does not bypass
APLL3. All other selections use digital feedback.
Address (hex): 66
Register Name
cnfg_DPLL2_bw
Bit 7
Bit 6
Description
Bit 5
(R/W) Register to configure the
bandwidth of DPLL2.
Bit 4
Bit 3
Bit 2
Default Value
Bit 1
0000 0000
Bit 0
DPLL2_bandwidth
Bit No.
[7:2]
Description
Bit Value
Not used.
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Address (hex): 66 (cont...)
Register Name
cnfg_DPLL2_bw
Bit 7
Bit 6
FINAL
Description
Bit 5
(R/W) Register to configure the
bandwidth of DPLL2.
Bit 4
Bit 3
Bit 2
Default Value
Bit 1
0000 0000
Bit 0
DPLL2_bandwidth
Bit No.
[1:0]
Description
Bit Value
DPLL2_bandwidth
Register to configure the bandwidth of DPLL2.
00
01
10
11
Value Description
DPLL2 18 Hz bandwidth.
DPLL2 35 Hz bandwidth.
DPLL2 70 Hz bandwidth.
Not used.
Address (hex): 67
Register Name
cnfg_DPLL1_locked_bw
Bit 7
Bit 6
Bit 5
Description
(R/W) Register to configure the
Default Value
bandwidth of DPLL1, when phase
locked to an input.
Bit 4
Bit 3
Bit 2
Bit 1
0001 0000
Bit 0
DPLL1_locked_bandwidth
Bit No.
Description
Bit Value
[7:2]
Not used.
-
[1:0]
DPLL1_locked_bandwidth
Register to configure the bandwidth of DPLL1 when
locked to an input reference. Reg. 3B Bit 7 is used
to control whether this bandwidth is used all of the
time or automatically switched to when phase
locked.
11
00
01
10
Value Description
DPLL1, 18 Hz locked bandwidth.
DPLL1, 35 Hz locked bandwidth.
DPLL1, 70 Hz locked bandwidth.
Not used.
Address (hex): 69
Register Name
Bit 7
cnfg_DPLL1_acq_bw
Bit 6
Description
Bit 5
(R/W) Register to configure the
bandwidth of DPLL1, when not
phase locked to an input.
Bit 4
Bit 3
Bit 2
Default Value
Bit 1
0001 0001
Bit 0
DPLL1_acquisition_bandwidth
Bit No.
[7:4]
Description
Bit Value
Not used.
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Address (hex): 69 (cont...)
Register Name
cnfg_DPLL1_acq_bw
Bit 7
Bit 6
FINAL
Description
Bit 5
(R/W) Register to configure the
bandwidth of DPLL1, when not
phase locked to an input.
Bit 4
Bit 3
Default Value
Bit 2
0001 0001
Bit 1
Bit 0
DPLL1_acquisition_bandwidth
Bit No.
[3:0]
Description
Bit Value
DPLL1_acquisition_bandwidth
Register to configure the bandwidth of DPLL1 when
acquiring phase lock on an input reference. Reg. 3B
Bit 7 is used to control whether this bandwidth is
not used or automatically switched to when not
phase locked.
11
00
01
10
Value Description
DPLL1, 18 Hz acquisition bandwidth.
DPLL1, 35 Hz acquisition bandwidth.
DPLL1, 70 Hz acquisition bandwidth.
Not used.
Address (hex): 6A
Register Name
Bit 7
cnfg_DPLL2_damping
Bit 6
Description
Bit 5
(R/W) Register to configure the
damping factor of DPLL2, along
with the gain of Phase Detector 2
in some modes.
Bit 4
Bit 3
Bit 2
DPLL2_PD2_gain_alog
Bit No.
7
[6:4]
3
Default Value
0001 0011
Bit 1
Bit 0
DPLL2_damping
Description
Bit Value
Value Description
Not used.
-
-
DPLL2_PD2_gain_alog
Register to control the gain of the Phase Detector 2
This setting is only used if Reg. 6C Bit 7,
cnfg_DPLL2_PD2_gain is enabled.
-
Gain value of the Phase Detector 2 when locking to
an 8 kHz reference in analog feedback mode.
Not used.
-
-
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Address (hex): 6A (cont...)
Register Name
cnfg_DPLL2_damping
Bit 7
Bit 6
FINAL
Description
Bit 5
(R/W) Register to configure the
damping factor of DPLL2, along
with the gain of Phase Detector 2
in some modes.
Bit 4
Bit 3
Bit 2
DPLL2_PD2_gain_alog
Bit No.
[2:0]
Bit Value
DPLL2_damping
Register to configure the damping factor of DPLL2.
The bit values correspond to different damping
factors, depending on the bandwidth selected.
Bit 1
Bit 0
Value Description
Damping Factor Damping Factor Damping Factor
for Bandwidth
for Bandwidth
for Bandwidth
of 18 Hz:
of 35 Hz:
of 70 Hz:
001
1.2
1.2
1.2
010
2.5
2.5
2.5
011
5
5
5
Gain Peak
100
5
10
10
0.4 dB
0.2 dB
0.1 dB
0.06 dB
0.03 dB
101
5
10
20
Default Value
0001 0100
The Gain Peak for the Damping Factors given in the
Value Description (right) are tabulated below:
1.2
2.5
5
10
20
0001 0011
DPLL2_damping
Description
Damping Factor
Default Value
Address (hex): 6B
Register Name
Bit 7
cnfg_DPLL1_damping
Bit 6
Description
Bit 5
(R/W) Register to configure the
damping factor of DPLL1, along
with the gain of the Phase
Detector 2 in some modes.
Bit 4
Bit 3
Bit 2
DPLL1_PD2_gain_alog_8k
Bit No.
7
[6:4]
3
Bit 1
Bit 0
DPLL1_damping
Description
Bit Value
Value Description
Not used.
-
-
DPLL1_PD2_gain_alog_8k
Register to control the gain of the Phase Detector 2
when locking to a reference of 8 kHz or less in
analog feedback mode. This setting is only used if
automatic gain selection is enabled in Reg. 6D Bit 7,
cnfg_DPLL1_PD2_gain.
-
Gain value of the Phase Detector 2 when locking to
an 8 kHz reference in analog feedback mode.
Not used.
-
-
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Address (hex): 6B (cont...)
Register Name
cnfg_DPLL1_damping
Bit 7
Bit 6
FINAL
Description
Bit 5
(R/W) Register to configure the
damping factor of DPLL1, along
with the gain of the Phase
Detector 2 in some modes.
Bit 4
Bit 3
Bit 2
[2:0]
0001 0100
Bit 1
DPLL1_PD2_gain_alog_8k
Bit No.
Default Value
Bit 0
DPLL1_damping
Description
Bit Value
DPLL1_damping
Register to configure the damping factor of DPLL1.
The bit values correspond to different damping
factors, depending on the bandwidth selected.
Value Description
Damping Factor Damping Factor Damping Factor
for Bandwidth
for Bandwidth
for Bandwidth
of 18 Hz:
of 35 Hz:
of 70 Hz:
The Gain Peak for the Damping Factors given in the
Value Description (right) are the same as those
tabulated in the description for Reg. 6A.
001
1.2
1.2
1.2
010
2.5
2.5
2.5
011
5
5
5
100
5
10
10
101
5
10
20
Default Value
1100 0010
Address (hex): 6C
Register Name
Bit 7
cnfg_DPLL2_PD2_gain
Bit 6
Description
Bit 5
(R/W) Register to configure the
gain of Phase Detector 2 in some
modes for DPLL2.
Bit 4
Bit 3
Bit 2
DPLL2_PD2_
gain_enable
Bit No.
7
Bit 1
Bit 0
DPLL2_PD2_gain_digital
Description
Bit Value
Value Description
DPLL2_PD2_gain_enable
0
1
DPLL2 Phase Detector 2 not used.
DPLL2 Phase Detector 2 gain enabled and choice of
gain determined according to the locking mode:
- digital feedback mode
- analog feedback mode
[6:3]
Not used.
-
-
[2:0]
DPLL2_PD2_gain_digital
Register to control the gain of Phase Detector 2
when locking in digital feedback mode. This setting
is always used if gain is disabled in Bit 7,
DPLL2_PD2_gain_enable.
-
Gain value of Phase Detector 2 when locking in
digital feedback mode.
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Address (hex): 6D
Register Name
Bit 7
cnfg_DPLL1_PD2_gain
Bit 6
DPLL1_PD2_
gain_enable
Bit No.
7
[6:4]
3
[2:0]
FINAL
Description
Bit 5
(R/W) Register to configure the
gain of Phase Detector 2 in some
modes for DPLL1.
Bit 4
Bit 3
Bit 2
Default Value
1100 0010
Bit 1
Bit 0
DPLL1_PD2_gain_digital
DPLL1_PD2_gain_alog
Description
Bit Value
DPLL1_PD2_gain_enable
Value Description
0
DPLL1 Phase Detector 2 not used.
1
DPLL1 Phase Detector 2 gain enabled and choice of
gain determined according to the locking mode:
- digital feedback mode
- analog feedback mode
- analog feedback at 8 kHz
DPLL1_PD2_gain_alog
Register to control the gain of Phase Detector 2
when locking to a reference, higher than 8 kHz, in
analog feedback mode. This setting is not used if
automatic gain selection is disabled in Bit 7,
DPLL1_PD2_gain_enable.
-
Gain value of Phase Detector 2 when locking to a
high frequency reference in analog feedback mode.
Not used.
-
-
DPLL1_PD2_gain_digital
Register to control the gain of Phase Detector 2
when locking to a reference in digital feedback
mode. Automatic gain selection must be enabled
(Bit 7, DPLL1_PD2_gain_enable), for
DPLL1_PD2_gain_digital to have any effect.
-
Gain value of Phase Detector 2 when locking to any
reference in digital feedback mode.
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Address (hex): 73
Register Name
Bit 7
fine_limit_en
Bit No.
cnfg_phase_loss_fine_limit
Bit 6
noact_ph_loss
Bit 5
FINAL
Description
(R/W) Register to configure some
of the parameters of the DPLL
phase detectors.
Bit 4
Bit 3
Bit 2
Default Value
1010 0010
Bit 1
Bit 0
phase_loss_fine_limit
narrow_en
Description
Bit Value
Value Description
7
fine_limit_en
Register bit to enable the phase_loss_fine_limit
Bits [2:0]. When disabled, phase lock/loss is
determined by the other means within the device.
This must be disabled when multi-UI jitter tolerance
is required, see Reg. 74,
cnfg_phase_loss_course_limit.
0
1
Phase loss indication only triggered by other means.
Phase loss triggered when phase error exceeds the
limit programmed in phase_loss_fine_limit,
Bits [2:0].
6
noact_ph_loss
The DPLL detects that an input has failed very
rapidly. Normally, when the DPLL detects this
condition, it does not consider phase lock to be lost
and will phase lock to the nearest edge (± 180º)
when a source becomes available again, hence
giving tolerance to missing cycles. If phase loss is
indicated, then frequency and phase locking is
instigated (± 360º locking). This bit can be used to
force the DPLL to indicate phase loss immediately
when no activity is detected.
0
1
No activity on reference does not trigger phase lost
indication.
No activity triggers phase lost indication.
narrow_en (test control bit)
Set to 1 (default value).
0
1
Do not use.
Set to 1.
[4:3]
Not used.
-
-
[2:0]
phase_loss_fine_limit
When enabled by Bit 7, this register coarsely sets
the phase limit at which the device indicates phase
lost or locked. The default value of 2 (010) gives a
window size of around ± 90 - 180º. The phase
position of the inputs to the DPLL has to be within
the window limit for 1 – 2 seconds before the device
indicates phase lock. If it is outside the window for
any time then phase loss is immediately indicated.
For most cases the default value of 2 (010) is
satisfactory. The window size changes in proportion
to the value, so a value of 1 (001) will give a narrow
phase acceptance or lock window of approximately
± 45 - 90º.
5
Revision 3.00/January 2003 © Semtech Corp.
Page 55
000
001
010
011
100
101
110
111
Do not use. Indicates phase loss continuously.
Small phase window for phase lock indication.
Recommended value.
)
)
) Larger phase window for phase lock indication.
)
)
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Address (hex): 74
Register Name
Bit 7
coarse_lim_
phaseloss_en
Bit No.
7
cnfg_phase_loss_coarse_limit
Bit 6
wide_range_en
Bit 5
FINAL
Description
(R/W) Register to configure some
of the parameters of DPLL phase
detectors.
Bit 4
Bit 3
Bit 2
Default Value
Bit 1
1110 0101
Bit 0
phase_loss_coarse_limit
multi_ph_resp
Description
Bit Value
Value Description
coarse_lim_phaseloss_en
Register bit to enable the coarse phase detector,
whose range is determined by
phase_loss_coarse_limit Bits [3:0]. This register
sets the limit in the number of input clock cycles (UI)
that the input phase can move by before the DPLL
indicates phase lost.
0
1
Phase loss not triggered by the coarse phase lock
detector.
Phase loss triggered when phase error exceeds the
limit programmed in phase_loss_coarse_limit,
Bits [3:0].
6
wide_range_en
To enable the device to be tolerant to large amounts
of applied jitter and still do direct phase locking at
the input frequency rate (up to 77.76 MHz), a wide
range phase detector and phase lock detector is
employed. This bit enables the wide range phase
detector. This allows the device to be tolerant to,
and therefore keep track of, drifts in input phase of
many cycles (UI). The range of the phase detector is
set by the same register used for the phase loss
coarse limit (Bits [3:0]).
0
1
Wide range phase detector off.
Wide range phase detector on.
5
multi_ph_resp
Enables the phase result from the coarse phase
detector to be used in the DPLL algorithm. Bit 6
should also be set when this is activated. The
coarse phase detector can measure and keep track
over many thousands of input cycles, thus allowing
excellent jitter and wander tolerance. This bit
enables that phase result to be used in the DPLL
algorithm, so that a large phase measurement gives
a faster pull-in of the DPLL. If this bit is not set then
the phase measurement is limited to ± 360º which
can give a slower pull-in rate at higher input
frequencies, but could also be used to give less
overshoot.
Setting this bit in direct locking mode, for example
with a 19.44 MHz input, would give the same
dynamic response as a 19.44 MHz input used with
8 k locking mode, where the input is divided down
internally to 8 kHz first.
0
DPLL phase detector limited to ± 360º (± 1 UI).
However it will still remember its original phase
position over many thousands of UI if Bit 6 is set.
1
DPLL phase detector also uses the full coarse
phase detector result. It can now measure up to:
± 360º x 8191 UI = ± 2,948,760º.
Not used.
-
-
4
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Address (hex): 74 (cont...)
Register Name
cnfg_phase_loss_coarse_limit
Bit 7
coarse_lim_
phaseloss_en
Bit No.
[3:0]
Bit 6
wide_range_en
Bit 5
FINAL
Description
(R/W) Register to configure some
of the parameters of DPLL phase
detectors.
Bit 4
Bit 3
Bit 2
Default Value
Bit 1
1110 0101
Bit 0
phase_loss_coarse_limit
multi_ph_resp
Description
Bit Value
phase_loss_coarse_limit
Sets the range of the coarse phase loss detector
and the coarse phase detector.
When locking to a high frequency signal, and jitter
tolerance greater than 0.5 UI is required, then the
DPLL can be configured to track phase errors over
many input clock periods. This is particularly useful
with very low bandwidths. This register configures
how many UI over which the input phase can be
tracked. It also sets the range of the coarse phase
loss detector, which can be used with or without the
multi-UI phase capture range capability.
This register value is used by Bits 6 and 7.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100-1111
Value Description
Input phase error tracked over ± 1 UI.
Input phase error tracked over ± 3 UI.
Input phase error tracked over ± 7 UI.
Input phase error tracked over ± 15 UI.
Input phase error tracked over ± 31 UI.
Input phase error tracked over ± 63 UI.
Input phase error tracked over ± 127 UI.
Input phase error tracked over ± 255 UI.
Input phase error tracked over ± 511 UI.
Input phase error tracked over ± 1023 UI.
Input phase error tracked over ± 2047 UI.
Input phase error tracked over ± 4095 UI.
Input phase error tracked over ± 8191 UI.
Address (hex): 76
Register Name
Bit 7
cnfg_ip_noise_window
Bit 6
Description
Bit 5
(R/W) Register to enable the
noise rejection function for low
frequency inputs.
Bit 4
Bit 3
Bit 2
Default Value
Bit 1
0000 0110
Bit 0
ip_noise_
window_en
Bit No.
7
[6:0]
Description
Bit Value
Value Description
ip_noise_window_en
Register bit to enable a window of 5% tolerance
around low-frequency inputs (2, 4 and 8 kHz). This
feature ensures that any edge caused by noise
outside the 5% window where the edge is expected
will not be considered within the DPLL. This reduces
any possible phase hit when a low-frequency
connection is removed and contact bounce is
possible.
0
1
DPLL considers all edges for phase locking.
DPLL ignores input edges outside a 95% to 105%
window.
Not used.
-
-
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ADVANCED COMMUNICATION
Address (hex): 7A
Register Name
Bit 7
cnfg_sync_pulses
Bit 6
FINAL
Description
Bit 5
(R/W) Register to configure the
Sync outputs available from
FrSync and MFrSync and select
the source for the 2 kHz and
8 kHz outputs from O1 and O2.
Bit 4
Bit 3
8k_invert
2k_8k_from_
DPLL2
Bit No.
7
Description
Bit Value
Bit 2
8k_pulse
Default Value
0000 0000
Bit 1
Bit 0
2k_invert
2k_pulse
Value Description
2k_8k_from_DPLL2
Register to select the source (DPLL1 or DPLL2) for
the 2 kHz and 8 kHz outputs available from O1 and
O2.
0
1
2/8 kHz on O1 and O2 generated from DPLL1.
2/8 kHz on O1 and O2 generated from DPLL2.
Not used.
-
-
3
8k_invert
Register bit to invert the 8 kHz output from FrSync.
0
1
8 kHz FrSync output not inverted.
8 kHz FrSync output inverted.
2
8k_pulse
Register bit to enable the 8 kHz output from FrSync
to be either pulsed or 50:50 duty cycle. Output 02
must be enabled to use “pulsed output” mode on
the FrSync output, and then the pulse width on the
FrSync output will be equal to the period of the
output programmed on O2.
0
1
8 kHz FrSync output not pulsed.
8 kHz FrSync output pulsed.
1
2k_invert
Register bit to invert the 2 kHz output from MFrSync.
0
1
2 kHz MFrSync output not inverted.
2 kHz MFrSync output inverted.
0
2k_pulse
Register bit to enable the 2 kHz output from
MFrSync to be either pulsed or 50:50 duty cycle.
Output 03 must be enabled to use “pulsed output”
mode on the MFrSync output, and then the pulse
width on the MFrSync output will be equal to the
period of the output programmed on O3.
0
1
2 kHz MFrSync output not pulsed.
2 kHz MFrSync output pulsed.
[6:4]
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ADVANCED COMMUNICATION
Address (hex): 7D
Register Name
cnfg_LOS_alarm
Bit 7
Bit 6
FINAL
Description
Bit 5
(R/W) Register to configure LOS
(Loss of Signal) Alarm.
Bit 4
Bit 3
Bit 2
LOS_GPO_en
Bit No.
[7:3]
Description
Bit Value
Default Value
Bit 1
0000 0010
Bit 0
LOS_tristate_en LOS_
polarity
Value Description
Not used.
-
-
2
LOS_GPO_en
(General Purpose Output). If the LOS_ALARM output
pin is not required, then setting this bit will allow the
pin to be used as a general purpose output. The pin
will be driven to the state of the polarity control bit,
int_polarity.
0
1
LOS_ALARM output pin used for interrupts.
LOS_ALARM output pin used for GPO purpose.
1
LOS_tristate_en
The LOS_ALARM pin can be configured to be either
connected directly to a processor, or wired together
with other sources.
0
1
LOS_ALARM pin always driven when inactive.
LOS_ALARM pin only driven when active, highimpedance when inactive.
0
LOS_polarity
The LOS_ALARM pin can be configured to be active
High or Low.
0
1
Active Low - pin driven Low to indicate active alarm.
Active High - pin driven High to indicate active alarm.
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ADVANCED COMMUNICATION
Address (hex): 7E
Register Name
cnfg_protection
Bit 7
Bit 6
FINAL
Description
Bit 5
(R/W) Protection register to
protect against erroneous
software writes.
Bit 4
Bit 3
Default Value
Bit 2
Bit 1
1000 0101
Bit 0
protection_value
Bit No.
[7:0]
Description
Bit Value
protection_value
This register can be used to ensure that the
software writes a specific value to this register,
before being able to modify any other register in the
device. Three modes of protection are offered,
(i) protected,
(ii) fully unprotected,
(iii) single unprotected.
When protected, no other register in the device can
be written to. When fully unprotected, any writeable
register in the device can be written to. When single
unprotected, only one register can be written before
the device automatically re-protects itself.
Note...This register cannot be protected.
Revision 3.00/January 2003 © Semtech Corp.
Value Description
0000 0000 –
1000 0100
Protected mode.
1000 0101
Fully unprotected.
1000 0110
Single unprotected.
1000 0111 –
1111 1111
Protected mode.
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ACS8526 LC/P LITE
ADVANCED COMMUNICATION
Electrical Specifications
FINAL
JTAG
Over-voltage Protection
The JTAG connections on the ACS8526 allow a full
boundary scan to be made. The JTAG implementation is
fully compliant to IEEE 1149.1[4], with the following minor
exceptions, and the user should refer to the standard for
further information.
The ACS8526 may require Over-voltage Protection on
input reference clock ports according to ITU
recommendation K.41[10]. Semtech protection devices
are recommended for this purpose (see separate
Semtech data book).
1. The output boundary scan cells do not capture data
from the core, and so do not support EXTEST.
However this does not affect board testing.
2. In common with some other manufacturers, pin TRST
is internally pulled Low to disable JTAG by default. The
standard is to pull High. The polarity of TRST is as the
standard: TRST High to enable JTAG boundary scan
mode, TRST Low for normal operation.
The JTAG timing diagram is shown in Figure 9.
Figure 9
JTAG Timing
tCYC
TCK
tSUR
tHT
TMS
TDI
tDOD
TDO
F8110D_022JTAGTiming_01
Table 18 JTAG Timing (for use with Figure 9)
Parameter
Symbol
Minimum
Typical
Maximum
Units
Cycle Time
tCYC
50
-
-
ns
TMS/TDI to TCK rising edge time
tSUR
3
-
-
ns
TCK rising to TMS/TDI hold time
tHT
23
-
-
ns
tDOD
-
-
5
ns
TCK falling to TDO valid
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ADVANCED COMMUNICATION
Maximum Ratings
FINAL
Important Note: The Absolute Maximum Ratings, Table 19, are stress ratings only, and functional operation of the
device at conditions other than those indicated in the Operating Conditions sections of this specification are not
implied. Exposure to the absolute maximum ratings for an extended period may reduce the reliability or useful lifetime
of the product.
Table 19 Absolute Maximum Ratings
Parameter
Symbol
Minimum
Maximum
Units
Supply Voltage VDD1, VDD2, VDD3,
VD1+,VD2+, VD3+, VA1+, VA2+, VA3+,
VDD_DIFF
VDD
-0.5
3.6
V
Input Voltage (non-supply pins)
VIN
-
5.5
V
VOUT
-
5.5
V
Output Voltage (non-supply pins)
TA
-40
+85
oC
TSTOR
-50
+150
oC
Ambient Operating Temperature Range
Storage Temperature
Operating Conditions
Table 20 Operating Conditions
Parameter
Symbol
Minimum
Typical
Maximum
Units
VDD
3.0
3.3
3.6
V
VDD5V
3.0
3.3/5.0
5.5
V
Ambient Temperature Range
TA
-40
-
+85
oC
Supply Current
(Typical - one 19 MHz output)
IDD
110
200
mA
Total Power Dissipation
PTOT
360
720
mW
Power Supply (dc voltage)
VDD1, VDD2, VDD3, VD1+,VD2+, VD3+,
VA1+, VA2+, VA3+, VDD_DIFF
Power Supply (dc voltage) VDD5V
DC Characteristics
Table 21 DC Characteristics: TTL Input Port
Across all operating conditions, unless otherwise stated
PARAMETER
Symbol
Minimum
Typical
Maximum
Units
VIN High
VIH
2
-
-
V
VIN Low
VIL
-
-
0.8
V
Input Current
IIN
-
-
10
µA
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ADVANCED COMMUNICATION
FINAL
Table 22 DC Characteristics: TTL Input Port with Internal Pull-up
Across all operating conditions, unless otherwise stated
Parameter
Symbol
Minimum
Typical
Maximum
Units
VIN High
VIH
2
-
-
V
VIN Low
VIL
-
-
0.8
V
Pull-up Resistor
PU
30
-
80
kΩ
Input Current
IIN
-
-
120
µΑ
Table 23 DC Characteristics: TTL Input Port with Internal Pull-down
Across all operating conditions, unless otherwise stated
Parameter
Symbol
Minimum
Typical
Maximum
Units
VIN High
VIH
2
-
-
V
VIN Low
VIL
-
-
0.8
V
Pull-down Resistor
PD
30
-
80
kΩ
Input Current
IIN
-
-
120
µA
Symbol
Minimum
Typical
Maximum
Units
VOUT Low (lOL = 4mA)
VOL
0
-
0.4
V
VOUT High (lOH = 4mA)
VOH
2.4
-
-
V
ID
-
-
4
mA
Symbol
Minimum
Typical
Maximum
Units
PECL Output Low Voltage (Note (i))
VOLPECL
VDD-2.10
-
VDD-1.62
V
PECL Output High Voltage (Note (i))
VOHPECL
VDD-1.25
-
VDD-0.88
V
PECL Output Differential Voltage (Note (i))
VODPECL
580
-
900
mV
Table 24 DC Characteristics: TTL Output Port
Across all operating conditions, unless otherwise stated
Parameter
Drive Current
Table 25 DC Characteristics: PECL Output Port
Across all operating conditions, unless otherwise stated
Parameter
Note:
(i) With 50 Ω load on each pin to VDD-2 V, i.e. 82 Ω to GND and 130 Ω to VDD.
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ADVANCED COMMUNICATION
FINAL
Figure 10 Recommended Line Termination for PECL Output Port
V DD
130 Ω
ZO=50Ω
O1POS
82 Ω
130 Ω
Fully
Programmable
Output Frequencies
O1NEG
ZO=50Ω
82 Ω
GND
V DD = +3.3 V
F8522D_024PECL_01
Table 26 DC Characteristics: LVDS Output Port
Across all operating conditions, unless otherwise stated
Parameter
Symbol
Minimum
Typical
Maximum
Units
LVDS Output High Voltage
(Note (i))
VOHLVDS
-
-
1.585
V
LVDS Output Low Voltage
(Note (i))
VOLLVDS
0.885
-
-
V
LVDS Differential Output Voltage
VODLVDS
250
-
450
mV
LVDS Change in Magnitude of Differential
Output Voltage for complementary States
(Note (i))
VDOSLVDS
-
-
25
mV
LVDS Output Offset Voltage
Temperature = 25oC (Note (i))
VOSLVDS
1.125
-
1.275
V
Notes: (i) With 100 Ω load between the differential outputs.
Figure 11 Recommended Line Termination for LVDS Output Port
ZO = 50 Ω
O1POS
100 Ω
Fully
Programmable
Output Frequencies
01NEG
ZO = 50 Ω
F8522D_025LVDS_02
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ADVANCED COMMUNICATION
Jitter Performance
FINAL
Output jitter generation measured over 60 second interval, UI pk-pk max measured using C-MAC E2747 12.8 MHz
TCXO on ICT Flexacom tester.
Table 27 Output Jitter Generation at 35 Hz bandwidth and 8 kHz Input
Test Definition
Specification
Filter
Jitter Spec
ACS8526 Jitter
UI
UI (TYP)
G813[8] for 155 MHz o/p option 1
65 kHz - 1.3 MHz
0.1 pk-pk
0.073 pk-pk
G813[8] & G812[7] for 2.048 MHz option 1
20 Hz - 100 kHz
0.05 pk-pk
0.012 pk-pk
12 kHz - 1.3 MHz
0.1 pk-pk
0.069 pk-pk
G812[7] for 1.544 MHz o/p
10 Hz - 40 kHz
0.05 pk-pk
0.011 pk-pk
G812[7] for 155 MHz electrical
500 Hz - 1.3 MHz
0.5 pk-pk
0.083 pk-pk
G812[7] for 155 MHz electrical
65 kHz - 1.3 MHz
0.075 pk-pk
0.073pk-pk
for 2.048 MHz SEC o/p
20 Hz - 100 kHz
0.5 pk-pk
0.012 pk-pk
ETS-300-462-3[2] for 2.048 MHz SEC o/p
49 Hz - 100 kHz
0.2 pk-pk
0.012 pk-pk
ETS-300-462-3[2] for 2.048 MHz SSU o/p
20 Hz - 100 kHz
0.05 pk-pk
0.012 pk-pk
ETS-300-462-5[3] for 155 MHz o/p
500 Hz - 1.3 MHz
0.5 pk-pk
0.083 pk-pk
ETS-300-462-5[3] for 155 MHz o/p
65 kHz - 1.3 MHz
0.1 pk-pk
0.073 pk-pk
GR-253-CORE[11] net i/f, 51.84 MHz o/p
100 Hz - 0.4 MHz
1.5 pk-pk
0.038 pk-pk
GR-253-CORE[11] net i/f, 51.84 MHz o/p
20 kHz to 0.4 MHz
0.15 pk-pk
0.019 pk-pk
GR-253-CORE[11] net i/f, 155 MHz o/p
500 Hz - 1.3 MHz
1.5 pk-pk
0.083 pk-pk
65 kHz - 1.3 MHz
0.15 pk-pk
0.073 pk-pk
12 kHz - 1.3 MHz
0.1 pk-pk
0.069 pk-pk
0.01 rms
0.009 rms
0.1 pk-pk
0.008 pk-pk
0.01 rms
0.004 rms
0.1 pk-pk
0.001 pk-pk
0.01 rms
<0.001 rms
G813
[8]
for 155 MHz o/p option 2
ETS-300-462-3
GR-253-CORE
[2]
[11] net
i/f, 155 MHz o/p
GR-253-CORE[11] cat II elect i/f, 155 MHz
GR-253-CORE[11] cat II elect i/f, 51.84 MHz
GR-253-CORE[11] DS1 i/f, 1.544 MHz
12 kHz - 400 kHz
10 Hz - 40 kHz
AT&T 62411[1] for 1.544 MHz
10 Hz - 8 kHz
0.02 rms
<0.001 rms
AT&T 62411[1] for 1.544 MHz
8 Hz - 40 kHz
0.025 rms
<0.001 rms
AT&T 62411[1] for 1.544 MHz
10 Hz - 40 kHz
0.025 rms
<0.001 rms
AT&T 62411[1] for 1.544 MHz
Broadband
0.05 rms
<0.001 rms
G-742[6] for 2.048 MHz
DC - 100 kHz
0.25 rms
0.012 rms
18 kHz - 100 kHz
0.05 pk-pk
0.012 pk-pk
20 Hz - 100 kHz
0.05 pk-pk
0.012 pk-pk
G-742
[6]
for 2.048 MHz
G-736[5] for 2.048 MHz
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ADVANCED COMMUNICATION
FINAL
Table 27 Output Jitter Generation at 35 Hz bandwidth and 8 kHz Input (cont...)
Test Definition
Specification
GR-499-CORE
[12]
& G824
[9]
Filter
Jitter Spec
ACS8526 Jitter
UI
UI (TYP)
for 1.544 MHz
10 Hz - 40kHz
5.0 pk-pk
0.001 pk-pk
GR-499-CORE[12] & G824[9] for 1.544 MHz
8 kHz - 40kHz
0.1 pk-pk
0.001 pk-pk
GR-1244-CORE[13] for 1.544 MHz
> 10 Hz
0.05 pk-pk
0.001 pk-pk
Note...This table is only for comparing the ACS8526 output jitter performance against values and quoted in various specifications for given
conditions. It should not be used to infer compliance to any other aspects of these specifications.
Revision 3.00/January 2003 © Semtech Corp.
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ACS8526 LC/P LITE
ADVANCED COMMUNICATION
Input/Output Timing
FINAL
Figure 12 Input/Output Timing (Typical Conditions)
Input/Output
Typical Delay
Output
8 kHz input
Typical Phase Alignment
(FrSync Alignment switched on)
FrSync (8 kHz)
8.2 ns
8 kHz output
MFrSync (2 kHz)
+0.3 ns
6.48 MHz input
4.7 ns
8 kHz
6.48 MHz output
19.44 MHz input
+0.6 ns
2 kHz
+1.0 ns
DS1 (1.544 MHz)
+0.3 ns
E1 (2.048 MHz)
+0.3 ns
DS3 (44.736 MHz)
-2.4 ns
E3 (34.368 MHz)
-2.65 ns
6.48 MHz
-2.4 ns
19.44 MHz
-2.4 ns
25.92 MHz
-2.4 ns
38.88 MHz
-2.4 ns
51.84 MHz
-2.4 ns
77.76 MHz
-2.4 ns
155.52 MHz
-2.5 ns
311.04 MHz
-2.5 ns
4.3 ns
19.44 MHz output
25.92 MHz input
4.7 ns
25.92 MHz output
38.88 MHz input
4.6 ns
38.88 MHz output
51.84 MHz input
3.0 ns
51.84 MHz output
77.76 MHz input
5.3 ns
77.76 MHz output
Typical Conditions: 25 deg. C, 3.3 V
F8526D_021IP_OPTiming_02
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ACS8526 LC/P LITE
ADVANCED COMMUNICATION
Package Information
FINAL
Figure 13 LQFP Package
D
2
D1 1
3
AN2
AN3
1
Section A-A
R1
S
E
1
2
R2
B
AN1
E1
A
A
B
3
AN4
L
4
L1
5
1 2 3
b
A
Section B-B
7
e
A2
7
c
c1
7
Seating plane
A1 6
b1 7
b
8
Notes
1
The top package body may be smaller than the bottom package body by as much as 0.15 mm.
2
To be determined at seating plane.
3
Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side.
D1 and E1 are maximum plastic body size dimensions including mold mismatch.
4
Details of pin 1 identifier are optional but will be located within the zone indicated.
5
Exact shape of corners can vary.
6
A1 is defined as the distance from the seating plane to the lowest point of the package body.
7
These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
8
Shows plating.
Table 28 64 Pin LQFP Package Dimension Data (for use with Figure 13)
Dimensions
in mm
Min.
Nom.
Max.
D/E
D1/
E1
A
A1
A2
e
1.40 0.05 1.35
12.00 10.00 1.50 0.10 1.40 0.50
1.60 0.15 1.45
Revision 3.00/January 2003 © Semtech Corp.
AN1 AN2 AN3 AN4
11o
11o
12o
13o
R1
0o
0o
12o
-
3.5o
-
13o
-
7o
-
Page 68
R2
L
L1
0.08 0.08 0.45
-
0.60 1.00
(ref)
0.20 0.75
S
b
b1
c
c1
0.20 0.17 0.17 0.09 0.09
-
0.22 0.20
-
-
-
0.27 0.23 0.20 0.16
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ADVANCED COMMUNICATION
Thermal Conditions
FINAL
The device is rated for full temperature range when this package is used with a 4 layer or more PCB. Copper coverage
must exceed 50%. All pins must be soldered to the PCB. Maximum operating temperature must be reduced when the
device is used with a PCB with less than these requirements.
Figure 14 Typical 64-Pin LQFP Package Landing Pattern
14 mm
14.3
13.0 mm ((1)
13
10.6 mm
10
1.85 mm
Pitch
ch 0.5 m
mm
idth
h 0.3
.3 m
mm
Widt
F8525D_029LQFootprt64
Notes: (i) Solderable to this limit.
(ii) Square package - dimensions apply in both X and Y directions.
(iii) Typical example. The user is responsible for ensuring compatibility with PCB manufacturing process, etc.
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ADVANCED COMMUNICATION
Application Information
FINAL
Figure 15 Simplified Application Schematic
VDD3
P1
VDD
VDD5v
IC2
3 VIN
1 GND
5v
VOUT
VDD2
2
VDDA
0v
EZ1086-3.3V
term_connect
(+)
(+)
C2
100uF
C4
C3
100nF
C5
100nF
10uF_TANT
A.ND
ZD1
BZV90C-5.6v
D.ND
D.ND 2
D.ND 3
Optional Processor
Interface connections
CSB SCLK
SDO SDI
D.ND
O2
An example setup where input and
output clocks are hard wired to
accept 19.44MHz on SEC1 and SEC2.
The outputs are configured as:
O1 -> 155.52MHz
O2 -> 38.88MHz
C14
VDDA
DGND
VDD
100nF
C15
100nF
PORB
C-MAC
E2747_ 12.8MHz
1 AGND1
2 IC1
3 AGND2
4 VA1+
5 LOS_ALARM
6 REFCLK
7 DGND1
8 VD1+
9 VD2+
10 DGND2
11 DGND3
12 VD3+
13 SRCSW
14 VA2+
15 AGND3
16 IC2
C6
100nF
GND 4
3 NC
NC
NC
1
NC
OP 5
X1
D.ND
A.ND
R1
10R
6
10 GNDb
7 NC
8 NC
9 VS
2
VDD
VDD3
VDDA
D.ND
C7
100nF
D.ND 3
source failure indication
AGND
source switch control
R5
10K
VDD
R3
1M
IC1
ACS8526
M1
R4
C16
220nF
VDD
C12
VDD
D.ND
100nF
VDD
C10
100nF
D.ND
optional only needed
for 5v
protection
BSH205
PORB
D.ND
PORB 48
SCLK 47
O1_FREQ1 46
O1_FREQ0 45
CSB 44
SDI 43
CLKE 42
TMS 41
DGND5 40
VDD2 39
O2_FREQ1 38
TRST 37
O2_FREQ2 36
O2_FREQ0 35
IP_FREQ2 34
IP_FREQ1 33
VDD5v
VDD
C13
1nF
17 FrSync
18 MFrSync
19 O1POS
20 O1NEG
21 GND_DIFF
22 VDD_DIFF
23 IC3
24 IC4
25 IC5
26 IC6
27 VDD5V
28 IP_FREQ0
29 SEC1
30 SEC2
31 DGND4
32 VDD1
C8
100nF
R2
10R
arrow
arrow
49 TCK
50 TDO
51 TDI
52 SDO
53 DGND6
54 VDD3
55 NC1
56 O2
57 VA3+
58 AGND4
59 NC2
60 IC7
61 IC8
62 IC9
63 O1_FREQ2
64
SONSDHB
A.ND
Typical 12.8MHz oscillator
1K
C11
100nF
D.ND
D.ND
Optional circuit to ensure SRCSW is
high on power-up
VDD2
FrSync
MFrSync O1P O1N
D.ND 2
C9
100nF
SEC1
SEC2
D.ND
D.ND 2
F8526D_031SimpleApp_01
Revision 3.00/January 2003 © Semtech Corp.
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ADVANCED COMMUNICATION
Abbreviations
APLL
Analogue Phase Locked Loop
BITS
DFS
DPLL
DS1
Building Integrated Timing Supply
Digital Frequency Synthesis
Digital Phase Locked Loop
1544 kb/s interface rate
DTO
E1
I/O
LOS
Discrete Time Oscillator
2048 kb/s interface rate
Input - Output
Loss Of Signal
LQFP
LVDS
MTIE
Low profile Quad Flat Pack
Low Voltage Differential Signal
Maximum Time Interval Error
NE
PBO
PDH
PD2
Network Element
Phase Build-out
Plesiochronous Digital Hierarchy
Phase Detector 2
PECL
PFD
PLL
POR
Positive Emitter Coupled Logic
Phase and Frequency Detector
Phase Locked Loop
Power-On Reset
ppb
ppm
pk-pk
R/W
parts per billion
parts per million
peak-to-peak
Read/Write
rms
RO
SDH
root-mean-square
Read Only
Synchronous Digital Hierarchy
SEC
SETS
SONET
SONSDHB
SDH/SONET Equipment Clock
Synchronous Equipment Timing source
Synchronous Optical Network
SONET High, SDH Low
SSU
STM
TDEV
TCXO
Synchronization Supply Unit
Synchronous Transport Module
Time Deviation
Temperature Compensated Crystal
Oscillator
Unit Interval
Crystal Oscillator
UI
XO
Revision 3.00/January 2003 © Semtech Corp.
FINAL
References
[1] AT & T 62411 (12/1990)
ACCUNET® T1.5 Service description and Interface
Specification
[2] ETSI ETS 300 462-3, (01/1997)
Transmission and Multiplexing (TM); Generic
requirements for synchronization networks; Part 3: The
control of jitter and wander within synchronization
networks
[3] ETSI ETS 300 462-5 (09/1996)
Transmission and Multiplexing (TM); Generic
requirements for synchronization networks; Part 5: Timing
characteristics of slave clocks suitable for operation in
Synchronous Digital Hierarchy (SDH) equipment
[4] IEEE 1149.1 (1990)
Standard Test Access Port and Boundary-Scan
Architecture
[5] ITU-T G.736 (03/1993)
Characteristics of a synchronous digital multiplex
equipment operating at 2048 kbit/s
[6] ITU-T G.742 (1988)
Second order digital multiplex equipment operating at
8448 kbit/s, and using positive justification
[7] ITU-T G.812 (06/1998)
Timing requirements of slave clocks suitable for use as
node clocks in synchronization networks
[8] ITU-T G.813 (08/1996)
Timing characteristics of SDH equipment slave clocks
(SEC)
[9] ITU-T G.824 (03/2000)
The control of jitter and wander within digital networks
which are based on the 1544 kbit/s hierarchy
[10] ITU-T K.41 (05/1998)
Resistability of internal interfaces of telecommunication
centres to surge overvoltages
[11] Telcordia GR-253-CORE, Issue 3 (09/ 2000)
Synchronous Optical Network (SONET) Transport
Systems: Common Generic Criteria
[12] Telcordia GR-499-CORE, Issue 2 (12/1998)
Transport Systems Generic Requirements (TSGR)
Common requirements
[13] Telcordia GR-1244-CORE, Issue 2 (12/2000)
Clocks for the Synchronized Network: Common Generic
Criteria
Page 71
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ACS8526 LC/P LITE
ADVANCED COMMUNICATION
Trademark Acknowledgements
FINAL
Notes
Semtech Corp. and the Semtech S logo are registered
trademarks of Semtech Corporation.
ACCUNET® is a registered trademark of AT & T.
Adobe® Portable Document Format (PDF) is a registered
trademark of Adobe Systems Incorporated.
C-MAC is a registered trademark of
C-MAC MicroTechnology - a division of Solectron
Corporation.
ICT Flexacom is a registered trademark of ICT Electronics.
Motorola is a registered trademark of Motorola, Inc.
Telcordia is a registered trademark of Telcordia
Technologies.
Revision 3.00/January 2003 © Semtech Corp.
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ACS8526 LC/P LITE
ADVANCED COMMUNICATION
Revision Status/History
FINAL
The Revision Status, as shown in top right corner of the
datasheet, may be TARGET, PRELIMINARY, or FINAL, and
refers to the status of the Device (not the datasheet), with
the design cycle. TARGET status is used when the design
is being realised but is not yet physically available, and the
datasheet content reflects the intention of the design. The
datasheet is raised to PRELIMINARY status when initial
prototype devices are physically available, and the
datasheet content more accurately represents the
realisation of the design. The datasheet is only raised to
FINAL status after the device has been fully characterized,
and the datasheet content updated with measured,
rather than simulated parameter values.
This is a FINAL release (Revision 3.00) of the ACS8526
datasheet. Changes made for this document revision are
given in Table 29, together with a brief summary of
previous revision changes. For specific changes between
earlier revisions, refer (where available) to those earlier
revisions. Always use the current version of the datasheet.
Table 29 Revision History
Revision
Reference
Description of changes
2.00/ December 2002
All pages
First full release.
3.00/ January 2003
All pages
Updated to FINAL status.
Revision 3.00/January 2003 © Semtech Corp.
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ACS8526 LC/P LITE
ADVANCED COMMUNICATION
Ordering Information
FINAL
Table 30 Parts List
Part Number
ACS8526
Description
LC/P LITE Line Card Protection Switch for PDH, SONET or SDH Systems
Disclaimers
Life support- This product is not designed or intended for use in life support equipment, devices or systems, or other critical
applications. This product is not authorized or warranted by Semtech for such use.
Right to change- Semtech Corporation reserves the right to make changes, without notice, to this product. Customers are advised
to obtain the latest version of the relevant information before placing orders.
Compliance to relevant standards- Operation of this device is subject to the User’s implementation and design practices. It is the
responsibility of the User to ensure equipment using this device is compliant to any relevant standards.
Contacts
For Additional Information, contact the following:
Semtech Corporation Advanced Communications Products
E-mail:
sales@semtech.com
Internet:
http://www.semtech.com
USA:
Mailing Address:
Street Address:
Tel: +1 805 498 2111,
acsupport@semtech.com
P.O. Box 6097, Camarillo, CA 93011-6097
200 Flynn Road, Camarillo, CA 93012-8790
Fax: +1 805 498 3804
FAR EAST: 11F, No. 46, Lane 11, Kuang Fu North Road, Taipei, R.O.C.
Tel: +886 2 2748 3380
Fax: +886 2 2748 3390
EUROPE:
Semtech Ltd., Units 2 and 3, Park Court, Premier Way,
Abbey Park Industrial Estate, Romsey, Hampshire, SO51 9DN
Tel: +44 (0)1794 527 600
Fax: +44 (0)1794 527 601
ISO9001
CERTIFIED
Revision 3.00/January 2003 © Semtech Corp.
Page 74
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