® ADC614 14-Bit 5.12MHz Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES APPLICATIONS ● HIGH SPURIOUS-FREE DYNAMIC RANGE: –90dB (L Grade) ● FFT SPECTRAL ANALYSIS ● MEDICAL IMAGING ● RADAR SIGNAL ANALYSIS ● WIDEBAND SAMPLE/HOLD: 60MHz ● SAMPLE RATE: DC to 5.12MHz ● HIGH SIGNAL/NOISE RATIO: 78dB ● CCD IMAGING SYSTEMS ● DIGITAL RECEIVERS ● TRANSIENT SIGNAL RECORDING ● NO MISSING CODES ● SINGLE 46-PIN DIP PACKAGE ● COMPLETE SUBSYSTEM: Contains Sample/Hold and Reference ● HIGH-SPEED DATA ACQUISITION ● SIGINT, ECM, AND EW SYSTEMS DESCRIPTION The ADC614 is a high dynamic range analog-todigital converter capable of digitizing signals at any rate from DC to 5.12 megasamples per second. Outstanding spurious-free dynamic range has been achieved by minimizing potential distortion sources. Signal Input Sample/ Hold MSB Flash Encoder The ADC614 is a two-step subranging ADC subsystem containing an ADC, sample/hold amplifier, voltage reference, timing, and error-correction circuitry in a 46-pin hybrid DIP package. The logic interface is TTL. An evaluation board (DEM-ADC614-E) is available for quick evaluation. Digital-to Analog Converter – + LSB Flash Encoder Digital Error Corrector (Adder) 14-Bit Digital Output International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1991 Burr-Brown Corporation PDS-1085F Printed in U.S.A., November, 1996 SPECIFICATIONS ELECTRICAL At TC = +25°C, 5.12MHz sampling rate, output data latched with the convert command, RS = 50Ω, ±VCC = +15V, +VDD1 = +5V, –VDD2 = –5.2V, and 15-minute warmup in convection environment, unless otherwise noted. ADC614JH PARAMETER CONDITIONS MIN TYP RESOLUTION ADC614KH MAX MIN TYP 14 INPUTS Analog Input Range Input Impedance Input Capacitance Full Scale –1.25 +1.25 ✽ Start Conversion t = Conversion Period TRANSFER CHARACTERISTICS Accuracy Gain Error Input Offset Differential Linearity Error No Missing Codes Power Supply Rejection CONVERSION CHARACTERSITICS Sample Rate Pipeline Delay DYNAMIC CHARACTERISTICS(1, 2) Differential Linearity Error Spurious-Free Dynamic Range (SFDR) f = 2.3MHz (–0.5dB) f = 100kHz (–0.5dB) Two-Tone Intermodulation Distortion(6) f = 2.2MHz (–6.5dB) f = 2.3MHz (–6.5dB) Signal-to-Noise Ratio (SNR)(6) f = 2.3MHz (–0.5dB) f = 100kHz (–0.5dB) SINAD f = 2.3MHz (–0.5dB) f = 100kHz (–0.5dB) Aperature Delay Time Aperature Jitter Analog Input Bandwidth (–3dB) Small Signal Full Power Overload Recovery Time OUTPUTS Logic Family Logic Coding Logic Levels EOC Delay Time Tri-State Enable/Disable Time 10 DC DC f = 100kHz: 100% of All Codes ∆+VCC = ±5% ∆–VCC = ±5% ∆+VDD1 = ±5% ∆–VDD2 = ±5% DC Logic Selectable f = 2.3MHz: 100% of All Codes 71 73 fs = 5.12MHz –20 –20dB Input 0dB Input 2x Full-Scale Input 40 Data Valid Pulse Width POWER SUPPLY REQUIREMENTS Supply Voltages: +VCC –VCC +VDD1 –VDD2 Supply Currents: +ICC –ICC +IDD1(4) –IDD2(5) Power Consumption V MΩ pF ✽ ns ±0.4 ±0.2 0.9 ±1 ±0.75 1.25 %FSR(1) %FSR LSB Guaranteed ±0.03 ±0.04 ±0.004 ±0.01 ±0.1 ±0.1 ±0.07 ±0.07 Guaranteed ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ %FSR/% %FSR/% %FSR/% %FSR/% ✽ Samples/s 1.25 LSB 5.12M ✽ 1, 2, or 3 Convert Command Periods 2.0 0.8 dBFS (3) dBFS(3) 80 82 –73 73 75 –85 dBFS (3) 74 76 dB dB 73 75 ✽ ✽ ✽ ✽ dB dB ns ps rms ✽ MHz MHz ns ✽ V ✽ ✽ V See Timing Diagram: Figure 13 37 100 ✽ ✽ ns ✽ ✽ ✽ ✽ +80 –80 +330 –630 ✽ V V V V mA mA mA mA W 72 74 –5 3 60 30 205 73 74 –78 +20 10 ✽ ✽ ✽ 400 ✽ ✽ ✽ +3.5 +5.0 ✽ See Timing Diagram: Figure 13 Operating +14.25 –14.25 +4.75 –4.95 Operating Operating ✽ Same specifications as next grade to the left. ® ADC614 ✽ TTL Compatible Two’s Complement or Inverted Two’s Complement 0 +0.3 +0.5 ✽ ✽ +2.4 ✽ ±2 ±2 1.5 –80 fs = 5.12MHz Bits ±0.8 ±0.4 1.3 77 79 fs = 5.12MHz Logic Selectable Logic “LO” IOL = –3.2mA Logic “HI” IOH = 160µA Data Out to DV IOL = –6.4mA, 50% In to 50% Out t-20 1.3 fs = 5.12MHz UNITS 14 ✽ ✽ 1.5 5 Digital Logic Family Convert Command Pulse Width MAX 2 +15 –15 +5 –5.2 +60 –60 +305 –550 6.1 +15.75 –15.75 +5.25 –5.46 6.5 ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ SPECIFICATIONS (CONT) ELECTRICAL (FULL TEMPERATURE RANGE SPECIFICATIONS) At ±VCC = +15V, +VDD1 = +5V, –VDD2 = –5.2V, RS = 50Ω, 5.12MHz sampling rate, output data latched with the convert command, 15-minute warmup, and TC = TMIN to TMAX, unless otherwise noted. ADC614JH PARAMETER TEMPERATURE RANGE Specification TRANSFER CHARACTERISTICS Accuracy Gain Error Input Offset Differential Linearity Error No Missing Codes Power Supply Rejection CONDITIONS MIN TCASE 0 DC DC f = 100kHz: 100% of all Codes ∆+VCC = ±5% ∆–VCC = ±5% ∆+VDD1 = ±5% ∆–VDD2 = ±5% CONVERSION CHARACTERISTICS Sample Rate Pipeline Delay DYNAMIC CHARACTERISTICS(2) Differential Linearity Error Spurious-Free Dynamic Range (SFDR) f = 2.3MHz (–0.5dB) f = 100kHz (–0.5dB) Two-Tone Intermodulation Distortion(6) f = 2.20MHz (–6.5dB) f = 2.3MHz (–6.5dB) Signal-to-Noise Ratio (SNR) f = 2.3MHz (–0.5dB) f = 100kHz (–0.5dB) SINAD f = 2.3MHz (–0.5dB) f = 100kHz (–0.5dB) Aperature Delay Time Aperature Jitter Analog Input Bandwidth (–3dB) Small Signal Full Power Overload Recovery Time OUTPUTS Logic Levels EOC Delay Time Tri-State Enable/Disable TIme DC f = 2.3MHz: 100% of all Codes MIN +85 ✽ UNITS ✽ °C ±1.5 ±1.5 1.5 %FSR(1) %FSR LSB Guaranteed ±0.04 ±0.05 ±0.004 ±0.02 ±0.2 ±0.2 ±0.1 ±0.1 Guaranteed ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ %FSR/% %FSR/% %FSR/% %FSR/% ✽ Samples/s 1.5 LSB 5.12M ✽ 1, 2, or 3 Convert Command Periods 2.0 1.0 dBFS(3) dBFS(3) 78 80 –76 dBFS(3) 69 72 71 74 dB dB 68 71 –6 3 70 73 ✽ ✽ dB dB ns ps rms –80 fS = 5.12MHz fS = 5.12MHz –20dB Input 0dB Input 2x Full Scale Input MAX ±0.4 ±0.2 1.0 75 77 –25 TYP ±2 ±2 2.0 fS = 5.12MHz Logic “LO” IOL = –3.2mA Logic “HI” IOH = 160µA Data Out to DV IOL = –6.4mA, 50% In to 50% Out ADC614KH MAX ±0.9 ±0.5 1.4 1.4 fS = 5.12MHz Data Valid Pulse Width POWER SUPPLY REQUIREMENTS Supply Currents: +ICC –I CC +IDD1(4) –I DD2(5) Power Consumption TYP –71 +25 10 –84 ✽ ✽ ✽ 60 30 220 MHz MHz ns 0 +0.3 +0.8 ✽ ✽ ✽ V +2.4 +3.5 +5.0 ✽ ✽ ✽ V See Figure 13; ∆ Timing Typically Within ±20% Over Temperature 42 100 ns See Figure 13; ∆ Timing Typically Within ±20% Over Temperature Operating +65 –61 +305 –550 6.1 Operating +80 –80 +333 –630 6.5 ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽ mA mA mA mA W ✽ Same specifications as next grade to the left. NOTES: (1) FSR: Full-Scale Range = 2.5Vp-p. (2) Units with lower distortion are available on special order; inquire. (3) dBFS = level referred to full scale. The input signal is within 1 dB of full scale; f = input frequency; fs = sampling frequency. (4) Pins 3 and 30 (analog typically draw 80% of the total +5V current. Pin 21 (digital) typically draws 20%. (5) Pin 6 (analog) typically draws 45% of the total –5.2V current. Pin 31 (digital) typically draws 55%. (6) SNR and two-tone intermodulation distortion are guaranteed but not 100% tested. ® 3 ADC614 PIN ASSIGNMENTS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Common (Analog) DNC +VDD1 (+5V) Analog S/H Out A/D In –VDD2 (–5.2V) Analog Bit 13 Bit 14 (LSB) Bit 1 (MSB) Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 +VDD1 (+5V) Digital Data Valid Output Common (Digital-Case) ORDERING INFORMATION 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 Common (Analog) Analog Signal In +VCC (+15V) Analog –VCC (–15V) Analog NC NC NC DNC DNC Gain Adjust Offset Adjust Common (Analog) +VCC (+15V) Analog –VCC (–15V) Analog Common (Analog) –VDD2 (–5.2V) Digital +VDD1 (+5V) Analog 1 Pipeline Delay Select 0 Pipeline Delay Select Output Logic Invert Common (Digital) 3-State ENABLE Convert Command In ADC614 ( ) H Basic Model Number Performance Grade Code J, K: 0°C to +85°C Case Temperature Package Code H: Metal and Ceramic ABSOLUTE MAXIMUM RATINGS ±VCC ............................................................................................... ±16.5V +VDD1 ............................................................................................... +7.0V ±VDD2 ............................................................................................... –7.0V Analog Input ..................................................................................... ±5.0V Logic Input ......................................................................... –0.5V to +VDD1 Case Temperature (Operating) ...................................................... +85°C Junction Temperature ................................................................... +100°C Storage Temperature ..................................................... –65°C to +125°C Stresses above these ratings may permanently damage the device. PACKAGING INFORMATION NOTE: NC = no connection, DNC = do not connect. PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) ADC614JH ADC614KH Metal and Ceramic Metal and Ceramic 234 234 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® ADC614 4 TYPICAL PERFORMANCE CURVES At ±VCC = ±15V, +VDD1 = +5V, –VDD2 = –5.2V, RS = 50Ω, 5.12MHz sampling rate, 15-minute warmup, and TC = +25°C, unless otherwise noted. 2.3MHz SPECTRAL PERFORMANCE 100kHz SPECTRAL PERFORMANCE 0 0 –10 fIN = 100kHz –20 –30 –40 Amplitude (dB) Amplitude (dB) –10 fIN = 2.3MHz –20 –50 –60 –70 –80 –90 –100 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –110 –120 0 0.640 1.281 1.921 2.561 0 0.648 Frequency (MHz) fIN = 5.00MHz 0.640 1.28 0 2.592 1.920 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 2.561 0 Frequency (MHz) 0.625 1.250 1.875 2.500 Frequency (MHz) 100kHz DIFFERENTIAL LINEARITY ERROR 2.3MHz DIFFERENTIAL LINEARITY ERROR 2.0 2 fs = 5.12MHz fIN = 100kHz 1.5 fS = 5.12MHz fIN = 2.3MHz 1.5 1.0 1 0.5 0.5 LSB Error LSB 1.944 TWO-TONE INTERMODULATION DISTORTION Amplitude (dB) Amplitude (dB) UNDERSAMPLING AT 5.0MHz 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 1.296 Frequency (MHz) 0.0 0 –0.5 –0.5 –1.0 –1 –1.5 –1.5 –2.0 –2.0 0 5000 10000 15000 0 Code 5000 10000 15000 Code ® 5 ADC614 TYPICAL PERFORMANCE CURVES (CONT) At ±VCC = ±15V, +VDD1 = +5V, –VDD2 = –5.2V, RS = 50Ω, 5.12MHz sampling rate, 15-minute warmup, and TC = +25°C, unless otherwise noted. SIGNAL-TO-NOISE RATIO vs TEMPERATURE SPURIOUS FREE DYNAMIC RANGE vs TEMPERATURE 85 90 fC = 100kHz 80 dBFS dB 75 80 fC = 2.3MHz 70 75 –25 2.5 30 57.5 85 –25 2.5 30 57.5 Case Temperature (°C) Case Temperature (°C) ANALOG INPUT BANDWIDTH SPURIOUS FREE DYNAMIC RANGE vs INPUT FREQUENCY 2 85 90 1 0 SFDR (dBFS) –1 –2 –3 VIN = 48mVp-p TC = +25°C –4 –5 85 80 –6 –7 –8 75 0.1 0.2 0.6 1 2 6 10 20 0.1 60 100 0.2 0.4 1 Frequency (MHz) SWEPT POWER AT fIN = 2MHz, fS = 5MHz 100 80 60 40 20 0 –56 –40 –20 Input Power (dBm) ® ADC614 2 4 Frequency (MHz) 120 Largest Harmonic SFDR (dBFS) Sample/Hold Input Response (dB) fC = 2.3MHz 85 fC = 100kHz 6 0 12 10 20 40 100 THEORY OF OPERATION the capacitor can acquire the signal in 65ns. The low-biascurrent output buffer is then required to settle to only the resolution (8 bits) of the first (MSB) flash encoder in 65ns, while an additional 85ns is allowed for settling to the resolution (14 bits) of the second (LSB) flash encoder. Sample/Hold droop appears as only an offset error and does not effect linearity. The ADC614 is a two-step subranging analog-to-digital converter. This architecture is shown in Figure 1. The major system building blocks are: sample/hold amplifier, MSB flash encoder, DAC and error amplifier, LSB flash encoder, digital error corrector, and timing circuits. The ADC614 uses hybrid technology with laser-trimmed integrated circuits mounted in a multilayer ceramic package to integrate this complex circuit into a complete analog-to-digital converter subsystem with state-of-the-art performance. Both the MSB and the LSB flash encoder (ADC) functions are performed by one 8-bit flash encoder. The DAC voltage reference is also used to generate reference voltages for the MSB and LSB encoder to compensate drift errors. Buffering and scaling amplifiers are laser-trimmed to minimize voltage offset errors and optimize gain (input full-scale range) symmetry. Conceptually, the subranging technique is simple: sample and hold the input signal, convert to digital with a coarse ADC, convert back to analog with a coarse-resolution (but high-accuracy) DAC, subtract this voltage from the S/H output, amplify this “remainder,” convert to digital with a second coarse ADC, and combine the digital output from the first ADC (MSB) with the digital output from the second ADC (LSB). In practice, however, achieving high conversion speed without sacrificing accuracy is a difficult task. The subtraction DAC is an ECL 8-bit resolution monolithic DAC with 14-bit accuracy. Laser-trimmed thin-film nichrome resistors and high-speed bipolar circuitry allow the DAC output to settle to 14-bit accuracy in only 35ns. A “remainder” or coarse conversion-error voltage is generated by resistively subtracting the DAC output from the output of the sample/hold amplifier. Before the second (LSB) conversion, the “remainder” is amplified by a wideband fast-settling two-input amplifier with a gain of 32V/V. To prevent overload on large amplitude transients, the active input is switched off to blank the amplifier input from the beginning of the S/H acquisition time to the end of the MSB encoder update time. The analog input signal is sampled by a high-speed sample/ hold amplifier with low distortion, fast acquisition time and very low aperture uncertainty (jitter). A diode bridge sampling switch is used to achieve an acceptable compromise between speed and accuracy. The diode bridge switching transients are buffered from the analog input by a high input impedance buffer amplifier. Since the hold capacitor does not appear in the feedback of the diode bridge output buffer, R Strobe Convert Command Data Valid L Strobe M Strobe T/H Command 8-Bit Reg Encoder Strobe + – Flash Encoder Signal Input T/H Output Amp Enable Digital/ Analog Converter + 14-Bit Adder DAC Latch MUX 16-Bit Register 8-Bit Reg Timing Digital Output Error Amp – + X16 – Reference Track/Hold A/D Converter Gain Adjust FIGURE 1. ADC614 Block Diagram—A Two-Step Subranging Architecture. ® 7 ADC614 Internal timing circuits (ECL logic is used internally) supply all the critical timing signals necessary for proper operation of the ADC614. Some noncritical timing signals are also generated in the digital error correction circuitry. Timing signals are laser-trimmed for both pulse width and delay. ECL logic is used for its speed, low noise characteristics and timing delay stability over a wide range of temperatures and power supply voltages. Basic timing is derived from the output of a three-stage shift register driven by a synchronized 20MHz oscillator. A typical test setup for performing high-speed FFT testing of analog-to-digital converters is shown in Figure 2 and 3. Highly accurate phase-locked signal sources allow high resolution FFT measurements to be made without using window functions. By choosing appropriate signal frequencies and sample rates, an integral number of signal frequency periods can be sampled. As no spectral leakage results, a “rectangular” window (no window function) can be used. This was used to generate the typical FFT performance curves shown on page 5. The convert command pulse is differentiated to allow triggering by pulses from as narrow as 10ns to as wide as 80% duty cycle. If generators cannot be phase-locked and set to extreme accuracy, a very low side-lobe window must be applied to the digital data before executing an FFT. A commonly used window such as the Hanning window is not appropriate for testing high performance converters; a minimum four-sample Blackman-Harris window is strongly recommended.(l) To assure that the majority of codes are exercised in the ADC614 (14 bits), a 4096-point FFT is taken. If the data storage RAM is limited, a smaller FFT may be taken if a sufficient number of samples are averaged (e.g., a l0-sample average of 512point FFTs). The ADC614 timing technique generates a variable width S/H gate pulse which is determined by the conversion command pulse period minus a fixed 135ns ADC conversion time. ADC614 conversion rates are therefore possible somewhat above the 5.12MHz specification but S/H acquisition time is sacrificed and accuracy is rapidly degraded. The output of the MSB and LSB encoders are read into separate 8-bit latches. The latched MSB data, along with the latched LSB data, is then read into a 16-bit latch after the leading edge of the LSB strobe and before being applied to the adder, where the actual error correction takes place. These latches eliminate any critical timing problems that could result when the converter is operated at the maximum conversion rate. DYNAMIC PERFORMANCE DEFINITIONS 1. Spurious Free Dynamic Range: Largest Harmonic Power (first 9 harmonics) Full Scale Power 2. Intermodulation Distortion (IMD): The function of the digital error correction circuitry is to assemble the 8-bit words from the two flash encoders into a 14-bit output word. Highest IMD Product Power (to 5th-order) Sinewave Signal Power The 16-bit register output is then sent to a 14-bit adder where the final data output word is created. The MSB data forms the most significant eight bits of a 14-bit word, with the last six bits being assigned zeros. In a similar fashion, the LSB data from the least significant bits forms the other input to the adder, with the first six bits being assigned zeros. As two 14-bit words are being added, the output of the adder could exceed 14 bits in range; however, the final data output is only a 14-bit word, so a means of detecting an overrange is included to prevent reading erroneous data. The converter data output is forced to all ones for a full-scale input or overrange. The data output does not “roll-over” if the converter input exceeds its specified full-scale range of ±l.25V. 3. Signal-to-Noise Ratio (SNR): Sinewave Signal Power Noise Power 4. Signal-to-(Noise + Distortion)(2) Ratio (SINAD): Sinewave Signal Power Noise + Harmonic Power (first 9 harmonics) IMD is referenced(3) to the larger of the test signals fl or f2. Five “bins” either side of peak are used for calculation of fundamental and harmonic power. The DC frequency bin is not included in these calculations as it is of little importance in dynamic signal processing applications. DISCUSSION OF PERFORMANCE APPLICATION TIPS Attention to test set-up details can prevent errors that contribute to poor test results. Important points to remember when testing high performance converters are: DYNAMIC PERFORMANCE TESTING The ADC614 is a very high performance converter and careful attention to test techniques is necessary to achieve accurate results. Spectral analysis by application of a fast Fourier transform (FFT) to the ADC digital output will provide data on all important dynamic performance parameters: spurious free dynamic range (SFDR), signal-to-noise ratio (SNR) or the more severe signal-to-noise-and-distortion ratio (SINAD), and intermodulation distortion (IMD). 1. The ADC analog input must not be overdriven. Using a signal amplitude slightly lower than FSR will allow a small amount of “headroom” so that noise or DC offset voltage will not overrange the ADC and “hard limit” on signal peaks. ® ADC614 8 +2.8V +0.2V HP8644A Frequency Synthesizer Convert Command ∅ Locked Fluke HP6080A or HP8644A Frequency Synthesizer Analog Input Low-Pass Filter ADC614 Under Test 3dB TTL Latches 74F574 High-Speed SRAM 64KB x 16 DSP Processor High-Speed SRAM 64KB x 16 DSP Processor 50Ω – or – Data Valid Crystal Filter FIGURE 2. Block Diagram of FFT Test for SNR, SFDR and Swept-Power Test. +2.8V +0.2V HP8644A Frequency Synthesizer Convert Command ∅ Locked Fluke HP6080A or HP8644A Frequency Synthesizer Band Pass Filter Signal Combiner Σ Analog Input ADC614 Under Test 3dB 50Ω 50Ω TTL Latches 74F574 Data Valid Fluke HP6080A or HP8644A Frequency Synthesizer FIGURE 3. Block Diagram of FFT Test for Two-Tone IMD. 50 Ω In L2 L4 L6 Bandwidth: ≈1MHz to ≈30MHz In-to-In Isolation: 45dB at 5MHz In-to-Out Loss: 6dB 50Ω Out L8 49.9Ω C1 C3 C5 C7 50Ω In C9 50Ω Out 49.9Ω 10 turns #24 AWG bifilar wound on Amidon FT 50-43 toroid core. 49.9Ω 9th-Order 0.5dB Ripple Tchebychev Low-Pass Filter Attenuation at 2X cutoff frequency = 90dB. Cutoff frequency = –3dB frequency; to convert cutoff frequency to –0.5dB frequency, multiply all LC values by 0.98997. Cutoff Freq. (MHz) C1 (pF) 2.5 1.25 0.625 2269 4538 9077 C3 (pF) C5 (pF) C7 (pF) 3458 3531 3458 6917 7062 6917 13,833 14,125 13,833 C9 (pF) L2 (µH) L4 (µH) L6 (µH) L8 (µH) 2269 4538 9077 4.11 8.23 16.45 4.43 4.43 8.86 8.86 17.73 17.73 4.11 8.23 16.45 50Ω In FIGURE 5. Passive Signal Combiner. FIGURE 4. Ninth-Order Harmonic Filter. ® 9 ADC614 11. Do not overload the data output logic. These outputs are designed to drive two TTL loads. Do not connect ADC614 data output pins directly to a noisy digital bus; use external 3-state logic for noise immunity. 2. Two-tone tests can produce signal envelopes that exceed FSR. Set each test signal to slightly less than –6B to prevent “hard limiting” on peaks. 3. Low-pass filtering (or bandpass filtering) of test signal generators is absolutely necessary for THD and IMD tests. An easily built LC low-pass filter (Figure 4) will eliminate harmonics from the test signal generator. Care must be taken not to saturate the filter. Saturation of these filters may cause odd order harmonics. 12. A well-designed, clean PC board layout will assure proper operation and clean spectral response.(4, 5) Proper grounding and bypassing, short lead lengths, separation of analog and digital signals, and the use of ground planes are particularly important for high frequency circuits. Multilayer PC boards are recommended for best performance, but a two-sided PC board with large, heavy (20 oz. foil) ground planes can give excellent results, if carefully designed. 4. Test signal generators must have exceptional noise performance to achieve accurate SNR measurements. Good generators together with fifth-order elliptical bandpass filters are recommended for SNR tests. Recommended generators are the Fluke 6080A or HP8644A. Narrowbandwidth crystal filters can also be used to filter generator broadband noise, but they should be carefully tested for operation at high levels. 13. Prototyping “plug-boards” or wire-wrap boards will not be satisfactory. 14. Connect analog and digital ground pins of the ADC614 directly to the ground plane. In our experience, connecting these pins to a common ground plane gives the best results. Analog and digital power supply commons should be tied together at the ground plane. Adding power supply and ground-return filtering(6) is optional and may improve noise rejection. The manual for the evaluation board (DEM-ADC614-E) gives a recommended layout. 5. The analog input of the ADC614 should be terminated directly at the input pin sockets with the correct filter terminating impedance (50Ω or 75Ω), or it should be driven by a low output impedance buffer such as an OPA642. Short leads are necessary to prevent digital noise pickup. 6. A low-noise (jitter) clock signal (convert command) generator is required for good ADC dynamic performance. A poor generator can seriously impair good SNR performance. A HP 8644A generator is a good clock source. Short leads are necessary to preserve fast TTL rise times. 15. If using a cable to drive the input of the ADC614, avoid reflections down the cable that could degrade dynamic performance by placing a 3dB attenuator at the end of the cable. Input amplitude should be doubled to maintain signal amplitude. 7. Two-tone testing will require isolation between test signal generators to prevent IMD generation in the test generator output circuits. A passive (hybrid transformer) signal combiner can also be used (Figure 5) over a range of about 0.lMHz to 30MHz. This combiner's port-toport isolation will be ≈45dB between signal generators and its input-output insertion loss will be ≈6dB. Distortion will be better than –85dBc. NOTES: 1. “On the Use of Windows for Harmonic Analysis with the Discrete Fourier Transform”, Fredric J. Harris. Proceedings of the IEEE, Vol. 66, No. 1, January 1978, pp 51-83. 8. A very low side-lobe window must be used for FFT calculations if generators cannot be phase-locked and set to exact frequencies. A minimum four-sample BlackmanHarris window function is recommended.(l) 6. Murata-Erie BNX002-01. 2. SINAD test includes harmonics whereas SNR does not include these important spurious products. 3. If IMD is referenced to peak envelope power, distortion will be 6dB better. 4. MECL System Design Handbook, 3rd Edition, Motorola Corp. 5. Motorola MECL, Motorola Corp. TIMING The ADC614 generates all necessary timing signals internally. Only timing between Convert Command, Output Data, and Data Valid must be considered. Proper timing is shown in Figures 12 and 13. There are two methods for reading output data, offering three selectable levels of data pipeline delay as described below: 9. Floating inputs can eliminate ground-loop noise. A simple common-mode choke shown in Figures 6 and 7, or a single-ended amplifier (Figures 8 and 9) can be used for gain. Optimized harmonic performance can only be achieved with a very low distortion buffer. Burr-Brown OPA642 is an ideal op amp for driving the ADC614. (1) Convert Command timing option (pin 29 = HIGH)— With this option, the Convert Command signal is used both for initiating a new conversion and for reading valid data from a previous conversion. This method is most useful in synchronous systems where data samples are taken continuously. See Figure 12 for timing relationships. 10. Digital data must be latched into an external TTL 14-bit register, preferably using the convert command pulse (Figures 10 and 11). Latches should be mounted on PC boards in very close proximity to the ADC614. Avoid long leads. Pin 28 is used to control the amount of pipeling delay. If pin 28 is held LOW, then output data “N-2” will be valid on the rising edge of Convert Command “N”. If pin 28 is held ® ADC614 10 HIGH, then output data “N-3” will be valid on the rising edge of Convert Command “N”. These timing relationships are valid at any conversion rate up to 5.12MHz, the data setup time before the rising Convert Command edge is about 50ns. Data should be latched into external TTL latches that can operate reliably with a set-up time of 6ns minimum. Two 74F574 hex latches are recommended. DATA OUTPUT Output logic inversion can be accomplished by programming pin 27. Binary Two’s Complement or Inverted Binary Two's Complement output data format is available (Table II). (2) Data Valid timing option (pin 29 = LOW)—With this option, data from conversion “N” becomes valid after a fixed delay from the rising edge of Convert Command “N”. The delay is about 165ns . At about t = 185ns, the Data Valid strobe signal will rise. This strobe signal may be connected directly to the clock input of the external data latches, providing a data setup time of approximately 20ns. The ADC614 output logic is TTL compatible. The 3-state output is controlled by ENABLE pin 25. For normal operation pin 25 will be tied LO. A logic HI on pin 25 will switch the output data register to a high-impedance state (Figure 14). Output OFF leakage current IOZL and IOZH will be less than 50µA over the converter's specified operating temperature range. The 3-state output should be isolated from noisy digital bus lines as the noise can couple back through the OFF data register and create noise in the ADC. See Figure 13 for timing relationships. Pin 28 must be left HIGH at all times when using the Data Valid timing option. This method does not require subsequent conversions in order to read the data (i.e., single-shot conversion capability). Therefore, the Data Valid option is useful in systems where the very first data latch output after power-up must represent a valid conversion. PIN NUMBER N-2 N-1 N-1 DIGITAL INPUTS Logic inputs are TTL compatible. Open inputs will assume a HI logic state; unused inputs may be allowed to float or they may be tied to an appropriate TTL logic level. 28 29 HI HI LO HI HI LO OFFSET AND GAIN ADJUSTMENT DATA LATCHED BY CONVERT COMMAND DATA LATCHED BY DATA VALID STROBE The ADC614 is carefully laser-trimmed to achieve its rated accuracy without external adjustments. If desired, both gain error and input offset voltage error may be trimmed with external potentiometers (Figure 15). Trim range is typically only 0.1%; large offsets and gain changes should be made TABLE I. Pipeline Delay Selection Logic. DIGITAL DATA OUTPUT LOGIC CODING BINARY TWO'S INPUT VOLTAGE COMPLEMENT (BTC) (EXACT CENTER OF CODE) PIN 27 = LO +FS (+1.25V) +FS –1LSB (+1.24985V) +FS –2LSB (+1.24969V) +3/4 FS (+0.9375V) +1/2 FS (+0.6250V) +1/4 FS (+0.3125V) +1LSB (+152µV) Bipolar Zero (0V) –1LSB (–152µV) –1/4 FS (–0.3125V) –1/2 FS (–0.625V) –3/4 FS (–0.9375V) –FS + 1LSB (–1.24985V) –FS (–1.25V) 01111111111111(1) 01111111111111 01111111111110 01100000000000 01000000000000 00100000000000 00000000000001 00000000000000 11111111111111 11100000000000 11000000000000 10100000000000 10000000000001 10000000000000 MSB LSB NOTE: (1) Indicates overrange condition. INVERTED BINARY TWO'S COMPLEMENT (BTC) PIN 27 = HI 10000000000000(1) 10000000000000 10000000000001 10011111111111 10111111111111 11011111111111 11111111111110 11111111111111 00000000000000 00011111111111 00111111111111 01011111111111 01111111111110 01111111111111 MSB Insulated BNC ADC614 45 Signal Input Signal Input RT 46 Balun Transformer LSB Analog Common R T = Cable Termination Impedance FIGURE 6. Floating-Input Balun Transformer. TABLE II. Coding Table for 14-bit ±1.25V ADC Function. Amidon FT 50-43 Ferrite Core 1 2 1 2 1 1 2 2 Impedance = 1:1 #26 AWG Bifilar Wound FIGURE 7. Common-Mode Choke Transformer Windings. ® 11 ADC614 CUSTOM SCREENING OPTIONS Custom screened versions of the ADC614 are available. Screening may include extended temperature ranges, higher guaranteed dynamic specifications, additional environmental screens, higher sampling rates, etc. Inquire with your local sales representative or contact factory. elsewhere in the system. Using an input buffer amplifier is the preferred way for injecting offset voltages and making wide gain adjustments. THERMAL REQUIREMENTS The ADC614 is tested and specified over a temperature range of 0°C to +85°C. The converters are tested in a forcedair environment with a 10 SCFM air flow. The ADC614 can be operated in a normal convection ambient air environment, provided the case temperature does not exceed the upper limit of its specification. 1kΩ Proper heat transfer can be assured by placing a small heat sink (#0808HS) and an appropriately sized piece of 10mil. Berquist Sil-Pad 400 between the unit and PC board ground plane. Refer to Figure 16 for details. ADC614 1kΩ – 45 OPA642 High junction temperature can be avoided by using forcedair cooling, but it is not required at moderate ambient temperatures. Thermal resistance of the ADC614 package is: θJC = 4.8°C/W. measured to the underside of the case. Signal Input + 499Ω 499Ω NOISE FIGURE The noise figure is defined as the degradation of signal-tonoise ratio as an analog input is processed through the ADC614. An approximation of the noise figure of the ADC614 can be derived from the SNR specifications. FIGURE 8. Single Ended Input Amplifier (Gain = –1V/V). The signal-to-noise ratio of the ADC614 is measured typically at 78dB. The full-scale input signal of the ADC614 is +12dBm, so the noise level at the output of the ADC614 is –66dBm for the 2.56MHz band. The input noise is derived from the formula: N = 10log (4kTB/0.001) = –168dBm 2kΩ ADC614 1k Ω – The noise figure can be calculated using the following equation: NF = output noise – (10log BWo/BWi) – input noise OPA642 Signal Input + 499Ω NF = –66dB – 64dB – (–168dB) = 38dB 665Ω An important consideration when using the Noise Figure for an analog-to-digital converter is the effect of input signal range on the noise figure. As the input range increases, the noise figure directly decreases. When the input is grounded, the RMS noise of the ADC614 is 72µV, and 99.7% of all codes will fall within a span of four codes. This figure represents the entire noise contribution of the ADC614. FIGURE 9. Single Ended Input Low Noise Amplifier (Gain = –2V/V). ® ADC614 45 12 –5.2V –15V +15V +5V + Parallel 0.01µF Ceramic and 1µF Tantalum (All) + + 9 + + 8 7 + + + + 31 Signal In 45 6 42 43 33 44 34 30 5 3 21 B13 In B14 (LSB) B1 B2 B3 B4 RT 46 4 5 1 35 32 26 25 23 27 28 29 ADC614 B5 B6 B7 B8 B9 B10 B11 B12 CC DV 24 6 4 7 8 9 10 11 12 3 2 8D 8Q 7D 7Q 6D 6Q 5Q 5D 74F574 4D 4Q 3D 3Q 2D 2Q 1D 1Q 12 13 14 15 16 LSB MSB 17 18 19 CLK 11 13 14 15 16 17 18 19 20 9 8 7 6 5 4 3 22 2 TTL Data Output 8D 8Q 7D 7Q 6D 6Q 5Q 5D 74F574 4D 4Q 3D 3Q 2D 2Q 1D 1Q 12 13 14 15 16 17 18 19 CLK 11 CC FIGURE 10. Interface Circuit—Digital Output Strobed by Convert Command. Supply connection shown: power supplies and grounds shared by analog and digital pins using common ground plane. Optimum noise performance is achieved when strobing the output data with the convert command. –5.2V Parallel 0.01µF Ceramic and 1µF Tantalum (All) –15V +15V +5V + + + 9 + + 8 7 + + + + 31 Signal In 45 6 42 43 33 44 34 30 In B14 (LSB) B1 B2 B3 B4 46 4 5 1 35 32 26 25 23 27 28 29 ADC614 CC DV 24 5 3 21 B13 RT 6 B5 B6 B7 B8 B9 B10 B11 B12 7 8 9 10 11 12 4 3 2 8D 8Q 7D 7Q 6D 6Q 5D 5Q 74F574 4D 4Q 3D 3Q 2D 2Q 1D 1Q 12 13 14 15 16 18 19 CLK 9 8 7 6 5 4 3 22 M SB 17 11 13 14 15 16 17 18 19 20 LSB 2 TTL Data Output 8D 8Q 7D 7Q 6D 6Q 5D 5Q 74F574 4D 4Q 3D 3Q 2D 2Q 1D 1Q 12 13 14 15 16 17 18 19 CLK 11 CC FIGURE 11. Interface Circuit—Digital Output Strobed by Data Valid Pulse. Supply connection shown: power supplies and grounds shared by analog and digital pins, using common ground plane. ® 13 ADC614 0 Nanoseconds 40 80 120 160 200 Convert Command 240 280 320 360 400 440 480 520 (3) Start Conversion N+1 Start Conversion N (1) tCID Data Output Pin 28 = High Pin 29 = High Data Output Pin 28 = Low Pin 29 = High tCID tDSU(5) tCVD(2) Start Conversion N+2 tCID tDSU tCVD tCVD Valid Data N–3 Invalid Data Valid Data N–2 Invalid Data Valid Data N–1 Invalid Data Valid Data N–2 Invalid Data Valid Data N–1 Invalid Data Valid Data N Invalid Data (4) tCH Internal Sample/Hold Command tCH tCH Sample Hold Sample Hold Hold NOTES: (1) tCID = delay time from Convert Command to Invalid Data. Typical value = 65ns. Independent of conversion rate. (2) tCVD = Delay time from Convert Command to Valid Data. Typical Value = 150ns. Independent of conversion rate. (3) The symbol indicates the portion of the waveform that will “stretch out” at lower conversion rates. (4) tCH = delay time from Convert Command to the internal hold command. Typical value = 6ns. Independent of conversion rate. (5) tDSU = data set-up time. This depends on conversion rate and may be calculated by: 1 tDSU = – tCVD fSAMPLE FIGURE 12. Convert Command Strobe Timing for a 5MHz Conversion Rate. Nanoseconds 0 40 80 120 Convert Command 160 200 240 280 320 360 400 440 480 520 (6) Start Conversion N Start Conversion N+2 Start Conversion N+1 t CDL(1) t CDL (2) t CDH Data Valid Strobe Output Strobe N t CID(3) t DSU(7) Strobe N+1 t DSU t CID (7) Valid Data N – 1 Invalid Data Valid Data N tCH(5) Internal Sample/Hold Command Valid Data N + 1 Invalid Data Sample Invalid Data tCH tCH Hold t CID t CVD t CVD Data Output Pin 28 = High Pin 29 = Low t CDL t CDH Hold Sample Hold NOTES: (1) tCDL = delay time from Convert Command to the falling edge of Data Valid strobe. Typical value = 140ns. Independent of conversion rate. (2) tCDH = delay time from Convert Command to the rising edge of Data Valid strobe. Typical value = 195ns. Independent of conversion rate. (3) tCID = delay time from Convert Command to Invalid Data. Typical value = 65ns. Independent of conversion rate. (4) tCVD = delay time from Convert Command to Valid Data. Typical Value = 188ns. Independent of conversion rate. (5) tCH = delay time from Convert Command to the internal hold command. Typical value = 6ns. Independent of conversion rate. (6) The symbol indicates the portion of the waveform that will “stretch out” at lower conversion rates. (7) tDSU = data setup time. Typical value = 7ns. Independent of conversion rate. FIGURE 13. Data Valid Strobe Timing for a 5MHz Conversion Rate. ® ADC614 14 Offset Trim +15V 10kΩ ENABLE Input Pin 25 HI –15V 36 LO 37ns Data HI High Impedance Output OFF LO Pins 9-20 Active ADC614 37ns High Impedance +15V 37 10kΩ Gain Trim FIGURE 14. Digital Data 3-State Output. FIGURE 15. Optional Gain and Offset Trim. 2.300" 0.350" AD C6 14 1.950" —A— 46-pin package 0.090" —B— Lead Sockets for 18mil Diameter Pins 10 mil. Berquist Sil-Pad 400 –15V Heat Sink #0808HS Conducts heat from bottom of package into copper ground plane. Mounting screws and nuts not included with 0808HS. 0.575" 1.150" 0.120" Diameter and CSK 82° 0.235" +0.005" –0" Diameter (2 Places) NOTES: (1) Material: 6061-T6 aluminum. (2) Finish: nickel-plate or irridite. (3) Deburr and break all sharp edges. FIGURE 16. Heat Sink Transfers Heat from the DIP Package into a Copper Ground Plane. ® 15 ADC614