MM54HC75/MM74HC75 4-Bit Bistable Latch with Q and Q Output General Description This 4-bit latch utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity and low power consumption normally associated with standard CMOS integrated circuits. These devices can drive 10 LS-TTL loads. This latch is ideally suited for use as temporary storage for binary information processing, input/output, and indicator units. Information present at the data (D) input is transferred to the Q output when the enable (G) is high. The Q output will follow the data input as long as the enable remains high. When the enable goes low, the information that was present at the data input at the time the transition occurred is retained at the Q output until the enable is permitted to go high again. Connection and Logic Diagrams The 54HC/74HC logic family is functionally as well as pinout compatible with the standard 54LS/74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. Features Y Y Y Y Y Y Typical operating frequency: 50 MHz Typical propagation delay: 12 ns Wide operating supply voltage range: 2 – 6V Low input current: 1 mA maximum Low quiescent supply current: 80 mA maximum (74HC Series) Fanout of 10 LS-TTL loads Truth Table Dual-In-Line Package Inputs Outputs D G Q Q L H X H H L L H Q0 H L Q0 H e High Level: L e Low Level X e Don’t Care Q0 e The level of Q before the transition of G TL/F/5303 – 1 Order Number MM54HC75 or MM74HC75 (1 of 4 latches) TL/F/5303 – 2 C1995 National Semiconductor Corporation TL/F/5303 RRD-B30M105/Printed in U. S. A. MM54HC75/MM74HC75 4-Bit Bistable Latch with Q and Q Output January 1988 Absolute Maximum Ratings (Notes 1 & 2) Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) b 0.5 to a 7.0V Supply Voltage (VCC) b 1.5 to VCC a 1.5V DC Input Voltage (VIN) b 0.5 to VCC a 0.5V DC Output Voltage (VOUT) g 20 mA Clamp Diode Current (IIK, IOK) g 25 mA DC Output Current, per pin (IOUT) g 50 mA DC VCC or GND Current, per pin (ICC) b 65§ C to a 150§ C Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) 600 mW S.O. Package only 500 mW Lead Temp. (TL) (Soldering 10 seconds) 260§ C Operating Temp. Range (TA) MM74HC MM54HC Min 2 Max 6 0 VCC Units V V b 40 b 55 a 85 a 125 §C §C 1000 500 400 ns ns ns Input Rise or Fall Times VCC e 2.0V (tr, tf) VCC e 4.5V VCC e 6.0V DC Electrical Characteristics (Note 4) Symbol Parameter Conditions TA e 25§ C VCC 74HC TA eb40 to 85§ C Typ 54HC TA eb55 to 125§ C Units Guaranteed Limits VIH Minimum High Level Input Voltage 2.0V 4.5V 6.0V 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V V V VIL Maximum Low Level Input Voltage** 2.0V 4.5V 6.0V 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V V V VOH Minimum High Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA 2.0V 4.5V 6.0V 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V V V 4.5V 6.0V 4.2 5.7 3.98 5.48 3.84 5.34 3.7 5.2 V V 2.0V 4.5V 6.0V 0 0 0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V V V VIN e VIH or VIL lIOUTl s4.0 mA lIOUTl s5.2 mA 4.5V 6.0V 0.2 0.2 0.26 0.26 0.33 0.33 0.4 0.4 V V VIN e VIH or VIL lIOUTl s4.0 mA lIOUTl s5.2 mA VOL Maximum Low Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA IIN Maximum Input Current VIN e VCC or GND 6.0V g 0.1 g 1.0 g 1.0 mA ICC Maximum Quiescent Supply Current VIN e VCC or GND IOUT e 0 mA 6.0V 4.0 40 80 mA Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C. Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. **VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89. 2 AC Electrical Characteristics VCC e 5V, TA e 25§ C, CL e 15 pF, tr e tf e 6 ns Typ Guaranteed Limit Units Maximum Propagation Delay, Data to Q 14 23 ns tPHL, tPLH Maximum Propagation Delay, Data to Q 10 20 ns tPHL, tPLH Maximum Propagation Delay, Enable to Q 16 27 ns tPHL, tPLH Maximum Propagation Delay, Enable to Q 11 23 ns ts Minimum Set Up Time tH Minimum Hold Time tW Minimum Pulse Width Symbol Parameter tPHL, tPLH Conditions b2 20 ns 0 ns 16 ns AC Electrical Characteristics CL e 50 pF, tr e tf e 6 ns (unless otherwise specified) Symbol Parameter Conditions VCC TA e 25§ C Typ 74HC TA eb40 to 85§ C 54HC TA eb55 to 125§ C Units Guaranteed Limits tPHL, tPLH Maximum Propagation Delay, Data to Q 2.0V 4.5V 6.0V 37 15 14 125 25 24 156 32 27 188 38 32 ns ns ns tPHL, tPLH Maximum Propagation Delay, Data to Q 2.0V 4.5V 6.0V 29 12 11 110 22 19 138 28 24 165 33 29 ns ns ns tPHL, tPLH Maximum Propagation Delay, Enable to Q 2.0V 4.5V 6.0V 40 18 16 145 29 25 181 36 31 218 44 38 ns ns ns tPHL, tPLH Maximum Propagation Delay, Enable to Q 2.0V 4.5V 6.0V 36 15 14 125 25 22 156 31 28 188 38 33 ns ns ns ts Minimum Set Up Time Data to Enable 2.0V 4.5V 6.0V 40 10 9 100 20 17 125 25 21 150 30 25 ns ns ns tH Minimum Hold Time Enable to Data 2.0V 4.5V 6.0V b 10 b2 b2 0 0 0 0 0 0 0 0 0 ns ns ns tW Minimum Enable Pulse Width 2.0V 4.5V 6.0V 40 11 9 80 16 14 100 20 18 120 24 21 ns ns ns tTLH, tTHL Maximum Output Rise and Fall Time 2.0V 4.5V 6.0V 25 7 6 75 15 13 95 19 16 110 22 19 ns ns ns CPD Power Dissipation Capacitance (Note 5) CIN Maximum Input Capacitance (per commonly clocked latched pair) 40 5 pF 10 10 10 pF Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC. 3 MM54HC75/MM74HC75 4-Bit Bistable Latch with Q and Q Output Physical Dimensions inches (millimeters) Order Number MM54HC75J or MM74HC75J NS Package J16A Order Number MM54HC75N NS Package N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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