16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR AFE16 FEATURES GENERAL DESCRIPTION The samsung analog front end(AFE) for CCD/CIS - 16-bit 6MSPS A/D Converter image - Integrated Triple Correlated Double signal is an integrated analog signal Sampler processor for color image signal. The AFE converts CCD/CIS output signal to digital - 3-Channel 2 MSPS Color Mode data. - 1 ~ 6.25x Analog Programmable Gain The AFE CDS(Correlated includes Double three-channel Sampling) Amplifier circuit, PGA(Programmable Gain Amplifier), and 16-bit - Internal Voltage Reference analog to digital converter with reference generator. - No Missing Code Guaranteed The - Multiplexed Byte-Wide Output 16-bit digital output is multiplexed into an (8+8 Format) 8-bit output word that is accessed using 8+8 format two read cycles. The internal resgisters are - 3-Wire Serial Digital Interface programmed through a 3-wire serial interface, and - Operation by Single 3.3V Supply provide - CMOS Low Power Dissipation adjustment of the gain, offset, and - 28-SOP-375 Package operating mode. KEY SPECIFICATION APPLICATIONS - Color and B/W Scanner - Resolution: 16-bit - Digital Copiers - Conversion Rate: 6 MHz(2 MHz*3) - General Purpose CCD/CIS imager - Supply Voltage: 3.3 V ± 5% - Power Dissipation: 257 mW(Typical) FUNCTIONAL BLOCK DIAGRAM RED CDS PGA REF DAC OEB GREEN CDS PGA MUX 16b ADC 1 6 16:8 8 MUX DAC BLUE CDS PGA GAIN REGISTERS DAC INPUT OFFSET REGISTERS Ver 1.0 (July, 2001) This datasheet is a preliminary version. No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this datasheet is subject to change without any notice. SAMSUNG ELECTRONICS Co. LTD SCLK MPU PORT SLOAD SDATA D[7:0] AFE16 16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR CORE PIN DESCRIPTION NAME I/O TYPE I/O PAD DESCRIPTION AVDDA AP vdda 3.3 V Analog Supply AVSSA AG vssa Analog Ground AVDDD AP vdda 3.3 V Digital Supply AVSSD AG vssa Digital Ground AVBBA AG vbba Analog Substrate AVBBD AG vbba Digital Substrate REFT AB poa_bb Reference Decoupling REFB AB poa_bb Reference Decoupling VCOM AB poa_bb Analog Common Voltage R_VIN AI piar10_bb Analog Input; Red G_VIN AI piar10_bb Analog Input; Green B_VIN AI piar10_bb Analog Input; Blue OFFSET AB piar10_bb Clamp Bias Level Decoupling CDS1_CLK DI picc_bb CDS Reset Clock Pulse Input CDS2_CLK DI picc_bb CDS Data Clock Pulse Input ADCCLK DI picc_bb A/D Converter Sample Clock Input SDATA DB poa_bb Serial Interface Data Input/Output SCLK DI picc_bb Serial Interface Clock Input SLOAD DI picc_bb Serial Interface Load Pulse OEB DI picc_bb Output Enable; Active Low D[7:0] DO pot4_bb Data Outputs I/O TYPE ABBR. - AI : Analog Input DI : Digital Input AO : Analog Output DO : Analog Output AP : Analog Power AG : Analog Ground SEC ASIC - DP DG AB DB : : : : 2 Digital Power Digital Ground Analog Bidirectional Port Digital Bidirectional Port MIXED AFE16 16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR CORE PIN CONFIGURATION REFT VCOM REFB AVSSD AVDDD AVSSA AVDDA OEB R_VIN G_VIN D[7:0] afe16 B_VIN SDATA SCLK SLOAD OFFSET AVBBA AVBBD CDS1_CLK CDS2_CLK ADCCLK ABSOLUTE MAXIMUM RATINGS Characteristic Symbol Value Unit Supply Voltage VDD 4.5 V Analog Input Voltage AIN VSS to VDD V Digital Input Voltage CLK VSS to VDD V VOH, VOL VSS to VDD V VRT/VRB VSS to VDD V Digital Output Voltage Reference Voltage Storage Temperature Range Tstg -45 to 150 ºC Operating Temperature Range Topr 0 to 70 ºC NOTES 1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to VSS unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5kΩ resistor (Human body model) SEC ASIC 3 MIXED AFE16 16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR ANALOG SPECIFICATIONS(VDDA1=3.3V, VDDA2=3.3V, ADCCLK=6MHz, CDS1_CLK=2MHz,CDS2_CLK=2MHz, PGA Gain=1 unless otherwise noted) Characteristics Symbol Resolution Min Typ Max Unit 16 Comment Bits Conversion Rate 3-Channel with CDS 1-Channel with CDS Signal-to-Noise & Distortion Ratio @ 1MHz Input Differential Nonlinearity Integral Nonlinearity 6 6 MSPS MSPS SNDR 78 dB DNL ±1.3 LSB ±25 LSB INL Entire Signal Path Unipolar Offset Error 1.5 %FSR Gain Error 3.0 %FSR 2.4 8 Vp-p pF 2.2 1.0 V V Analog Input 0.04 Full-Scale Input Input Capacitance Reference Top Reference Bottom Amplifier PGA Gain PGA Resolution OFFSET Range OFFSET Resolution 1 - 6 6.25 - V/V Bits -200 - 9 +200 - mV Bits Power Supply Analog Voltage Digital Voltage VDDA1 VDDA2 3.3 3.3 V V Analog Current IDD1 73 mA Digital Current IDD2 5 mA 257 mW Power Consumption Temperature Range 0 70 ºC 3.3V±5% 3.3V±5% Operating DIGITAL SPECIFICATIONS(VDDA1=3.3V, VDDA2=3.3V, ADCCLK=6MHz, CDS1_CLK=2MHz, CDS2_CLK=2MHz, CL=20pF unless otherwise noted) Characteristics Symbol Min High Level Input Voltage VIH 2.0 Low Level Input Voltage VIL High Level Input Current IIH 10 µA Low Level Input Current IIL 10 µA High Level Output Voltage VoH Low Level Output Voltage VOL SEC ASIC Typ Max Unit Comment V 0.7 3.0 0.3 4 V V IoH = 0.5mA V IoL = -0.5mA MIXED AFE16 16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR TIMING SPECIFICATIONS Characteristics (VDDA1=3.3V, VDDA2=3.3V unless otherwise noted) Symbol Min Typ Max Unit CLOCK CHARACTERISTICS 3-Channel Conversion Rate 500 ns 1-Channel Conversion Rate 166 ns CDSCLK1 Pulse Width tC1CLK 60 ns CDSCLK2 Pulse Width tC2CLK 70 ns CDSCLK2B Pulse Width tC2CLKB 70 ns CDSCLK1 Falling to CDSCLK2 Rising tC1C2A 5 ns CDSCLK2 Falling to CDSCLK1 Rising tC2C1A 5 ns ADCCLK Pulse Width tADCLK 70 ns CDSCLK2 Rising to ADCCLK Rising tC2ADA 70 ns CDSCLK2 Falling to ADCCLK Falling tC2ADB 5 ns ADCCLK Rising to CDS2CLK Falling tADC2A 5 ns Aperture Delay tAD 2 ns Maximum SCLK Frequency fCLK 10 MHz SLOAD to SCLK Set-up Time tLS 10 ns SCLK to SLOAD Hold Time tLH 10 ns SDATA to SCLK Rising Set-up Time tDS 10 ns SCLK Rising to SDATA Hold Time tDH 10 ns SCLK Falling to SDATA Valid tRDV 10 ns SERIAL INTERFACE DATA OUTPUT ADC Output Delay tADDT 10 ns Tri-State to Data Valid tDEV 15 ns Output Enable High to Tri-State tHZ 5 ns 3 ADCCLK Cycles ADC Latency(Pipeline Delay) * Aperture delay is a timing measurement between the sampling clocks and CDS. It is measured from the falling edge of the CDS2_CLK input to when the input signal is held for data conversion SEC ASIC 5 MIXED AFE16 16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR TIMING DIAGRAM 3-Channel CDS Mode Analog Input R0,G0,B0 R1,G1,B1 tC1C2A R2,G2,B2 tC2C1A tC1CLK CDS1_CLK tC2ADA tADC2A tC2CLKB CDS2_CLK tADCLK ADCCLK tADDT OUTPUT D[7:0] R-2 R-2 G-2 G-2 B-2 B-2 R-1 R-1 G-1 G-1 B-1 B-1 R0 R0 G0 G0 B0 B0 3-Channel SHA Mode Analog Input R0,G0,B0 R1,G1,B1 tC2ADA R2,G2,B2 tADC2A tC2CLKB CDS2_CLK tADCLK ADCCLK tADDT OUTPUT D[7:0] R-2 R-2 SEC ASIC G-2 G-2 B-2 B-2 R-1 R-1 6 G-1 G-1 B-1 B-1 R0 R0 G0 G0 B0 B0 MIXED AFE16 16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR 1-Channel CDS Mode Analog Input tC1CLK tC1C2A tC2C1A CDS1_CLK tC2CLK CDS2_CLK tC2ADA tC2ADB tADCLK ADCCLK 1-Channel SHA Mode Analog Input R0,G0,B0 R1,G1,B1 R2,G2,B2 tC2CLK CDS2_CLK tC2ADA tC2ADB tADCLK ADCCLK SEC ASIC 7 MIXED AFE16 16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR Digital Output Data Timing ADCCLK tADDT OUTPUT D[7:0] tADDT High Byte D13-D6 Low Byte D5-D0 High Low Low tHZ High tDEV OEB Serial Write Operation Timing SDATA R/Wb A2 A1 A0 XX XX XX D8 tDH D7 D6 D5 D4 D3 D2 D1 D0 tDS SCLK tLH tLS SLOAD Serial Read Operation Timing SDATA R/Wb A2 A1 A0 XX XX XX D8 tDH tDS D7 D6 D5 D4 D3 D2 D1 D0 tRDV SCLK tLH tLS SLOAD 'Read' means microcontroller reads SDATA SEC ASIC 8 MIXED AFE16 16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR FUNCTIONAL DESCRIPTION MAIN BLOCK DESCRIPTION 1) 3-Channel Operation with CDS 1) Programmable Gain Amplifier This mode enables simultaneous sampling of a The analog programmable gain can accommodate triple output CCD. The CCD waveforms are ac a wide range of input voltage spans. The transfer coupled to the R_VIN, G_VIN and B_VIN pins function of the PGA is as follows. where they are automatically biased at an H(X) = 1/12*X + 1, appropriate voltage using the on-chip clamp. The where the range of X is 0 to 63. internal CDSs take two samples of the incoming Thus, the minimum gain value is equal to 1, and pixel data; the first samples are taken during the the maximum gain value is equal to 6.25. The reset time while the second samples are taken transfer function has linearity in linear scale. The during data portion of the input pixels. overall gain is equal to analog gain by digital 2) 3-Channel SHA Operation gain. multiplied So, the multiplier should be required in back end of AFE. This mode enables simultaneous sampling of a triple output CIS or something like that. The CDS functions are replaced with the sample and hold amplifiers. The input waveforms are either dc coupled or dc restored to the R_VIN, G_VIN and 6 16 14 12 10 8 6 4 2 0 B_VIN pins. The input reference voltage in this 5 mode will be defined by external OFFSET pin. 4 3) 1-Channel Operation with CDS This mode enables single channel or monochrome 3 sampling. The CCD waveforms are ac coupled to 2 the analog input pin where they are automatically 1 biased at an appropriate voltage using the on-chip clamp. PGA Register Value Bit4, bit5 and bit6 in MUX register select the desired input among red, green and blue. 4) 1-Channel SHA Operation This mode enables single-channel or monochrome sampling. The CDS function is replaced with the sample and hold amplifier. The input waveforms are either dc coupled or dc restored to the analog input pin. The input reference voltage in this mode will be defined by clamp level control register. Bit4, bit5 and bit6 in MUX register select the desired input among red, green and blue. SEC ASIC 9 MIXED AFE16 16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR BLOCK DIAGRAM VDDA1 VSSA1 VDDA2 VSSA2 VDDDR VSSDR REFT VCOM REFB RED R_VIN CDS CLAMP PGA R_OFFSET[8:0] DAC REF R_GAIN[5:0] GREEN G_VIN PGA CDS CLAMP MUX 16-bit ADC 14 8 16:8 MUX D[7:0] G_OFFSET[8:0] DAC G_GAIN[5:0] OEB BLUE B_VIN PGA CDS CLAMP Configuration Register B_OFFSET[8:0] DAC B_GAIN[5:0] SDATA R_OFFSET[8:0] Input Offset G_OFFSET[8:0] Register B_OFFSET[8:0] (R,G,B) OFFSET R_GAIN[5:0] G_GAIN[5:0] MPU SCLK PORT SLOAD PGA Gain Register (R,G,B) B_GAIN[5:0] CDS1_CLK SEC ASIC CDS2_CLK ADCCLK 10 MIXED AFE16 16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR 2) INTERNAL REGISTER OVERVIEW The internal register map is accessed through serial data pin SDATA's A0, A1 and A2. Register Map Address Data Bits Register A2 A1 A0 D8 D7 D6 D5 D4 D3 D2 D1 D1 Configuration 0 0 0 0 0 0 3Ch/1Ch CDS on 0 PWR Dn 0 0 MUX 0 0 1 0 RGB/BGR Red Green Blue 0 0 0 0 Red PGA 0 1 0 0 0 0 MSB LSB Green PGA 0 1 1 0 0 0 MSB LSB Blue PGA 1 0 0 0 0 0 MSB LSB Red Offset 1 0 1 MSB LSB Green Offset 1 1 0 MSB LSB Blue Offset 1 1 1 MSB LSB Configuration Register D8 D7 D6 Set to 1* 0 X D5 D4 # of Channels CDS Operation 1=3-CH mode* 1=CDS Mode* 0=1-CH mode 0=SHA Mode* D3 1* X D2 D1 D0 Power Down Set to 0 1=On 0=Off (Operation)* *Power-on Default Value, X: Don't care MUX Register D8 Set to 0 D7 D6 D5 D4 3-CH Select 1-CH 1-CH 1-CH 1=R-G-B* 1=RED* 1=Green 1=Blue 0=B-G-R 0=Off 0=Off* 0=Off* D3 D2 D1 D0 Set to 0 *Power-on Default Value SEC ASIC 11 MIXED AFE16 16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR PGA Gain Register Gain Gain (V/V) (dB) 0* 1 0 0 1 1.083 0.693 0 1 0 1.167 1.341 D8 D7 D6 D5(MSB) D4 D3 D2 D1 D0(LSB) 0* 0* 0* 0* 0* 0* 0* 0* 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . 0 0 0 1 1 1 1 1 0 6.167 15.801 0 0 0 1 1 1 1 1 1 6.25 15.918 *Power-on Default Value Offset Register D8(MSB) Offset D7 D6 D5 D4 D3 D2 D1 D0(LSB) 0* 0* 0* 0* 0* 0* 0* 0* 0* 0 0 0 0 0 0 0 0 0 1 0.781 0 0 0 0 0 0 0 1 0 1.563 Sign Bit (mV) . . . 0 1 1 1 1 1 1 1 1 200 1 0 0 0 0 0 0 0 0 -0.781 1 0 0 0 0 0 0 0 1 -1.563 1 1 1 -200 . . . 1 1 1 1 1 1 *Power-on Default Value SEC ASIC 12 MIXED AFE16 16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR INPUT COUPLING CAPACITOR OVERALL TRANSFER FUNCTION The overall transfer function can be calculated as Because of the DC offset present at the output of follows. CCD, ADCout=[(Vin+Input_Offset)* PGA_Gain]/(2*REF)*65536, some kind of DC restoration is required. In case of CDS enable mode, to simplify input level shifting, a DC decoupling where REF is equal to (REFT-REFB) and Input _Offset means the DAC value of the input offset register. The analog offset range of the input offset register is varied between 200mV and -200 mV. The 9-bit data format for the input offset register is sign magnitude, with D8 as the sign bit. To maximize the dynamic range of the ADC input, it is necessary to program the input offset register code to move the ADC code corresponding to the black level towards 'zero'. And also PGA_gain is to maximize the dynamic range of the 16-bit ADC's input. The PGA_gain range is varied between 1 and 6.25 by PGA gain register. The 6-bit data format for the PGA gain register is straight binary coding. capacitor is used in conjuction with the internal input circuitry. The capacitor charging or discharging depends on the clamping time, the analog input resistance of the AFE and the output resistance of the circuit driving the coupling capacitor. The clamping time is typically (n*T), where n is the number of periods CDSCLK1 is asserted and T is the period of assertion. CDSCLK2 should not be asserted during clamping time. The analog input resistance of the AFE's Clamp is equal to 1 kΩ. The recommended input coupling capacitor is more than 0.1uF. The time constant of the input clamp is determined by the internal 1K resistance and the external 0.1uF input capacitance. Thus, to extend the clamping time, the time a transport motor moves the scanner carriage can be available, for example. SEC ASIC 13 MIXED AFE16 16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR POWER-ON INITIALIZATION CALIBRATION Decide clamp level for SHA mode (Refer to next page) Set PGA gain (Input offset = 0 mV) Write to configuration register Set CDS or SHA operation Set 3 or 1 channel mode Set color pointer Set clamp mode Scan dark line Compute pixel offsets Write to PGA gain register Set to gain of one(000000) Set input offset Write to input offset register Set to 0mV(100000000) Set odd/even offset in back end YES YES Set another color Set another color NO NO Set gain/offset bus size in back end Set external pixel offset in back end Scan white line Compute pixel gains in back end YES Adjust PGA gain NO SEC ASIC 14 MIXED AFE16 16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR CORE EVALUATION GUIDE 0.1u 0.1u 0.1u AVSSD AVDDD AVSSA REFT VCOM REFB AVDDA OEB R_VIN D[7:0] G_VIN afe16 B_VIN SDATA SCLK SLOAD OFFSET AVBBA AVBBD CDS2_CLK CDS1_CLK ADCCLK TIMING GENERATOR MPU INTERFACE MUX DSP ASIC MUX Externally forced digital input/output SEC ASIC 15 MIXED AFE16 16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR APPLICATIONS INFORMATION CDS Mode Applications - The recommended input coupling capacitor value is 0.1uF. - A single ground plane is recommended for the afe16. Thus the digital pins should be well decoupled to the analog ground plane. - If possible, a separate power supply should be used for VDDDR, but this supply pin should still be decoupled to the same ground plane as the rest of the afe16. - The loading of digital outputs should be minimized. - All 0.1uF decoupling capacitors should be located as close as possible to the afe16 pins. - When operating in single channel mode, the unused analog inputs must be grounded. 0.1u 1 CDSCLK1 VDDA2 28 2 CDSCLK2 VSSA2 27 3 ADCCLK R_VIN 26 4 OEB OFFSET 25 5 VDDDR G_VIN 24 6 VSSDR VCOM 23 7 D7(MSB) B_VIN 22 0.1u 0.01u 0.01u 0.1u 0.1u afe16 8 D6 REFT 21 9 D5 REFB 20 10 D4 VSSA1 19 11 D3 VDDA1 18 12 D2 SLOAD 17 13 D1 SCLK 16 14 D0(LSB) SDATA 15 1.0u 0.01u 0.1u 10u 0.1u 0.1u 0.1u Data Outputs 3-Channel CDS Mode Application Circuit Configuration SEC ASIC 16 MIXED AFE16 16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR SHA Mode Applications - All of the CDS mode's considerations also apply for this configuration, except that analog inputs are directly connected to the afe16 without coupling capacitors. - The OFFSET pin may be used in a CIS application for DC offset adjustment. By connecting the appropriate dc voltage to the OFFSET pin, the CIS signal will be restored to "zero". 0.1u 1 CDSCLK1 VDDA2 28 2 CDSCLK2 VSSA2 27 3 ADCCLK R_VIN 26 4 OEB OFFSET 25 5 VDDDR G_VIN 24 6 VSSDR VCOM 23 7 D7(MSB) B_VIN 22 8 D6 REFT 21 9 D5 REFB 20 10 D4 VSSA1 19 11 D3 VDDA1 18 12 D2 SLOAD 17 13 D1 SCLK 16 14 D0(LSB) SDATA 15 0.1u 0.1u afe16 0.1u 10u 0.1u 0.1u 0.1u Data Outputs 3-Channel SHA Mode Application Circuit Configuration SEC ASIC 17 MIXED AFE16 16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR PACKAGE PIN DESCRIPTION PIN NO. PIN NAME I/O TYPE DESCRIPTION 1 CDS1_CLK DI CDS Reference Sampling Clock 2 CDS2_CLK DI CDS Data Sampling Clock 3 ADCCLK DI A/D Converter Clock 4 OEB DI Output Enable (Active Low) 5 VDDDR DP Output Buffer Power 6 VSSDR DG Output Buffer Ground 7 D[7] DO 8 D[6] DO Digital Output (D14, D6) 9 D[5] DO Digital Output (D13, D5) 10 D[4] DO Digital Output (D12, D4) 11 D[3] DO Digital Output (D11, D3) 12 D[2] DO Digital Output (D10, D2) 13 D[1] DO Digital Output (D9, D1) 14 D[0] DO Digital Output (LSB) High Byte: D8, Low Byte: D0 15 SDATA DB Serial Interface Data Input/Output 16 SCLK DI Serial Interface Clock Input 17 SLOAD DI Serial Interface Load Pulse 18 VDDA1 AP Analog Power 19 VSSA1 AG Analog Ground 20 REFB AB Reference Decoupling 21 REFT AB Reference Decoupling 22 B_VIN AI Analog Input : Blue 23 VCOM AB Analog Common Voltage 24 G_VIN AI Analog Input : Green 25 OFFSET AB Clamp Bias Level Decoupling 26 R_VIN AI Analog Input : Red 27 VSSA2 DG Digital Ground 28 VDDA2 DP Digital Power SEC ASIC 18 Digital Output (MSB) High Byte: D15, Low Byte: D7 MIXED AFE16 16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR USER GUIDE SYSTEM CONFIGURATION It is necessary that output signal of analog front end be shading-compensated by back end logic block including subtracter and multiplier. (Shading-Compensation Block) Memory CCD/CIS SEC ASIC Subtracter Multiplier AFE 19 Controller MIXED AFE16 16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR Questionnaire for Analog Core Characteristics Symbol Min Typ Max Resolution Signal-to-Noise & Distortion Ratio Unit Bits SNDR dB Conversion Rate 3-Channel with CDS 1-Channel with CDS MSPS MSPS Differential Nonlinearity DNL LSB Integral Nonlinearity INL LSB Unipolar Offset Error %FSR Gain Error %FSR Anlog Input Full-Scale Input Power Supply Analog Voltage Digital Voltage Comment Vp-p VDDA VDDD V V Power Consumption mW Temperature Range ºC - What do you want to choose as power supply voltages? For example, the analog VDD needs to be 3.3V. The digital VDD can be 2.5V/3.3V. - Which modes of AFE do you use for overall system ? (Refer to page 9) For example: 3channel operation with CDS / 3channel SHI(CIS) operation 1channel operation with CDS / 1channel SHI(CIS) operation - Would you define the gain range and input offset range ? - Could you explain external/internal pin configurations as required? - If possible, present other requirements below. SEC ASIC 20 MIXED 16-Bit AFE FOR CCD/CIS SIGNAL PROCESSOR AFE16 HISTORY CARD Version Date ver 1.0 2001.07 Modified Items Comments Original version published (preliminary) SEC ASIC MIXED