June 2000 AS6WA5128 ® 3.0V to 3.6V 512K × 8 Intelliwatt™ low-power CMOS SRAM with one chip enable Features • AS6WA5128 • Intelliwatt™ active power circuitry • Industrial and commercial temperature ranges available • Organization: 524,288 words × 8 bits • 3.0V to 3.6V at 55 ns • Low power consumption: ACTIVE - 144 mW at 3.6V and 55 ns • Easy memory expansion with CS, OE inputs • Smallest footprint packages - 36(48)-ball FBGA 32-pin TSOP I (available September 2000) 32-pin sTSOP I (available September 2000) 32-pin TSOP II (forward) (available September 2000) 32-pin TSOP II (reverse) (available September 2000) • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA • Low power consumption: STANDBY - 72 µW max at 3.6V • 1.2V data retention • Equal access and cycle times Logic block diagram Pin arrangement VCC A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS GND I/O8 512K × 8 Array (4,194,304) Sense amp A0 A1 A2 A3 A4 A5 A6 A7 A8 Row decoder Input buffer I/O1 A9 A10 A11 A12 A13 A14 A15 A16 Column decoder WE OE CS Control circuit 36(48)-CSP BGA Package (shading indicates no ball) 1 2 3 4 5 6 A A0 A1 NC A3 A6 A8 B I/O5 A2 WE A4 A7 I/O1 C I/O6 NC A5 D VSS VCC E VCC VSS F I/O7 G I/O8 H A9 I/O2 A18 A17 OE CS A16 A15 I/O4 A10 A11 A12 A13 A14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-pin TSOPII (Forward) A11 A9 A8 A13 WE A17 A15 VCC A18 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 32-pin TSOPII 32-pin sTSOPI (Forward) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-pin TSOPII (Reverse) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS OE A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3 I/O3 Selection guide VCC Range Product AS6WA5128 7/14/00 Min (V) 3.0 Typ2 (V) 3.3 Max (V) 3.6 Speed (ns) 55 ALLIANCE SEMICONDUCTOR Powered by ICminer.com Electronic-Library Service CopyRight 2003 Power Dissipation Operating (ICC1) Standby (ISB2) Max (mA) Max (µA) 2 20 1 Copyright ©2000 Alliance Semiconductor. All rights reserved. AS6WA5128 ® Functional description The AS6WA5128 is a low-power CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 524,288 words × 8 bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 55 ns are ideal for low-power applications. Active high and low chip selects (CS) permit easy memory expansion with multiple-bank memory systems. When CS is high, the device enters standby mode: the AS6WA5128 is guaranteed not to exceed 72 µW power consumption at 3.6V and 55ns. The device also returns data when VCC is reduced to 1.5V for even lower power consumption. A write cycle is accomplished by asserting write enable (WE) and chip select (CS) low. Data on the input pins I/O1–I/O8 is written on the rising edge of WE (write cycle 1) or CS (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable ( OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE), chip select (CS), with write enable (WE) High. The chip drives I/O pins with the data word referenced by the input address. When either chip select or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. All chip inputs and outputs are CMOS-compatible, and operation is from a single 3.0 to 3.6V supply. The device is available in the JEDEC standard 32-pin TSOP I, 32-pin sTSOP I, 400-mL TSOP II, and 36(48)-ball FBGA packages. Absolute maximum ratings Parameter Device Symbol Min Max Unit Voltage on V CC relative to VSS VtIN –0.5 VCC + 0.5 V Voltage on any I/O pin relative to GND VtI/O –0.5 Power dissipation PD – 1.0 W Storage temperature (plastic) Tstg –65 +150 °C Temperature with VCC applied Tbias –55 +125 °C DC output current (low) IOUT – 20 mA V Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specificati on is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CS WE OE Supply Current I/O1–I/O8 Mode H X X ISB High Z Standby (ISB) L X X ISB High Z Standby (ISB) L H H ICC High Z Output disable (ICC) L H L ICC DOUT Read (ICC) L L X ICC DIN Write (ICC) Key: X = Don’t care, L = Low, H = High. 2 ALLIANCE SEMICONDUCTOR Powered by ICminer.com Electronic-Library Service CopyRight 2003 7/14/00 AS6WA5128 ® Recommended operating condition (over the operating range) Parameter Description Test Conditions Min VOH Output HIGH Voltage IOH = –2.1mA VCC = 3.0V VOL Output LOW Voltage IOL = 2.1mA VCC = 3.0V VIH Input HIGH Voltage VCC = 3.0V VIL Input LOW Voltage VCC = 3.0V IIX Input Load Current IOZ Output Load Current ICC VCC Operating Supply Current Max 2.4 Unit V 0.4 V 2.2 VCC + 0.5 V –0.5 0.8 V GND < VIN < VCC –1 +1 µA GND < VO < VCC; Outputs High Z –1 +1 µA VCC = 3.6V 2 mA CS = VIL, IOUT = 0mA, f = 0, VIN = VIL or VIH ICC1 @ 1 MHz CS < 0.2V, VIN < 0.2V, Average VCC Operating or VIN > VCC – 0.2V, Supply Current at 1 MHz f = 1 mS VCC = 3.6V 2 mA ICC2 Average VCC Operating CS ≠ VIL, VIN = VIL or Supply Current VIH, f = fMax VCC = 3.6V (55 ns) 40 mA ISB CS Power Down Current; CS > VIH, other inputs TTL Inputs = 0V – VCC VCC = 3.6V 100 µA ISB1 CS > VCC – 0.2V, CS Power Down Current; other inputs = 0V – CMOS Inputs VCC, f = fMax VCC = 3.6V 20 µA VCC = 1.2V 2 µA Data Retention ISBDR CS > VCC – 0.1V, f=0 Capacitance (f = 1 MHz, T a = Room temperature, VCC = NOMINAL) Parameter Symbol Signals Test conditions Max Unit Input capacitance CIN A, CS, WE, OE VIN = 0V 5 pF I/O capacitance CI/O I/O VIN = VOUT = 0V 7 pF 7/14/00 ALLIANCE SEMICONDUCTOR Powered by ICminer.com Electronic-Library Service CopyRight 2003 3 AS6WA5128 ® Read cycle (over the operating range) Parameter Symbol Min Max Unit Notes Read cycle time tRC 55 – ns Address access time tAA – 55 ns 3 Chip select (CS) access time tACS – 55 ns 3 Output enable (OE) access time tOE – 25 ns Output hold from address change tOH 10 – ns 5 CS low to output in low Z tCLZ 10 – ns 4, 5 CS high to output in high Z tCHZ 0 20 ns 4, 5 OE low to output in low Z tOLZ 5 – ns 4, 5 OE high to output in high Z tOHZ 0 20 ns 4, 5 Power up time tPU 0 – ns 4, 5 Power down time tPD – 55 ns 4, 5 Shaded areas indicate preliminary information. Key to switching waveforms Rising input Falling input Undefined/don’t care Read waveform 1 (address controlled) tRC Address tOH D OUT tAA tOH Previous data valid Data valid Read waveform 2 (CS, OE controlled) tRC1 CS tOE OE tOLZ tOHZ tACE tCHZ DOUT Data valid tCLZ Supply current 4 tPU tPD 50% 50% ALLIANCE SEMICONDUCTOR Powered by ICminer.com Electronic-Library Service CopyRight 2003 ICC ISB 7/14/00 AS6WA5128 ® Write cycle (over the operating range) Parameter Symbol Min Max Unit Notes Write cycle time tWC 55 – ns Chip select to write end tCW 40 – ns Address setup to write end tAW 40 – ns Address setup time tAS 0 – ns Write pulse width tWP 35 – ns Address hold from end of write tAH 0 – ns Data valid to write end tDW 25 – ns Data hold time tDH 0 – ns 4, 5 Write enable to output in high Z tWZ 0 20 ns 4, 5 Output active from write end tOW 5 – ns 4, 5 12 12 Shaded aread indicate preliminary information. Write waveform 1 (WE controlled) tAW tWC tAH Address tWP WE tAS tDW DIN tDH Data valid tWZ tOW DOUT Write waveform 2 (CS controlled) tAW tWC tAH Address tAS tCW CS tWP WE tWZ DIN tDW tDH Data valid D OUT 7/14/00 ALLIANCE SEMICONDUCTOR Powered by ICminer.com Electronic-Library Service CopyRight 2003 5 AS6WA5128 ® Data retention characteristics (over the operating range) Parameter Symbol VCC for data retention VDR Data retention current ICCDR Chip deselect to data retention time tCDR Operation recovery time Test conditions VCC = 1.2V CS ≥ VCC – 0.1V or VIN ≥ VCC – 0.1V or VIN ≤ 0.1V tR Min Max Unit 1.2V 3.6 V – 2 mA 0 – tRC – ns Data retention waveform Data retention mode VCC VDR ≥ 1.2V VCC VCC tCDR tR VDR VIH CS VIH AC test loads and waveforms VCC OUTPUT Thevenin equivalent: R1 R1 VCC OUTPUT 30 pF 5 pF VCC Typ R2 INCLUDING JIG AND SCOPE (a) V ALL INPUT PULSES R2 INCLUDING JIG AND SCOPE RTH OUTPUT GND 90% 10% (b) 90% < 5 ns 10% (c) Parameters VCC = 3.0V VCC = 2.5V VCC = 2.0V Unit R1 1105 16670 15294 Ohms R2 1550 15380 11300 Ohms RTH 645 8000 6500 Ohms VTH 1.75V 1.2V 0.85V Volts Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 14 6 During V CC power-up, a pull-up resistor to VCC on CS is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions. tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500 mV from steady-state voltage. This parameter is guaranteed, but not tested. WE is HIGH for read cycle. CS and OE are LOW for read cycle. Address valid prior to or coincident with CS transition LOW. All read cycle timings are referenced from the last valid address to the first transitioning address. CS or WE must be HIGH during address transitions. Either CS or WE asserting high terminates a write cycle. All write cycle timings are referenced from the last valid address to the first transitioning address. N/A. 1.2V data retention applies to commercial and industrial temperature range operations. C = 30pF, except at high Z and low Z parameters, where C = 5pF. ALLIANCE SEMICONDUCTOR Powered by ICminer.com Electronic-Library Service CopyRight 2003 7/14/00 AS6WA5128 ® Typical DC and AC characteristics Normalized supply current vs. supply voltage Normalized access time vs. supply voltage 1.4 Normalized standby current vs. ambient temperature 1.0 3.0 2.5 0.8 VIN = VCC typ TA = 25 ° C 0.6 0.4 0.75 Normalized ISB2 1.0 Normalized TAA Normalized ICC 1.2 TA = 25° C 0.5 1.5 1.0 0.5 0.0 0.25 0.2 VCC = VCC typ VIN = VCC typ 2.0 –0.5 0.0 1.7 2.2 2.7 3.2 3.7 Supply voltage (V) 0.0 1.7 2.2 2.7 3.2 3.7 –55 Supply Voltage (V) Normalized standby current vs. supply voltage Normalized ICC vs. Cycle Time 1.4 1.0 Normalized ICC Normalized ISB 1.5 ISB2 1.2 0.8 0.6 VIN = V CC typ TA = 25° C 0.4 0.2 VIN = 3.6V TA = 25 ° C 1.0 0.50 0.10 0.0 1 7/14/00 25 105 Ambient temperature (°C) 2.8 1.9 Supply voltage (V) 3.7 ALLIANCE SEMICONDUCTOR Powered by ICminer.com Electronic-Library Service CopyRight 2003 1 5 10 Supply voltage (V) 15 7 AS6WA5128 ® Package diagrams and dimensions 32-pin Thin Small Outline Package Type I (Forward) (T) 20.00+0.20 +0.10 0.20 -0.05 0.008 +0.004 -0.002 0.787+0.008 #1 #32 8.40 0.331 MAX 0.50 0.0197 #16 8.00 0.315 ( 0.25 ) 0.010 #17 18.40 +0.10 0.528 +0.004 0.25 0.010 TYP +0.10 0.15 -0.05 0.006 +0.004 -0.002 0.05 MIN 0.002 1.00+0.10 0.039+0.004 1.20 MAX 0.047 1.10 MAX 0.004 MAX 0~8o 0.45 ~0.75 0.018 ~0.030 ( 0.50 ) 0.020 32-pin Thin Small Outline Package Type I (Forward) (T) 13.40 +0.10 0.528+0.008 0.20 +0.10 -0.05 0.008 +0.004 -0.002 #1 #32 8.40 0.331 MAX 0.50 0.0197 #16 #17 11.80 +0.10 0.465 +0.004 0.25 0.010 TYP 1.00+0.10 0.039+0.004 0.05 MIN 0.002 +0.10 1.20 -0.05 0.047 MAX +0.004 0.006 -0.002 0.15 1.10 MAX 0.004 MAX 0~8o 0.45 ~0.75 0.018 ~0.030 8 8.00 0.315 ( 0.25 ) 0.010 ( 0.50 ) 0.020 ALLIANCE SEMICONDUCTOR Powered by ICminer.com Electronic-Library Service CopyRight 2003 7/14/00 AS6WA5128 ® 0~8o 32-pin Thin Small Outline Package Type II (Forward) (HE) #32 #17 ( 0.25 ) 0.010 11.76+0.20 0.463+0.008 10.16 0.400 0.45~0.75 0.018~0.030 #1 #16 1.00+0.10 0.039+0.004 21.35 MAX 0.841 1.20 MAX 0.047 20.95 +0.10 0.825 +0.004 +0.10 0.15 -0.05 0.006+0.004 -0.002 ( 0.50 ) 0.020 1.10 MAX 0.004 MAX 0.05 MIN 0.002 ( 0.95 ) 0.037 1.27 0.050 0.40 +0.10 0.016 +0.004 0~8o 32-pin Thin Small Outline Package Type II (Reverse) (HR) #1 ( 0.25 ) 0.010 #16 0.45~0.75 0.018~0.030 11.76+0.20 10.16 0.400 0.463+0.008 #32 #17 1.00+0.10 0.039+0.004 21.35 MAX 0.841 +0.10 0.15 -0.05 0.006+0.004 -0.002 ( 0.50 ) 0.020 1.20 MAX 0.047 20.95 +0.10 0.825 +0.004 1.10 MAX 0.004 MAX 0.05 MIN 0.002 0.95 ( ) 0.037 7/14/00 0.40 +0.10 0.016 +0.004 1.27 0.050 ALLIANCE SEMICONDUCTOR Powered by ICminer.com Electronic-Library Service CopyRight 2003 9 AS6WA5128 ® 36(48)-ball FBGA Bottom View 6 5 4 3 Top View 2 Ball #A1 index Ball #A1 1 A B C D SRAM Die C1 C E F A1 G H Elastomer A B B1 Detail View Side View A E2 D E E2 Y E Die Die E1 10 0.3/Typ Minimum Typical Maximum A – 0.75 – B 6.90 7.00 7.10 1. Bump counts: 36(48) (8 row × 6 column). B1 – 3.75 – 2. Pitch: (x,y) = 0.75 mm × 0.75 mm (typ). C 10.90 11.00 11.10 C1 – 5.25 – D 0.30 0.35 0.40 5. Typ: typical. E – – 1.20 6. Y is coplanarity: 0.08 (max). E1 – 0.68 – E2 0.22 0.25 0.27 Y – – 0.08 Notes 3. Units: millimeters. 4. All tolerance are ±0.050 unless otherwise specified. ALLIANCE SEMICONDUCTOR Powered by ICminer.com Electronic-Library Service CopyRight 2003 7/14/00 AS6WA5128 ® Ordering codes Speed (ns) 55 55 Ordering Code Package Type AS6WA5128-TC 32-pin 8×20 TSOP I AS6WA5128-STC 32-pin 8×13.4 TSOP I AS6WA5128-HFC 32-pin TSOP II (forward) AS6WA5128-HRC 32-pin TSOP II (reverse) AS6WA5128-BC 48-ball fine pitch BGA AS6WA5128-TI 32-pin 8×20 TSOP I AS6WA5128-STI 32-pin 8×13.4 TSOP I AS6WA5128-HFI 32-pin TSOP II (forward) AS6WA5128-HRI 32-pin TSOP II (reverse) AS6WA5128-BI 48-ball fine pitch BGA Operating Range Commercial Industrial Part numbering system AS6WA SRAM Intelliwatt™ prefix 7/14/00 5128 T, ST, HF, HR, B C, I Device number Package: T: TSOP I ST: sTSOPI HF: TSOP2 Forward HR: TSOP2 Reverse B: CSP BGA Temperature range: C: Commercial: 0° C to 70° C I: Industrial: –40°C to 85° C ALLIANCE SEMICONDUCTOR 11 Copyright © 2000. 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The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such lifesupporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. Powered by ICminer.com Electronic-Library Service CopyRight 2003