Preliminary Datasheet FS8806/FS8826 Data Sheet Product Name FS8806/FS8826 Date 2007/1/31 1 Issue Date: January, 2007 Rev. 1.3 The above information is the exclusive intellectual property of FameG and shall not be disclosed, distributed or reproduced without permission from FameG Preliminary Datasheet FS8806/FS8826 Contents CONTENTS .........................................................................................................................................................2 1. FEATURES ....................................................................................................................................................3 2. GENERAL DESCRIPTION..........................................................................................................................3 3. CONNECTION DIAGRAMS........................................................................................................................3 4. ELECTRICAL SECIFICATIONS.................................................................................................................4 4.1. ABSOLUTE MAXIMUM RATING .........................................................................................................4 4.2. OPERATING CONDITION ..................................................................................................................4 4.3. CAPACITANCE ................................................................................................................................4 4.4. DC CHARACTERISTICS ...................................................................................................................5 4.5. AC CHARACTERISTICS ...................................................................................................................6 4.5.1. I2C AC Characteristics .........................................................................................................6 4.5.2. SPI AC Characteristics.........................................................................................................7 4.5.3. SPI Mode Selection..............................................................................................................8 5. APPLICATION CIRCUIT ..................................................................................................................9 5.1. ONLY I2C MODE .............................................................................................................................9 5.2. I2C AND SPI MODE .........................................................................................................................9 6. PACKAGE DIMENSION .............................................................................................................................10 7. PRODUCT ORDER INFORMATION.........................................................................................................11 8. REVISION HISTORY ...................................................................................................................................12 2 Issue Date: January, 2007 Rev. 1.3 The above information is the exclusive intellectual property of FameG and shall not be disclosed, distributed or reproduced without permission from FameG Preliminary Datasheet FS8806/FS8826 1. Features Secure the authentication and completeness of embedded software Supports I2C and SPI serial interface with secure information exchanged Supports I2C standard mode (100 kbit/s) and fast mode (400 kbit/s) Supports SPI two clock modes, CPOL=0, CPHA=0 and CPOL=1, CPHA=1 under 100 kbit/s or 400 kbit/s. Support 768 bits EEPROM to store user data 8-pin SOP package Part Number CLK Frequency Range FS8806 1M ~ 10MHz FS8826 1M ~ 80MHz 2. General Description FS8806/FS8826 is a companion chip with a solution to authenticate the embedded software license right at the embedded system. It provides a simple and easy solution to implement authentication mechanism in an embedded system. Just connect FS8806/FS8826 with host CPU via I2C or SPI and add pieces of concerto software in original run-time software, then a secure system is ready. The authentication for the embedded software (ESW) license is also very easy. The ESW failed to run in the customer board without FS8806/FS8826 companion or the unmatched FS8806/FS8826 connected with customer board. Two application configurations are shown as below: C ustom er B oard - A C ustom er B oard - B Flash E SW C oncerto SW E SW C oncerto SW M a in C P U M ain C P U I2C /S P I I2C /S P I F S 8 80 6 F S 8 82 6 F S 880 6 F S 882 6 3. Connection Diagrams 8 VDD SDA 1 SCL 2 CLK 3 FS8806 FS8826 6 SS_N 5 RST_N GND 4 Pin NO. 7 SDOUT Pin Name I/O 1 SDA I/O 2 SCL I/O 3 4 5 6 CLK GND RST_N SS_N I I 7 SDOUT I/O 8 VDD I Description Open-drain configuration with external pull-up resistor. I2C serial data or SPI slave data input. 3.3V/5V tolerant. Open-drain configuration with external pull-up resistor. I2C or SPI serial clock. 3.3V/5V tolerant. Clock input. 3.3V/5V tolerant. Ground. Low active hardware reset. 3.3V/5V tolerant. Low active SPI slave select. 3.3V/5V tolerant. Open-drain output with external pull-up resistor. SPI slave data output. 3.3V/5V tolerant. 3.3V VDD. 3 Issue Date: January, 2007 Rev. 1.3 The above information is the exclusive intellectual property of FameG and shall not be disclosed, distributed or reproduced without permission from FameG Preliminary Datasheet FS8806/FS8826 4. Electrical Secifications 4.1. Absolute Maximum Rating Symbol Parameter Min. Max. Unit 0 TSTG Storage Temperature -10 85 VIO Input and Output Voltage -0.5 VCC+0.5 V -4000 4000 V Electrostatic Discharge Voltage (Machine mode) -200 200 V Latch-up -200 200 mA Min. Max. Unit 3.0 3.6 VESD VESD Electrostatic Discharge Voltage (Human Body mode) C 4.2. Operating Condition Symbol VCC TA FS8806 CLK Parameter Supply Voltage V 0 Ambient Operating Temperature 0 70 I2C under 100kbit/s 1 10 MHz I C 400kbit/s 4 10 MHz SPI under 100kbit/s 1 10 MHz 2 C (Note 1,2) SPI 400kbit/s 2.5 10 MHz 2 1 80 MHz 2 I C 400kbit/s 32 80 MHz SPI under 100kbit/s 1 80 MHz SPI 400kbit/s 20 80 MHz I C under 100kbit/s FS8826 CLK (Note 1,3) Note: 1. Concerto software need to do proper modification when CLK frequency changes. 2. CLK frequency must be more than 10 times I2C/SPI serial clock of FS8806. 3. CLK frequency must be more than 80 times I2C/SPI serial clock of FS8826. 4.3. Capacitance Symbol CIN COUT Parameter Test Condition Min. Max. Unit Input Capacitance VIN = 0V -- 10 pF Output Capacitance VOUT = 0V -- 10 pF 4 Issue Date: January, 2007 Rev. 1.3 The above information is the exclusive intellectual property of FameG and shall not be disclosed, distributed or reproduced without permission from FameG Preliminary Datasheet FS8806/FS8826 4.4. DC Characteristics CLK: 10MHz Operation Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Test Condition Min. Typ. Max. Unit VIN = VCC or GND -- 0.01 1 uA VOUT = VCC or GND -- 0.01 1 uA I2C at 100kbit/s -- 3.3 -- mA I C at 400kbit/s -- 3.5 -- mA SPI at 100kbit/s -- 3.3 -- mA SPI at 400kbit/s -- 3.5 -- mA ICC1 Operating Current ICC2 Operating Current ISB1 Standby Current) CLK signal is running -- 160 -- uA ISB2 Standby Current CLK signal is stop -- 10 -- uA VIL Input Low Voltage VCC = 3.3V -- -- 0.8 V VIH Input High Voltage VCC = 3.3V 2.4 -- -- V VOL Output Low Voltage VCC = 3.3V -- -- 0.4 V VOH Output High Voltage VCC = 3.3V 3 -- -- V 2 5 Issue Date: January, 2007 Rev. 1.3 The above information is the exclusive intellectual property of FameG and shall not be disclosed, distributed or reproduced without permission from FameG Preliminary Datasheet FS8806/FS8826 4.5. AC Characteristics 4.5.1. I2C AC Characteristics CLK: 10MHz Operation Symbol Standard-Mode Min. Max. Parameter fSCL tHD;STA tLOW tHIGH tHD;DAT tSU;DAT tr tf SCL clock frequency Hold time START condition Low period of SCL clock HIGH period of SCL clock Data hold time Data setup time Rise time of SDA and SCL Fall time of SDA and SCL Setup time for STOP tSU;STO condition Bus free time between STOP tBUF and START condition Cb = capacitance of one bus line in pF. Fast-Mode Min. Max. Unit 0 4.0 4.7 4.0 0 250 --- 100 ---3.45 -1000 300 0 0.6 1.3 0.6 0 100 20+0.1Cb 20+0.1Cb 400 ---0.9 -300 300 kHz us us us us ns ns ns 4.0 -- 0.6 -- us 4.7 -- 1.3 -- us tf SDA tBUF tr tr tSU;DAT tLOW tf SCL tHD;STA S tHD;DAT 6 tHIGH tSU;STO P Issue Date: January, 2007 Rev. 1.3 The above information is the exclusive intellectual property of FameG and shall not be disclosed, distributed or reproduced without permission from FameG S Preliminary Datasheet FS8806/FS8826 4.5.2. SPI AC Characteristics CLK: 10MHz Operation Symbol Parameter 100kHz-Mode Min. Max. 400kHz-Mode Min. Max. Unit tDC Data to SCL setup time 100 -- 100 -- ns tCDH SCL to Data hold time 100 -- 100 -- ns tCDD SCL to Data delay -- 200 -- 200 ns tCL SCL low time -- 5 -- 1.25 us tCH SCL high time -- 5 -- 1.25 us tCLK SCL clock frequency -- 100 -- 400 kHz tR, tF SCL rise and fall time -- 100 -- 100 ns tCC SS_N to SCL setup time 5 -- 1.25 -- us tCCH SCL to SS_N hold time 5 -- 1.25 -- us tCWH SS_N inactive time 5 -- 1.25 -- us SS_N tCC tCWH tDC tCL SCL tCH tCDH SDA D7 tR D6 tF D1 D0 tCCH SS_N tCDD SCL SDOUT D7 D6 D1 D0 SCL CAN BE EITHER POLARITY, TIMING SHOWN FOR CPOL=1 7 Issue Date: January, 2007 Rev. 1.3 The above information is the exclusive intellectual property of FameG and shall not be disclosed, distributed or reproduced without permission from FameG Preliminary Datasheet FS8806/FS8826 4.5.3. SPI Mode Selection FS8806/FS8826 will operate in I2C mode by default. SPI mode will be entered by receiving 3 rising pulses on SS_N pin after hardware reset. The waveform is shown as below. It will still enter SPI mode if more than 3 rising pulses on SS_N is detected. It is suggested to connect SS_N to power or ground when operating in I2C mode. This serial interface operation mode will be reset only by hardware reset and it will not be changed by software reset. 1 2 3 SS_N Enter SPI mode on third rising edge 8 SPI data transfer starts Issue Date: January, 2007 Rev. 1.3 The above information is the exclusive intellectual property of FameG and shall not be disclosed, distributed or reproduced without permission from FameG Preliminary Datasheet FS8806/FS8826 5. Application Circuit 5.1. Only I2C mode FS8806/FS8826 5.2. I2C and SPI mode FS8806/FS8826 9 Issue Date: January, 2007 Rev. 1.3 The above information is the exclusive intellectual property of FameG and shall not be disclosed, distributed or reproduced without permission from FameG Preliminary Datasheet FS8806/FS8826 6. Package Dimension SYMBOLS MIN. MAX. A 0.053 0.069 A1 0.004 0.010 A2 — 0.059 D 0.189 0.196 E 0.150 0.157 H 0.228 0.244 L 0.016 0.050 θ0 0 8 UNIT: INCH NOTES: 1. 2. 3. JEDEC OUTLINE: MS-012 AA DIMENSIONS “D” DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.MOLD FLASH, PROTRUSIONS AND GATE BURRS SHALL NOT EXCEED .15mm (.006in) PER SIDE. DIMENSIONS “E” DOES NOT INCLUDE INTER-LEAD FLASH OR PROTRUSIONS. INTER-LEAD FLASH AND PROTURSIONS SHALL NOT EXCEED .25mm (.010in) PER SIDE. 10 Issue Date: January, 2007 Rev. 1.3 The above information is the exclusive intellectual property of FameG and shall not be disclosed, distributed or reproduced without permission from FameG Preliminary Datasheet FS8806/FS8826 7. Product Order Information FS8806 - ESPL Package Type ESPL = 8-pins SOP (Non-RoHS) ESPR = 8-pins SOP(RoHS) FameG ASoC Device Name Part Number Package Type FS8806ESPL 8-pin SOP Package (Non-RoHS) FS8806ESPR 8-pin SOP Package (RoHS) FS8826ESPR 8-pin SOP Package (RoHS) 11 Issue Date: January, 2007 Rev. 1.3 The above information is the exclusive intellectual property of FameG and shall not be disclosed, distributed or reproduced without permission from FameG Preliminary Datasheet FS8806/FS8826 8. Revision History Rev. Date Page Description of Changes V1.0 March.2006 10 Initial Release V0.2 March.2006 9 Re-compose V0.3 March.2006 9 Revise DC Characteristics V1.0 Mar.28.2006 10 Initial Release to Customers. V1.1 Aug.29.2006 10 Revise DC Characteristics. V1.2 Dec.29.2006 10 V1.3 Jan.31.2007 12 1. Revise CLK descriptions in DC Characteristics section. 2. Revise page header. 1. Revise for FS8826 2. Add package dimension 12 Issue Date: January, 2007 Rev. 1.3 The above information is the exclusive intellectual property of FameG and shall not be disclosed, distributed or reproduced without permission from FameG