2 2 SCHS303 – JANUARY 2001
AC Types Feature 1.5-V to 5.5-V Operation
CD54AC00 . . . F PACKAGE
CD74AC00 . . . E OR M PACKAGE
(TOP VIEW)
and Balanced Noise Immunity at 30% of the
Supply
Speed of Bipolar FCT, AS, and S, With
Significantly Reduced Power Consumption
Balanced Propagation Delays
±24-mA Output Drive Current
– Fanout to 15 FCT Devices
– Drives 50-Ω Transmission Lines
SCR-Latchup-Resistant CMOS Process and
Circuit Design
Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
1A
1B
1Y
2A
2B
2Y
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
4B
4A
4Y
3B
3A
3Y
description
The ‘AC00 devices contain four independent 2-input NAND gates. Each gate performs the Boolean function
of Y = A B or Y = A + B in positive logic.
ORDERING INFORMATION
PDIP – E
–40°C
40 C to 85°C
85 C
ORDERABLE
PART NUMBER
PACKAGE†
TA
SOIC – M
Tube
CD74AC00E
Tube
CD74AC00M
Tape and reel
CD74AC00M96
TOP-SIDE
MARKING
CD74AC00E
AC00M
–55°C to 125°C
CDIP – F
Tube
CD54AC00F3A
CD54AC00F3A
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB
design guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS
A
B
OUTPUT
Y
H
H
L
L
X
H
X
L
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
%(")+'-%)( %, .++!(- , )" *.&%-%)( -!
+) .-, )(")+' -) ,*!%"%-%)(, *!+ -$! -!+', )" !0, (,-+.'!(-,
,-( + /++(-1 +) .-%)( *+)!,,%(# )!, ()- (!!,,+%&1 %(&. !
-!,-%(# )" && *+'!-!+,
( *+) .-, )'*&%(- -) 22
&& *+'!-!+, +! -!,-!
.(&!,, )-$!+/%,! ()-! ( && )-$!+ *+) .-, *+) .-%)(
*+)!,,%(# )!, ()- (!!,,+%&1 %(&. ! -!,-%(# )" && *+'!-!+,
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1
SCHS303 – JANUARY 2001
logic symbol†
1A
1B
2A
2B
3A
3B
4A
4B
1
&
2
3
1Y
4
6
5
2Y
9
8
10
3Y
12
11
13
4Y
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram, each gate (positive logic)
A
Y
B
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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•
SCHS303 – JANUARY 2001
recommended operating conditions (see Note 3)
TA = 25°C
MIN
MAX
VCC
VIH
VIL
VI
VO
Supply voltage
1.5
High-level
High
level in
input
ut voltage
Input transition rise or fall rate
1.5
5.5
1.5
5.5
2.1
2.1
3.85
3.85
1.2
0.3
0
∆t/∆v
MAX
2.1
VCC = 4.5 V
VCC = 5.5 V
Low level output current
Low-level
MIN
3.85
Output voltage
IOL
MAX
VCC = 5.5 V
VCC = 1.5 V
0
High level output current
High-level
MIN
1.2
Input voltage
IOH
CD74AC00
VCC = 1.5 V
VCC = 3 V
VCC = 3 V
VCC = 5.5 V
Low-level
Low
level in
input
ut voltage
5.5
CD54AC00
0.3
V
0.3
0.9
0.9
0.9
1.65
1.65
0
0
V
1.2
1.65
VCC
VCC
UNIT
VCC
VCC
0
0
VCC
VCC
–24
–24
–24
–24
–24
–24
24
24
24
24
24
24
VCC = 4.5 V
VCC = 5.5 V
VCC = 1.5 V to 3 V
0
50
0
50
0
50
VCC = 3.6 V to 5.5 V
0
20
0
20
0
20
V
V
V
mA
mA
ns/V
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = –50
50 µA
VOH
VI = VIH or VIL
II
ICC
VI = VIH or VIL
VI = VCC or GND
VI = VCC or GND,
CD54AC00
CD74AC00
MIN
MIN
MAX
1.5 V
1.4
1.4
1.4
3V
2.9
2.9
2.9
4.5 V
4.4
4.4
4.4
IOH = –4 mA
IOH = –24 mA
IOH = –50 mA†
3V
2.58
2.4
2.48
4.5 V
3.94
3.7
3.8
IOH = –75 mA†
5.5 V
5.5 V
IOL = 50 µA
VOL
TA = 25°C
MIN
MAX
MAX
V
3.85
3.85
1.5 V
0.1
0.1
0.1
3V
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
IOL = 12 mA
IOL = 24 mA
IOL = 50 mA†
3V
0.36
0.5
0.44
4.5 V
0.36
0.5
0.44
IOL = 75 mA†
5.5 V
5.5 V
IO = 0
UNIT
V
1.65
1.65
5.5 V
±0.1
±1
±1
µA
5.5 V
4
80
40
µA
Ci
10
10
10
pF
† Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize
power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.
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3
SCHS303 – JANUARY 2001
switching characteristics over recommended operating free-air temperature range,
VCC = 1.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
Y
CD54AC00
CD74AC00
MIN
MIN
MAX
MAX
91
83
91
83
UNIT
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
Y
CD54AC00
CD74AC00
MIN
MAX
MIN
MAX
2.6
10.2
2.7
9.3
2.6
10.2
2.7
9.3
UNIT
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
Y
CD54AC00
CD74AC00
MIN
MAX
MIN
MAX
1.8
7.3
1.9
6.6
1.8
7.3
1.9
6.6
UNIT
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
4
TYP
Power dissipation capacitance
45
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UNIT
pF
SCHS303 – JANUARY 2001
PARAMETER MEASUREMENT INFORMATION
S1
R1 = 500 Ω†
From Output
Under Test
2 × VCC
Open
GND
CL = 50 pF
(see Note A)
R2 = 500 Ω†
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
tw
VCC
† When VCC = 1.5 V, R1 = R2 = 1 kΩ
Input
50% VCC
50% VCC
0V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATION
CLR
Input
VCC
Reference
Input
VCC
50% VCC
50% VCC
0V
0V
tsu
trec
Data
50%
Input 10%
VCC
50% VCC
CLK
90%
VOLTAGE WAVEFORMS
RECOVERY TIME
tf
VCC
50% VCC
50% VCC
tPLH
tPHL
50%
10%
90%
90%
tr
tPHL
Out-of-Phase
Output
VCC
50% VCC
10% 0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
0V
In-Phase
Output
90%
tr
0V
Input
th
90%
VOH
50% VCC
10%
VOL
tf
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
50% VCC
10%
tf
50%
10%
90%
tr
VOH
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VCC
Output
Control
50% VCC
50% VCC
0V
tPLZ
tPZL
50% VCC
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
≈VCC
20% VCC
VOL
50% VCC
VOH
80% VCC
≈0 V
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
Phase relationships between waveforms are arbitrary.
D. For clock inputs, fmax is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLH and tPHL are the same as tpd.
G. tPZL and tPZH are the same as ten.
H. tPLZ and tPHZ are the same as tdis.
Figure 1. Load Circuit and Voltage Waveforms
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5
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