CGS2537V Commercial Quad 1 to 4 Clock Drivers CGS2537TV Industrial Quad 1 to 4 Clock Drivers General Description Features These Clock Generation and Support clock drivers are specifically designed for driving memory arrays requiring large fanouts while operating at high speeds. CGS2537 is a 4 to 16 inverting driver with TTL compatible I/Os. This device features the same characteristics of CGS2534 with an added series resistor on the output for ease of termination while reducing the undershoot. This device has skew specifications of 350 ps pin-to-pin as well as a 650 ps specification for part-to-part propagation delay variation. Y Y Y Y Y Y Y Y Y Y Nominal 8X output series resistor Guaranteed and tested: Ð 350 ps pin-to-pin skew (TOSHL and TOSLH) 650 ps part-to-part variation on positive OR negative transition Implemented on National’s ABT family process Output current drive: Ð b36 mA/ a 20 mA IOH/IOL Industrial temperature of b40§ C to a 85§ C 28-pin PLCC for optimum skew performance Symmetric package orientation Large fanout for memory driving applications Guaranteed 2 kV ESD protection Connection Diagrams Pin Assignment for 28-Pin PLCC TL/F/11957 – 2 CGS2537 Truth Table Input Output In (0 – 3) ABCD Out (0–3) TL/F/11957 – 1 C1995 National Semiconductor Corporation TL/F/11957 RRD-B30M115/Printed in U. S. A. CGS2537V Commercial Quad 1 to 4 Clock Drivers CGS2537TV Industrial Quad 1 to 4 Clock Drivers September 1995 Absolute Maximum Ratings (Note) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) Input Voltage (VI) Input Current Current Applied to Output (High/Low) Supply Voltage (VCC) 4.5V to 5.5V Maximum Input Rise/Fall Time (0.8V to 2.0V) 5 ns Free Air Operating Temperature b 40§ C to a 85§ C Industrial Commercial 0§ C to a 70§ C 7.0V 7.0V b 30 mA Note: The Absolute Maximum Rating are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the DC and AC Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions will define the conditions for actual device operation. twice the rated IOH/IOL mA b 65§ C to a 150§ C Storage Temperature Range (Tstg) Airflow Typical iJA 0 LFM 62§ C/W 225 LFM 43§ C/W 500 LFM 34§ C/W 900 LFM 27§ C/W DC Electrical Characteristics Over recommended operating free air temperature range. All typical values are measured at VCC e 5V, TA e 25§ C. Symbol Parameter VIL Input Low Level Voltage VIH Input High Level Voltage VIK Input Clamp Voltage VOH High Level Output Voltage (Note 5) VOL Conditions Min Typ Max Unit 0.8 V b 1.2 V 2.0 V VCC e 4.5V, II e b18 mA Low Level Output Voltage (Note 5) 2.4 2.0 V VCC e 4.5V, IOL e 20 mA 0.4 0.5 VCC e 4.5V, IOL e 50 mA 0.1 0.1 V II Input Current VCC e 5.5V, VIH e 7V 7 IIH High Level Input Current VCC e 5.5V, VIH e 2.7V 5 IIL Low Level Input Current VCC e 5.5V, VIL e 0.4V IOS Output Drive Current VCC e 5.5V, VO e 0V IOLD Minimum Dynamic Output Current (Note 1) VCC e 5.5V, VOLD e 0.8V 40 mA IOHD Minimum Dynamic Output Current (Note 1) VCC e 5.5V, VOHD e 2.0V b 55 mA ICCT Maximum ICC/Input VCC e 5.5V 3.6 mA ICC Supply Current Ê 2537 (Quiescent) VCC e 5.5V 235 mA CIN Input Capacitance VCC e 5V @ Max Input Voltage IOH e b3 mA, VCC e 4.5V IOH e b36 mA, VCC e 4.5V Note 1: Maximum test duration 2.0 ms, one output loaded at a time. 2 b5 mA mA mA b 100 275 5 mA pF AC Electrical Characteristics Over recommended operating conditions unless otherwise specified. All typical values are measured at VCC e 5V, TA e 25§ C. CGS2537 Symbol Parameter TA e a 25§ C CL e 50 pF, RL e 500X Min Typ Max TA e b40 to a 85§ C CL e 50 pF, RL e 500X Min Typ Units Max fmax Frequency Maximum tPLH Low-to-High Propagation Delay INn to Outn 3.75 3.75 ns High-to-Low Propagation Delay INn to Outn 3.75 3.75 ns tPHL tOSHL tOSLH 125 MHz Maximum Skew Common Edge Output-to-Output Variation (Note 2) 150 350 300 350 ps Maximum Skew Common Edge Output-to-Output Variation (Note 2) 150 350 300 350 ps 1.7 ns trise, tfall Rise/Fall Time (from 0.8V/2.0V to 2.0V/0.8V) tHIGH tLOW Pulse Width Duration High Pulse Width Duration Low tPVLH Part-to-Part Variation of Low-to-High Transitions (Note 3) 650 650 ps tPVHL Part-to-Part Variation of High-to-Low Transitions (Note 3) 650 650 ps 1.7 4 4 4 4 ns Note 2: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Limits are guaranteed by design. Note 3: Part to Part transition variation is defined as the absolute difference between the propagation delay of any output on one device to any output on another device. The specifications apply to any outputs switching in the same direction either HIGH to LOW (tPVHL) or LOW to HIGH (tPVLH). Limits are guaranteed by design. Note 4: Time high is measured at 2.0V, Time low is measured at 0.8V. Note 5: For increased output drive, output pins may be connected together when the corresponding input pins are connected together. Timing Information TL/F/11957 – 4 3 CGS2534/35/36/37 Memory Array Driving Also this larger fan-out helps to save board space since for every one of these drivers, two conventional buffers were typically being used. Another feature associated with these clock drivers is a 250 ps – 500 ps pin-to-pin skew specification. The minimum skew specification allows high speed memory system designers to optimize the performance of their memory subsystem by operating at higher frequencies without having concerns about output-to-output (bank-to-bank) synchronization problem which are associated with driving high capacitive loads (Point B). The diagram below depicts a ‘‘2534/35/36/37’’ a memory subsystem operating at high speed with large memory capacity. The address bus is common to both the memory and the CPU and I/Os. These drivers can operate beyond 150 MHz, and are also available in 3V – 5V TTL/CMOS versions with large current drive . In order to minimize the total load on the address bus, quite often memory arrays are being driven by buffers while having the inputs of the buffers tied together. Although this practice was feasible in the conventional memory designs, in today’s high speed, large buswidth designs which require address fetching at higher speeds, this technique produces many undesired results such as cross-talk and over/undershoot. CGS2534/35/36/37 Quad 1 to 4 Clock Drivers were designed specifically to address these application issues on high speed, large memory arrays systems. These drivers are optimized to driver large loads, with 3.5 ns propagation delays. These drivers produce less noise while reducing the total capacitive loading on the address bus by having only four inputs tied together (see the diagram below, point A). This helps to minimize the overshoot and undershoot by having only four outputs being switched simultaneously. Device VCC I/O Output Configuration 2534 5 TTL 2535 3 or 5 CMOS Inverting quad 1–4 Non-inverting quad 1–4 2536 3 or 5 CMOS Inverting, Non-inverting, a 2 2537 5 TTL Inverting quad 1–4 with series 8X output resistors TL/F/11957 – 5 4 Ordering Information (Contact NSC Marketing for specific date of availability) CGS 252x T V Family Clock Generation and Support Packaging V e PCC Device Type 2534 2535 2536 2537 Grade Blank e Commercial T e Industrial 5 CGS2537V Commercial Quad 1 to 4 Clock Drivers CGS2537TV Industrial Quad 1 to 4 Clock Drivers Physical Dimensions inches (millimeters) 28-Lead Molded Plastic Leaded Chip Carrier Order Number CGS2537V, CGS2537TV NS Package Number V28A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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