CL81188A Laser-Configured ASIC Family Key Features u Laser-Configured ASIC (LASIC®) technology offers the ultimate combination of performance, flexibility, and low cost u Functionally, architecturally, and electrically compatible with industry-standard FLEX® 8000 series FPGAs u High Density - 12,000 Usable gates - 1,188 Flip-flops - 184 Maximum user I/O pins u Laser fuse technology provides very fast, dense interconnect routing u Optional Instant-On configuration eliminates the need for an external configuration EPROM u Fabricated using 0.5 micron CMOS process u Very low current consumption (active and standby) u Supports 3.3 volt or 5.0 volt I/O operation u Alpha particle immune CL8000 Product Family Overview Parameter CL8282A CL8452A CL8636A CL8820A CL81188A Available Gates 5,000 8,000 12,000 16,000 24,000 Useable Gates 2,500 4,000 6,000 8,000 12,000 Flip-flops 282 452 636 820 1,188 Logic Elements 208 336 504 672 1,008 78 120 136 152 184 84 pin PLCC 100 pin TQFP 84 pin PLCC 100 pin TQFP 160 pin PQFP 84 pin PLCC 160 pin PQFP 208 pin PQFP 144 pin TQFP 160 pin PQFP 208 pin PQFP 208 pin PQFP 240 pin PQFP Max user I/O pins Packages 8K tbl 01 December 2000 Page 1 CL81188A Laser-Configured ASIC Description The Clear Logic CL8000 Laser-Configured ASIC (LASIC®) family offers the ultimate combination of performance, flexibility, and cost. This family is a system level second source to Altera FLEX® 8000 products. For designs not requiring in-system reprogrammability, design verification can be performed using the programmable Altera devices, and Clear Logic LASICs can be used for low cost, high volume production. Clear Logics innovative laser ASIC technology eliminates NRE costs, test vector development, ordering minimums and long lead times. No re-simulation or re-layout is required, as the device is engineered using a cell-based, PLD-like architecture. Clear Logics TestCell technology ensures complete test coverage through the use of specialized testing modes which are transparent to the user. The Clear Logic CL8000 Laser-Configured ASIC family is based upon a large array of logic elements. Each logic element contains a configurable look up table for combinatorial functions and a register for sequential operations. A group of eight logic elements forms a block. Laser-configured metal fuses implement logical functions and control signal routing Laser configuration provides reduced cost and enhanced performance. These inherent performance benefits include extremely consistent propagation delays, reduced power consumption, and improved immunity to noise and upset events. Configuration Clear Logics CL8000 LASIC® family is compatible with all six configuration modes defined for the FLEX® 8000 product family. These configuration modes include the following: u Active Serial u Active Parallel Up u Active Parallel Down u Passive Parallel Synchronous u Passive Parallel Asynchronous u Passive Serial Page 2 CL81188A Laser-Configured ASIC The CL8000 is already configured when it is shipped, and can be configured to bypass the FLEX® 8000 configuration modes. This Instant-On configuration mode eliminates the need for external EPROMs or microcode. In the Instant-On mode, the CL8000 device begins Initialization immediately upon a low-tohigh transition on the nCONFIG pin. Additional Information For further information on designing with the CL8000 LASIC family, please refer to the following documents: u AN-01: Requesting a First Article. This document provides instructions on how to submit a bitstream file for generation of first articles. u AN-02: Clear Logic Packaging Guide. This document provides specifications and drawings for packages used by the CL10K family and other Clear Logic devices. u AN-03: CL8000 and System Configuration. This document contains a detailed discussion of all aspects of configuring CL8000-based systems. u AN-04: CL8000 Technology White Paper. This document outlines the technologies employed by the CL8000 LASIC family. u AN-05: Calculating CL8000 Power Consumption. This document provides guidelines for calculating power consumption based on CL8000 design characteristics. u AN-06: Eliminating the Serial EPROM from FLEX 8000 Designs. This document outlines how additional savings can be achieve by removing the EPROM from the CL8000 LASIC family. u AN-07: CL8000 Test Methodology. This document describes how Clear Logic provides 100% stuck-at fault coverage. u AN-08: CL8000 LASIC Timing and Function Compatibility. This document shows how a seamless conversion from FPGA to ASIC can be achieve with no additional engineering can be achieved with Clear Logic. Page 3 CL81188A Laser-Configured ASIC Block Diagram DI IOE IOE IOE nSP MSEL0 MSEL1 nCONFIG nWS nRS nCS CS CLKUSR nSTATUS DCLK CONF_DONE DATA7 DATA[0:6] RDCLK RDYnBUSY ADD[0:17] TDI TDO TCK TMS nTRST IOE IOE LBB LBB LBB IOE Configuration and Emulation Logic LBB: Logic Building Block IOE: Input/Output Element DI: Dedicated Input IOE LBB LBB LBB IOE IOE LBB LBB LBB IOE IOE LBB LBB LBB IOE IOE LBB LBB LBB IOE IOE LBB LBB LBB Array Size: 126 LBBs (6 Rows by 21 Columns) 81188A drw 01 IOE IOE IOE User-Defined Input/Outputs Page 4 User-Defined Input/Outputs CL81188A Laser-Configured ASIC Pin Configuration Pin Name 208 pin PQFP 240 pin PQFP 5 237 MSEL0 21 21 MSEL1 33 40 nSTATUS 124 141 nCONFIG 107 117 DCLK 154 184 CONF_DONE 138 160 nWS 118 133 nRS 121 137 RDCLK 137 158 nCS 142 166 CS 144 169 RDYnBUSY 128 146 CLKUSR 134 155 ADD17 46 58 ADD16 45 56 ADD15 44 54 ADD14 39 47 ADD13 37 45 ADD12 36 43 ADD11 31 36 ADD10 30 34 ADD9 29 32 ADD8 26 29 ADD7 25 27 ADD6 24 25 ADD5 18 18 ADD4 17 16 nSP 81188A tbl 01A Page 5 CL81188A Laser-Configured ASIC Pin Configuration Pin Name 208 pin PQFP 240 pin PQFP ADD3 16 14 ADD2 10 7 ADD1 9 5 ADD0 8 3 DATA7 177 205 DATA6 175 203 DATA5 172 200 DATA4 170 198 DATA3 168 196 DATA2 166 194 DATA1 163 191 DATA0 161 189 TDI - - TDO - - TCLK - - TMS - - nTRST - - 13, 41, 116, 146 10, 51, 130, 171 VCCINT 4, 20, 35, 48, 50, 102, 114, 131, 147 20, 42, 64, 66, 114, 128, 150, 172, 236 VCCIO 3, 19, 34, 49, 69, 87, 106, 123, 140, 156, 174, 192 19, 41, 65, 81, 99, 116, 140, 162, 186, 202, 220, 235 11, 12, 27, 28, 42, 43, 60, 78, 96, 105, 115, 122, 132, 139, 148, 155, 159, 165, 183, 201 8, 9, 30, 31, 52, 53, 72, 90, 108, 115, 129, 139, 151, 161, 173, 185, 187, 193, 211, 229 NC (No Connect) 1, 2, 51, 52, 53, 54, 103, 104, 157, 158, 207, 208 - Total user I/O pins 144 18 Dedicated Inputs GND 81188A tbl 01B Page 6 CL81188A Laser-Configured ASIC DC Electrical Specifications Absolute Maximum Ratings Symbol Min Max Unit Supply voltage -2.0 7.0 V DC input voltage [1] -2.0 7.0 V IOUT DC output current, per pin -25 25 mA TSTG Storage temperature No bias -65 150 °C TAMB Ambient temperature Under bias -65 135 °C TJ Junction temperature Under bias 135 °C VCC VI Parameter Conditions 8K tbl 02 Recommended Operating Conditions Symbol Parameter VCCINT VCCIO [2] Conditions Min Max Unit Supply voltage, internal logic and input buffers Commercial Grade Devices Industrial Grade Devices 4.75 4.50 5.25 5.50 V V DC input voltage 5.0 volt commercial 5.0 volt industrial 3.3 volt operation 4.75 4.50 3.00 5.25 5.50 3.60 V V V VI Input voltage 0 VCCINT V VO Output voltage 0 VCCIO V TA Operating temperature Commercial temperature range Industrial temperature range 0 -40 70 85 °C °C tR Input signal rise time 40 ns tF Input signal fall time 40 ns VCC rise time 100 ms tRVCC 8K tbl 03 Page 7 CL81188A Laser-Configured ASIC DC Electrical Specifications cont. DC Electrical Characteristics (over the operating range) Symbol Parameter Conditions Min Typ[3] Max Unit VIH Input HIGH Voltage 2.0 VCCINT + 0.3 V VIL Input LOW Voltage -0.3 0.8 V VOH Output HIGH Voltage IOH = -4.0 mA, VCCIO = VCCIO[Min] VOL Output LOW Voltage IOL = 12.0 mA, VCCIO = VCCIO[Min] IIN Input Leakage Current VI = VCC or GND IOZ Output Leakage Current VO = VCC or GND ICC0 Standby Current VI = GND, no load 2.4 V 0.45 V -10 10 µA -40 40 µA 10 mA 0.5 8K tbl 04 Capacitance Symbol Parameter Conditions C IN Input Capacitance COUT Output Capacitance Min Max Unit VIN = 0 V, f = 1.0 MHz 10 pF VOUT = 0 V, f = 1.0 MHz 10 pF 8K tbl 05 Page 8 CL81188A Laser-Configured ASIC AC Electrical Specifications I/O Element Timing Parameters Symbol Parameter [5] Conditions Speed: -2 Min Max Speed: -3 Min Max Speed: -4 Min Max Unit tIOD IOE register data delay 0.7 0.8 0.9 ns tIOC IOE register control signal delay 1.7 1.8 1.9 ns tIOE Output enable delay 1.7 1.8 1.9 ns IOE register clock to output delay 1.0 1.0 1.0 ns 0.3 0.2 0.1 ns tIOCO tIOCOMB IOE combinatorial delay tIOSU IOE register setup time before clock 1.4 1.6 1.8 ns tIOH IOE register hold time after clock 0.0 0.0 0.0 ns tIOCLR tIN IOE register clear delay 1.2 1.2 1.2 ns Input pad and buffer delay 1.5 1.6 1.7 ns tOD1 Output buffer and pad delay Slow Slew Rate = off, VCCIO = 5.0v, C L = 35 pF 1.1 1.4 1.7 ns tOD2 Output buffer and pad delay Slow Slew Rate = off, VCCIO = 5.0v, C L = 35 pF 1.6 1.9 2.2 ns tOD3 Output buffer and pad delay Slow Slew Rate = off, VCCIO = 5.0v, C L = 35 pF 4.6 4.9 5.2 ns tZX Output buffer disable delay C L = 5 pF 1.4 1.6 1.8 ns tZX1 Output buffer disable delay Slow Slew Rate = off, VCCIO = 5.0v, C L = 35 pF 1.4 1.6 1.8 ns tZX2 Output buffer disable delay Slow Slew Rate = off, VCCIO = 5.0v, C L = 35 pF 1.6 2.1 2.3 ns tZX3 Output buffer disable delay Slow Slew Rate = off, VCCIO = 5.0v, C L = 35 pF 4.9 5.1 5.3 ns 8K tbl 06C External Timing Parameters[4] Symbol Parameter tDRR Register to register delay via four LEs, three row interconnects, and four local interconnects tODH Output data hold time after clock Conditions Speed: -2 Min Max Speed: -3 Min 16 1.0 Max Speed -4 Min 20 1.0 Max Unit 25 1.0 ns ns 8K tbl 07B Page 9 CL81188A Laser-Configured ASIC AC Electrical Specifications cont. Logic Element Timing Parameters[5] Symbol Parameter Conditions Speed: -2 Min Max Speed: -3 Min Max Speed: -4 Min Max Unit tLUT Look up table delay for data-in 2.0 2.5 3.2 ns tCLUT Look up table delay for carry-in 0.0 0.0 0.0 ns tRLUT Look up table delay for LE register feedback 0.9 1.1 1.5 ns tGATE Cascade gate delay 0.0 0.0 0.0 ns tCASC Cascade chain routing delay 0.6 0.7 0.9 ns tCICO Carry-in to carry-out delay 0.4 0.5 0.6 ns tCGEN Data-in to carry-out delay 0.4 0.5 0.7 ns tCGENR LE register feedback to carry-out delay 0.9 1.1 1.5 ns tC LE register control signal delay 1.6 2.0 2.5 ns tCH Clock high time 1.7 1.7 2.7 ns tCL Clock low time 1.7 1.7 2.7 ns tCO LE register clock-to-output delay 0.4 0.5 0.6 ns Combinatorial delay 0.4 0.5 0.6 ns tCOMB tSU LE register setup time before clock 0.8 1.1 1.2 ns tH LE register hold time after clock 0.9 1.1 1.5 ns tPRE LE register preset delay 0.6 0.7 0.8 ns tCLR LE register clear delay 0.6 0.7 0.8 ns 8K tbl 08A Interconnect Timing Parameters[5] Symbol Parameter Conditions Speed: -2 Min Max Speed: -3 Min Max Speed: -4 Min Max Unit tLABCASC Cascade delay between LEs in different LABs 0.3 0.4 0.4 ns tLABCARRY Carry delay between LEs in different LABs 0.3 0.4 0.4 ns tLOCAL LAB local interconnect delay 0.5 0.5 0.7 ns tROW Row interconnect routing delay 5.0 5.0 5.0 ns tCOL Column interconnect routing delay 3.0 3.0 3.0 ns tDIN_C Dedicated input to LE control delay 5.0 5.0 5.5 ns tDIN_D Dedicated input to LE data delay 7.0 7.0 7.5 ns tDIN_IO Dedicated input to IOE control delay 5.0 5.0 5.5 ns 8K tbl 09B Page 10 CL81188A Laser-Configured ASIC AC Test Conditions (A) (B) 464 Ω VCCIO OUTPUT Includes jig capacitance All Input Pulses 464 Ω VCCIO 3.0V 90% 90% OUTPUT 250 Ω 35 pF Includes jig capacitance 5 pF 250 Ω GND 10% 10% ≤ 3ns ≤ 3ns 8K drw 01 Notes to Tables 1. During transitions, inputs may undershoot to -2.0V for periods shorter than 20ns. Otherwise, minimum DC input voltage is -0.3V. 2. The following devices do not have VCCIO pins: CL8282A, CL8452A. For these devices, all references to VCCIO should be changed to VCCINT 3. Typical values are at VCC of 5.0 volts and ambient temperature of 25 ºC. 4. Guaranteed but not tested. Characterized initially, and after any design changes which may affect these parameters. 5. Internal timing delays are based on characterization, and cannot be explicitly tested. Internal timing parameters should be used for performance estimation only. Revision History 16 Jan. 1998: Created new document 31 Jul. 1999: Recompiled databook, 8820 package update. 29 Nov. 1999: Remove reference to the 8282AV device which is not supported. 01 Dec. 2000: Review and reprint. Ordering Information Part Number CL81188AQC208-4 Temperature Range Commercial Package Type 208-pin Plastic QFP CL81188AQC208-3 EPF81188AQC208-3 -2 (fastest) EPF81188AQC208-2 CL81188AQC240-4 240-pin Plastic QFP CL81188AQC240-3 -4 (slowest) EPF81188AQC240-4 -3 CL81188AQC240-2 EPF81188AQC240-3 -2 (fastest) EPF81188AQC240-2 Industrial 208-pin Plastic QFP CL81188AQI208-3 CL81188AQI240-4 Altera Equivalent -4 (slowest) EPF81188AQC208-4 -3 CL81188AQC208-2 CL81188AQI208-4 Speed -4 (slowest) EPF81188AQI208-4 -3 (fastest) EPF81188AQI208-3 240-pin Plastic QFP -4 EPF81188ARI240-4 81188A tbl 02 Page 11 CL81188A Laser-Configured ASIC Page 12