DS36C200 Dual High Speed Bi-Directional Differential Transceiver General Description Features The DS36C200 is a dual transceiver device optimized for high data rate and low power applications. This device provides a single chip solution for a dual high speed bi-directional interface. Also, both control pins may be routed together for single bit control of datastreams. Both control pins are adjacent to each other for ease of routing them together. The DS36C200 is compatible with IEEE 1394 physical layer and may be used as an economical solution with some considerations. Please reference the application information on 1394 for more information. The device is in a 14-lead small outline package. The differential driver outputs provides low EMI with its low output swings typically 210 mV. The receiver offers ± 100 mV threshold sensitivity, in addition to common-mode noise protection. n n n n n n n n n Connection Diagram Functional Diagram Optimized for DSS to DVHS interface link Compatible IEEE 1394 signaling voltage levels Operates above 100 Mbps Bi-directional transceivers 14-lead SOIC package Ultra low power dissipation ± 100 mV receiver sensitivity Low differential output swing typical 210 mV High impedance during power off DS012621-1 Note: * denotes active LOW pin Order Number DS36C200M See NS Package Number M14A DS012621-2 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1998 National Semiconductor Corporation DS012621 www.national.com DS36C200 Dual High Speed Bi-Directional Differential Transceiver June 1998 Absolute Maximum Ratings (Note 1) (Soldering, 4 sec.) ESD Rating (Note 4) (HBM, 1.5 kΩ, 100 pF) (EIAJ, 0 Ω, 200 pF) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) −0.3V to +6V Enable Input Voltage −0.3V to (VCC + 0.3V) (DE, RE*) Voltage (DI/RO) −0.3V to +5.9V −0.3V to +5.9V Voltage (DO/RI ± ) Maximum Package Power Dissipation @+25˚C M Package 1255 mW Derate M Package 10.04 mW/˚C above +25˚C Storage Temperature Range −65˚C to +150˚C Lead Temperature Range +260˚C ≥ 3.5 kV ≥ 300V Recommended Operating Conditions Supply Voltage (VCC) Receiver Input Voltage Operating Free Air Temperature (TA) Min +4.5 0 Typ +5.0 Max +5.5 2.4 Units V V 0 25 70 ˚C Electrical Characteristics (Notes 2, 3, 7) Over supply voltage and operating temperature ranges, unless otherwise specified Symbol Parameter Conditions DIFFERENTIAL DRIVER CHARACTERISTICS (RE* = VCC) VOD Output Differential Voltage RL = 55Ω, (Figure 1) Pin Min Typ Max Units DO+, DO− 172 210 285 mV 0 4 35 mV ∆VOD VOD Magnitude Change VOH Output High Voltage 1.36 VOL Output Low Voltage 1.15 VOS Offset Voltage ∆VOS Offset Magnitude Change IOZD TRI-STATE ® Leakage IOXD Power-Off Leakage IOSD Output Short Circuit Current VOUT = VCC or GND VOUT = 5.5V or GND, VCC = 0V VOUT = 0V DIFFERENTIAL RECEIVER CHARACTERISTICS (DE = GND) VTH Input Threshold High VCM = 0V to 2.3V VTL Input Threshold Low IIN Input Current VOH Output High Voltage V 1.0 1.25 1.6 V 0 5 25 mV −10 ±1 ±1 +10 µA +10 µA −4 −9 mA −10 RI+, RI− V +100 −100 mV mV −10 ±1 3.8 4.9 Inputs Open 3.8 4.9 V 3.8 4.9 V −15 VIN = +2.4V or 0V IOH = −400 µA RO VOL Output Low Voltage Inputs Terminated, Rt = 55Ω Inputs Shorted, VID = 0V IOL = 2.0 mA, VID = −200 mV IOSR Output Short Circuit Current VOUT = 0V +10 µA V 4.9 V 0.1 0.4 V −60 −100 mA 2.0 VCC V GND 0.8 V ± 10 ± 10 µA 3 7 mA 11 17 mA 6 10 mA DEVICE CHARACTERISTICS VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current VIN = VCC or 2.4V VIN = GND or 0.4V VCL Input Clamp Voltage ICL = −18 mA ICCD Power Supply Current No Load, DE = RE* = VCC RL = 55Ω, DE = RE* = VCC ±1 ±1 −1.5 DE = RE* = 0V ICCR DI, DE RE* VCC −0.8 µA V Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD and VID. Note 3: All typicals are given for VCC = +5.0V and TA = +25˚C. Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF) ≥ 3.5 kV EIAJ (0Ω, 200 pF) ≥ 300V Note 5: CL includes probe and fixture capacitance. www.national.com 2 Electrical Characteristics (Notes 2, 3, 7) (Continued) Note 6: Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr ≤ 1 ns, tf ≤ 1 ns (0%–100%). Note 7: The DS36C200 is a current mode device and only function with datasheet specification when a resistive load is applied to the drivers outputs. Switching Characteristic Over supply voltage and operating temperature ranges, unless otherwise specified. (Notes 5, 6) Symbol Parameter Conditions Min Typ Max Units 1.0 2.5 5.5 ns 1.0 2.6 5.5 ns DIFFERENTIAL DRIVER CHARACTERISTICS RL = 55Ω, CL = 10 pF (Figure 2 and Figure 3) tPHLD Differential Propagation Delay High to Low tPLHD Differential Propagation Delay Low to High tSKD Differential Skew |tPHLD – tPLHD| 0 0.1 2 ns tTLH Transition Time Low to High 0 0.5 2 ns tTHL Transition Time High to Low 0 0.5 2 ns tPHZ Disable Time High to Z 0.3 5 20 ns tPLZ Disable Time Low to Z 0.3 5 20 ns tPZH Enable Time Z to High 0.3 10 30 ns tPZL Enable Time Z to Low 0.3 10 30 ns 1.5 5 9 ns 1.5 4.6 9 ns RL = 55Ω (Figure 4 and Figure 5) DIFFERENTIAL RECEIVER CHARACTERISTICS CL = 10 pF, VID = 200 mV (Figure 6 and Figure 7) tPHLD Differential Propagation Delay High to Low tPLHD Differential Propagation Delay Low to High tSKD Differential Skew |tPHLD – tPLHD| 0 0.4 3 ns tr Rise Time 0 1.5 5 ns tf Fall Time 0 1.5 5 ns tPHZ Disable Time High to Z 1 5 20 ns tPLZ Disable Time Low to Z 1 5 20 ns tPZH Enable Time Z to High 0.3 10 30 ns tPZL Enable Time Z to Low 0.3 10 30 ns CL = 10 pF (Figure 8 and Figure 9) Parameter Measurement Information DS012621-3 FIGURE 1. Differential Driver DC Test Circuit DS012621-4 FIGURE 2. Differential Driver Propagation Delay and Transition Time Test Circuit 3 www.national.com Parameter Measurement Information (Continued) DS012621-5 FIGURE 3. Differential Driver Propagation Delay and Transition Time Waveforms DS012621-6 FIGURE 4. Driver TRI-STATE Delay Test Circuit DS012621-7 FIGURE 5. Driver TRI-STATE Delay Waveforms DS012621-8 FIGURE 6. Receiver Propagation Delay and Transition Time Test Circuit www.national.com 4 Parameter Measurement Information (Continued) DS012621-9 FIGURE 7. Receiver Propagation Delay and Transition Time Waveforms DS012621-10 FIGURE 8. Receiver TRI-STATE Delay Test Circuit DS012621-11 FIGURE 9. Receiver TRI-STATE Delay Waveforms Application Information TRUTH TABLES The DS36C200 has two enable pins DE and RE*, however, the driver and receiver should never be enabled simultaneously. Enabling both could cause multiple channel contention between the receiver output and the driving logic. It is recommended to route the enables together on the PC board. This will allow a single bit [DE/RE*] to control the chip. This DE/RE* bit toggles the DS36C200 between Receive mode and Transmit mode. When the bit is asserted HIGH the device is in Transmit mode. When the bit is asserted LOW the device is in Receive mode. The mode determines the function of the I/O pins: DI/RO, DO/RI+, and DO/RI−.Please note that some of the pins have been identified by its function in the corresponding mode in the three tables below. For example, in Transmit mode the DO/RI+ pin is identified as DO+. This was done for clarity in the tables only and should not be confused with the pin identification throughout the rest of this document. Also note that a logic low on the DE/RE* bit corresponds to a logic low on both the DE pin and the RE* pin. Similarly, a logic high on the DE/RE* bit corresponds to a logic high on both the DE pin and the RE* pin. 5 www.national.com Application Information Transmit Mode (Continued) Receive Mode Input(s) Input(s) Input/Output DE RE* [RI+] − [RI−] RO L L H L L L L > +100 mV < −100 mV 100 mV > & > −100 mV L H X Z L X Input/Output DE RE* DI DO+ DO− H H L L H H H H H L H H 2 > & > 0.8 X X L H X Z Z H = Logic high level L = Logic low level X = Indeterminant state Z = High impedance state TABLE 1. Device Pin Descriptions Pin# Name Mode Description (In mode only) 3 DE 1, 7 DI 10, 13 DO+ 11, 12 DO− 4 RE* Transmit Driver Enable: When asserted low driver is disabled. And when asserted high driver is enabled. TTL/CMOS driver input pins Non-inverting driver output pin Inverting driver output pin Receive Receiver Enable: When asserted low receiver is enabled. And when asserted high receiver is disabled. 1, 7 RO Receiver output pin 10, 13 RI+ Positive receiver input pin 11, 12 RI− 5 GND Transmit and 2 VCC Receive 6, 8, 9, 14 NC Negative receiver input pin Ground pin Positive power supply pin, +5V ± 10% No Connect sible as long as transmission line effects are taken into account. Discontinuities are caused by mid-bus stubs, connectors, and devices that affect signal integrity. The differential line driver is a balanced current source design. A current mode driver, generally speaking has a high output impedance and supplies a constant current for a range of loads (a voltage mode driver on the other hand supplies a constant voltage for a range of loads). Current is switched through the load in one direction to produce a logic state and in the other direction to produce the other logic state. The typical output current is mere 3.8 mA, a minimum of 3.1 mA, and a maximum of 5.2 mA. The current mode requires that a resistive termination be employed to terminate the signal and to complete the loop as shown in Figure 11. The 3.8 mA loop current will develop a differential voltage of 210 mV across the 55Ω termination resistor which the receiver detects with a 110 mV minimum differential noise margin neglecting resistive line losses (driven signal minus receiver threshold (210 mV – 100 mV = 110 mV)). The signal is centered around +1.2V (Driver Offset, VOS) with respect to ground as shown in Figure 7. The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its quiescent current remains relatively flat versus switching frequency. Whereas the RS-422 voltage mode driver increases exponentially in most case between 20 MHz–50 MHz. This is due to the overlap current that flows between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed current between its output without any substantial overlap current. This is similar to IEEE 1394 The DS36C200 drives and receives IEEE 1394 physical layer signal levels. The current mode driver is capable of driving a 55Ω load with VOD between 172 mV and 285 mV. The DS36C200 is not designed to work with a link layer controller IC requiring full 1394 physical layer compliancy to the standard. No clock generator, no arbitration, and no encode/ decode logic is provided with this device. For a 1394 link where speed sensing, bus arbitration, and other functions are not required, a controller and the DS36C200 will provide a cost effective, high speed dedicated link. This is shown in Figure 10. In applications that require fully compliant 1394 protocol, a link layer controller and physical layer controller will be required as shown in Figure 10. The physical layer controller supports up to three DC36C200 devices (not shown). The DS36C200 drivers are current mode drivers and intended to work with a two 110Ω termination resistors in parallel with each other. The termination resistors should match the characteristic impedance of the transmission media. The drivers are current mode devices therefore the resistors are required. Both resistors are required for half duplex operation and should be placed as close to the DO/RI+ and DO/ RI− pins as possible at opposite ends of the bus. However, if your application only requires simplex operation, only one termination resistor is required. In addition, note the voltage levels will vary from those in the datasheet due to different loading. Also, AC or unterminated configurations are not used with this device. Multiple node configurations are pos- www.national.com 6 Application Information down resistors to set the output to a HIGH state. This internal circuitry will guarantee a HIGH, stable output state for open inputs. (Continued) some ECL and PECL devices, but without the heavy static ICC requirements of the ECL/PECL designs. LVDS requires > 80% less current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other existing RS-422 drivers. 2. Terminated Input. If the driver is disconnected (cable unplugged), or if the driver is in a TRI-STATE or power-off condition, the receiver output will again be in a HIGH state, even with the end of the cable 100Ω termination resistor across the input pins. The unplugged cable can become a floating antenna which can pick up noise. If the cable picks up more than 10mV of differential noise, the receiver may see the noise as a valid signal and switch. To insure that any noise is seen as common-mode and not differential, a balanced interconnect should be used. Twisted pair cable will offer better balance than flat ribbon cable. 3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0V differential input voltage, the receiver output will remain in a HIGH state. Shorted input fail-safe is not supported across the common-mode range of the device (GND to 2.4V). It is only supported with inputs shorted and no external common-mode voltage applied. Fail-safe Feature: The LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20mV) to CMOS logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from appearing as a valid signal. The receiver’s internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safe protection (a stable known state of HIGH output voltage) for floating, terminated or shorted receiver inputs. 1. Open Input Pins. The DS36C200 is a dual transceiver device, and if an application requires only one receiver, the unused channel inputs should be left OPEN. Do not tie the receiver inputs to ground or any other voltages. The input is biased by internal high value pull up or pull DS012621-14 FIGURE 10. (A) Dedicated IEEE 1394 Link (B) Full IEEE 1394 Compliant Link 7 www.national.com Application Information (Continued) DS012621-12 FIGURE 11. Typical in Home Application DS012621-13 FIGURE 12. Typical Interface Connection (Note 7) www.national.com 8 9 DS36C200 Dual High Speed Bi-Directional Differential Transceiver Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead (0.150" Wide) Molded Small Outline Package, JEDEC Order Number DS36C200M NS Package Number M14A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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