ETC CS5231-3/D

CS5231-3
500 mA, 3.3 V Linear
Regulator with Auxiliary
Control
Features
• Linear Regulator
– 3.3 V ± 2.0% Output Voltage
– 3.0 mA Quiescent Current @ 500 mA
– Fast Transient Response
– Current Limit Protection
– Thermal Shutdown with Hysteresis
– 450 µA Reverse Output Current
• System Power Management
– Auxiliary Supply Control
– “Glitch Free” Transition Between Two Supplies
• Internally Fused Leads in SO–8 Package
 Semiconductor Components Industries, LLC, 2001
March, 2001 – Rev. 4
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D2PAK
5–PIN
DP SUFFIX
CASE 936F
1
5
SO–8
DF SUFFIX
CASE 751
8
1
PIN CONNECTIONS AND
MARKING DIAGRAMS
D2PAK 5–PIN
Pin 1. No Connect
2. VIN
3. GND
4. VOUT
5. AuxDrv
Tab = GND
CS5231–3
AWLYWW
1
NC
1
GND
GND
VIN
A
WL, L
YY, Y
WW, W
SO–8
5231–
ALYW3
The CS5231–3 combines a three–terminal linear regulator with
circuitry controlling an external PFET transistor thus managing two
input supplies. The part provides a 3.3 V regulated output either from
the main 5.0 V supply or a 3.3 V auxiliary that switches on when the
5.0 V supply is not present. This delivers constant, uninterrupted
power to the load. The CS5231–3 meets Intel’s “Instantly Available”
power requirements which follows from the “Advanced Configuration
and Power Interface” (ACPI) standards developed by Intel, Microsoft
and Toshiba.
The CS5231–3 linear regulator provides a fixed 3.3 V output at
500 mA with an overall accuracy of ± 2.0%. The internal NPN–PNP
composite pass transistor provides a low dropout voltage and requires
less supply current than a straight PNP design. Full protection with
both current limit and thermal shutdown is provided.
Designed for low reverse current, the IC prevents excessive current
from flowing from VOUT to either VIN or ground when the regulator
input voltage is lower than the output voltage.
The CS5231–3 can be used to provide power to an ASIC on a PCI
Network Interface Card (NIC). When the system enters a Sleep State
and the 5.0 V input drops below 4.4 V, the AuxDrv control signal on the
CS5231–3 is activated turning on the external PFET. This switches the
supply source from the 5.0 V input to the 3.3 V input through the PFET,
guaranteeing a constant 3.3 V output to the ASIC that is “glitch free.”
The CS5231–3 is available in two package types: the 5–Lead D2 PAK
(TO263) package and the 8–Lead SOIC 4–Lead–fused (DF) package.
Other applications include desktop computers, power supplies with
multiple input sources and PCMCIA/PCI interface cards.
8
AuxDrv
GND
GND
VOUT
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
1
Package
Shipping
CS5231–3GDP5
D2PAK*
50 Units/Rail
CS5231–3GDPR5
D2PAK*
750 Tape & Reel
CS5231–3GDF8
SO–8
95 Units/Rail
CS5231–3GDFR8
* 5–PIN
SO–8
2500 Tape & Reel
Publication Order Number:
CS5231–3/D
CS5231–3
VOUT
VIN
10 kΩ
Internal
Bias
50 kΩ
Current
Limit
AuxDrv
−
Error
Amp
+
Shutdown
−
+
VIN UV
Comparator
VREF
Bandgap
Reference
GND
Thermal
Shutdown
Figure 1. Block Diagram
ABSOLUTE MAXIMUM RATINGS*
Rating
Maximum Operating Junction Temperature
Storage Temperature Range
Lead Temperature Soldering:
Reflow: (SMD styles only) (Note 1.)
ESD Damage Threshold (Human Body Model)
Value
Unit
150
°C
–65 to +150
°C
230 peak
°C
2.0
kV
1. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
ABSOLUTE MAXIMUM RATINGS
Pin Name
Pin Symbol
VMAX
VMIN
ISOURCE
ISINK
IC Power Input
VIN
14 V
–0.3 V
100 mA
Internally Limited
Output Voltage
VOUT
6.0 V
–0.3 V
Internally Limited
100 mA
Auxiliary Drive Output
AuxDrv
14 V
–0.3 V
10 mA
50 mA
IC Ground
GND
N/A
N/A
N/A
N/A
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CS5231–3
ELECTRICAL CHARACTERISTICS (0°C < TA < 70°C; 0°C < TJ < 125°C; 4.75 V ≤ VCC < 6.0 V; COUT ≥ 10 µF with
ESR < 1.0 Ω, IOUT = 10 mA; unless otherwise specified.)
Test Conditions
Characteristic
Min
Typ
Max
Unit
3.234
(– 2%)
3.3
3.366
(+ 2%)
V
Linear Regulator
Output Voltage
10 mA < IOUT < 500 mA.
Line Regulation
IOUT = 10mA; VIN = 4.75 V to 6.0 V
–
1.0
5.0
mV
Load Regulation
VIN = 5.0 V; IOUT = 10 mA to 500 mA
–
5.0
15
mV
Ground Current
IOUT = 10 mA
IOUT = 500 mA
–
–
2.0
3.0
3.0
6.0
mA
mA
Reverse Current
VIN = 0 V, VOUT = 3.3 V
–
0.45
1.0
mA
Current Limit
0 V < VOUT < 3.2 V
0.55
0.85
1.2
A
Thermal Shutdown
Note 2.
150
180
210
°C
Thermal Shutdown Hysteresis
Note 2.
–
25
–
°C
Auxiliary Drive
Upper VIN Threshold
Increase VIN until regulator turns on and
AuxDrv drives high
4.35
4.5
4.65
V
Lower VIN Threshold
Decrease VIN until regulator turns off and
AuxDrv drives low
4.25
4.4
4.55
V
75
100
125
mV
VIN Threshold Hysteresis
–
Output Low Voltage
IAuxDrv = 100 µA, 1.0 V < VIN < 4.5 V
–
0.1
0.4
V
Output Low Peak Voltage
Increase VIN from 0V to 1.0 V.
Record peak AuxDrv output voltage
–
0.65
0.9
V
AuxDrv Current Limit
VAuxDrv = 1.0 V; VIN = 4.0 V
0.5
6.0
25
mA
Response Time
Step VIN from 5.0 V to 4.0 V, measure time for
VAuxDrv to drive low. Note
–
1.0
10
µs
Pull–Up/Down Resistance
VIN = 0 V and VIN > 4.7 V.
5.0
10
25
kΩ
2. Guaranteed by design, not 100% production tested. Thermal shutdown is 100% functionally tested at wafer probe.
PACKAGE PIN DESCRIPTION
Package Lead #
D2PAK
5–Pin
SO–8
Lead Symbol
1
1
NC
No connection.
2
4
VIN
Input voltage.
3, Tab
2, 3, 6, 7
GND
Ground and IC substrate connection.
4
5
VOUT
Regulated output voltage.
5
8
AuxDrv
Function
Output used to control an auxiliary supply voltage. This lead is driven
low if VIN is less than 4.5 V, and is otherwise pulled up to VIN through
an internal 10 kΩ resistor.
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CS5231–3
TYPICAL PERFORMANCE CHARACTERISTICS
IOUT = 10 mA
3.302
1.2
125°C
Load Regulation (mV)
Output Voltage (V)
1.0
3.300
IOUT = 500 mA
3.298
0.8
0.6
0.4
27°C
0.2
3.296
0°C
0
0
20
40
60
80
100
Junction Temperature (°C)
120
0.2
IOUT (A)
0
Figure 2. Output Voltage vs. Junction Temperature
0.4
Figure 3. Line Regulation vs. IOUT Over
Temperature
1.2
1.0
Reverse Current (µA)
Load Regulation (mV)
125°C
0.8
0.6
0.4
27°C
390
380
370
0.2
360
0°C
0.0
0.0
0
0.4
0.2
IOUT (A)
20
Figure 4. Load Regulation vs. IOUT Over
Temperature
40
60
80
Junction Temperature (°C)
100
120
Figure 5. Reverse Current vs. Junction
Temperature
4.52
125°C
4.50
VIN Threshold Voltage (V)
3
VOUT (V)
27°C
2
0°C
1
VIN
Turn–On
Threshold
4.48
4.46
4.44
4.42
VIN
Turn–Off
Threshold
4.40
0
0.0
0.2
0.4
IOUT (A)
0.6
0.8
4.38
1.0
Figure 6. VOUT vs. IOUT Over Junction
Temperature
0
20
40
60
80
100
Junction Temperature (°C)
120
Figure 7. VIN Thresholds vs. Junction
Temperature
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140
CS5231–3
1000
2.4
TJ = 0°C
IGND @ 0°C
2.2
Capacitance (µF)
Ground Current (mA)
2.6
TJ = 27°C
IGND @ 27°C
2.0
1.8
Stable Region
TJ = 25°C
100
TJ = 125°C
IGND @ 125°C
1.6
0.2
Load Current (A)
0.0
10
0.4
0
Figure 8. Ground Current vs. Load Current
2.0
3.0
4.0
5.0
Capacitance ESR (Ω)
6.0
Figure 9. Region of Stable Operation
3.4
VOUT
5.0
4.8
4.6
3.3
CIN = 33 µF
COUT = 33 µF
VIN = 5.00 V
3.2
4.4
IOUT (mA)
Current Limit (mA)
1.0
4.2
4.0
0
20
40
60
80
100
Temperature (°C)
120
500
10
Time, 5.0 µs per division
140
Figure 10. AuxDrv Current Limit vs. Junction
Temperature
5.0 V PCI
VOUT
VIN
C1
33 µF
Figure 11. Transient Response
CS5231–3
GND
AuxDrv
ASIC
M1
3.3 V VAUX
VDD
C3
33 µF
C1
33 µF
* indicates PFET body diode
Figure 12. Application Circuit
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7.0
CS5231–3
APPLICATION INFORMATION
THEORY OF OPERATION
The CS5231–3 is a fixed 3.3 V linear regulator that
contains an auxiliary drive control feature. When VIN is
greater than the typical 4.5 V threshold, the IC functions as
a linear regulator. It provides up to 500 mA of current to a
load through a composite PNP–NPN pass transistor. An
output capacitor greater than 10 µF with equivalent series
resistance less than 1.0 Ω is required for compensation.
More information is provided in the Stability Considerations
section.
The CS5231–3 provides an auxiliary drive feature that
allows a load to remain powered even if the VIN supply for
the IC is absent. An external p–channel FET is the only
additional component required to implement this function if
an auxiliary power supply is available. The PFET gate is
connected to the AuxDrv lead. The PFET drain is connected
to the auxiliary power supply, and the PFET source is
connected to the load. The polarity of this connection is very
important, since the PFET body diode will be connected
between the load and the auxiliary supply. If the PFET is
connected with its drain to the load and its source to the
supply, the body diode will be forward–biased if the
auxiliary supply is turned off. This will result in the linear
regulator providing current to everything on the auxiliary
supply rail.
The AuxDrv lead is internally connected to a 10 kΩ
resistor and to a saturating NPN transistor that acts as a
switch. If the VIN supply is off, the AuxDrv output will
connect the PFET gate to ground through the 10 kΩ resistor,
and the PFET will conduct current to the load.
As the VIN supply begins to rise, the AuxDrv lead will also
rise until it reaches a typical voltage of about 650 mV. The
NPN transistor connected to the AuxDrv lead will saturate
at this point, and the gate of the PFET will be pulled down
to a typical voltage of about 100 mV. The PFET will
continue to conduct current to the load.
The VIN supply voltage will continue to rise, but the linear
regulator output is disabled until VIN reaches a typical
threshold of 4.5 V. During this time, the load continues to be
powered by the auxiliary driver. Once the 4.5 V VIN
threshold is reached, the saturating NPN connected to the
AuxDrv lead turns off. The on–chip 10 kΩ pull–up resistor
will pull the PFET gate up to VIN, thus turning the PFET off.
The linear regulator turns on at the same time. An external
compensation capacitor is required for the linear regulator
to be stable, and this capacitance also serves as a charge
reservoir to minimize any “glitching” that might result
during the supply changeover. Hysteresis is present in the
AuxDrv circuitry, requiring VIN to drop by 100 mV (typical)
after the linear regulator is providing power to the load
before the AuxDrv circuitry can be re–enabled.
VIN
VOUT
VAUXDRV
IOUT = STARTUP 375 mA
Figure 13. Initial Power–Up, VAUX Not
Present ROUT = 8.8 VIN
VOUT
VAUXDRV
IOUT = 375 mA VAUX = 3.30 V
Figure 14. Power–Up, VAUX = 3.3 V. Note the
“Oscillatory Performance” as the Linear Regulator
Changes the VOUT Node. IOUT RDS(ON) 130 mV
VIN
VOUT
VAUXDRV
IOUT = 375 mA VAUX = 3.30
Figure 15. Power–Down, VAUX = 3.3 V. Again,
Note V = I RDS(ON) 130 mV
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CS5231–3
VIN
VIN
VOUT
VOUT
VAUXDRV
VAUXDRV
IOUT = 375 mA VAUX = 3.465
IOUT = 375 mA VAUX = 3.135 V
Figure 19. Power–Down, VAUX = 3.465 V
Figure 16. Power–Up, VAUX = 3.135 V. The
“Oscillatory Performance” Mode Lasts Longer
Because the Difference Between VAUX and 3.3 is
Greater
STABILITY CONSIDERATIONS
The output capacitor helps determine three main
characteristics of a linear regulator: startup, transient
response and stability.
Startup is affected because the output capacitor must be
charged. At initial startup, the VIN supply may not be
present, and the output capacitor will be charged through the
PFET. The PFET will initially provide current to the load
through its body diode. The diode will act as a voltage
follower until sufficient voltage is present to turn the FET
on. Since most commercial power supplies have a fairly low
ramp rate, charging through the body diode should
effectively limit in–rush current to the capacitor.
During normal operation, transient load current
requirements will be satisfied from the charge stored in the
output capacitor until either the linear regulator or the
auxiliary supply can respond. Larger values of capacitance
will improve transient response, but will also cost more. A
linear regulator will respond within microseconds, where an
external power supply may take milliseconds to react. The
output capacitance will provide the difference in current
until this occurs. The result will be an instantaneous voltage
change at the output. This change is the product of the
current change and the capacitor ESR:
VIN
VOUT
VAUXDRV
IOUT = 375 mA VAUX = 3.135
Figure 17. Power–Down, VAUX = 3.135 V. The
Difference in Voltage is Now IOUT RDS(ON) Plus
the Difference in Supply Voltages (3.3 – VAUX)
VOUT ILOAD ESR
VIN
This limitation directly affects load regulation. Capacitor
ESR must be minimized if output voltage must be
maintained within tight tolerances. In such a case, it is often
advisable to use a parallel network of different types of
capacitors. For example, electrolytic capacitors provide
high charge storage capacity in a small size, while tantalum
capacitors have low ESR. The parallel combination will
result in a high capacity, low ESR network. It is also
important to physically locate the capacitance network close
to the load, and to connect the network to the load with wide
PC board traces to minimize the metal resistance.
VOUT
VAUXDRV
IOUT = 375 mA VAUX = 3.465
Figure 18. Power–Up, VAUX = 3.465 V. IOUT RDS(ON)
is Compensated By Higher Value of VAUX
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CS5231–3
turn–on threshold. Choosing a switch transistor with
VGS(ON) ≈ 1.0 V will ensure the PFET will be fully enhanced
with only 3.3 V of gate drive voltage. Second, the switch
transistor should be chosen to have a low RDS(ON) to
minimize the voltage drop due to current flow in the switch.
The formula for calculating the maximum allowable
on–resistance is
The CS5231–3 has been carefully designed to be stable
for output capacitances greater than 10 µF with equivalent
series resistance less than 1.0 Ω. While careful board layout
is important, the user should have a stable system if these
constraints are met. A graph showing the region of stability
for the CS5231–3 is included in the “Typical Performance
Characteristics” section of this datasheet.
V
VOUT(MIN)
RDS(ON)MAX AUX(MIN)
1.5 IOUT(MAX)
INPUT CAPACITORS AND THE VIN THRESHOLDS
A capacitor placed on the VIN pin will help to improve
transient response. During a load transient, the input
capacitor serves as a charge “reservoir,” providing the
needed extra current until the external power supply can
respond. One of the consequences of providing this current
is an instantaneous voltage drop at VIN due to capacitor
ESR. The magnitude of the voltage change is again the
product of the current change and the capacitor ESR.
It is very important to consider the maximum current step
that can exist in the system. If the change in current is large
enough, it is possible that the instantaneous voltage drop on
VIN will exceed the VIN threshold hysteresis, and the IC will
enter a mode of operation resembling an oscillation. As the
part turns on, the output current IOUT will increase, reaching
current limit during initial charging. Increasing IOUT results
in a drop at VIN such that the shutdown threshold is reached.
The part will turn off, and the load current will decrease. As
IOUT decreases, VIN will rise and the part will turn on,
starting the cycle all over again. This oscillatory operation
is most likely at initial start–up when the output capacitance
is not charged, and in cases where the ramp–up of the VIN
supply is slow. It may also occur during the power transition
when the regulator turns on and the PFET turns off. A 15 µs
delay exists between turn–on of the regulator and the
AuxDrv pin pulling the gate of the PFET high. This delay
prevents “chatter” during the power transitions. During this
interval, the linear regulator will attempt to regulate the
output voltage as 3.3 V. If the output voltage is significantly
below 3.3 V, the IC will go into current limit while trying to
raise VOUT. It is a short–lived phenomenon and is mentioned
here to alert the user that the condition can exist. It is
typically not a problem in applications. Careful choice of the
PFET switch with respect to RDS(ON) will minimize the
voltage drop which the output must charge through to return
to a regulated state. More information is provided in the
section on choosing the PFET switch.
If required, using a few capacitors in parallel to increase
the bulk charge storage and reduce the ESR should give
better performance than using a single input capacitor.
Short, straight connections between the power supply and
VIN lead along with careful layout of the PC board ground
plane will reduce parasitic inductance effects. Wide VIN and
VOUT traces will reduce resistive voltage drops.
where VAUX(MIN) is the minimum value of the auxiliary
supply voltage, VOUT(MIN) is the minimum allowable
output voltage, IOUT(MAX) is the maximum output current
and 1.5 is a “fudge factor” to account for increases in
RDS(ON) due to temperature.
OUTPUT VOLTAGE SENSING
It is not possible to remotely sense the output voltage of
the CS5231–3 since the feedback path to the error amplifier
is not externally available. It is important to minimize
voltage drops due to metal resistance of high current PC
board traces. Such voltage drops can occur in both the
supply traces and the return traces.
The following board layout practices will help to
minimize output voltage errors:
• Always place the linear regulator as close to both load
and output capacitors as possible.
• Always use the widest possible traces to connect the
linear regulator to the capacitor network and to the
load.
• Connect the load to ground through the widest possible
traces.
• Connect the IC ground to the load ground trace at the
point where it connects to the load.
CURRENT LIMIT
The CS5231–3 has internal current limit protection.
Output current is limited to a typical value of 850 mA, even
under output short circuit conditions. If the load current
drain exceeds the current limit value, the output voltage will
be pulled down and will result in an out of regulation
condition. The IC does not contain circuitry to report this
fault.
THERMAL SHUTDOWN
The CS5231–3 has internal temperature monitoring
circuitry. The output is disabled if junction temperature of
the IC reaches 180°C. Thermal hysteresis is typically 25°C
and allows the IC to recover from a thermal fault without the
need for an external reset signal. The monitoring circuitry is
located near the composite PNP–NPN output transistor,
since this transistor is responsible for most of the on–chip
power dissipation. The combination of current limit and
thermal shutdown will protect the IC from nearly any fault
condition.
CHOOSING THE PFET SWITCH
The choice of the external PFET switch is based on two
main considerations. First, the PFET should have a very low
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CS5231–3
The value of θJC both packages of the CS5231–3 are
provided in the Packaging Information section of this data
sheet. The value of θCS can be considered zero, since heat is
conducted out of the D2PAK package by the IC leads and the
tab, and out of the SOIC package by its IC leads that are
soldered directly to the PC board.
Modification of θSA is the primary means of thermal
management. For surface mount components, this means
modifying the amount of trace metal that connects to the IC.
The thermal capacity of PC board traces is dependent on
how much copper area is used, whether or not the IC is in
direct contact with the metal, whether or not the metal
surface is coated with some type of sealant, and whether or
not there is airflow across the PC board. The chart provided
below shows heatsinking capability of a square, single sided
copper PC board trace. The area is given in square
millimeters, and it is assumed there is no airflow across the
PC board.
REVERSE CURRENT PROTECTION
During normal system operation, the auxiliary drive
circuitry will maintain voltage on the VOUT pin when VIN
is absent. IC reliability and system efficiency are improved
by limiting the amount of reverse current that flows from
VOUT to ground and from VOUT to VIN. Current flows from
VOUT to ground through the feedback resistor divider that
sets up the output voltage This resistor can range in value
from 6.0 kΩ to about 10 kΩ, and roughly 500 µA will flow
in the typical case. Current flow from VOUT to VIN will be
limited to leakage current after the IC shuts down. On–chip
RC time constants are such that the output transistor should
be turned off well before VIN drops below the VOUT voltage.
CALCULATING POWER DISSIPATION AND
HEATSINK REQUIREMENTS
Most linear regulators operate under conditions that result
in high on–chip power dissipation. This results in high
junction temperatures. Since the IC has a thermal shutdown
feature, ensuring the regulator will operate correctly under
normal conditions is an important design consideration.
Some heatsinking will usually be required.
Thermal characteristics of an IC depend on four
parameters: ambient temperature (TA in °C), power
dissipation (PD in watts), thermal resistance from the die to
the ambient air (θJA in °C per watt) and junction temperature
(TJ in °C). The maximum junction temperature is calculated
from the formula below:
70
Thermal Resistance, °CW
60
TJ(MAX) TA(MAX) (JA PD(MAX))
Maximum ambient temperature and power dissipation are
determined by the design, while θJA is dependent on the
package manufacturer. The maximum junction temperature
for operation of the CS5231–3 within specification is
150°C. The maximum power dissipation of a linear
regulator is given as
50
40
30
20
10
0
0
2000
4000
PC Board Trace Area (mm2)
6000
Figure 20. Thermal Resistance Capability of
Copper PC Board Metal Traces
PD(MAX) (VIN(MAX) VOUT(MIN))
(ILOAD(MAX) VIN(MAX))
IGND(MAX)
TYPICAL D2PAK PC BOARD HEATSINK DESIGN
A typical design of the PC board surface area needed for
the D2PAK package is shown on page 11. Calculations were
made assuming VIN(MAX) = 5.25 V, VOUT(MIN) = 3.266 V,
IOUT(MAX) = 500 mA, IGND(MAX) = 5.0 mA and TA = 70°C.
where IGND(MAX) is the IC bias current.
It is possible to change the effective value of θJA by adding
a heatsink to the design. A heatsink serves in some manner
to raise the effective area of the package, thus improving the
flow of heat from the package into the surrounding air. Each
material in the path of heat flow has its own characteristic
thermal resistance, all measured in °C per watt. The thermal
resistances are summed to determine the total thermal
resistance between the die junction and air. There are three
components of interest: junction–to–case thermal resistance
(θJC), case–to–heatsink thermal resistance (θCS) and
heatsink–to–air thermal resistance (θSA). The resulting
equation for junction–to–air thermal resistance is
PD (5.25 V 3.266 V) 0.5 A
(5.25 V)(0.005 A) 1018 mW
Maximum temperature rise
T TJ(MAX) TA 150°C 70°C 80°C
JA(worst case) TPD 80°C1.018 W 78.56°CW
JA JC CS SA
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CS5231–3
First, we determine the need for heatsinking. If we assume
the maximum θJA = 50 °C/W for the D2PAK, the maximum
temperature rise is found to be
Operating at higher power dissipation without CS5231–3
heatsink may result in a thermal shutdown condition.
600
T PD JA 1.018 W 50°CW 50.9°C
500
This is less than the maximum specified operating
junction temperature of 125°C, and no heatsinking is
required. Since the D2PAK has a large tab, mounting this
part to the PC board by soldering both tab and leads will
provide superior performance with no PC board area
penalty.
IOUT (mA)
400
300
200
TYPICAL 8 LEAD FUSED LEAD SOIC DESIGN
We first determine the need for a heat sink for the 8 Lead
SOIC package at a load of 500 mA. Using the dissipation
from the D2PAK example of 1018 mW and the θJA of the
SOIC package of 110°C/W gives a temperature rise of
112°C. Adding this to an ambient temperature of 70°C gives
182°C junction temperature. This is an excessive
temperature rise but it can be reduced by adding additional
cooling in the form of added surface area of copper on the
PCB. Using the relationship of maximum temperature rise
of
100
0
5
6
7
8
9
10
VIN (Volts)
11
12
13
14
Figure 21. Demo Board Output Current
Derating vs. VIN
The VIN Connection
The VIN connection is denoted as such on the PC board.
The maximum input voltage to the IC is 14 V before damage
to the IC is possible. However, the specification range for the
IC is 4.75 V < VIN < 6.0 V.
TJA TJ(MAX) TA 150°C 70°C 80°C
We calculate the thermal resistance allowed from junction
to air:
The GND Connection
The GND connection ties the IC power return to two turret
pins. The extra turret pin provides for connection of multiple
instrument grounds to the demonstration board.
JA(worst case) TJAPD 80°C1.018 W 79.6°CW
The thermal resistance from the die to the leads (case) is
25°C/W. Subtracting these two numbers gives the allowable
thermal resistance from case to ambient:
The AuxDrv Connection
The AuxDrv lead of the CS5231–3 is connected to the gate
of the external PFET. This connection is also brought to a
turret pin to allow easy connection of an oscilloscope probe
for viewing the AuxDrv waveforms.
CA JA JC 79.6°CW 25°CW 54.6°CW
The thermal resistance of this copper area will be
54.6°C/W. We now look at Figure 20 and find the PCB trace
area that will be less than 54.5°C/W. Examination shows that
750 mm2 of copper will provide cooling for this part. This
would be the SOIC part with the center 4 ground leads
soldered to pads in the center of a copper area about 27 mm
× 27 mm. A lower dissipation or the addition of air–flow
could result in a smaller required surface area.
The VAUX Connection
The VAUX turret pin provides a connection point between
an external 3.3 V supply and the PFET drain.
The VOUT Connection
The VOUT connection is tied to the VOUT lead of the
CS5231–3 and the PFET source. This point provides a
convenient point at which some type of lead may be applied.
DESCRIPTION
The CS5231–3 application circuit has been implemented
as shown in the following pages. The schematic, bill of
materials and printed circuit board artwork can be used to
build the circuit. The design is very simple and consists of
two capacitors, a p–channel FET and the CS5231–3. Five
turret pins are provided for connection of supplies, meters,
oscilloscope probes and loads. The CS5231–3 power supply
management solution is implemented in an area less than 1.5
square inches. Due to the simplicity of the design, output
current must be derated if the CS5231–3 is operated at VIN
voltages greater than 7.0 V. Figure 21 provides the derating
curve on a maximum power dissipation if heatsink is added.
VIN
VIN TP1
+3.3 V
U1
TP5
CS5231–3
C1
GND
TP2
TP3
VOUT
GND
AuxDrv
TP6
AuxDrv
Q1
TP4
VAUX
C2
Figure 22. Application Circuit Schematic
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10
CS5231–3
PC Board Layout Artwork
Temperature Performance
The PC Board is a single layer copper design. The layout
artwork is reproduced at actual size below.
The graph below shows thermal performance for the
CS5231–3 across the normal operating output current range.
55
2”
Package Temperature (C)
50
1.8”
45
40
35
30
25
Figure 23. Top Copper Layer
20
0
2”
VIN 5.0 V
50
100 150 200 250 300 350 400 450 500
Load Current (mA)
Figure 25. Package Temperature vs. Load
Current (VIN = 5.0 V, TA = 23C)
AUX.DRV
PFET RDS(ON) Performance
1.8”
The graph provided below show typical RDS(ON)
performance for the PFET. The data is provided as VDS vs
IOUT for different values of VAUX.
AUX 3.3 V
VOUT 3.3 V
GND
GND
160
VAUX = 3.135 V
140
Figure 24. Top Silk Screen Layer
VAUX = 3.300 V
120
Test Description
100
VDS (mV)
The startup and supply transition waveforms shown in
Figures 13 through 19 were obtained using the application
circuit board with a resistive load of 8.8 Ω. This provides a
DC load of 375 mA when the regulated output voltage is 3.3
V. A standard 2.0 A bench supply was used to provide power
to the application circuit. The transient response waveforms
shown in the Typical Performance Characteristics section
were obtained by switching a 6.3 Ω resistor across the
output.
VAUX = 3.465 V
80
60
40
20
0
0
100
200
300
400
500
IOUT (mA)
Figure 26. PFET VDS vs. IOUT
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
APPLICATIONS CIRCUIT BILL OF MATERIALS
Refdes
C1, C2
Q1
U1
T1–T6
Description
Part Number
Manufacturer
33 µF, 16 V tantalum capacitors
TAJD336K016
AVX Corp
p–channel FET transistor
MGSF1P02ELT1
ON Semiconductor
Linear regulator with auxiliary
CS5231–3DPS
ON Semiconductor
Turret pins
40F6023
Newark Electronics
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ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
Contact Information
www.avxcorp.com
1–843–448–9411
http://onsemi.com
http://onsemi.com
www.newark.com
1–800–463–9275
CS5231–3
PACKAGE DIMENSIONS
D2PAK
5–PIN
DP SUFFIX
CASE 936F–01
ISSUE O
–T– SEATING
PLANE
B
NOTES:
1. DIMENSIONS AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS
B AND M.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH OR GATE PROTRUSIONS. MOLD FLASH
AND GATE PROTRUSIONS NOT TO EXCEED
0.025 (0.635) MAX.
C
M
E
DIM
A
B
C
D
E
F
G
H
J
K
M
N
A
1 2 3 4 5
K
F
G
D
H
5 PL
0.13 (0.005)
M
T B
J
M
INCHES
MIN
MAX
0.326
0.336
0.396
0.406
0.170
0.180
0.026
0.035
0.045
0.055
0.090
0.110
0.067 BSC
0.098
0.108
0.018
0.025
0.204
0.214
0.055
0.066
0.000
0.004
MILLIMETERS
MIN
MAX
8.28
8.53
10.05
10.31
4.31
4.57
0.66
0.91
1.14
1.40
2.29
2.79
1.70 BSC
2.49
2.74
0.46
0.64
5.18
5.44
1.40
1.68
0.00
0.10
N
SO–8
DF SUFFIX
CASE 751–06
ISSUE T
D
A
8
E
5
0.25
H
1
B
M
M
4
h
B
X 45 e
DIM
A
A1
B
C
D
E
e
H
h
L
A
C
SEATING
PLANE
L
0.10
A1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETER.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
C
B
0.25
M
C B
S
A
S
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.35
0.49
0.19
0.25
4.80
5.00
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0
7
PACKAGE THERMAL DATA
Parameter
D2PAK 5–Pin
SO–8
Unit
RΘJC
Typical
2.5
25
°C/W
RΘJA
Typical
10–50*
110
°C/W
*Depending on thermal properties of substrate. RθJA = RθJC + RθCA.
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CS5231–3
Notes
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13
CS5231–3
Notes
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CS5231–3
Notes
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CS5231–3
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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CS5231–3/D