ETC CS5305/D

CS5305
Three-Phase Synchronous
Switching Step-Down
Controller with Single
Wire Current Sharing
The CS5305 provides a low–cost, single–controller solution for the
low–voltage, high–current power needs of next–generation
workstation and server processors. This IC provides high accuracy and
the industry’s fastest transient response, reducing the need for large
banks of output capacitors and providing the most compact, reliable,
and economical power supply.
Since each phase’s output voltage and current feed back to develop
the PWM ramp signal (enhanced V2 control), the CS5305 shares
output current accurately between phases. Accurate current sharing
means that the power supply design does not need to use power
components rated to handle mismatched current per phase. The
enhanced V2 control compensates for variations in both line and load.
The IC’s built–in single wire current sharing capability allows easy
paralleling of multiple Voltage Regulator Modules (VRMs) based on
the CS5305. The paralleled VRMs use a shared bus to provide high
current and high reliability to multiple microprocessor workstations
or servers.
The CS5305 meets VRM 9.x specifications with its Power Good,
Enable, Differential Remote Sense, and single–wire Current Share
features. The product fits server and workstation VRMs, and can be
used to power Embedded Processors. The IC provides the simplest,
lowest–cost solution for any low voltage, high current power supply.
Features
Enhanced V2 Control Method
VRM 9.x Compatible VID Codes
Lossless Inductor Current Sensing
Single Wire Active Current Sharing Between Converters
Auto Master–Slave Current Share Control Method
Programmable 200 to 800 kHz Switching Frequency
Programmable Adaptive Voltage Positioning
Differential Remote Sense
Pulse–by–Pulse Current Limit
Master Hiccup Overcurrent Protection through Single
Wire Share Bus
• 5–Bit DAC with 1% Tolerance
• ENABL Input
• VRM 9.x–Compliant Power Good Output
• Active Current Sharing During Soft Start
•
•
•
•
•
•
•
•
•
•
 Semiconductor Components Industries, LLC, 2001
May, 2001 – Rev. 5
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MARKING
DIAGRAMS
28
CS5305
AWLYYWW
28
1
1
SO–28L
DW SUFFIX
CASE 751F
A
WL, L
YY, Y
WW, W
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN CONNECTIONS
1
28
GND
GATE1
GATE2
GATE3
DRVON
VCC
SGND
PWRGDS
VID0
VID1
VID2
VID3
VID4
PWRGD
OCSET
ROSC
ENABL
CS1
CS2
CS3
CSREF
IFB
IOUT
SHARE
SCOMP
VDRP
VFB
COMP
ORDERING INFORMATION
Device
CS5305GDW28
CS5305GDWR28
1
Package
Shipping
SO–28L
27 Units/Rail
SO–28L
1000 Tape & Reel
Publication Order Number:
CS5305/D
CS5305
APPLICATION DIAGRAMS
270 nH
+12 V
100 µF
×5
PGND
10 µF
×3
NTD
4302
×2
CS2
CS3
CSREF
IFB
22 nF
VCC
NTD
4302
×2
SGND
PWRGDS
IOUT
VID0
SHARE
VID1
SCOMP
VID2
VDRP
VID3
VFB
91 k
DRVON
BAS40LT1
NTD
4302
×2
VID4
COMP
PWRGD
1 µF
47 nF
×3
SWN
.01 µF
1205
IN
12 k
.47 µF
GATE3
SWN
CS1
1 µF
NTD
4302
×2
PGND
GATE2
IN
ENABL
VCC
GL
GATE1
CS5305
47 nF
3.9 k
GND
ROSC
ENABLE
OCSET
BST
GH
20 k
BST
GH
BAS40LT1
28.7 k
.47 nF
0.1 µF
17 k
220 Ω
PGND
ENABLE
1205
VCC
GL
3k
470 nH
VOUT
2.2 µF
ENABLE
NTD
4302
×2
1205
ENABLE
GND
SWN
IN
1 µF
20 Ω
6.2 V
VCC
GL
0.1 µF
BST
GH
220 k
.47 µF
BAS40LT1
5.6 V
NTD
4302
×2
220 Ω
12 k
×3
GND SENSE
POWERGOOD
VOUT SENSE
SHARE
VID4
60.4 k
VID3
VID2
VID1
VID0
Figure 1. VRM 9.0, 60 A Converter
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2
CS5305
5.0 V
1.5 k
12 V
12 V
ENABLE
VID0
VID1
VID2
VID3
VID4
VOUT SENSE
VOUT
VOUT
ENABLE
VID0
GND
GND SENSE
VID1
VID2
POWERGOOD
VID3
SHARE
VID4
12 V
GND
POWERGOOD
* Inductors & Resistors
represent distribution
impedances.
VOUT SENSE
VOUT
ENABLE
GND
VID0
GND SENSE
VID1
VID2
POWERGOOD
VID3
SHARE
VID4
Figure 2. Two–Converter System with Sharing
MAXIMUM RATINGS*
Rating
Value
Unit
150
°C
–65 to 150
°C
ESD Susceptibility (Human Body Model)
2.0
kV
Thermal Resistance, Junction–to–Case, RθJC
15
°C/W
Thermal Resistance, Junction–to–Ambient, RθJA
75
°C/W
Level 5
–
230 peak
°C
Operating Junction Temperature
Storage Temperature Range
JEDEC Moisture Sensitivity
Lead Temperature Soldering:
Reflow: (SMD styles only) Note 1.
1. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
MAXIMUM RATINGS
Pin Number
Pin Symbol
VMAX
VMIN
ISOURCE
ISINK
1
OCSET
7.0 V
–0.3 V
1.0 mA
1.0 mA
2
ROSC
7.0 V
–0.3 V
1.0 mA
1.0 mA
3
ENABL
16 V
–0.3 V
1.0 mA
1.0 mA
4–6
CS1–3
7.0 V
–0.3 V
1.0 mA
1.0 mA
7
CSREF
7.0 V
–0.3 V
1.0 mA
1.0 mA
8
IFB
7.0 V
–0.3 V
1.0 mA
1.0 mA
9
IOUT
7.0 V
–0.3 V
10 mA
10 mA
10
SHARE
16 V
–0.3 V
50 mA
1.0 mA
11
SCOMP
7.0 V
–0.3 V
1.0 mA
1.0 mA
12
VDRP
7.0 V
–0.3 V
1.0 mA
1.0 mA
13
VFB
7.0 V
–0.3 V
1.0 mA
1.0 mA
14
COMP
7.0 V
–0.3 V
10 mA
1.0 mA
15
PWRGD
16 V
–0.3 V
1.0 mA
20 mA
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3
CS5305
MAXIMUM RATINGS (continued)
Pin Number
Pin Symbol
VMAX
VMIN
ISOURCE
ISINK
16–20
VID4–VID0
16 V
–0.3 V
1.0 mA
1.0 mA
21
PWRGDS
7.0 V
–0.3 V
1.0 mA
1.0 mA
22
SGND
0.3 V
–0.3 V
1.0 mA
1.0 mA
23
VCC
16 V
–0.3 V
N/A
0.4 A, 1.0 µs 100 mA DC
24
DRVON
7.0 V
–0.3 V
10 mA
1.0 mA
25–27
GATE 3–1
16 V
–0.3 V
0.1 A, 1.0 µs; 25 mA DC
0.1 A, 1.0 µs 25 mA DC
28
GND
N/A
N/A
0.4 A, 1.0 µs; 100 mA DC
N/A
ELECTRICAL CHARACTERISTICS (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.5 V < VCC < 14 V; CGATEX = 100 pF,
CCOMP = 0.01µF, CSCOMP = 0.01µF, CVCC = 0.1µF, RROSC = 32.4 kΩ, RSHARE = 60.4 kΩ, V(OCSET) = 0.54 V, DAC Code 01110; unless
otherwise stated.)
Test Conditions
Parameter
Min
Typ
Max
Unit
Voltage Identification DAC (0 = Connected to GND, 1 = Open (Pulled–up to internal 3.3 V) or Pulled–up to external voltage 13 V)
Accuracy (all codes)
VID code – 125 mV
± 1.0
Connect VFB to COMP,
SGND < 55 mV,
Measure COMP – SGND
%
VID4
VID3
VID2
VID1
VID0
VID Maximum Voltage
1
1
1
1
1
DRVON < 1.0 V, GATEX < 1.0 V
1
1
1
1
0
1.100
0.965
0.975
0.985
V
1
1
1
0
1
1.125
0.990
1.000
1.010
V
1
1
1
0
0
1.150
1.015
1.025
1.035
V
1
1
0
1
1
1.175
1.040
1.050
1.061
V
1
1
0
1
0
1.200
1.064
1.075
1.086
V
1
1
0
0
1
1.225
1.089
1.100
1.111
V
1
1
0
0
0
1.250
1.114
1.125
1.136
V
1
0
1
1
1
1.275
1.139
1.150
1.162
V
1
0
1
1
0
1.300
1.163
1.175
1.187
V
1
0
1
0
1
1.325
1.188
1.200
1.212
V
1
0
1
0
0
1.350
1.213
1.225
1.237
V
1
0
0
1
1
1.375
1.238
1.250
1.263
V
1
0
0
1
0
1.400
1.263
1.275
1.288
V
1
0
0
0
1
1.425
1.287
1.300
1.313
V
1
0
0
0
0
1.450
1.312
1.325
1.338
V
0
1
1
1
1
1.475
1.337
1.350
1.364
V
0
1
1
1
0
1.500
1.361
1.375
1.389
V
0
1
1
0
1
1.525
1.386
1.400
1.414
V
0
1
1
0
0
1.550
1.411
1.425
1.439
V
0
1
0
1
1
1.575
1.436
1.450
1.465
V
0
1
0
1
0
1.600
1.460
1.475
1.490
V
0
1
0
0
1
1.625
1.485
1.500
1.515
V
0
1
0
0
0
1.650
1.510
1.525
1.540
V
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4
FAULT Mode
V
CS5305
ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.5 V < VCC < 14 V; CGATEX = 100 pF,
CCOMP = 0.01µF, CSCOMP = 0.01µF, CVCC = 0.1µF, RROSC = 32.4 kΩ, RSHARE = 60.4 kΩ, V(OCSET) = 0.54 V, DAC Code 01110; unless
otherwise stated.)
Parameter
Test Conditions
Min
Typ
Max
Unit
Voltage Identification DAC (0 = Connected to GND, 1 = Open (Pulled–up to internal 3.3 V) or Pulled–up to external voltage 13 V)
0
0
1
1
1
1.675
1.535
1.550
1.566
V
0
0
1
1
0
1.700
1.560
1.575
1.591
V
0
0
1
0
1
1.725
1.584
1.600
1.616
V
0
0
1
0
0
1.750
1.609
1.625
1.641
V
0
0
0
1
1
1.775
1.634
1.650
1.667
V
0
0
0
1
0
1.800
1.658
1.675
1.692
V
0
0
0
0
1
1.825
1.683
1.700
1.717
V
0
0
0
0
0
1.850
1.708
1.725
1.742
V
Input Threshold
VID4, VID3, VID2, VID1, VID0
1.00
1.25
1.5
V
Input Pull–up Resistance
0 V < VID4, VID3, VID2,VID1,
VID0 < 3.3 V
25
50
100
kΩ
Pull–up Voltage
1.0 MΩ to GND
2.5
2.7
3.0
V
10
20
40
µA
SGND Bias Current
SGND < 55 mV, All DAC Codes
Power Good Output
Upper Threshold
Force PWRGDS–SGND
SGND < 55 mV
1.876 (–5%)
1.975
2.074 (+5%)
V
Lower Threshold
Force PWRGDS–SGND
SGND < 55 mV
0.95 ×
(VID – 125 mV)
or –2.6% from
nominal PWRGD
Threshold
0.975 ×
(VID – 125 mV)
VID – 125 mV
or +2.6% from
nominal
PWRGD
Threshold
V
VID4
VID3
VID2
VID1
VID0
1
1
1
1
0
0.926
0.951
0.975
V
1
1
1
0
1
0.950
0.975
1.000
V
1
1
1
0
0
0.974
1.000
1.025
V
1
1
0
1
1
0.998
1.024
1.050
V
1
1
0
1
0
1.021
1.048
1.075
V
1
1
0
0
1
1.045
1.073
1.100
V
1
1
0
0
0
1.069
1.097
1.125
V
1
0
1
1
1
1.093
1.122
1.150
V
1
0
1
1
0
1.116
1.146
1.175
V
1
0
1
0
1
1.140
1.170
1.200
V
1
0
1
0
0
1.164
1.195
1.225
V
1
0
0
1
1
1.188
1.219
1.250
V
1
0
0
1
0
1.211
1.243
1.275
V
1
0
0
0
1
1.235
1.268
1.300
V
1
0
0
0
0
1.259
1.292
1.325
V
0
1
1
1
1
1.283
1.316
1.350
V
0
1
1
1
0
1.306
1.341
1.375
V
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5
CS5305
ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.5 V < VCC < 14 V; CGATEX = 100 pF,
CCOMP = 0.01µF, CSCOMP = 0.01µF, CVCC = 0.1µF, RROSC = 32.4 kΩ, RSHARE = 60.4 kΩ, V(OCSET) = 0.54 V, DAC Code 01110; unless
otherwise stated.)
Parameter
Test Conditions
Min
Typ
Max
Unit
Power Good Output
0
1
1
0
1
1.330
1.365
1.400
V
0
1
1
0
0
1.354
1.389
1.425
V
0
1
0
1
1
1.378
1.414
1.450
V
0
1
0
1
0
1.401
1.438
1.475
V
0
1
0
0
1
1.425
1.463
1.500
V
0
1
0
0
0
1.449
1.487
1.525
V
0
0
1
1
1
1.473
1.511
1.550
V
0
0
1
1
0
1.496
1.536
1.575
V
0
0
1
0
1
1.520
1.560
1.600
V
0
0
1
0
0
1.544
1.584
1.625
V
0
0
0
1
1
1.568
1.609
1.650
V
0
0
0
1
0
1.591
1.633
1.675
V
0
0
0
0
1
1.615
1.658
1.700
V
0
0
0
0
0
1.639
1.682
1.725
V
Switch Leakage Current
VCC = 14 V, PWRGDS = 1.4 V
–
–
1.0
µA
Delay
PWRGDS low to PWRGD low
50
250
600
µs
Output Low Voltage
PWRGDS = 1.0 V,
IPWRGOOD = 4.0 mA
–
0.15
0.4
V
Voltage Feedback Error Amplifier
VFB Bias Current
Note 2.
9.5
10.3
11.5
µA
Comp Source Current
COMP = 0.5 V to 2.0 V,
VFB = 1.6 V
15
30
60
µA
Comp Sink Current
COMP = 0.5 V to 2.0 V,
VFB = 1.0 V
15
30
60
µA
Transconductance
–10 µA < ICOMP < +10 µA, Note 3.
–
32.0
–
mmho
Output Impedance
Note 3.
–
2.5
–
mΩ
Open Loop DC Gain
Note 3.
60
95
–
dB
Unity Gain Bandwidth
COMP = 0.01 µF, Note 3.
–
50
–
kHZ
PSRR @ 1.0 kHz
Note 3.
–
70
–
dB
COMP Max Voltage
VFB = 0 V
2.4
2.7
–
V
COMP Min Voltage
VFB = 1.6 V
–
0.1
0.2
V
0.15
0.2
0.25
V
2.0
5.0
10
µA
4.5
6.0
7.5
–
COMP Discharge Threshold
Hiccup Latch Discharge Current
–
CSx – CSREF = .05 V,
OCSET = 0.1 V,
COMP = 0.5 V
Hiccup Charge / Discharge Ratio
–
2. The VFB Bias Current changes with the value of ROSC per Figure 5.
3. Guaranteed by design. Not tested in production.
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6
CS5305
ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.5 V < VCC < 14 V; CGATEX = 100 pF,
CCOMP = 0.01µF, CSCOMP = 0.01µF, CVCC = 0.1µF, RROSC = 32.4 kΩ, RSHARE = 60.4 kΩ, V(OCSET) = 0.54 V, DAC Code 01110; unless
otherwise stated.)
Parameter
Test Conditions
Min
Typ
Max
Unit
SHARE = 3.5 V,
COMP = 0.5 V,
CSx = CSREF = 0 V,
OCSET = 0.5 V
0.3
2.5
5.0
mA
Threshold Voltage
Monitor DRVON
1.12
1.25
1.38
V
Pull–up Voltage
1 MΩ to GND
2.5
2.7
3.0
V
25
50
100
kΩ
Voltage Feedback Error Amplifier
SHARE Fault Discharge Current
Enable Input
Input Pull–up Resistance
–
PWM Comparators
Minimum Pulse Width
Measured from CSx to GATEx,
VFB = CSREF = 0.5 V,
COMP = 0.5 V,
60 mV step on CSx;
measure at GATEx = 1.0 V
–
75
220
ns
Transient Response Time
Measured from CSREF to GATEx,
COMP = 2.1 V,
CSx = CSREF = 0.5 V,
CSREF stepped
from 1.2 V – 2.0 V
–
100
150
ns
Channel Start–up Offset
CSx = CSREF = VFB = 0 V,
measure V(COMP) when
GATEx switch high
0.34
0.6
0.75
V
Channel Start–up Offset
Mismatch
CSx = CSREF = VFB = 0 V,
measure V(COMP) when
GATEx switch high, Note 4.
–5.0
–
5.0
mV
High Voltage
IGATEx = 1.0 mA
2.25
2.5
3.0
V
Low Voltage
IGATEx = 1.0 mA
–
0.2
0.4
V
Rise Time GATE
0.8 V < GATE < 2.0 V,
VCC = 10 V
–
15
30
ns
Fall Time GATE
2.0 V > GATE > 0.8 V,
VCC = 10 V
–
15
30
ns
Gates
Oscillator
Switching Frequency
ROSC = 32.4 kΩ
300
400
500
kHz
Switching Frequency
ROSC = 63.4 kΩ, Note 4.
150
200
250
kHz
Switching Frequency
ROSC = 16.2 kΩ, Note 4.
600
800
1000
kHz
ROSC Voltage
Note 4.
0.90
1.00
1.10
V
90
120
150
deg
Phase Delay
–
4. Guaranteed by design. Not tested in production.
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CS5305
ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.5 V < VCC < 14 V; CGATEX = 100 pF,
CCOMP = 0.01µF, CSCOMP = 0.01µF, CVCC = 0.1µF, RROSC = 32.4 kΩ, RSHARE = 60.4 kΩ, V(OCSET) = 0.54 V, DAC Code 01110; unless
otherwise stated.)
Parameter
Test Conditions
Min
Typ
Max
Unit
Current Sense Amplifiers
CSREF Input Bias Current
CSREF = CSx = 0 V
–
0.3
3.0
µA
CSx Input Bias Current
CSREF = CSx = 0 V
–
0.1
1.0
µA
Sense Amp Gain
CSREF = 0 V, CSx = 0.05 V,
Measure V(COMP) when
GATEx switches high
.95
1.06
1.17
V/V
Mismatch
0 ≤ (CSx – CSREF) ≤ 50 mV,
Note 5.
–3.0
–
3.0
mV
Common Mode Input Range
Note 5.
0
–
2.0
V
Bandwidth
Note 5.
–
7.0
–
MHz
Single Phase Pulse by Pulse
Current Limit
VFB = CSREF = 0.5 V,
COMP = 2.0 V, Measure
CSx – CSREF when GATEx
goes low
80
90
100
mV
OCSET Input Bias Current
OCSET = 0 V
–
0.1
1.0
µA
Current Sense Input to OCSET
Gain
OCSET / R (CSx – CSREF),
OCSET = 0.6 V,
Monitor DRVON < 1.0 V
3.4
3.7
4.0
V/V
Current Limit Filter Slew Rate
CSREF = 1.1 V, CSx = 1.0 V,
pulse CSx to 1.16 V, Note 5.
2.0
5.0
13
mV / µs
VDRP Output Voltage to
DACOUT Offset
CSx = CSREF, VFB = COMP,
Measure VDRP – COMP
–30
2.0
60
mV
Maximum VDRP Voltage
CSx – CSREF = 50 mV,
VFB = COMP,
Measure VDRP – COMP
500
560
620
mV
Current Sense Amp to VDRP
Gain
CSx – CSREF = 50 mV,
VFB = COMP,
Measure VDRP – COMP
3.4
3.7
4.0
V/V
VDRP Source Current
CSx – CSREF = 50 mV,
VFB = COMP,
VDRP = 1.5 V
1.0
7.0
14
mA
–
0.2
1.0
µA
Adaptive Voltage Positioning
SHARE Current Sense Amplifier
IFB Input Bias Current
IFB = 0 V
Input Offset Voltage
Note 5.
–5.0
0
5.0
mV
Common Mode Input Range
Note 5.
0
–
2.0
V
Output Current
IOUT = 0 V, CSx = 0.667 V,
CSREF = 0.5 V
1.0
10
22
mA
Gain
Note 5.
–
120
–
dB
Output Unity Gain BW
Note 5.
–
5.0
–
MHz
5. Guaranteed by design. Not tested in production.
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8
CS5305
ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.5 V < VCC < 14 V; CGATEX = 100 pF,
CCOMP = 0.01µF, CSCOMP = 0.01µF, CVCC = 0.1µF, RROSC = 32.4 kΩ, RSHARE = 60.4 kΩ, V(OCSET) = 0.54 V, DAC Code 01110; unless
otherwise stated.)
Parameter
Test Conditions
Min
Typ
Max
Unit
SHARE Bus
SHARE Amplifier Offset Voltage
Measure V(SHARE) – V(IOUT),
0 < IOUT < 2.0 V
20
40
60
mV
SHARE Amplifier Source
Current
IOUT = 2.1 V, SHARE = 2.0 V
1.0
7.5
24
mA
SHARE Amplifier Max Voltage
IOUT = 3.5 V, TA = 25°C
2.65
2.80
3.20
V
SHARE Fault Threshold
DRVON < 1.0 V, TA = 25°C
3.2
3.4
3.7
V
SHARE OK Threshold
DRVON > 1.0 V
2.0
2.3
2.5
V
SHARE Fault Hysteresis
–
1.0
1.15
1.3
V
SHARE Fault Output Voltage
–
3.8
4.25
4.7
V
SHARE Fault Output Current
SHARE = 3.8 V
1.2
2.0
2.5
mA
SHARE Full Load Accuracy
CSREF = 0.5 V, CSx = 0.52 V,
IOUT / FB Divider = 22 kΩ/3.0 kΩ
1.7
1.95
2.2
V
SHARE Short Circuit Current
V(IOUT) = 2.0 V, SHARE = GND
1.0
17
28
mA
SHARE Fault Short Circuit
Current
CSREF = 0.5 V, CSx = 0.6 V
2.0
19
30
mA
Transconductance from IOUT to
SCOMP
0 < IOUT < 2.0 V,
0 < SCOMP < 2.0 V
23
40
53
µA / V
Gain from IOUT to COMP
Note 6.
30
50
140
mA / V
Maximum SCOMP source
current
SCOMP = 1.5 V
15
30
60
µA
Maximum SCOMP sink current
SCOMP = 1.5 V
15
30
60
µA
Unity Gain BW
C(SCOMP) = TBD, Note 6.
30
56
100
Hz
Pull–Up Voltage
DRVON Floating
4.5
5.5
6.0
V
DRVON Source Current
DRVON = 1.5 V
.5
3.0
6.5
mA
DRVON Pull Down Resistor
DRVON = 1.5 V, ENABL = 0 V,
R = 1.5 V / I(1.5 V)
35
70
140
kΩ
VCC Disable Current
ENABLE = 0 V (no switching)
–
30
60
mA
UVLO Start Threshold
COMP charging, DRVON > 1.0 V
8.5
9.0
9.5
V
UVLO Stop Threshold
Gates not switching, COMP
discharging, DRVON < 1.0 V
7.5
8.0
8.5
V
UVLO Hysteresis
Start – Stop
0.8
1.0
1.2
V
VCC Operating Current
ENABLE Open
–
22
30
mA
Current SHARE Adjust Amplifier
MOSFET Driver Enable
General Electrical Specifications
6. Guaranteed by design. Not tested in production.
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CS5305
PACKAGE PIN DESCRIPTION
Package Pin Number
SO–28L
Pin Symbol
Pin Name
1
OCSET
Over–Current Set
2
ROSC
Oscillator Frequency
Adjust
Resistance to GND programs the oscillator frequency. It also programs the VFB
bias current shown in Figure 5.
3
ENABL
Enable Input
TTL–Compatible logic input with 50 kΩ internal pull–up resistor to 3.3 V. A logic
low puts the IC in FAULT mode.
4–6
CS1–3
Current Sense Inputs
7
CSREF
Current Sense
Reference
8
IFB
Share Current Amp
Inverting Input
Inverting input to share current amp. Connect resistor divider between IOUT, IFB,
and IC GND pin 28 to program Share Current Amp gain.
9
IOUT
Share Current Amp
Output
Share current amplifier output and input to share adjust amplifier.
10
SHARE
Share Bus
11
SCOMP
Share Compensation
Connect compensation network to stabilize share loop.
12
VDRP
Current Sense Output
for AVP
The offset of this pin above the DAC voltage is proportional to the output current.
Connect a resistor from this pin to VFB to program the AVP voltage or leave this
pin open for no AVP.
13
VFB
Voltage Feedback
Error Amp inverting input. Input bias current used to program AVP light load
offset via resistor connected to converter output voltage. Short VFB to the
converter output voltage for no AVP.
14
COMP
Error Amp Output and
PWM Comparator
Input
Provides loop compensation. Also used to control Softstart and Fault timing.
15
PWRGD
Power Good Output
16–20
VID4–VID0
Voltage ID DAC
Inputs
21
PWRGDS
Power Good Sense
Provides remote output voltage sensing.
22
SGND
Reference Ground
Ground connection for the DAC. Provides remote sensing of ground at the load.
23
VCC
Supply Input
IC Power Supply Input.
24
DRVON
Driver Enable
Logic High enables outputs of compatible MOSFET Driver ICs. Low turns all
MOSFETs OFF. Pin driven from internal 5.5 V; 70 kΩ internal resistor to GND.
25–27
GATE 3–1
FET Driver Outputs
28
GND
Ground
Function
Resistor divider from ROSC to GND programs the threshold of the hiccup
over–current protection.
Non–inverting inputs to the current sense amplifiers.
Inverting input to the current sense amplifiers, and fast feedback input to the
PWM comparator.
Connect with other modules for single–wire current sharing.
Open collector output goes low when VFB is out of regulation. User must
externally limit current into this pin to less than 20 mA.
Programs Output Voltage. 50 kΩ internal pull–up resistors to 3.3 V.
PWM Signal Input to external MOSFET Gate Driver ICs.
IC Power Supply Return; connected to IC substrate.
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CS3
CS2
CS1
CSREF
PWRGDS
PWRGD
VDRP
SGND
VID0
VID1
VID2
VID3
VID4
OCSET
ENABL
50 k
AVP Amp
1.25 V
3.3 V
Delay
50 k
×1
−
+
×1
−
+
×1
−
+
CO3F
×3.7
−
CO3
+
CO2F
×3.7
−
CO2
+
CO1F
1.975 V
* 0.975 V
DAC OUTPUT
VID = 11111 ?
×3.7
−
CO1
+
DAC
OC
Filter
ENABLE
Comparator
3.3 V
−
+
+
IFB
IOUT
SHARE
Current
Sense
Amp
+
−
30 mV
SHARE
Fault
3.3 V
SHARE
Adjust Amp
+
−
3.8 V
SHARE
Fault
+
−
VFB
FAULT
COMP
Reset
Error Amp
+
SHARE Fault
Comparator
Start
Stop
R
S
Reset
Dominant
SHARE SCOMP
SHARE
Bus Amp
+
−
3.1 V
2.1 V
−
Discharge
Comparator
+
−
OC
Comparator
0.2 V
−
+
COMP
IDISCHG
ILIM1
Comparator
ILIM2
Comparator
+
−
ROSC
PULSEOUT3
PULSEOUT2
IOSC
PULSEOUT1
OSCILLATOR
ILIM3
Comparator
0.33 V
+
−
PWM3
Comparator
−
+
0.33 V
+
−
PWM2
Comparator
−
+
0.33 V
+
−
PWM1
Comparator
−
+
Current
Source
Generator
CO3
CO2
CO1
1.0 V
CO3F
CO2F
CO1F
FAULT
IBIAS
0.6 V
FAULT
S
PGND
5.5 V
PWM3
Latch
R
S
PWM2
Latch
R
S
PWM1
Latch
R
Reset
Dominant
Reset
Dominant
Reset
Dominant
9.0 V
8.0 V
−
UVLO
Comparator
+
Start
Stop
−
+
−
+
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−
+
−
+
11
−
+
−
+
−
+
−
+
−
+
Figure 3. Block Diagram
−
+
−
+
−
+
−
+
−
−
+
−
+
−
+
−
+
VCC
70 k
PGND
VCC
PGND
VCC
PGND
VCC
GND
DRVON
GATE3
GATE2
GATE1
CS5305
CS5305
TYPICAL PERFORMANCE CHARACTERISTICS
900
25
VFB Bias Current (µA)
800
Frequency (kHz)
700
600
500
400
300
20
15
10
5
200
100
10
20
30
40
50
ROSC Value (kΩ)
60
0
10
70
Figure 4. Oscillator Frequency
39
9.2
Threshold Voltage (V)
9.4
38
ICC (mA)
ENABL = Low
37
ENABL = Floating
Gates Switching
35
34
33
30
40
50
ROSC Value
60
70
80
Figure 5. VFB Bias Current vs. ROSC Value
40
36
20
Start Threshold
9.0
8.8
8.6
8.4
Stop Threshold
8.2
0
25
50
75
Temperature (°C)
100
8.0
125
Figure 6. ICC vs. Temperature
0
25
50
75
Temperature (°C)
100
125
Figure 7. UVLO Start and Stop Thresholds vs.
Temperature
410
1.353
DAC Output (V)
Oscillator Frequency (kHz)
1.354
405
1.352
1.351
1.350
1.349
400
0
25
50
75
Temperature (°C)
100
125
Figure 8. Oscillator Frequency vs. Temperature for
ROSC = 32.4 k
1.348
0
25
50
75
Temperature (°C)
100
Figure 9. DAC Output for VID = 01111 (1.475 V)
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125
CS5305
TYPICAL PERFORMANCE CHARACTERISTICS
1.582
140
135
Phase Delay (degrees)
DAC Output (V)
1.580
1.578
1.576
1.574
130
GATE3 to GATE1
125
120
GATE2 to GATE3
115
GATE1 to GATE2
110
105
1.572
0
25
50
75
Temperature (°C)
100
100
125
Figure 10. DAC Output for VID = 00110 (1.700 V)
25
50
75
Temperature (°C)
100
125
Figure 11. GATE Phase Delay vs. Temperature
95
Minimum Pulse Width (ns)
10
Rise/Fall Times (ns)
0
Rise Time
8.0
6.0
Fall Time
90
85
80
75
CLOAD = 100 pF
4.0
0
25
50
75
Temperature (°C)
100
70
125
0
Figure 12. GATE Rise and Fall Time vs. Temperature
100
125
700
Start–Up Offset Voltage (mV)
Transient Response Time (ns)
50
75
Temperature (°C)
Figure 13. PWM Comparator Minimum Pulse
Width vs. Temperature
160
140
120
100
80
25
0
25
50
75
Temperature (°C)
100
125
Figure 14. PWM Transient Response Time vs.
Temperature
650
600
550
500
450
400
0
25
50
75
Temperature (°C)
100
Figure 15. Current Sense Amp Channel Start–Up
Offset Voltage vs. Temperature
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125
CS5305
TYPICAL PERFORMANCE CHARACTERISTICS
10.90
Current Sense Amp to VDRP Gain
V(VFB) = 1.9 V
10.85
Current Sense Amp to OSCETGain
3.5
VFB Bias Current (µA)
Current Sense Gain (V/V)
4.0
3.0
2.5
2.0
1.5
10.80
V(VFB) = 1.0 V
10.75
10.70
10.65
10.60
Current Sense Amp to PWM Comparator Gain
1.0
0
25
50
75
Temperature (°C)
100
10.55
125
VDRP to DAC Output Offset Voltage (mV)
VDRP Source Current (mA)
8.5
8.0
7.5
7.0
6.5
0
25
50
75
Temperature (°C)
100
25
50
75
Temperature (°C)
100
125
Figure 17. VFB Bias Current vs. Temperature for
ROSC = 32.4 k
Figure 16. Current Sense Amplifier Gain vs.
Temperature
6.0
0
125
Figure 18. VDRP Source Current vs. Temperature
1.6
1.4
1.2
1.0
0.8
0
25
50
75
Temperature (°C)
100
125
Figure 19. VDRP to DAC Output Offset Voltage vs.
Temperature
4.5
16.0
3.5
IOUT Output Current (mA)
SHARE Bus Voltages (V)
SHARE Fault Output Voltage
4.0
SHARE Fault Threshold
3.0
SHARE Max Output Voltage
2.5
SHARE OK Threshold
2.0
15.5
15.0
14.5
14.0
13.5
SHARE Full Load Accuracy
1.5
0
25
50
75
Temperature (°C)
100
125
Figure 20. SHARE Bus Voltages vs. Temperature
13.0
0
25
50
75
Temperature (°C)
100
Figure 21. IOUT Output Current vs. Temperature
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125
CS5305
TYPICAL PERFORMANCE CHARACTERISTICS
IOUT to SCOMP Transconductance (µA/V)
SHARE Offset Voltage (mV)
45
44
43
42
41
40
39
38
0
25
50
75
Temperature (°C)
100
125
45
40
35
30
25
20
15
Power Good Upper Threshold Voltage (V)
Percentage Change Over Nominal (%)
0.06
VID = 11110
0.02
VID = 01110
0
–0.02
VID = 00000
–0.04
–0.06
0
25
50
75
Temperature (°C)
100
25
50
75
Temperature (°C)
125
Figure 24. Power Good Lower Threshold Voltage vs.
Temperature
2.010
2.005
2.000
1.995
1.990
1.985
1.980
1.975
0
25
50
75
Temperature (°C)
Power Good Delay (µs)
225
220
215
25
100
125
Figure 25. Power Good Upper Threshold Voltage vs.
Temperature
230
0
125
2.015
235
210
100
Figure 23. IOUT to SCOMP Transconductance vs.
Temperature
Figure 22. SHARE Offset Voltage vs. Temperature
0.04
0
50
75
Temperature (°C)
100
Figure 26. Power Good Delay vs. Temperature
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125
CS5305
APPLICATIONS INFORMATION
comparator rises and terminates the PWM cycle. If the
inductor starts the next cycle with higher current, the PWM
Fixed Frequency Multi–phase Control
cycle terminates earlier, thus providing negative feedback.
Multi–phase CPU controllers include the necessary control
A CSx input is provided for each channel, but the CSREF,
circuitry to implement several buck converters in parallel.
VFB and COMP inputs are common to all phases. Current
These converters are configured to turn on at different times.
sharing between phases is accomplished by referencing all
This allows much higher output current than could be
phases to the same error amplifier. Any phase with a larger
provided by a single converter. The apparent ripple frequency
current signal will turn off earlier than the channels with a
is increased and so output current can ramp up or down faster
lower current signal.
than a single converter with the same value of output
Including both current and voltage information in the
inductor. Heat is also spread among multiple components.
feedback signal allows the open loop output impedance of the
The CS5305 uses a fixed frequency, Enhanced V2
power stage to be controlled. In the absence of any load
architecture. Each phase is delayed by approximately 120°
current, the COMP pin voltage will be equal to the sum of the
from the previous phase. The GATE output for each channel
output voltage, the offset voltage and half of the steady–state
changes to a logic high at the beginning of its oscillator cycle.
ramp voltage. (At no load, the output ripple current’s positive
Inductor current ramps up until the combination of the current
and negative contributions are equal, and the DC averaged
sense signal and the output ripple trip the PWM comparator,
voltage is equal to half the ripple voltage.) If the COMP pin
at which time the GATE output changes to a logic low. Once
is held steady and the inductor current is forced to change, the
low, the GATE output remains low until the next oscillator
output voltage will also change. In a closed–loop situation,
cycle begins, and the control loop will not respond until that
changing the inductor current will force the COMP voltage to
time. The Enhanced V2 control loop will respond to line and
change so the output voltage can remain the same. The change
load transients while the GATE output is high. Enhanced V2
in COMP voltage depends on the scaling of the current
control will respond within the off time of the converter.
feedback signal, and can be defined as:
THEORY OF OPERATION
VCOMP (ESRL)(Current Sense Gain)(IPHASE)
SWITCH
NODE
L
Since the current sense gain for this loop is unity, this
equation reduces to:
RCSx
CSx
VCOMP (ESRL)(IPHASE)
+
and so the single–phase power stage output impedance is:
CS AMP
ESRL
OFFSET
+
The CS5305 has three phases, so the total power stage
output impedance is then ESRL/3.
PWM
COMP
CSREF
VOUT
VCOMPIPHASE ESRL
–
CCSx
–
VFB
–
Lossless Inductive Current Sensing
ERROR
AMP
Current can be sensed across the inductor as shown in
Figure 27. The output inductor is designated L and the
inductor’s equivalent series resistance is designated ESRL.
In the ideal case, the values of Rcsx and Ccsx are chosen
such that (L/ESRL) = (Rcsx)(Ccsx). If this criterion is met,
the current sense signal will have the same shape as the
inductor current, and the circuit can be analyzed as if a sense
resistor with value equal to ESRL was placed in series with
the inductor. However, these components also determine the
ramp signal that is used to prevent pulse skipping and duty
cycle jitter. Choosing (Rcsx)(Ccsx) < (L/ESRL) will result
in the AC portion of the current sense signal being scaled
more than the DC portion. This results in a larger ramp
signal, but the current signal will overshoot during
transients. This will affect transient response, adaptive
voltage positioning and current limit. The COMP pin
voltage will overshoot along with the current signal in order
to maintain the output voltage. The COMP voltage will
eventually find the correct level for regulation, but the error
will decay with the time constant (Rcsx)(Ccsx). The VDRP
+
COMP
CCOMP
Figure 27.
V2
The Enhanced
architecture measures and adjusts
current in each phase. An additional input (CSx pin)
provides current information for each output phase to the
control loop as shown in Figure 27. Inductor current is
measured across capacitor Ccsx. The voltage across this
capacitor is equal to the product of the output current and the
inductor ESR if these components are chosen such that
(Ccsx)(Rcsx) = (L)/ESRL. This signal is buffered by the
current sense amplifier (unity gain in the CS5305) and
summed with an offset voltage before it is presented as input
to non–inverting input of the PWM comparator. Inductor
current provides the PWM ramp. As inductor current
increases, the voltage at the positive input to the PWM
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CS5305
causes the output voltage to exceed the upper limit. The fast
adaptive positioning waveform shows how AVP can reduce
transient voltage requirements by about one half compared
to a “normal” converter.
voltage will also overshoot and response will be slowed,
since the current signal is a component of that voltage. The
single phase current limit will trip earlier since the current
signal appears larger than it should be, and the module
current limit will have a lower threshold for fast transients
than it will for slow transients. Additional external
components in the droop circuit and in the error amp
compensation will correct this condition. Details are provided
in the data sheet section on choosing external components.
Adaptive Voltage Positioning
Normal
Fast Adaptive Positioning
Slow Adaptive Positioning
Limits
Adaptive voltage positioning is a technique used to reduce
peak–to–peak output deviations during output current
transients. The output voltage is set higher than nominal at
light loads to reduce output voltage sag when load current is
suddenly increased. Similarly, output voltage is set lower
than nominal at heavy loads to reduce overshoot when load
current suddenly decreases. The CS5305 implements
adaptive voltage positioning by placing a resistor divider
between VDRP and VOUT. The center tap of the divider
connects to VFB. These resistors, along with two or three
other external components, implement a lossless droop
voltage function.
Past implementations of adaptive voltage positioning
used a droop resistor. This resistor was placed in series
between the regulation point of the output voltage and the
load. Increasing the current to the load caused the voltage at
the load to droop below the regulation point. The amount of
droop was equal to the change in current multiplied by the
droop resistor value. This method was acceptable for low
values of output current, where the droop resistor provided
a minimal change in voltage without dissipating a great deal
of power. Higher output current levels and tighter droop
voltage requirements in today’s microprocessors have
rendered this droop resistor technique unusable. The
lossless technique solves these problems.
The AVP function addresses DC and slow transient output
voltage positioning. Response during the first few hundreds
of nanoseconds of a transient are addressed primarily by the
power stage output impedance, and the ESR and ESL of the
output filter. The ramp size and the error amplifier
compensation control the transition between these two
regions. If ramp size is too large or the error amp is too slow,
there will be a long transition to the final voltage after a
transient. This will be most apparent if the output
capacitance is low.
Figure 28 shows how adaptive positioning works. The
waveform labeled “normal” shows output voltage for a
converter without adaptive voltage positioning. The voltage
sags when current steps up, returns to its nominal value and
then overshoots when the current load is decreased. Using
a slow adaptive positioning circuit can actually worsen
performance. The slow adaptive positioning waveform
above shows the output voltage sag, but the voltage recovers
to its initial value before the adaptive positioning circuit
becomes active. When the load decreases, the overshoot
Figure 28. Adaptive Positioning
Current Limit
The CS5305 features two separate current limit circuits.
First, the per–phase current limit terminates topside switch
conduction in a phase if the voltage between any CSx pin
and CSREF exceeds a typical value of 90 mV. This provides
fast peak current protection for individual phases. In
addition, the output current signals for all three phases are
summed and filtered to provide an average module current
signal. This signal is compared to a voltage that is
user–programmable. If this voltage is exceeded, the fault
latch is set and the COMP capacitor is discharged by a 5 µA
current sink until the COMP voltage falls below 0.2 V. The
soft–start cycle begins when this threshold is reached, and the
converter will operate in hiccup–mode until the overcurrent
condition is cleared.
Error Amplifier
200
100
160
60
120
VDB(VY2) in db(Volts)
Phase(VY2) in Deg
The CS5305 uses the Enhanced V2 control method to
offer the fastest and most accurate regulation available. One
of the features of this control method is ease of error
amplifier compensation. A single capacitor placed from the
COMP pin to ground is sufficient to adequately stabilize the
error amplifier.
20
1
2
80
–20
40
–60
2
1
100
1.0 k
10 k
Frequency in Hz
100 k
Figure 29. Error Amplifier Frequency
Response with No Compensation
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CS5305
170
40
150
0
Phase(VY1) in Deg
+Result of VDB(VY1)
Enable
80
The CS5305 has a dedicated enable pin, in accordance with
the latest VRM specifications. This pin is internally pulled up
to a 3.3 V rail through a blocking diode and a 50 kΩ resistor.
The blocking diode allows external pull up to a bias voltage
greater than 3.3 V but below 13 V.
130
2
Fault Protection Logic
The CS5305 is equipped with sophisticated
fault–detection and protection circuitry to ensure proper
operation in a paralleled VRM environment. In such an
environment, any one of several distinct failures could not
only destroy the VRM that sees the fault, but also those
VRMs that are connected in parallel with the faulted VRM.
Table 1 describes the fault logic circuitry, shown below in
Figure 31.
110
–40
–80
1
90
2
1
10
100
1.0 k
Frequency in Hz
10 k
Figure 30. Error Amplifier Frequency
Response with 0.1 F Capacitor
UVLO
Soft Start/Hiccup Mode
S
ENABLE
At initial power–up, the COMP voltage is zero. The total
COMP capacitance will begin to charge with a typical
current of 30 µA. (There may be more than one capacitor
connected between COMP and ground depending on the
adaptive voltage positioning compensation.) All GATE
outputs are held low until the COMP voltage reaches 0.6 V.
Once this threshold is reached, the GATE outputs are
released to operate normally. In hiccup–mode, this will
result in GATE pulses being generated until the module
overcurrent condition reoccurs, and the discharge/Soft Start
cycle begins anew.
VID FAULT
COMP
DISCHG’D?
OVC
R
LOCAL
FAULT
LATCH
FAULT
S
R
SHARE
FAULT
LATCH
SHARE
FAULT
SHARE
BUS
HIGH?
Undervoltage Lockout
Figure 31. Fault Logic Circuitry
The CS5305 includes an under–voltage lockout circuit.
This circuit disables the output drivers until VCC applied to
the IC reaches a typical value of 9 V. The GATE outputs are
disabled when VCC drops below 8 V typical.
Table 1. Description of Fault Logic
Stop
Switching
DRVON
Level
PWRGD
Level
SHARE
Controller
Off
COMP Pin
Characteristics
Reset Method
Under Voltage Lockout
yes
low
low via Power Good
window comparator
n/a
no
–5.0 µA
Comp < 0.2 V
VID = 11111
yes
low
low via Power Good
window comparator
n/a
no
–5.0 µA
Comp < 0.2 V
Enable Low
yes
low
low
n/a
no
–5.0 µA
Comp < 0.2 V
Module Over Current
(set by OCSET)
yes
low
low via Power Good
window comparator
> 3.8 V
no
–5.0 µA
Comp < 0.2 V
Phase Over Current
(0.33 V limit)
terminate
pulse
high
n/a
n/a
no
not affected
not affected
External Share Fault
(SHARE > 3.8 V)
yes
low
low via Power Good
window comparator
n/a
no
–2.5 mA
remove external
3.8 V from SHARE
PWRGDS out of window range
no
high
low
n/a
no
not affected
not affected
Fault Modes
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Gate Outputs
The CS5305 is designed to operate with external gate
drivers. Accordingly, the gate outputs are capable of driving
a 100 pF load with typical rise and fall time of 15 ns.
sees such a code, the GATE pins stop switching and go low.
The DRVON signal also goes low, which turns off all FETs
on the module if the FET driver has an enable input. This
condition is described in Table 1.
DRVON
PWRGD
When the CS5305 is used with DRVON–compatible gate
drivers, the ability of the system to survive a fault in a
paralleled environment is greatly increased. The DRVON
signal tells the gate drivers to shut off both FETs while
entering a fault condition. This action takes the faulted VRM
“out of the picture,” allowing the system to operate until the
bad module can be replaced.
According to the latest VRM specifications, the PWRGD
signal is to be asserted when the output voltage is within a
window defined by the VID code, as shown in Figure 33.
PWRGD
PWRGD
low
HIGH
Digital to Analog Converter (DAC)
The output voltage of the CS5305 module is set by means
of a 5–bit, 1% DAC. The DAC pins are internally pulled up
to a 3.3 V rail through a blocking diode and a set of 50 kΩ
resistors. The blocking diode allows external pull up to a
bias voltage greater than 3.3 V and less than 13 V.
The output of the DAC is described in the Electrical
Characteristics section of the datasheet. These outputs are
consistent with the latest VRM specifications. The DAC
produces an output voltage 125 mV lower than the VID code
would indicate in order to produce an accurate PWRGD
output. The relationship between the VID code and the DAC
code is described by Figure 32 shown below. The shaded
area shows the acceptable range of output voltages.
In order to produce a workable VRM using the CS5305,
the designer is expected to use AVP as described earlier to
position the output voltage above the DAC output, resulting
in an output voltage somewhere in the middle of the
acceptable range.
LOW
–2.6% +2.6%
0.975 × (VID – 125 mV)
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
–5.0% +5.0%
VOUT
1.975 V
In addition, certain fault modes must cause PWRGD to go
low to signal the system board that a VRM fault has
occurred. In that sense, the PWRGD signal operates as a
“VRM BAD” signal. These fault modes, as shown in Table 1
above, are ENABL low and CSx out of window.
When the ENABL pin is pulled low, PWRGD is pulled
low to indicate that the VRM is off. DRVON is pulled low
to turn both FETs off if the FET driver has an enable input.
The logic circuitry inside the chip sets PWRGD low only
after a delay period has been passed. A “power bad” event
does not cause PWRGD to go low unless it is sustained
through the delay time, typically 200 µs. If the anomaly
disappears before the end of the delay, the PWRGD output
will never be set low.
In order to use the PWRGD pin as specified, the user is
advised to connect external resistors as necessary to limit the
current into this pin to 4 mA or less.
VID code
125 mV
MIN VOUT
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÉÉÉÉ
ÉÉÉÉ
PWRGD
low
Figure 33. PWRGD Assertion Window
VOUT
MAX VOUT
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÉÉÉ
ÉÉÉ
PWRGD
high
Share Bus
VRM 9.x specifications require that a single–wire share
bus be provided from each module. This bus allows output
current information to be communicated between modules
such that the total load current is shared equally by each
module. The CS5305 employs a proprietary share algorithm
called direct duty cycle control. A block diagram is provided
in Figure 34.
DAC output
Figure 32. VRM 9.0 Output
Voltage Accuracy Requirements
The latest VRM specifications require a module to turn its
output off in the event of a 11111 VID code. When the DAC
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CS5305
VOUT + VOFFSET + 1× CURRENT SENSE INPUT
3.7× CURRENT
SENSE INPUT
+
SHARE
ADJUST AMP
+
3.3 V
+
–
SHARE
CURRENT
SENSE AMP
–
+
SHARE
BUS AMP
–
GATEx
RESET
–
PWM
COMPARATOR
– +
PWM
LATCH
GATE
DRIVER
SET
30 mV
FROM
OSCILLATOR
IFB
IOUT
SHARE
SCOMP
COMP
Figure 34.
CHOOSING EXTERNAL COMPONENTS
FOR THE CS5305
Direct duty cycle control utilizes a master–slave approach
to current sharing. At any given current load, one module
will have a higher share bus voltage than the other modules.
This module acts as the master. It conveys output current
information to the other modules via the share bus. This
information is buffered and provided to the PWM
comparators, thus directly controlling duty cycle for the
slave modules.
The share current sense amplifier allows the user to
customize the share bus transconductance. Current sense
information is provided to the non–inverting input from the
3.7× current sense amplifier from each phase. This provides
a representation of the total module current. An external
resistor divider between IOUT and ground, center–tapped at
IFB programs the share bus voltage for a particular current
level.
The share bus amplifier serves as a buffer and places the
IOUT voltage on the SHARE pin. Note there is a diode in the
schematic between the share bus amplifier and the SHARE
pin. This is an “ideal” diode, and indicates that the share bus
amplifier does not have current sink capability. This allows
the share bus to be driven by the module with the highest
share bus voltage. A 30 mV offset voltage provides noise
immunity to ensure that any given module does not cycle
between master and slave in a random fashion. It also
guarantees that the master module is not driving duty cycle
from the share bus. For the master module, the IOUT and
SHARE voltages will be equal. In this case, the 30 mV offset
holds the share adjust amplifier inactive, and the PWM
channel is controlled in the normal manner. The offset
voltage results in a current error between the master and
slave modules, but this error is small compared to the current
share tolerance found in the VRM 9.x specifications.
The share adjust amplifier takes the share bus voltage and
directly drives the PWM comparators of all slave modules
as previously described. The SCOMP pin provides a
connection point for a compensation capacitor for the share
adjust amplifier.
ROCSET and ROSC
The ROSC lead of the CS5305 provides a fixed 1 V
reference to the user. A resistive divider is connected from
ROSC to ground as shown in Figure 35. The center tap of the
divider is connected to the OCSET lead. The total
resistance from the ROSC lead to ground programs the
oscillator frequency for the converter according to the chart
in Figure 36.
The resistive divider also sets a voltage on the OCSET lead.
This voltage programs the module overcurrent trip point. The
module overcurrent comparator, or OC Comparator, uses the
OCSET lead voltage as the reference against which the
module output current signal is compared. The output current
of each phase is given as (VCSx – VCSREF) divided by the
equivalent series resistance of the inductor. The voltage
information (VCSx – VCSREF) is gained up by a factor of 3.7
and summed for all three phases at the non–inverting input of
the OC Comparator. The fault latch is set if the module
overcurrent limit is exceeded. This results in “hiccup–mode”
operation until the overcurrent condition is cleared.
ROSC
R1
OCSET
ROCSET
ROSC = R1 + ROCSET
Figure 35.
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CS5305
900
for the CS1, CS2 and CS3 leads, but the value of resistance
should be one third that of RCSx:
800
RCSREF RCSx3
FOSC (kHz)
700
This change is necessary to compensate for the difference
in bias current between the CSREF lead and each CSx lead.
The schematic in Figure 37 shows the connection of these
components.
600
500
400
Switch
Node x
300
200
100
RCSx
10
20
30
40
50
R1 + ROSCSET (kΩ)
60
CCSx
RCSREF = RCSx/3
CSREF
70
CSx
Figure 36. FOSC vs. R1 + ROCSET
CCSREF
Figure 37.
Additionally, the total value of resistance between ROSC
and ground also programs the VFB pin bias current. VFB bias
current is equal to 0.333 V divided by the total resistance
from ROSC to ground. This current is used to generate the
droop function in the adaptive voltage positioning circuitry
and is discussed further in that section.
Share Bus Components
Five external components are required to implement the
module–to–module current share function. These
components set the current sense load line, provide the share
bus pull–down and compensate the share adjust amplifier.
The share current sense amplifier monitors the total
module current and provides a DC voltage output
proportional to that current. The share sense amplifier gain
is programmable and allows the user to set the share bus
transconductance. It is important that all modules in a
system have a share current load line that approximates that
of all the other modules to ensure accurate
module–to–module current sharing. Let us arbitrarily set the
share bus maximum voltage for full load at 2 V. If a module
is designed to provide 81 A at full load, the module share
transconductance should be 81 A/2 V or 40.5 A/V. Two
resistors and a capacitor set the share current sense amplifier
gain. The resistors set the DC gain while the capacitor
provides a zero to minimize errors due to noise.
The total module current is measured as described in the
section dealing with the OCSET current limit function. That
is, each phase within a module generates a voltage between
the CSx and CSREF leads that is proportional to the current
flow in the output inductor and the inductor’s ESR:
Current Sense Components
Current sense components are chosen for two reasons.
First, the value of RCSx and CCSx should be chosen to meet
the criterion:
(RCSx)(CCSx) (L)(ESRL)
where L is the inductor value and ESRL is the inductor
equivalent series resistance. Meeting this criterion will
ensure that the module overcurrent limit is not exceeded
during current transients. Second, RCSx and CCSx should be
chosen to add a small amount of ramp to the system. This
will provide stable, jitter–free operation. The amount of
ramp voltage required depends on several factors: supply
voltage, output voltage (DAC code), switching frequency
and board layout all affect the amount of artificial ramp
required to some degree. The power supply designer should
be aware that choosing the value of artificial ramp is a
trade–off. As artificial ramp amplitude increases, the system
becomes less prone to duty cycle jitter, but transient
response will suffer. Adding 20 mV of artificial ramp is a
good compromise and can be used to start design.
The current sense ramp is generated from the square wave
obtained at the switching node of each phase by using an RC
filter. The RC filter components for the CSx leads should be
chosen to satisfy the following formula:
(VOUT)
1 VOUTVCC
RCSx CCSx VOUT
L1
VCSx VCSREF (IL)(ESRL)
This signal is amplified by a factor of 3.7 for each phase
and then summed for all three phases. This signal is provided
as input to the share current sense amplifier. If we assume
that all three phases are sharing current equally within a
single module, the input to the share current sense amplifier
can be expressed as:
(fOSC)(VRAMP)
VIN(SENSE) 11.1(VCSx VCSREF)
11.1(IL)(ESRL) 3.7(IOUT)(ESRL)
Choose a convenient standard value for CCSx and solve for
the value of RCSx. Each of the three output phases requires
its own RC combination.
An RC filter is also required for the CSREF connection.
This filter may use the same value of capacitance identified
If we set IL equal to the maximum per phase current at full
load, and if we know the value of ESR for our inductors, we
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CS5305
lead voltage to 3 V. The share bus of one module serves as
master to all and drives the total resistance of all SHARE
leads. Thus, the total impedance of all share resistors should
be made greater than or equal to 3 kΩ. That is,
can calculate the required share current sense amplifier
gain as:
AV(SHARESENSE) share maximimum voltage
VIN(SENSE)
3 k RSHAREN
As an example, let us again consider the case for a module
providing full load current of 81 A. Each output phase is
conducting 27 A. If we assume ESR = 1.5 mΩ then input to
the share current sense amplifier is (11.1)(27 A)(1.5 mΩ) =
0.45 V. The required share current sense amplifier gain is
then 2 V/0.45 V = 4.44.
where N is the maximum number of modules that can be
placed in parallel as defined by the designer. As an
example, if ten is the maximum number of modules that
may be paralleled, then the minimum value of RSHARE
should be 30 kΩ.
The share resistor should also not be made too large, since
this is the only pull–down on the SHARE lead. Transient
response of the share bus is limited by the RC time constant
of the share resistance and any parasitic capacitance found
on the SHARE line between modules.
+
VIN(SENSE)
–
RIOUT
IFB
IOUT
Droop Components
CIOUT
RIFB
The CS5305 offers adaptive voltage positioning. This
feature allows the output voltage to be set at different levels
according to the amount of current being provided by the
module. The output voltage is somewhat higher than
nominal under no load or light load conditions and
somewhat lower than nominal under heavy load conditions.
Both set points must fall within the Power Good window.
The adaptive positioning allows for overshoot and
undershoot conditions that occur during load current
transients and results in a reduction in the peak–to–peak
VOUT voltage excursion during load current transients.
Three components are required to implement DC
adaptive voltage positioning. Resistor RFB is connected
between the module VOUT(SENSE)+ lead and the VFB lead.
Resistor RDRP is connected between the VDRP lead and
VFB lead. Resistor RVSENSE is connected between the
VOUT(SENSE)+ lead and the module VOUT lead. These
connections are shown in Figure 39.
Figure 38.
From the schematic in Figure 38, we derive the DC gain as:
AV(SHARESENSE) 4.44 RIOUTRIFB 1
This specifies that RIOUT should be 3.44 times greater than
RIFB.
Another important consideration is the type of resistor
selected for RIFB. The thermal performance of RIFB must
match that of whatever sense element is being used to monitor
module current. Inductive sensing has been shown to be
reasonably accurate, but copper’s thermal coefficient of
resistivity is approximately +4000 parts per million per °C
(0.4% per °C). In order to maintain accurate control of the
share bus over temperature, RIFB must have a similar thermal
coefficient. This requires a positive temperature coefficient
element such as the KOA–Speer LT73. If a standard sense
resistor is used in series between the inductor and the load,
there is no need to use special resistors for sensing, but
efficiency will suffer due to power dissipation in the sense
resistor.
As regards the value of CIOUT, it should be noted that the
complete transfer function for the share current sense
amplifier in Figure 38 is:
AV(SHARESENSE) VDRP
RDRP
VFB
RFB
VOUT(SENSE)+
RVSENSE
RIOUT
1
RIFB(1 sCIOUT RIOUT)
VOUT
CIOUT causes the gain for high frequency noise to
decrease, thus quieting the share bus.
The share resistor provides a passive pull–down on the
SHARE lead. This allows the share bus voltage to be pulled
all the way down to ground. The share resistor is selected to
satisfy a number of criteria. First, the resistor cannot be made
too small. The SHARE lead source current is guaranteed to
be above 1 mA and must be capable of driving the SHARE
Figure 39.
The first step in choosing these components is to select the
appropriate no–load and full–load output voltage set points
for the particular DAC code being used. Additionally, the
values of ROSC and ROCSET should be known, as should
ESR of the output inductors and the full–load output current.
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CS5305
the test tool so a function generator can drive it. Using lower
frequency (approximately 100 Hz) and lower duty cycle
(10%) allow the designer to better observe the true settling
behavior of the VRM module.
It may be necessary to add some filtering components to
the droop voltage divider. These components cause the AC
and DC gain from the current sense circuitry to match and
allow the user to tailor the droop output voltage
performance.
There are two methods for tuning droop performance. The
first is illustrated in Figure 41. In this case, capacitors CDRP
and CFB are placed in parallel with RDRP and RFB. A third
capacitor CDRCMP is connected between the COMP and
VDRP leads. The first two capacitors correct any gain errors
introduced in the selection of current sense components
Rcsx and Ccsx. Values for these components are defined as:
+
V(DAC)
OUTPUT
STAGE
–
RDRP
VDRP
VFB
RFB
I(VFB)
VOUT
Figure 40.
As was previously noted, the total value of resistance
between the ROSC pin and ground sets the VFB lead bias
current according to:
I(VFB) 0.333 V(ROSC ROCSET)
Referring to Figure 40, the VDRP lead voltage is equal to
the DAC voltage plus the current sense information. Under
no load conditions, the VDRP and VFB pin voltages are equal,
and the entire VFB bias current flows between
VOUT(SENSE)+ and VFB through RFB. Because the VFB bias
current sinks into VFB, the output voltage is forced to be
higher than the DAC voltage, and so the value of RFB can be
calculated as:
CFB L((RFB)(ESRL))
and
CDRP ((CCSx)(RCSx))RDRP
The capacitor between VDRP and COMP allows the user
to fine–tune the transition between “fast” AVP and the
slower positioning set by resistors RDRP and RFB. This
capacitor may or may not be required and is empirically
chosen based on the fine–tuning procedure described below.
A value of 1 nF is recommended as an initial value.
RFB (VOUT no load set point VDAC)I(VFB)
With RFB chosen, we can now select the value of RDRP.
If we again refer to Figure 40, we can use Kirchoff’s
Current Law at the VFB node to find that the value of RDRP
is defined as:
VDRP
(full load current)(3.7)(ESRL)(RFB)
RDRP (RFB)(I(VFB)) V(DAC) VOUT full load set point
CDRP
RDRP
CFB
RFB
VFB
RVSENSE is used to ensure that a connection between
VOUT and VOUT(SENSE) always exists. This ensures that the
module will operate correctly in the event that the
VOUT(SENSE) connection is broken. The module–to–load
interface and the number of modules placed in parallel
determine the value of RVSENSE. The CS5305 is specified to
operate correctly with up to 55 mV dropped across the
module connector. It is assumed that the maximum current
allowed to flow in this connection to the load is 1 mA.
VOUT(SENSE)+
CDRCMP
RVSENSE
VOUT
COMP
Figure 41.
RVSENSE 55 mV(1 mAN)
Set up the circuit to be tested with a DVM and
oscilloscope to the output. Have the scope set to DC input
and set its offset so a resolution of at least 100 mV/div is used
and the output is visible on the screen.
Using a DVM, measure the output voltage with no load.
If this value differs from the expected value, adjust RFB until
the nominal value is reached. Once this is set, mark this DC
level on the scope with a cursor.
Next, measure the output voltage with full DC load. If this
value deviates from the expected value, adjust RDRP until
the nominal value is reached. Once this is set, mark this DC
level on the scope with another cursor.
where:
N = the number of modules to be paralleled.
If four modules are to be paralleled, each contributes a
maximum of 250 µA to this connection, and so RVSENSE =
55 mV/250 µA = 220 Ω. This component is placed to ensure
the VRM module will regulate correctly if the module
VOUT(SENSE)+ connection to the load is opened.
The transient droop performance should be checked next.
Performance should be verified using the transient test tool
typically provided in a microprocessor development kit.
True transient performance can be masked even at test
frequencies as low as 2 kHz. It should be possible to modify
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CS5305
No Load Cursor Marker
Full Load Cursor Marker
Trace 1: Optimal
Trace 2: CFB too large
Trace 3: CFB too small
Trace 4: CDRCMP too large, CCOMP too small
Trace 5: CDRCMP too small, CCOMP too large
Figure 42.
Using the transient test tool, set up a current load step from
low current (1 A) to maximum load at the slew rate being
designed for. Set the current step at about 100 Hz with a duty
cycle of 10%. Converter response should be similar to that
shown in Figure 42.
Next, determine if there is a “bump” (trace 4 or trace 5) in
the output. Adjust CCOMP and CDRCMP to flatten out this
bump. If the “bump” is negative (trace 5), make CDRCMP
slightly larger and CCOMP slightly smaller. If you see a
positive “bump” (trace 4), make CDRCMP slightly smaller
and CCOMP slightly larger. If performance is better without
CDRCMP, just make C1 larger.
Once the bump is removed, look to see if the “pulse step”
magnitude is larger or smaller than the DC level (trace 2 or
trace 3). Make CFB slightly larger if the AC gain (trace 3) is
too large or slightly smaller if the AC gain (trace 2) is too
small. Once the output response resembles the “optimal”
trace (trace 1), the controller has been optimized for the
design from a static and dynamic response.
If the output appears to be jittering slightly prior to
optimizing transient response, make the previous
adjustments first, since they may solve the problem. If the
problem persists, decreasing the value of Rcsx across the
inductor will increase ramp amplitude, and jitter
performance should improve with increased ramp.
The second method uses a capacitor to “square up” the
COMP waveform and a series resistor and capacitor to tune
the VDRP waveform. These components are chosen
empirically based on observations of COMP and VDRP
performance.
First, set the test tool for a load current transient from no
load (1 A) to full load and observe the COMP waveform.
The COMP waveform should ideally be flat, or at worst
decrease slightly during a current increase transient. The
principle at work here is that the increase in current sense
information will generate a voltage that should exactly
cancel the droop voltage, and thus the COMP capacitor
voltage should not change. In reality, it is unlikely that every
manufactured module can be built to perfectly compensate
the droop voltage, and so the COMP voltage should exhibit
a small amplitude square wave during transient conditions.
If the COMP voltage is decreasing gradually, the current
sense information is too small to fully compensate for the
droop voltage, and the designer should add a capacitor
between VOUT and COMP. This capacitor is chosen
empirically, with 1 nF a good starting point. This capacitor
will pull the COMP pin down initially and “square up” the
COMP waveform as shown in Figure 43.
Current Transient
COMP Ideal Waveform
COMP Uncorrected
Waveform
VOUT Uncorrected
Waveform
COMP Corrected
Waveform
VOUT Corrected
Waveform
Figure 43.
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CS5305
In a similar manner, if the current information is too large,
the COMP voltage will rise to compensate. Again, a square
wave is preferable to a slow change in the COMP voltage,
and placing a capacitor between VDRP and COMP will
“square up” the COMP waveform as shown in Figure 44.
VFB up so COMP voltage decreases results in increasing
output duty cycle. The series RC filter is now located in
parallel with RDRP.
Current Step
Current Transient
VDRP
COMP Ideal Waveform
(RCSx)(CCSx) > L/ESRL
COMP Uncorrected
Waveform
Figure 46.
VOUT Uncorrected
Waveform
These components are chosen empirically. The fastest
way to optimize the design is to start with a 1 nF capacitor
and a 500 kΩ potentiometer and “dial in” performance.
COMP Corrected
Waveform
Error Amplifier Compensation
VOUT Corrected
Waveform
Error amplifier compensation is very simple using the
enhanced V2 control architecture. A single 0.1 µF capacitor
from the COMP lead to ground is usually sufficient. As an
alternative, a resistor and capacitor in series between COMP
and ground may improve output voltage positioning during
current transients. The resistance will speed up the effective
slew rate of the error amplifier output.
The COMP capacitor also provides soft start and
hiccup–mode timing. At start–up, the COMP capacitance
must charge from ground through a typical channel start–up
offset of 0.6 V before the GATE outputs are allowed to begin
switching. The COMP capacitance includes both the COMP
capacitor and any droop compensation capacitance that may
be connected to the COMP pin. The typical soft start time
can then be approximated as:
Figure 44.
Once the COMP waveform has been squared up, it is
necessary to check the VDRP waveform. The VDRP
waveform is dependent on the choice of ramp
components. If these components have been chosen such
that (RCSx)(CCSx) = L / ESRL, the VDRP waveform should
be a square wave that matches the current step. At this
point, the VOUT waveform should also be a square wave
and transient performance should be optimized.
If (RCSx)(CCSx) < L / ESRL, the VDRP waveform will be
faster than current step. The VDRP voltage will exhibit a fast
rise followed by an exponential droop down to a DC level,
as shown in Figure 45. This waveform has the effect of
telling the system that transient current signals are larger
than the true current. Response will be slowed, and VOUT
will overshoot until the error amplifier “catches up”. In this
case, it is desirable to push the VFB pin down, so that COMP
voltage is forced up and duty cycle is reduced slightly. This
is done by placing a series RC filter across resistor RFB.
TSOFT–START(ms) 20 CCOMP(TOTAL)(F)
Hiccup timing has a similar equation. During
hiccup–mode, the COMP voltage traverses between the
fault reset threshold (approximately 0.2 V) and the channel
start–up offset voltage. When the fault circuitry becomes
active, the COMP capacitor is discharged with a 5 µA
current until the fault reset threshold is reached. The time
this initial discharge takes is variable depending on the
COMP voltage when the fault occurred. Once the reset
threshold is reached, the COMP capacitor is charged with
the 30 µA current until the start–up offset voltage is reached.
The GATE outputs will begin to pulse, quickly ramping the
inductor current. The fault circuitry can then re–detect the
fault condition some number of GATE pulses later if it is still
present. Thus, the period of the fault hiccup mode is
approximately defined as:
Current Step
VDRP
(RCSx)(CCSx) < L/ESRL
Figure 45.
If (RCSx)(CCSx) > L / ESRL, the VDRP waveform will be
slower than the current step. VDRP will exhibit an initial
spike, but the voltage will then exponentially rise toward its
correct DC level, as shown in Figure 46. This waveform
effectively tells the system that the current signal is smaller
than the true current, and response will be faster than
optimal. VOUT will then undershoot. In this case, forcing
THICCUP(ms) 93.3 CCOMP(TOTAL)(F)
Period is only approximately defined since the number of
GATE pulses between restart and redetection of a fault
condition is unpredictable.
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CS5305
Inductors
Since the maximum output current must be less than the
maximum switch current, the minimum inductance required
for a single phase can be determined.
There are many factors to consider when choosing the
output inductors. Maximum load current, core and winding
losses, ripple current, short circuit current, saturation
characteristics, component height and cost are all variables
that the designer should consider. However, the most
important consideration in designing for the VRM 9.x
specifications may be the effect inductor value has on
transient response.
The amount of overshoot or undershoot exhibited during
a current transient is defined as the product of the current
step and the output filter capacitor ESR. To some degree,
adaptive voltage positioning is used to “pre–position” the
output voltage so the voltage step during a current transient
will not cause the output voltage to exceed the Power Good
window. However, adaptive positioning will not completely
eliminate the overshoot or undershoot conditions, and
choosing the inductor value appropriately can minimize the
amount of energy that must be transferred from the inductor
to the capacitor or vice–versa. In the subsequent paragraphs,
we will determine the minimum value of inductance
required for our system and consider the trade–off of ripple
current vs. transient response.
In order to choose the minimum value of inductance, input
voltage, output voltage and output current must be known.
Most computer applications use reasonably well regulated
bulk power supplies so that, while the equations below
specify VIN(MAX) or VIN(MIN), it is possible to use the
nominal value of VIN in these calculations with little error.
Current in the inductor while operating in the continuous
current mode is defined as the load current plus ripple
current.
(VIN(MIN) VOUT)VOUT
L(MIN) (fOSC)(ISWITCH(MAX))(VIN(MIN))
This equation identifies the value of inductor that will
provide the full rated switch current as inductor ripple
current, and will usually result in inefficient system
operation. The system will sink current away from the load
during some portion of the duty cycle unless load current is
greater than half of the rated switch current. Some value
larger than the minimum inductance must be used to ensure
the converter does not sink current. Choosing larger values
of inductor will reduce the ripple current, and inductor value
can be designed to accommodate a particular value of ripple
current by replacing ISWITCH(MAX) with a desired value of
IRIPPLE:
(VIN(MIN) VOUT)VOUT
L(RIPPLE) (fOSC)(IRIPPLE)(VIN(MIN))
However, reducing the ripple current will cause transient
response times to increase. The response times for both
increasing and decreasing current steps are shown below.
TRESPONSE(INCREASING) TRESPONSE(DECREASING) The ripple current waveform is triangular, and the current
is a function of voltage across the inductor, switch FET
on–time and the inductor value. FET on–time can be defined
as the product of duty cycle and switch frequency, and duty
cycle can be defined as a ratio of VOUT to VIN. Thus,
(VIN VOUT)VOUT
(fOSC)(L)(VIN)
VRIPPLE ESRC
IRIPPLE Peak inductor current is defined as the load current plus
half of the peak current. Peak current must be less than the
maximum rated FET switch current, and must also be less
than the inductor saturation current. Thus, the maximum
output current for a single phase can be defined as:
IOUT(MAX) ISWITCH(MAX) (L)(IOUT)
(VOUT)
Inductor value selection also depends on how much output
ripple voltage the system can tolerate. Output ripple voltage
is defined as the product of the output ripple current and the
output filter capacitor ESR. However, since the CS5305 has
three paralleled phases, the net effect is that the switching
frequency as seen by the output capacitance is tripled relative
to the CS5305 operating frequency. This is because each
phase switches in sequence and the ripple currents in each
phase are superimposed on the output capacitance. This is
illustrated graphically in Figures 45 and 46.
Thus, output ripple voltage can be calculated as:
IL ILOAD IRIPPLE
IRIPPLE (L)(IOUT)
(VIN VOUT)
ESRC
VIN VOUTVOUT
3
fOSC
L
VIN
It is also important to note that the maximum value of
inductor ESR is limited by the single–phase pulse–by–pulse
current limit. The specified minimum value for this
parameter is 80 mV, so the maximum inductor ESR is:
VIN(MAX) VOUTVOUT
2
fOSC
L
VIN(MAX)
ESRL(MAX)(in ohms) http://onsemi.com
26
(0.08 V)
single phase current limit value in Amps
CS5305
VCC Bypass Filtering
PHASE 2 SWITCH NODE
A small RC filter should be added between module VCC and
the VCC input to the CS5305. A 10 Ω resistor and a 0.1 µF
capacitor should be sufficient to ensure the controller IC does
not operate erratically due to injected noise.
PHASE 3 SWITCH NODE
Module Input Filter Capacitors
SUPERIMPOSED PHASE
INDUCTOR CURRENTS
The input filter capacitors for the VRM module provide
a charge reservoir that minimizes supply voltage variations
due to changes in current flowing through the switch FETs.
These capacitors must be chosen primarily for ripple current
rating.
PHASE 1 SWITCH NODE
PHASE 1 CURRENT
PHASE 2 CURRENT
PHASE 3 CURRENT
OUTPUT RIPPLE CURRENT
LIN
LOUT
VIN
VOUT
IIN(AVE)
Figure 47.
Finally, we should consider power dissipation in the
output inductors. Power dissipation is proportional to the
square of inductor current:
CIN
IRMS(CIN)
COUT
CONTROL
INPUT
PD I 2PHASE)(ESRL)
Figure 48.
The temperature rise of the inductor relative to the air
surrounding it is defined as the product of power dissipation
and thermal resistance to ambient:
Consider the schematic shown in Figure 48. The average
current flowing in the input inductor LIN for any given
output current is:
T(inductor) (Ra)(PD)
IIN(AVE) (IOUT)(VOUTVIN)
(IOUT per phase)(n)(D)
Ra for an inductor designed to conduct 20 A to 30 A is
approximately 45°C/W. The inductor temperature is given as:
where:
D = duty cycle,
n = number of phases.
Input capacitor current is positive into the capacitor when
the switch FETs are off, and negative out of the capacitor
when the switch FETs are on. When the switches are off,
IIN(AVE) flows into the capacitor. When the switches are on,
capacitor current is equal to the per–phase output current
minus IIN(AVE). If we ignore the small current variation due
to the output ripple current, we can approximate the input
capacitor current waveform as a square wave. We can then
calculate the RMS input capacitor ripple current:
T(inductor) T(inductor) Tambient
Output Filter Capacitors
Each microprocessor manufacturer specifies output filter
capacitors for the motherboards. In addition, the designer
may need to add some output capacitance on the VRM
module. These added output capacitors would serve to
reduce the noise floor and help ensure jitter–free operation.
If needed, one or two ceramic capacitors should be
sufficient. They should have a 4 WVDC rating. Large
amounts of bulk capacitance placed on the VRM module are
not useful, since the impedance of the VRM connector exists
between the module and the load. Low equivalent series
resistance is important since output ripple voltage and
response to output current transients are largely dependent
on this parasitic parameter.
IRMS(CIN) http://onsemi.com
27
I 2IN(AVE) D n
IOUT per phase IIN(AVE)2 I 2IN(AVE)
CS5305
parallel, the effective RDS(ON) is reduced, thus reducing the
ohmic power loss. However, placing FETs in parallel
increases the gate capacitance so that switching losses
increase. As long as adding another parallel FET reduces the
ohmic power loss more than the switching losses increase,
there is some advantage to doing so. However, at some point
the law of diminishing returns will take hold, and a marginal
increase in efficiency may not be worth the board area
required to add the extra FET. Additionally, as more FETs
are used, the limited drive capability of the FET driver will
have to charge a larger gate capacitance, resulting in
increased gate voltage rise and fall times. This will affect the
amount of time the FET operates in its ohmic region and will
increase power dissipation.
The following equations can be used to calculate power
dissipation in the switch FETs.
For ohmic power losses due to RDS(ON):
The input capacitance must be designed to conduct the
worst case input ripple current. This will require several
capacitors in parallel. In addition to the worst case current,
attention must be paid to the capacitor manufacturer’s
derating for operation over temperature.
As an example, let us define the input capacitance for a
12 V to 1.7V conversion at 81 A, or 27 A per phase at an
ambient temperature of 60°C. A droop voltage of 90 mV to
1.61 V and efficiency of 80% is assumed. Average input
current in the input filter inductor is:
IIN(AVE) (27 A)(3 phases)(1.61 V12 V)
10.868 A
80%
Input capacitor RMS ripple current is then
IIN(RMS) 10.8682 1.61 V 3
12 V
27 A 10.868 A2 10.868 A2
13.347 A
PON(TOP) If we consider a Sanyo SP series capacitor, the ripple
current rating for a 16SPS100M capacitor is 2820 mA at
100 kHz and 45°C. The derating factor is 0.85 for operation
up to 65°C, resulting in an effective ripple current rating of
2397 mA. We determine the number of input capacitors by
dividing the ripple current by the per–capacitor current
rating:
PON(BOTTOM) (RDS(ON)(TOP))(IRMS(TOP))2(n)
(number of topside FETs per phase)
RDS(ON)(BOTTOM)
IRMS(BOTTOM)2
n)
number of bottom–side FETs per phase
where:
n = number of phases.
Note that RDS(ON) increases with temperature. It is good
practice to use the value of RDS(ON) at the FET’s maximum
junction temperature in the calculations shown above.
Number of capacitors 13.347 A2.397 A 5.52
A total of at least 6 capacitors in parallel must be used to
meet the input capacitor ripple current requirements.
IRMS(TOP) Output Switch FETs
Output switch FETs must be chosen carefully, since their
properties vary widely from manufacturer to manufacturer.
The CS5305 system is designed assuming that a FET driver
IC and n–channel FETs will be used. The FET
characteristics of most concern are the gate
charge/gate–source threshold voltage, gate capacitance,
on–resistance, current rating and the thermal capability of
the package.
FET driver ICs have a limited drive capability. If the
switch FET has a high gate charge, the amount of time the
FET stays in its ohmic region during the turn–on and
turn–off transitions is larger than that of a low gate charge
FET, with the result that the high gate charge FET will
consume more power. Similarly, a low on–resistance FET
will dissipate less power than will a higher on–resistance
FET at a given current. Thus, low gate charge and low
RDS(ON) will result in higher module efficiency and will
reduce heat being generated by the VRM module.
It can be advantageous to use multiple switch FETs to
reduce power consumption. By placing a number of FETs in
I
2
PK
(IPK)(IRIPPLE) D I 2RIPPLE
3
IRMS(BOTTOM) I 2PK (IPKIRIPPLE) IRIPPLE (1 D) 2
I RIPPLE
3
(VIN VOUT)(VOUT)
(fOSC)(L)(VIN)
I
I
I
IPEAK ILOAD RIPPLE OUT RIPPLE
2
3
2
where:
D = Duty cycle.
For switching power losses:
PD nCV2(fOSC)
where:
n = number of switch FETs (either top or bottom) per phase,
C = FET gate capacitance,
V = maximum gate drive voltage (usually VCC),
fOSC = switching frequency.
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CS5305
External FET Driver
Layout Considerations
The CS5305 is designed such that an external FET driver
IC is required. The GATE pin outputs are designed to drive
a 100 pF load, and do not have sufficient drive capability to
directly drive the gates of switch FETs. The GATE outputs
have a typical output high voltage of 2.5 V, so the turn–on
threshold of the FET driver should be approximately 2 V.
The GATE outputs are also phased such that the FET driver
IC should turn on the topside n–channel FET when the
GATE output goes high. The bottom–side n–channel FET
should be on when the GATE output is below the FET driver
IC turn–on threshold.
Additionally, the CS5305 provides a signal called
DRVON that can be connected to the ENABLE pin of FET
drivers that offer an enable feature. If the FET driver’s
ENABLE input is high, the FET driver output is determined
by the GATE input, and the switch FETs are driven
according to the conditions described above. If the FET
driver’s ENABLE input is low, all switch FETs are turned
off and no current is conducted to the load. This DRVON
signal is a logic output from the CS5305. DRVON goes high
when all internal functions of the CS5305 are operating
correctly and the IC is not in fault mode. A table of the
DRVON logic may be found in the Theory of Operation
section.
Choosing a FET driver IC with an enable feature
significantly improves system reliability, since a faulty
module is essentially disconnected from the load.
Enhanced V2 performs best under dynamic load
conditions if current ramp is kept small. However, this may
lead to pulse–width jitter or pulse skipping, particularly as
the ambient noise level at the control circuit increases. This
is a complicated design trade–off that can not be
mathematically characterized, and it is crucial to have a
“quiet” layout. Following the design/layout guidelines
below will provide the best system performance. Refer to
Figure 50 for a layout example and to page 2 for the
associated schematic. Numbers in parentheses refer to IC
pin numbers. Component names refer to the reference
designators for the application schematic.
1. Noise across the PWM comparator inputs needs to be
low or pulse width jitter will occur. Referring to the
block diagram, the CSREF pin (7) and the COMP pin
(14) present external information to the PWM
comparator. Any differential signal across these pins
is expressed directly across the PWM comparator,
which may cause pulse–width jitter or pulse skipping.
The solution is to provide a dedicated Kelvin
connection for sensing the VRM’s VOUT–. The IC’s
GND pin (28) and COMP capacitance need a
dedicated sense line to VOUT–, in effect making the IC
and COMP capacitance VOUT–ground–referenced.
This is desirable since the fast feedback path through
CSREF is connected to VOUT+ and is therefore also
VOUT–ground–referenced. Furthermore, a ground
strip under the IC is desirable since the COMP pin is
located at the opposite corner of the IC from the GND
pin. This ground strip further reduces the ambient
noise level of the CS5305 along with providing a
good connection from COMP return to GND and
VOUT–. Following this guideline will provide the
most system improvement from a layout standpoint.
SGND Resistor
The module–to–load interface and the number of modules
placed in parallel determine the value of RSGND. The
CS5305 is specified to operate correctly with up to 55 mV
dropped across the module connector. It is assumed that the
maximum current allowed to flow in this connection to the
load is 1 mA.
RSGND 55 mV(1 mAN)
where:
N = the number of VRM modules to be paralleled.
If four modules are to be paralleled, each contributes a
maximum of 250 µA to this connection, and so,
RSGND 55 mV250 A 220 This component is placed to ensure the VRM module will
regulate correctly if the module VOUT(SENSE)– connection
to the load is opened.
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29
CS5305
or
VOUT+ sense
VOUT+ sense
VOUT– sense
VOUT– sense
Figure 49.
component should be placed near the one of the
inductors to achieve the best thermal coupling, and so
the best current sharing performance. Remote
placement with respect to the IC requires dedicated
parallel runs of GND and IFB to reduce share bus
noise sensitivity.
2. Differential noise across the PWM comparator can be
further reduced if the VOUT+ and VOUT– sense lines
going to CSREF and GND are paralleled to minimize
loop area. VOUT+ ripple information provided to the
PWM comparator via the CSREF pin needs to be
symmetric for all three phases or poor current sharing
between phases will occur. This can be accomplished
by placing the VOUT+ and VOUT– sense locations
symmetrically with respect to the three output
inductors. See Figure 49.
3. Frequency jitter could occur if the ROSC pin (2) and
OCSET pin (1) components are not properly located.
Most layouts will have two resistors in series from
ROSC to GND. Keep these two components as close
as possible to the IC and ensure a short ground
connection to the IC GND. Provision for a small cap
(1000 pF or less) from ROSC to GND can be placed
although this is rarely needed. If the ROSC capacitor
value is too large, the ROSC voltage reference will
oscillate.
4. The VCC (23) bypass capacitor (0.1 µF or greater)
should be located as close as possible to the IC. This
capacitor’s connection to GND must be as short as
possible. The most effective way to implement this
tight component placement is to via the GATE1, 2, 3
and DRVON runs to internal layers right at the IC
pins.
5. The switch nodes of all three phases must be sensed
for inductive current sensing. Care should be given to
how this information is brought to the CS5305.
Switch node voltages should not be routed
underneath or near the IC; however, the resistors in
the RC filter of CS1, 2, 3 must be reasonably close to
their associated capacitors so noise pick–up on the
CS1, 2, 3 pins is minimized. The best solution is to
locate the RC filter capacitors close to the CS1, 2, 3
pins and to place the respective resistors off to the side
of the IC.
6. A positive temperature coefficient thermistor can be
used for R11 (see Share Bus section) to compensate
for thermal variation in the inductor ESR. This
Thermal Considerations
Typically, the controller IC and the FET gate drivers do
not dissipate significant amounts of power, and do not
contribute greatly to module power dissipation. The main
components of concern are the switch FETs and the
inductors.
We have already reviewed the power calculations for
these components, but we haven’t related them to a thermal
solution. Standards exist limiting the maximum VRM
printed circuit board temperature (105°C is common), and
thus power dissipation becomes a thermal consideration in
addition to playing a part in overall module efficiency.
Power dissipation on the VRM results in heat radiation
to the surrounding air. Power dissipated by the components
is conducted to the PCB. The PCB acts as a heat sink and
provides a larger surface area for heat exchange to the
surrounding air. The PCB temperature is dependent on total
PCB power dissipation, the surface area of the PCB
available to act as a heat sink, the ambient temperature of
the surrounding air and the thermal resistance to ambient of
the PCB.
While it is possible to model power dissipation on the PCB
for efficiency purposes, it is very difficult to accurately
model thermal performance. In particular, thermal
resistance to ambient of the PCB varies widely. This
parameter depends on many factors: board shape, size and
material; copper weight; amount of exposed copper;
insulating characteristics of the solder mask layers; air flow
properties (amount, direction, PCB orientation to the
airflow); and even whether a particular component is
“hidden” behind others. In reality, modeling PCB resistance
to ambient is highly complex and the best way to guarantee
thermal performance is to actually build prototypes and
measure it directly.
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CS5305
Figure 50. Sample Layout
Additional Information
2. “Excel Spreadsheet Method for Choosing CS5305
External Components”. This Excel spreadsheet that
can be used to generate a first–pass schematic design
for VRM 9.x designs based on user input, and is
available from the factory.
3. “Excel Spreadsheet Method for CS5305 Power
Budget Optimization”. This Excel spreadsheet that
can be used to calculate power dissipation in all the
high–power dissipation components (including metal
traces). This allows the design to be optimized for
power/thermal management, and is available from the
factory.
Several additional resources are available to make system
design with the CS5305 a simpler task. The power supply
designer is invited to obtain the following documents and
files from ON Semiconductor.
1. AND8045/D, “Enhanced V2 Multiphase SMPS for
Microprocessor.” This application note provides
details on the theory of operation, selection of
components, layout practices and thermal
management strategies necessary to design power
supplies with the CS5305 controller.
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CS5305
PACKAGE DIMENSIONS
SO–28L
DW SUFFIX
CASE 751F–05
ISSUE F
D
A
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSIONS.
4. MAXIMUM MOLD PROTRUSION 0.015 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
15
0.25
E
H
M
B
M
28
1
14
PIN 1 IDENT
A1
A
B
e
B
0.025
C
M
C A
S
B
S
L
0.10
C
SEATING
PLANE
DIM
A
A1
B
C
D
E
e
H
L
MILLIMETERS
MIN
MAX
2.35
2.65
0.13
0.29
0.35
0.49
0.23
0.32
17.80
18.05
7.40
7.60
1.27 BSC
10.05
10.55
0.41
0.90
0
8
Patents Pending.
V2 is a trademark of Switch Power, Inc.
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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CS5305/D