ETC CS8120/D

CS8120
5.0 V, 300 mA Linear
Regulator with RESET
and ENABLE
The CS8120 is a 5.0 V, 300 mA precision linear regulator with two
microprocessor compatible control functions and protection circuitry
included on chip. The composite NPN–PNP output pass transistor
assures a lower dropout voltage (1.0 V @ 200 mA) without requiring
excessive supply current (2.5 mA).
The CS8120’s two logic control functions make this regulator well
suited to applications requiring microprocessor–based control at the
board or module level. ENABLE controls the output stage. A high
voltage (> 2.9 V) on the ENABLE lead turns off the regulator’s pass
transistor and sends the IC into Sleep mode where it draws only 250 µA.
The RESET function sends a RESET signal when the IC is powering up
or whenever the output voltage moves out of regulation. The RESET
signal is valid down to VOUT = 1.0 V.
The CS8120 design optimizes supply rejection by switching the
internal bandgap reference from the supply input to the regulator
output as soon as the nominal output voltage is achieved. Additional
on chip filtering enhances rejection of high frequency transients on all
external leads.
The CS8120 is fault protected against short circuit, over voltage and
thermal runaway conditions.
Features
• 5.0 V ±4.0% Output Voltage 300 mA
• Low Dropout Voltage (1.0 V @ 150 mA)
• Low Quiescent Current (2.5 mA @ IOUT = 150 mA)
• µP Compatible Control Functions
– RESET
– ENABLE
• Low Current Sleep Mode
– IQ = 250 µA
• Fault Protection
– Thermal Shutdown
– Short Circuit
– 60 V Load Dump
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TO–220
FIVE LEAD
T SUFFIX
CASE 314D
1
5
TO–220
FIVE LEAD
TVA SUFFIX
CASE 314K
1
TO–220
FIVE LEAD
THA SUFFIX
CASE 314A
1
5
D2PAK
5–PIN
DP SUFFIX
CASE 936F
1
5
DIP–8
N SUFFIX
CASE 626
8
1
SO–14
D SUFFIX
CASE 751A
14
1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 10 of this data sheet.
 Semiconductor Components Industries, LLC, 2001
March, 2001 – Rev. 7
1
Publication Order Number:
CS8120/D
CS8120
PIN CONNECTIONS
D2PAK 5–PIN
1 DIP–8 8
TO–220 5 LEAD
Tab = GND
Pin 1. VIN
2. ENABLE
3. GND
4. RESET
5. VOUT
1
GND
VOUT
VIN
SENSE
NC
RESET
ENABLE
Pin 1. VIN
2. ENABLE
3. GND
4. RESET
5. VOUT
NC
1
SO–14
14
VOUT
GND
SENSE
NC
RESET
NC
NC
VIN
NC
NC
NC
ENABLE
NC
NC
1
VOUT
VIN
Over Voltage
Shutdown
ENABLE
–
Output
Current
Limit
ENABLE
Comparator
–
Bandgap
Supply
+
Error
Amplifier
Thermal
Protection
VREF
Bandgap
Reference
To VOUT
RESET
+
Reset
Comparator
+
–
GND
Figure 1. Block Diagram – TO–220
ABSOLUTE MAXIMUM RATINGS*
Rating
Value
Unit
–0.7 to 26
V
60
V
Internally Limited
–
2.0
kV
Operating Temperature
–40 to +125
°C
Junction Temperature
–40 to +150
°C
Storage Temperature Range
–55 to +150
°C
260 peak
230 peak
°C
°C
DC Input Voltage
Load Dump
Output Current
Electrostatic Discharge (Human Body Model)
Lead Temperature Soldering:
Wave Solder (through hole styles only) (Note 1.)
Reflow (SMD styles only) (Note 2.)
1. 10 second maximum.
2. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
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2
CS8120
ELECTRICAL CHARACTERISTICS (VIN = 14 V, IOUT = 5.0 mA; –40 ≤ TJ ≤ 150°C, –40°C ≤ TC ≤ 125°C,
unless otherwise noted.) Note 3.
Characteristic
Test Conditions
Min
Typ
Max
Unit
Output Voltage, VOUT
7.0 V ≤ VIN ≤ 26 V, 1.0 mA ≤ IOUT ≤ 300 mA
4.8
5.0
5.2
V
Line Regulation
7.0 V ≤ VIN ≤ 26 V, IOUT = 200 mA
–
–
50
mV
Load Regulation
1.0 mA ≤ IOUT ≤ 300 mA
–
–
50
mV
Supply Voltage Rejection
VIN = 14 VDC + 1.0 VRMS @ 120Hz
LOAD = 25 Ω
40
70
–
dB
Dropout Voltage
IOUT = 200 mA
–
1.0
1.5
V
Quiescent Current
ENABLE = High, VIN = 12 V
ENABLE = Low, IOUT = 200 mA
–
–
0.25
2.5
0.65
15
mA
mA
Output Stage
Protection Circuits
Short Circuit Current
–
300
600
–
mA
Thermal Shutdown
–
150
190
–
°C
Overvoltage Shutdown
–
26
40
–
V
RESET
RESET Saturation Voltage
1.0 V < VOUT < VRT(OFF),
3.1 kΩ Pull–Up to VOUT
–
0.1
0.4
V
RESET Output Leakage Current
ENABLE = Low, VOUT > VRT(ON),
VRESET = VOUT
–
0
25
µA
Power ON/OFF RESET
Peak Output Voltage
3.1 kΩ Pull–Up to VOUT
–
0.7
1.0
V
–
4.75
VOUT – 0.10
VOUT – 0.14
VOUT – 0.04
–
V
V
10
40
–
mV
RESET Threshold
HIGH (VRH)
LOW (VRL)
VOUT Increasing
VOUT Decreasing
RESET Threshold Hysteresis
–
ENABLE
Input High Voltage
7.0 V < VIN < 26 V
–
2.9
3.9
V
Input Low Voltage
7.0 V < VIN < 26 V
1.1
2.1
–
V
Input Hysteresis
7.0 V < VIN < 26 V
0.4
0.8
2.8
V
Input Current
GND < VIN(HI) < VOUT
–10
0
+10
µA
3. To have safe operating junction temperatures, low duty cycle pulse testing is used on tests where applicable.
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CS8120
PACKAGE LEAD DESCRIPTION
PACKAGE LEAD #
SO–14
D2Pak
5 PIN
LEAD SYMBOL
2
1
1
VIN
2
4
5
2
ENABLE
3
8
13
3
GND
4
6
10
4
RESET
5
1
14
5
VOUT
N/A
7
12
–
SENSE
–
3, 5
2, 3, 4, 6,
7, 8, 9, 11
TO–220
5 LEAD–
DIP–8
1
FUNCTION
Supply voltage to IC, usually direct from the battery.
CMOS compatible logical input. VOUT is disabled i.e. placed
in a high impedance state when ENABLE is high.
Ground Connection.
CMOS compatible output lead. RESET goes low whenever
VOUT falls out of regulation. The RESET delay is externally
programmed.
Regulated output voltage, 5.0 V (typ).
Kelvin Connection which allows remote sensing of output
voltage for improved regulation. If remote sensing is not desired, connect to VOUT.
NC
No Connection.
TYPICAL PERFORMANCE CHARACTERISTICS
5.02
0
IOUT = 100 mA
5.01
5.0 V @ 25°C
–10
Load Reg. (mV)
5.0
VOUT (V)
40°C
–5
4.99
4.98
4.97
125°C
–15
25°C
VIN = 14 V
–20
–25
–30
–35
–40
4.96
–45
4.95
–40
–50
–20
0
20
40
60
80
100
120
140
150
0
100
200
300
400
IOUT (mA)
Junction Temperature (°C)
Figure 3. Load Regulation vs. Output
Current Over Temperature
Figure 2. Output Voltage vs. Temperature
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500
CS8120
TYPICAL PERFORMANCE CHARACTERISTICS
50
1.4
VIN = 7 to 25 V
Dropout Voltage. (V)
Line Reg. (mV)
40
30
20
25°C
125°C
10
–40°C
0
1.2
1.0
–40°C
0.8
25°C
125°C
0.6
0.4
0.2
–10
0
50
100
150
200
250
300
350
400
450
0.0
500
0
50
100
IOUT (mA)
150
200
250
300
350
Output Current (mA)
Figure 4. Line Regulation vs. Output
Current Over Temperature
Figure 5. Dropout Voltage vs. Output
Current Over Temperature
5.5
3.5
VIN = 14 V
22
20
5
VOUT
4
16
VOUT (V)
25°C
2.0
125°C
1.5
3
12
IQ
2
8
1.0
4
1
0.5
0.0
0
0
50
100
150
200
250
300
350
0
2
4
Figure 7. Output Voltage and Supply
Current vs. Input Voltage
Figure 6. Quiescent Current vs. Output
Current Over Temperature
2000
1800
VIN = 5.0 V
1400
1200
1000
800
600
400
200
0
1
5
8
Supply Voltage (V)
Output Current (mA)
1600
6
10
15
20
25
30
35
Reset Output Current (mA)
Figure 8. RESET Output Voltage vs.
Output Voltage
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5
40
10
0
Supply Current (mA)
–40°C
2.5
Reset Output Voltage (mV)
Quiescent Current (mA)
3.0
CS8120
CIRCUIT DESCRIPTION
VOLTAGE REFERENCE AND OUTPUT CIRCUITRY
circuitry and enables the IC to survive unexpected voltage
transients.
Using an emitter sense scheme, the amount of current
through the NPN pass transistor is monitored. Feedback
circuitry insures that the output current never exceeds a
preset limit.
Should the junction temperature of the power device
exceed 180°C (typ) the power transistor is turned off.
Thermal shutdown is an effective means to prevent die
overheating since the power transistor is the principle heat
source in the IC.
Precision Voltage Reference
The regulated output voltage depends on the precision band
gap voltage reference in the IC. By adding an error amplifier
into the feedback loop, the output voltage is maintained
within ±4.0% over temperature and supply variation.
Output Stage
The composite PNP–NPN output structure (Figure 9)
provides 300 mA (typ) of output current while maintaining
a low drop out voltage (1.00 V, typ) and drawing little
quiescent current (2.5 mA). The NPN pass device prevents
deep saturation of the output stage which in turn improves
the IC’s efficiency by preventing excess current from being
used and dissipated by the IC.
REGULATOR CONTROL FUNCTIONS
The CS8120 contains two microprocessor compatible
control functions: ENABLE and RESET (Figure 11).
ENABLE Function
The ENABLE function switches the output transistor.
When the voltage on the ENABLE lead exceeds 2.9 V typ,
the output pass transistor turns off, leaving a high impedance
facing the load. The IC will remain in Sleep mode, drawing
only 250 µA, until the voltage on the lead drops below 2.1
V typ. Hysteresis (800 mV) is built into the ENABLE
function to provide good noise immunity.
VIN
For 7.0 V < VIN < 26 V
VIN
VOUT
ENABLE
Figure 9. Composite Output Stage of the CS8120
VIN(H)
VRH
Output Stage Protection
The output stage is protected against overvoltage, short
circuit and thermal runaway conditions (Figure 10).
VOUT
VRL
(1)
VRPEAK
> 26 V
(2)
VRPEAK
VRLO
RESET
VIN
(1) = No Reset Delay Capacitor
(2) = With Reset Delay Capacitor
VOUT
Figure 11. Circuit Waveform for CS8120
RESET Function
IOUT
Load
Dump
Short
Circuit
A RESET signal (low voltage) is generated as the IC
powers up (VOUT > VOUT – 100 mV) or when VOUT drops
out of regulation (VOUT < VOUT – 140 mV, typ). 40 mV of
hysteresis is included in the function to minimize
oscillations.
The RESET output is an open collector NPN transistor,
controlled by a low voltage detection circuit. The circuit is
functionally independent of the rest of the IC, thereby
Thermal
Shutdown
Figure 10. Typical Circuit Waveforms for
Output Stage Protection
If the input voltage rises above 26 V (e.g. load dump), the
output shuts down. This response protects the internal
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CS8120
guaranteeing that the RESET signal is valid for VOUT as low
as 1.0 V.
5.0 V to µP
and System
Power
VOUT
RRST
CS8120
An external RC network on the RESET lead (Figure 12)
provides a sufficiently long delay for most microprocessor
based applications. RC values can be chosen using the
following formula:
RTOT CRST C2
22 µF
–tDelay
lnV
VTVOUT
RSTVOUT
where:
RTOT = RRST in parallel with RIN,
RIN = µP port impedance,
CRST = RESET delay capacitor,
tDelay = desired delay time,
VRST = VSAT of RESET lead (0.7 V @ turn – ON), and
VT = µP logic threshold voltage.
to µP
RESET
Port
RESET
CRST
Figure 12. RC Network for RESET Delay Circuitry
APPLICATION NOTES
allows the microprocessor to finish key housekeeping
functions before power is removed.
The logic options are summarized in Table 1.
The circuit depicted in Figure 13 lets the microprocessor
control its power source, the CS8120 regulator. An I/O port
on the µP and the SWITCH port are used to drive the base
of Q1. When Q1 is driven into saturation, the voltage on the
ENABLE lead falls below its lower threshold. The
regulator’s output is switched out. When the drive current is
removed, the voltage on the ENABLE lead rises, the output
is switched off and the IC moves into Sleep mode where it
draws 250 µA.
By coupling these two controls with the ENABLE, the
system has added flexibility. Once the system is running, the
state of the SWITCH is irrelevant as long as the I/O port
continues to drive Q1. The microprocessor can turn off its
own power by withdrawing drive current, once the
SWITCH is open. This software control at the I/O port
Table 1. Logic Control of CS8120 Output
Microprocessor
I/O Drive
SWITCH
ENABLE
Output
ON
Closed
LOW
ON
Open
LOW
ON
OFF
C1
0.1 µF
ON
HIGH
OFF
VOUT
CS8120
500 kΩ
LOW
Open
The I/O port of the microprocessor typically provides
50 µA to Q1. In automotive applications the SWITCH is
connected to the ignition switch.
VIN
VBAT
Closed
ENABLE
GND
VCC
C2
22µF
RRST
RESET
µP
RESET
CRST
Q1
100 kΩ
500 kΩ
100 kΩ
SWITCH
Figure 13. Microprocessor Control of CS8120 Using External Switching Transistor Q1
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I/O Port
CS8120
STABILITY CONSIDERATIONS
the greatest oscillation. This represents the worst case load
conditions for the regulator at low temperature.
Step 4: Maintain the worst case load conditions set in
step 3 and vary the input voltage until the oscillations
increase. This point represents the worst case input voltage
conditions.
Step 5: If the capacitor is adequate, repeat steps 3 and 4
with the next smaller valued capacitor. A smaller capacitor
will usually cost less and occupy less board space. If the
output oscillates within the range of expected operating
conditions, repeat steps 3 and 4 with the next larger standard
capacitor value.
Step 6: Test the load transient response by switching in
various loads at several frequencies to simulate its real
working environment. Vary the ESR to reduce ringing.
Step 7: Raise the temperature to the highest specified
operating temperature. Vary the load current as instructed in
step 5 to test for any oscillations.
The output or compensation capacitor, C2, helps
determine three main characteristics of a linear regulator:
start–up delay, load transient response and loop stability.
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum or
aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause
instability. The aluminum electrolytic capacitor is the least
expensive solution, but, if the circuit operates at low
temperatures (–25°C to –40°C), both the value and ESR of
the capacitor will vary considerably. The capacitor
manufacturers data sheet usually provides this information.
The value for the output capacitor C2 shown in Figure 14
should work for most applications, however it is not
necessarily the optimized solution.
5.0 V to µP and
System Power
VIN
C1 *
0.1 µF
Once the minimum capacitor value with the maximum
ESR is found, a safety factor should be added to allow for the
tolerance of the capacitor and any variations in regulator
performance. Most good quality aluminum electrolytic
capacitors have a tolerance of ± 20% so the minimum value
found should be increased by at least 50% to allow for this
tolerance plus the variation which will occur at low
temperatures. The ESR of the capacitor should be less than
50% of the maximum allowable ESR found in step 3 above.
VOUT
CS8120
RESET
ENABLE
RRST
to µP
RESET
port
C2**
10 µF
CRST
*C1 is required if regulator is far from the power source filter.
CALCULATING POWER DISSIPATION IN A SINGLE
OUTPUT LINEAR REGULATOR
**C2 is required for stability.
The maximum power dissipation for a single output
regulator (Figure 15) is:
Figure 14. Circuit Showing Output
Compensation Capacitor
To determine an acceptable value for C2 for a particular
application, start with a tantalum capacitor of the
recommended value and work towards a less expensive
alternative part.
Step 1: Place the completed circuit with a tantalum
capacitor of the recommended value in an environmental
chamber at the lowest specified operating temperature and
monitor the outputs with an oscilloscope. A decade box
connected in series with the capacitor will simulate the
higher ESR of an aluminum capacitor. Leave the decade box
outside the chamber, the small resistance added by the
longer leads is negligible.
Step 2: With the input voltage at its maximum value,
increase the load current slowly from zero to full load while
observing the output for any oscillations. If no oscillations
are observed, the capacitor is large enough to ensure a stable
design under steady state conditions.
Step 3: Increase the ESR of the capacitor from zero using
the decade box and vary the load current until oscillations
appear. Record the values of load current and ESR that cause
PD(max) VIN(max) VOUT(min)IOUT(max) VIN(max)IQ
(1)
where:
VIN(max) is the maximum input voltage,
VOUT(min) is the minimum output voltage,
IOUT(max) is the maximum output current for the
application, and
IQ is the quiescent current the regulator consumes at
IOUT(max).
Once the value of PD(max) is known, the maximum
permissible value of RΘJA can be calculated:
RJA 150°C TA
PD
(2)
The value of RΘJA can then be compared with those in the
package section of the data sheet. Those packages with
RΘJA’s less than the calculated value in equation 2 will keep
the die temperature below 150°C.
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CS8120
HEAT SINKS
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
IIN
VIN
A heat sink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of RΘJA.
IOUT
VOUT
SMART
REGULATOR
Control
Features
RJA RJC RCS RSA
(3)
where:
RΘJC = the junction–to–case thermal resistance,
RΘCS = the case–to–heatsink thermal resistance, and
RΘSA = the heatsink–to–ambient thermal resistance.
RΘJC appears in the package section of the data sheet. Like
RΘJA, it too is a function of package type. RΘCS and RΘSA
are functions of the package type, heatsink and the interface
between them. These values appear in heat sink data sheets
of heat sink manufacturers.
IQ
Figure 15. Single Output Regulator With Key
Performance Parameters Labeled
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CS8120
ORDERING INFORMATION
Device
Description
Shipping
TO–220 FIVE LEAD STRAIGHT
50 Units/Rail
CS8120YTVA5
TO–220 FIVE LEAD VERTICAL
50 Units/Rail
CS8120YTHA5
TO–220 FIVE LEAD HORIZONTAL
50 Units/Rail
CS8120YT5
CS8120YN8
DIP–8
50 Units/Rail
CS8120YDP5
D2PAK, 5–Pin
50 Units/Rail
CS8120YDPR5
D2PAK, 5–Pin
750 Tape & Reel
CS8120YD14
SO–14
55 Units/Rail
CS8120YDR14
SO–14
2500 Tape & Reel
MARKING DIAGRAMS
TO–220
FIVE LEAD
T SUFFIX
CASE 314D
TO–220
FIVE LEAD
TVA SUFFIX
CASE 314K
TO–220
FIVE LEAD
THA SUFFIX
CASE 314A
DIP–8
N SUFFIX
CASE 626
8
D2PAK
5–PIN
DP SUFFIX
CASE 936F
SO–14
D SUFFIX
CASE 751A
14
CS8120
AWL
YYWW
CS8120
AWLYWW
CS8120
AWLYWW
CS8120
AWLYWW
CS8120
AWLYWW
1
1
1
1
1
1
A
WL, L
YY, Y
WW, W
AWLYWW
CS8120
= Assembly Location
= Wafer Lot
= Year
= Work Week
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CS8120
PACKAGE DIMENSIONS
TO–220
FIVE LEAD
T SUFFIX
CASE 314D–04
ISSUE E
–T–
–Q–
SEATING
PLANE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.
DIMENSION D INCLUDING PROTRUSION SHALL
NOT EXCEED 10.92 (0.043) MAXIMUM.
C
B
E
A
U
L
K
J
H
G
D
DIM
A
B
C
D
E
G
H
J
K
L
Q
U
1234 5
5 PL
0.356 (0.014)
M
T Q
M
INCHES
MIN
MAX
0.572
0.613
0.390
0.415
0.170
0.180
0.025
0.038
0.048
0.055
0.067 BSC
0.087
0.112
0.015
0.025
0.990
1.045
0.320
0.365
0.140
0.153
0.105
0.117
MILLIMETERS
MIN
MAX
14.529 15.570
9.906 10.541
4.318
4.572
0.635
0.965
1.219
1.397
1.702 BSC
2.210
2.845
0.381
0.635
25.146 26.543
8.128
9.271
3.556
3.886
2.667
2.972
TO–220
FIVE LEAD
TVA SUFFIX
CASE 314K–01
ISSUE O
–T–
SEATING
PLANE
C
B
–Q–
E
W
A
U
F
L
1
2
3
4
K
5
M
D
0.356 (0.014)
M
J
5 PL
T Q
M
G
S
R
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11
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.
DIMENSION D INCLUDING PROTRUSION SHALL
NOT EXCEED 10.92 (0.043) MAXIMUM.
DIM
A
B
C
D
E
F
G
J
K
L
M
Q
R
S
U
W
INCHES
MIN
MAX
0.560
0.590
0.385
0.415
0.160
0.190
0.027
0.037
0.045
0.055
0.530
0.545
0.067 BSC
0.014
0.022
0.785
0.800
0.321
0.337
0.063
0.078
0.146
0.156
0.271
0.321
0.146
0.196
0.460
0.475
5°
MILLIMETERS
MIN
MAX
14.22
14.99
9.78
10.54
4.06
4.83
0.69
0.94
1.14
1.40
13.46
13.84
1.70 BSC
0.36
0.56
19.94
20.32
8.15
8.56
1.60
1.98
3.71
3.96
6.88
8.15
3.71
4.98
11.68
12.07
5°
CS8120
TO–220
FIVE LEAD
THA SUFFIX
CASE 314A–03
ISSUE E
–T–
B
–P–
Q
C
E
OPTIONAL
CHAMFER
A
U
F
L
G
5X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.
DIMENSION D INCLUDING PROTRUSION SHALL
NOT EXCEED 0.043 (1.092) MAXIMUM.
SEATING
PLANE
K
5X
J
S
D
0.014 (0.356)
T P
M
M
DIM
A
B
C
D
E
F
G
J
K
L
Q
S
U
INCHES
MIN
MAX
0.572
0.613
0.390
0.415
0.170
0.180
0.025
0.038
0.048
0.055
0.570
0.585
0.067 BSC
0.015
0.025
0.730
0.745
0.320
0.365
0.140
0.153
0.210
0.260
0.468
0.505
MILLIMETERS
MIN
MAX
14.529 15.570
9.906 10.541
4.318
4.572
0.635
0.965
1.219
1.397
14.478 14.859
1.702 BSC
0.381
0.635
18.542 18.923
8.128
9.271
3.556
3.886
5.334
6.604
11.888 12.827
D2PAK
5–PIN
DP SUFFIX
CASE 936F–01
ISSUE O
–T– SEATING
PLANE
B
M
C
E
A
1 2 3 4 5
K
F
G
D
H
5 PL
0.13 (0.005)
M
T B
M
J
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12
DIM
A
B
C
D
E
F
G
H
J
K
M
N
INCHES
MIN
MAX
0.326
0.336
0.396
0.406
0.170
0.180
0.026
0.035
0.045
0.055
0.090
0.110
0.067 BSC
0.098
0.108
0.018
0.025
0.204
0.214
0.055
0.066
0.000
0.004
MILLIMETERS
MIN
MAX
8.28
8.53
10.05
10.31
4.31
4.57
0.66
0.91
1.14
1.40
2.29
2.79
1.70 BSC
2.49
2.74
0.46
0.64
5.18
5.44
1.40
1.68
0.00
0.10
CS8120
SO–14
D SUFFIX
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
14
8
–B–
1
P 7 PL
0.25 (0.010)
7
G
B
M
M
F
R X 45 C
–T–
SEATING
PLANE
D 14 PL
0.25 (0.010)
M
T B
J
M
K
S
A
S
DIP–8
N SUFFIX
CASE 626–05
ISSUE L
8
–B–
4
DIM
A
B
C
D
F
G
H
J
K
L
M
N
F
–A–
NOTE 2
L
C
J
–T–
INCHES
MIN
MAX
0.337
0.344
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0
7
0.228
0.244
0.010
0.019
MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
--10
0.76
1.01
N
SEATING
PLANE
D
H
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
7
5.80
6.20
0.25
0.50
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5
1
DIM
A
B
C
D
F
G
J
K
M
P
R
M
K
G
0.13 (0.005)
M
T A
M
B
M
PACKAGE THERMAL DATA
Parameter
TO–220
FIVE LEAD
D2PAK
FIVE LEAD
DIP–8
SO–14
Unit
RΘJC
Typical
3.1
3.1
52
30
°C/W
RΘJA
Typical
50
10–50*
100
125
°C/W
* Depending on thermal properties of substrate. RΘJA = RΘJC + RΘCA
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13
INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
--10
0.030
0.040
CS8120
Notes
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14
CS8120
Notes
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15
CS8120
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CS8120/D