DEM-DDC101P-C EVALUATION FIXTURE ® FEATURES DESCRIPTION ● EASY INSTALLATION AND USE The DEM-DDC101P-C Evaluation Fixture is designed for ease of use when evaluating the DDC101 precision integrating analog-to-digital converter. The only additional equipment required to do a complete evaluation of the performance of the DDC101 is an IBM compatible PC with EGA or VGA graphics, a parallel interface port, a laser printer (optional), a ±5VDC power supply, and a signal source. ● KEYBOARD AND MOUSE CONTROL ● COLLECTS UP TO 32,768 CONVERSIONS ● RETRIEVES DATA INTO PC FOR ON-SCREEN, OSCILLOSCOPE-LIKE DISPLAYS ● PERFORMS FOURIER TRANSFORMS ON DATA ● AUTOMATICALLY DETERMINES FUNDAMENTAL FREQUENCY AND CALCULATES: SNR, SNDR, SFDR ● EVALUATES DIFFERENTIAL LINEARITY ● SAVES AND RETRIEVES DATA TO DISK ● SUPPORTS HP LASERJET FOR HARDCOPY AND GRAPHIC DISPLAYS International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • © 1993 Burr-Brown Corporation The DEM-DDC101P-C software is mouse compatible and retrieves the data from the DDC101 in an easy to read, graphical format on the screen. The DEMDDC101P-C Evaluation Fixture includes a PC Interface Board (with necessary parts), a DDC101 Board, a 25-pin ribbon connector and a 34-pin ribbon connector. The PC Interface Board makes timing commands and access to and from the DDC101 test board possible through the provided PC software. • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 LI-439A Printed in U.S.A. March, 1995 INSTALLATION tion completes the link to the DDC101 being tested, so that setup configurations can be sent to the DDC101 on the DUT Board and data retrieved to the PC. The data from the DDC101 being tested is also retrieved through this connection. PC directed timing control is handled by the PC Interface Board. Thirdly, insert appropriate resistors, shorting bars and/or capacitors in the Z1, Z2 and Z3 sockets on the DDC101 DUT Board as discussed in the THEORY OF OPERATION section of this data sheet. See Figure 2 for circuit connection details. DEM-DDC101P-C EVALUATION FIXTURE To install the DEM-DDC101P-C Evaluation Fixture, connect the 25-pin ribbon cable between one of the PC’s parallel ports and the DEM-DDC101P-C PC Interface Board, as shown in Figure 1. This establishes a communication link between the PC Interface Board and the PC. Next, connect the 34-pin ribbon cable between the PC Interface Board and the DDC101 DUT (Device Under Test) Board. This connec- 25 Pin Cable PC Interface Board Your PC Analog Input DUT Board Assembly 34 Pin Cable ±5VDC, ±35mA typ. +5VDC, 100mA typ. Power Supply FIGURE 1. DEM-DDC101 P-C Evaluation Fixture Connection Diagram. Z1 To input of DDC101 on DUT board Z2 Signal Source Z3 I1 Optional Capacitor I2 Optional Offset Current a) Circuit configuration for current inputs. Z1 IIN (MAX) Z2 Signal Source V1 To input of DDC101 on DUT board Z3 + V2 Optional Capacitor Optional Offset Voltage IIN (max) = Maximum allowable input current according to DDC101 setup code. b) Circuit configuration for voltage inputs. FIGURE 2. Suggested Input Configurations for Various Input Signals. ® DEM-DDC101P-C 2 Insert the 5-1/4" diskette into the PC and start the program by typing “DDC101”. If a DDC101.CFG file is not present in the PC directory, the software will default to the DDC101 setup configuration shown in Table I. When exiting the program, a new DDC101.CFG file will be generated to store the last program settings. FUNCTION Acquisition Time BITS DIGITAL WORD 0,1 00 INSTRUCTIONS Step 1. Pull down the Data menu with the mouse or by pressing Alt-D. Select Test Sine, which will open the software utility that verifies software functionality. Verify the data points to be tested as 4096 by clicking the “ok” box. The next screen will indicate that the data points/cycle will be equal to 25.60 and the phase (in degrees) is equal to 0. Continuing to the next screen, change the x-axis maximum value to 200 keeping the x-axis minimum equal to 0. Initiate the plot command. Click “Display” at the bottom of the screen, to leave the dots connected. The screen should look like Figure 3. Correlated double sampling, 0 initial data points # of Samples/Integration 2,3,4,5 0000 One sample per integration # of Integrations/ Conversion 0000 One integration per conversion 6,7,8,9 QUICK START The following quick tutorial is designed to help the user verify that the boards and software are functional and also help the user to become familiar with the software. This quick start-up should be performed after the DEMDDC101P-C is completely installed as discussed in the previous section. Input Signal Range 10 0 Unipolar input range Output Data Format 11 0 Binary Two’s Complement output format TABLE I. Software Default Setting for the DDC101 DUT Board Setup Code. Exit the graphics screen by using the “esc” key or “Cancel” at the bottom of the screen. The Test Sine mode is automatically turned off. Verify the power supplies are set for ±5VDC with a volt meter, then turn power supplies off and wire them into the terminal block. Insert the DDC101 to be tested in the zero insertion force socket on the DDC101 DUT Board. Turn on the ±5VDC power supplies and execute the Refresh command by pressing Alt-R on the PC keyboard. The Refresh command can also be found in the Setup pull-down menu. When removing or replacing a DDC101 from the DUT Board, the power to the boards should be turned off. The Refresh command should be used immediately after powerup, or if there is a power supply disturbance to the boards. If the Refresh command is not used, the data that is retrieved from the PC Interface Board will be invalid. Step 2. Pull down the Setup menu and select DDC Test Signal. Turn the DDC test signal “on”. This utility verifies that the DDC101 on-board test signal of 100nA is functional as well as the connection to the PC Interface Board and the PC. Pull down the Data menu and initiate the Retrieve command. Verify that the number of data points is 4096 and use auto-scaling for the data. The average Y-axis value should be approximately 0.2 ±20%. This can be found at the top of the graphics screen. The graphics screen should look like Figure 4. At this point it should be noted that the Y-axis reflects a relative reading based on the current full scale range. FIGURE 3. Time Plot of Numerical Sinusoidal Wave that is Generated by the PC Software. ® 3 DEM-DDC101P-C FIGURE 4. Time Plot of 100nA DC Test Signal Using Default Setting for the DDC101 DUT Board Described in Table I. FIGURE 5. Example of a Plot Screen with Using an Input Signal of 1Vp-p (1Hz), with Offset of 0.5V Via a 10MΩ Input Resistor. ® DEM-DDC101P-C 4 FIGURE 6. Frequency Plot Example of the Signal Shown in Figure 5 Using the FFT with a Blackman-Harris Window. Exit the graphics screen and pull down the Setup menu. Select DDC Test Signal and turn “off” the DDC test signal. 32,728 data words of the DDC101 serial output. The data stored is read via the PC’s parallel port. Step 3. Insert a 10MΩ resistor in the Z1 socket on the DDC101 DUT Board. Attach a 1Vp-p, VOFFSET = 0.5V, 1Hz signal into Input 1 on the DDC101 DUT Board. Retrieve the DDC101 output data by pulling down the Data menu and performing a Retrieve operation. Verify that the number of data points is 4096 and use auto-scaling for the data. The graphics screen should look like Figure 5. The PC Interface Board contains 32k of 24-bit RAM. This twenty-four bit word contains the DDC101’s serial data in bits 0 to 20 (LSB = bit 0). Bit 21 indicates the data format. Bits 22 and 23 contain the plus and minus overflow status. The data is read back as six four-bit nibbles. The DDC101 DUT Board contains a zero insertion force socket for one DDC101 to be tested, data buffers, 2.5V reference and decoupling capacitors (see Figure 8 for circuit diagram and Figures 13 and 14 for layout artwork). A DDC101 DUT board can be built and easily configured by the user for multiple DDC101 channels. The suggested layout and circuit diagram for the multiple channel DDC101 DUT Board is shown in Figures 9, 15 and 16. The multiple DDC101 DUT Board is not available from the factory. Initiate FFT calculations by selecting the “FFT” option at the bottom of the screen. Select the Blackman-Harris algorithm. When the calculations are complete, the screen should look like Figure 6. THEORY OF OPERATION Figure 2 shows several different input configurations that can be implemented on the DDC101 DUT Board. To use the DDC101 with a current input, a jumper should be connected across the appropriate Z1 or Z2 sockets. The DDC101 has one analog input. Two analog inputs are provided on the DDC101 DUT board to allow the user to sum two input signals, such as a DC offset and ac signal. The DDC101 can also convert voltage inputs by using a resistor in series with the voltage signal to create a current into the virtual ground of the analog input of the DDC101. For voltage input operation, the jumpers are replaced with the desired resistor. DEM-DDC101P-C EVALUATION FIXTURE The DEM-DDC101P-C Evaluation Fixture consists of two printed circuit boards, two flat cables (25-pin and 34-pin cables), and a diskette containing the evaluation software. The two printed circuit boards are the PC Interface Board and the DDC101 DUT Board. The PC Interface Board contains the circuitry used to control the DDC101 timing and the interface to the PC (see Figure 7 for circuit diagram and Figures 11 and 12 for layout artwork.). Full control of the DDC101(s) is accomplished via registers that contain information controlling clock rates, integration time, number of DDCs, readback delay, and mode control register. This board has the capacity to collect Grounding and shielding practices should be taken into consideration when designing the circuit layout for the ® 5 DEM-DDC101P-C ® DEM-DDC101P-C 6 FIGURE 7. Circuit Diagram of PC Interface Board. ® 7 DEM-DDC101P-C P2 3 7 9 OFLOW+ 19 GND –5VDC +5VDC 1 2 3 1 2 D3 IN5820 8 TEST 5 Y3 Y4 Y5 Y6 Y7 Y8 A4 A5 A6 A7 A8 D4 C8 IN5820 + 10µF at 20V 19 Y2 Y1 A3 EN2 EN1 1 U1 74ALS541 19 2A1 2A2 2A3 2A4 A2 A1 2Y1 2Y2 2Y3 2Y4 1Y4 1Y3 1A4 1A3 1Y1 1Y2 2G 1G 1 U2 74ALS244 1A2 1A1 –5V Analog 9 7 4 6 SET RESET 5 RD D/S 8 6 4 7 3 FDS R SYS 10 9 2 S CLK 11 12 13 14 15 16 17 18 5 D VAL OFLOW– 3 D OUT 22 20 8 21 6 D CLK D XMIT 4 2 23 D IN 24 25 26 27 28 29 30 31 32 33 34 FIGURE 8. Circuit Diagram of DDC-101 DUT Board. NC NC NC GND Test GND R_SET GND SET GND RD_D/S GND R_SYS GND FDS GND S_CLK GND OFLOW+ GND D_XMIT GND OFLOW– GND D_CLK GND D_VAL GND D_OUT GND D_IN GND NC NC P1 - R3 10kΩ + C9 10µF at 20V +5V Analog D2 IN5820 11 13 15 17 12 14 16 18 11 13 15 17 12 14 16 18 R8 10Ω R7 10Ω R1 10kΩ +5V Digital 26 25 24 23 9 10 11 19 18 17 16 20 12 13 +5V Digital R2 10kΩ TEST R SETUP S UP RD D/S R SYS FDS SCLK OFLOW+ OFLOW– D VALID D OUT D XMIT D CK D IN GNDD VDD VBUFD VREFIN VSPAS VSPA GNDA INPUT GNDA VSNA U3 DDC101P 15 14 28 27 8 7 6 5 4 3 2 1 C5 0.1µF C7 + 10µF R6 10Ω R4 1kΩ C4 0.1µF C3 0.1µF = Analog Ground = Digital Ground C6 + 10µF NC NC +5V Analog –5V Analog –5V Analog GND J2 BNC J1 BNC +5V Analog D1 –2.5 Ref R5 24.9kΩ Z3 Z2 Z1 ® DEM-DDC101P-C 8 + 10µF 10µF VDD 10Ω 2.5kΩ + Z2 BNC Z1 9 8 7 6 5 4 3 2 1 12 11 VDD D_IN D_CK CK FDS– GNDD D_OUT D_VALID– –OFLOW– +OFLOW– D_XMIT– RD_D/S SETUP R_SETUP– TEST VREFIN 13 14 15 16 17 18 19 20 21 22 23 24 10µF + VBUFD DDC101 R_SYS– VSPAS VSPA GNDA INP GNDA VSNA U1 0.1µF 10 BNC 0.1µF 10µF 0.1µF 1kΩ –2.5 Ref FIGURE 9. Suggested Circuit Diagram for a Multiple DDC101 DUT Board. +5V VSPA –5V VSNA Units U2 and U3 10kΩ +5V Digital 5kΩ Units U2 and U3 0.1µF BNC BNC 0.1µF 12 11 10 9 8 7 6 5 4 3 2 1 VDD D_IN D_CK CK FDS– 3 4 R_SYS 8 TEST 6 4 2 19 1 13 15 17 017 016 014 19 1 11 018 D_XMIT 8 D_CK D_IN 7 R_SET 9 6 SET RD_D/S 5 2 FDS 13 14 15 16 17 18 19 20 21 22 23 CK GNDD D_OUT D_VALID– –OFLOW– +OFLOW– D_XMIT– RD_D/S SETUP R_SETUP– TEST VREFIN 24 10µF VBUFD DDC101 R_SYS– VSPAS VSPA GNDA INP GNDA VSNA U4 0.1µF 2G 1G 2A4 2A3 2A2 2A1 1A4 1A3 1A2 1A1 G2 G1 A8 A7 A6 A5 A4 A3 A2 A1 74ALS244 74ALS541 10kΩ 2Y4 2Y3 2Y2 2Y1 1Y4 1Y3 1Y2 1Y1 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 3 5 7 9 D_OUT D_VAL OFLOW– OFLOW+ 12 I15 14 I10 16 NC 18 I11 11 NC 12 I22 13 I21 14 I20 15 I19 16 I7 17 I8 18 I9 +5V Digital 5kΩ TEST R_SET SET RD_D/S R_SYS FDS CK OFLOW+ D_XMIT OFLOW– D_CK D_VAL D_OUT D_IN NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 CON34 C1 DDC101. A PC trace shield around the input of the DDC101 (pin 3) is used to prevent increased bias current from parasitic resistances and prevent capacitively coupled noise. A filter resistor of 1kΩ and capacitor of 10µF is used from the –5V supply to VREFIN (pin 23 of the DDC101) to filter supply noise. The digital ground and analog ground plane are separated. 10µF by-pass capacitors are placed as close to the DDC101 supply pins as possible. voltage conversion, integration, input programmable gain amplification, A/D conversion, and digital filtering to produce precision, wide dynamic range results. During conversion, the input signal is collected on the internal integration capacitance for a user determined conversion period. The tracking logic updates the high resolution D/A converter at a 2MHz rate to keep the analog input at virtual ground. At the end of each integration cycle, the tracking logic’s output is oversampled by the digital filter. The digital filter passes a low noise, high resolution digital output to the serial I/O register. The PC Interface Board and DUT Board are separate to minimize digital noise effects on the DDC101 being tested, and to allow evaluation of user-designed boards with multiple DDCs (up to 32). The suggested layout and circuit diagram for the multiple channel DDC101 DUT Board is shown in Figures 9, 15 and 16. The command stream from the PC Interface Board is connected to the DDC101s in parallel, regardless of the configuration of the signal path of the multiple DDC101s. The input signal is integrated on the internal integration capacitor array for a user determined conversion period. During the conversion period, the tracking logic and high resolution D/A converter follows the input signal to create a digital result. The output digital filter of the DDC101 provides a low noise, high resolution output. The PC Interface Board returns the digital result from the DDC101 at a 1, 2, 4, or 8MHz data clock rate (as determined by the user through the Data Transfer menu.) For more detail about the DDC101, refer to the Product Data Sheet. DDC101 The DDC101 is a precision, wide dynamic range, charge digitizing A/D converter. A block diagram of the DDC101 is shown in Figure 10. The charge signal can originate directly from a current source (sensor) or from a voltage source via a user selected resistor. A patented delta modulation topology combines charge integration and digitization functions. Oversampling and digital filtering reduces system noise to low levels. Correlated double sampling captures and eliminates steady state and conversion cycle dependent offset and switching errors. The output of the DDC101 is a 21-bit digital word for both unipolar and bipolar input signals. The DDC101 combines the functions of current to SOFTWARE FEATURES The pop down menus are activated with the mouse or by typing the first letter of a desired category with the Alt key down. For instance, if the user wants to access the Setup menu, type “Alt-S”. Once the desired pop down menu appears on the screen, menu selections can be made with the up and down arrows and a carriage return or by typing the highlighted letter. The tab key and left and right arrows can Reset CDAC DDC Integrated Circuit Analog Input 3 VREF C-Int High Resolution Digital Out 20 Analog Common Tracking & Control Logic Digital Filter Oversampled Digital Out 11 12 System Clock Data Clock 16 Data Output Comparator 2, 4 Data In 10 Final Data Point Start (FDS) FIGURE 10. Block Diagram of DDC101. ® 9 DEM-DDC101P-C selected through this menu. Integration timing is directed to the DDC101 by strobing the FDS pin. Refer to the DDC101 product data sheet for more information. then be used to move inside the menu categories. The Refresh command, “Alt-R”, should be used immediately after power-up of the PC Interface Board and DUT Board or if there is a power supply disturbance to the boards. If the Refresh command is not used, data will be invalid. Data Transfer – The clock rate of data transfer from the DDC101 DUT Board to the PC Interface Board and number of DDC101s being tested is programmed through this area. The number of system clocks per integration cycle is equivalent to two clocks per µsec. The system clock transmit delay is especially useful when correlated double sampling is selected. The minimum number of system clock transmit delay should be set greater than the acquisition clock counts plus the sample/integration clock counts. For instance, if the acquisition time is set to 16 and the sample/integration clock is set to 32, the minimum number for system clock delay should be 48. If the system clock delay is set less than 48, the data retrieved from the DDC101 under test will contain additional noise. The three main pop down menus are Setup, Data and Analysis. The Setup menu allows the user to access the commands that will initialize the DDC101 to desired modes of operation, readback the DDC101 mode setting, control the conversion timing, control the data clock rate, set the multiple channel option, configure the differential linearity display, initiate the DC test signal, select the PC Interface Board port and printer port, and refresh (or reset) the setup conditions of the DDC101. The Data menu allows the user to initiate the data collection process, view the data graphically, save data to disk (in ASCII format), read data from disk, and perform a numerical functionality benchmark with software calculated sinusoidal wave data. It is possible to configure the DEM-DDC101P-C with up to 32 DDC101s. A suggested layout and circuit diagram is shown in Figures 9, 15 and 16. DUT boards with multiple DDC101s are not available from the factory. The command stream from the PC Interface Board is connected to the DDC101s in parallel, regardless of the configuration of the signal path of the multiple DDC101s. The Analysis menu allows the user to view data that has been read from a previously stored file or review data that was collected during the last test sequence. The Setup Menu The Setup menu allows the user to perform eight functions, all of which control the configuration of the test setup for the DDC101 test. The eight functions are : DL Display – The DL (differential linearity) Display determines the output wave form of the BNC DISPLAY OUTPUT connector on the PC Interface Board. This output can be connected to a digital or storage oscilloscope in the X-Y mode to see monotonicity and differential linearity of the DDC101 being tested. The BNC’s output should be connected to the Y-axis while the input signal is connected to the X-axis. The Major Carry Bit determines the output bit of the DDC101 that the hardware uses as the MSB for the output of the DL Display connector. The Bit Level determines the resolution of the DL display on the oscilloscope. The differential linearity errors and monotonicity performance of the DDC101 can quickly be seen on the graphics plot screen of the DEM-DDC101P-C software in the time domain, in most cases, making the DL Display option unnecessary. Setup DDC Readback DDC Timing Data Transfer DL Display DDC Test Signal PC Ports Refresh Each function is described below. DDC Setup – To configure the DDC101, the Setup Input pin of the DDC101 receives a serial 12-bit stream from the PC Interface Board. This is activated and controlled by the user in the Setup DDC section. This 12-bit word establishes the following: DDC Test Signal – A DC signal source that is approximately 100nA can be activated on the DDC101. This signal is generated by the DDC101 and is used to verify operation of the PC Interface Board and DDC101 DUT Board. Retrieve the data through the Data menu to see the measured results of the DDC Test Signal. The 100nA internal test signal will be summed with any external input signal. Acquisition Time (bits 11-10) Number of Samples per Integration (bits 9-6) Number of Integrations per Conversion (bits 5-2) Input Signal Range (unipolar or bipolar) (bit 1) Output Data Format (bit 0) PC Ports – The communication port for the PC Interface Board to the computer and the printer port is set in this area. The PC Interface must be connected to a parallel port. The graphs generated by the software can be sent to a printer. The output to the printer is a bit map. The HP LaserJet Series II is the recommended printer. A graph can also be stored as a file on the disk for future printing. The default print file name is DDC101.PRT. This can be changed by the user. Stored plot files are printed from the DOS environment by typing “Print <filename>”. Refer to the data sheet for details about DDC101 operation versus these setup codes. Readback DDC – When Readback DDC is selected, PC Interface board is instructed to read the DUT’s setup register and verify the state that the DDC101 is configured to. The digital code should match the 12-bit code in the Setup DDC section. Timing – The timing control that sets the DDC101 integration cycle can be programmed to be continuous or externally triggered. The length of the continuous integration cycle is ® DEM-DDC101P-C 10 All settings on the PC Port screen are saved after exiting the program except for the graphics print file name. presentation between dots and lines connecting the data points. The Scale option allows the user to set X-and Y-axis scales. The Prev and Next option (only available when multiple DDC101s are tested) allows the user to view each DDC101’s data output. The Cur1 and Cur2 activate cursors to determine exact values of data points as numerically displayed at the top of the screen. Movement of the cursors is effected by place and drag of the mouse or arrow and Ctrlarrow operation. An FFT option is available with seven windowing options. After FFT calculations are performed, the data is plotted in the frequency domain. An example of the frequency domain plot is shown in Figure 6. Finally, in the time display, if a DDC101 goes into an overflow condition, that test point is identified by red dots on the top and bottom X-axis. Refresh – The Refresh command should be used immediately after power-up or if there is a power supply disturbance to the boards. This command sends the setup information to the DDC101 on the DDC101 DUT Board. If the Refresh command is not used, the data that is collected during a test will be invalid. The Data Menu The Data menu allows the user to perform four functions, which control the collection, storage or retrieval of the data. The four functions are: Retrieve Save Read File Test Sine Save – This utility allows the user to save current test data and test setup in ASCII format on the PC disk. It is recommended that all data files be stored with a *.DDC format. Files stored through this utility cannot be printed into plots from the DOS environment, but can be loaded into spread sheet software with graphics utilities. If a printed plot is required, refer to the PRINTING PLOTS section of this data sheet for detailed instructions. Each function is described below. Retrieve – The output data from the DDC101 on the DUT Board is continuously read and that data stored in the RAM memory on the PC Interface Board. The Retrieve command brings the latest data from the PC Interface Board to PC RAM memory for graphical evaluation. The graphical evaluation tools are available in this section of the software after the retrieval process has been completed. Time plots and FFT analysis tools are also available in the analysis section. Read File – This utility allows the user to read files on the disk containing saved data and setup information. Test Sine – This utility is used to verify the software functionality. The software generates a numerical sinusoidal wave. Functionality of the graphical evaluation tools can be performed. The expected output for this test is shown in the time plot in Figure 3. The x-axis scale has been adjusted to a 0-200ms range and the display option set to connect the data points. The Retrieve screen, also initiated by pressing F1, allows the user to specify the number of data points that will be taken during the DDC101 test. The PC Interface Board RAM is able to store up to 32,768 of the most recently collected data points. If the user has configured more than one DDC101 to be tested in the Data Transfer screen, the maximum number of data points per device is divided by that number; ie., if four DDC101s are being tested the maximum number of data points for each DDC101 will be 32,768/4 or 8192 data points. If the user elects the “other” option to have a user selected number of data points collected that do not match the predefined menu options, FFT analysis is not available. The Analysis Menu The Analysis menu allows the user to perform three functions, all on existing data in the PC memory. The three functions are : Time Plots FFT Freq Plots After the data is collected, the user is given the option to select plot scales. Auto-scale will attempt to give an optimal data fit. To continue to the plot screen, click on “Plot” or press return. Each function is described below. Time Plots – The time plot utility gives a time representation of the data. The plot utility is the same utility described in the Retrieve section of this data sheet. An example of the plot screen in the time domain is shown in Figure 5. The title of the screen identifies the type of plot displayed (time or frequency), and if, multiple DDC101s were tested, which DDC101 data is shown. In the time domain, the X-axis unit of measure is time, the Y-axis is the normalized data output (1 = full-scale in a 20-bit system). Any data point falling between 0 and 1 on the Y-axis can be multiplied by 202 to calculate the decimal representation of the digital word. In the frequency domain, the X-axis unit of measure is frequency, the Y-axis is magnitude, where 0dB = full-scale. FFT – The FFT utility gives the options of a Hamming, Hanning, Blackman, Blackman-Harris, Continuous 5th Derivative, Triangle or Rectangle evaluation of the data. The Continuous 5th Derivative window is a cosine window derivative where: window = 0.3125 – 0.46875 cos(2πn/N) + 0.1875 cos(4πn/N) – 0.03125 cos(6πn/N) This window provides a good balance between spectral resolution and side lobe peaks. Along the bottom of the screen several options are available. If the data is displayed in the time domain, the Retrieve option allows the user to retrieve the most current data from the PC Interface Board. The Display option toggles the data The SNR and SINAD calculations include the ability for the user to define the spectral resolution of the fundamental and harmonics in the FFT. The user specifies the width of the ® 11 DEM-DDC101P-C spectral peaks (30 bins is the default resolution). Since the signal will have spectral spreading from the FFT, this allows correct measurement of the signal power while preventing the signal power from being mistaken as noise power. One half of the resolution term is used to skip past the FFT’s DC component when calculating SNR and SINAD. and printed using the print driver of the spread sheet software. The data format of the stored file is: 010000000001 ** SetUp Code 1000 ** Integration Timing 1 ** # of DDCs 2MHz ** Data Clock 128 ** Xmit Delay 17 ** DL Display Setting 1 ** Test Signal Status 4096 ** # of Data Points BLACKHARRIS ** FFT analysis tool 0 ** 0 ** DDC Data Overflow 0.00000000000000E+0000 0 1.21490089951635E–0001 0 2.35698368412841E–0001 0 3.35779477423330E–0001 0 4.15734806151249E–0001 0 4.70772032591412E–0001 0 4.97592363336025E–0001 0 4.94588254982318E–0001 0 • • • • • TROUBLE SHOOTING SUGGESTIONS If the data on the plot screen does not look believable, try the following suggestions: For the bandwidth selected, the SNR calculation is the rms signal power divided by the rms noise power. The signal power is the power in the bins between plus or minus 1/2 the spectral resolution from the fundamental bin. The noise power is summed as the noise in all another bins except for harmonics and the DC components’ bins. As for the fundamental, the spectral resolution term is used to skip the signal’s harmonics when summing noise power. The SNR noise power summation is “corrected” by multiplying the sum by the ratio of all bins in the bandwidth divided by the bins counted as noise without harmonics, DC or signal. For the bandwidth selected, the SINAD calculation is the rms square root of the signal power divided by the rms noise and distortion power. The signal power is the power in the bins between plus or minus 1/2 the spectral resolution from the fundamental bin. The noise and distortion power is the power in all other bins except the DC component’s bins. The SINAD noise and distortion power summation is “corrected” by multiplying the sum by the ratio of all bins in the bandwidth divided by the bins counted as noise and harmonics without DC or signal. The spurious free dynamic range (SFDR) is calculated as the magnitude of the fundamental bin divided by the peak magnitude of the next highest bin in the bandwidth selected (ignoring DC and the fundamental’s spectral spreading). For this measurement to be exactly correct and consistent, the fundamental should be located on bin exactly. That is, the input sine wave signal should be coherent with an exact integral number of cycles per time sample. 1. Verify that the desired set-up to the DDC101 has actually been sent to the DDC101 under test by using the Readback DDC utility in the Setup menu or by changing the setup and looking for output changes. 2. Verify that the boards and devices on the boards have power. Freq Plot – The frequency plot utility displays the last FFT representation of the data. 3. Double check the ribbon cable connections from the PC to the PC Interface Board and the PC Interface Board to the DDC101 DUT Board. EXIT – To exit the program, click on exit in the lower left corner of the screen or type “Alt-X”. The program will save the existing test configuration in a DDC101.CFG file. When the program is restarted, the last DDC101.CFG will be used to set the test conditions to previous settings. 4. If test results seem to be too noisy, check for EMI sources in the vicinity. Equipment such as computer CRTs, copy machines, etc. can create interference in the signal source. 5. Cycle the power supplies to both boards, then send a “Refresh” (Alt-R) command to the DDC101 DUT Board. PRINTING PLOTS Plots can be printed or sent to a disk file while in the graphics screen by pressing “Ctrl-Print Screen” keys. The output to the printer is a bit map. A graph can also be stored as a file on the disk for future printing. Stored plot files are printed from the DOS environment by typing “Print <filename>”. Refer to PC Ports section of this data sheet for detailed instructions on how to designate the file name. 6. Verify that the LEDs on the PC Interface Board are on. This verifies that the XILINX field programmable gate arrays have been confirmed. If LEDs are not on, recycle the supplies and verify power is on the board. If problem persists, contact the factory. 7. If output seems too noisy, verify that the hinged stand offs connecting the DDC101 DUT Board layers are secured tightly. If not, tighten stud screws that hold the DDC101 DUT board together to reconnect the ground connect between the layers. Data files can also be saved by using the Data menu and the Save File section. When files are saved in this manner, the saved files are stored on the disk in ASCII format. These files can be loaded into a spread sheet software. In the spread sheet format the data can be manipulated to desired formats 8. Make sure the proper PC ports have been selected through the Setup menu. 9. Verify that the input signal is correct with an oscilloscope. ® DEM-DDC101P-C 12 FIGURE 11. Silkscreen and Topside Layout of PC-Interface Board. ® 13 DEM-DDC101P-C FIGURE 12. Solder Side of PC-Interface Board. ® DEM-DDC101P-C 14 FIGURE 13. Silkscreen of DDC101 DUT Board. ® 15 DEM-DDC101P-C FIGURE 14. Component Side of DDC101 DUT Board. FIGURE 15. Solder Side of DDC101 DUT Board. ® DEM-DDC101P-C 16 FIGURE 16. Suggested Topside Layout for a Multiple Channel DDC101 DUT Board. FIGURE 17. Suggested Backside Layout for a Multiple Channel DDC101 DUT Board. ® 17 DEM-DDC101P-C PC Parallel Port DDC101 PC Interface Board J2 J1 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 Connector DB25 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 Connector DB25 FIGURE 18. Cable Connection Diagram for PC Interface Board to PC. DDC101 DUT Board J2 P1 34 22 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 CON34 CON34 FIGURE 19. Cable Connection Diagram for DDC101 DUT Board to PC Interface Board. ® DEM-DDC101P-C DDC101 PC Interface Board 18 NUMBER OF PARTS PER KIT PART NUMBER COMPANY PART DESCRIPTION TE06746 1 TE06746 Burr-Brown DDC101 Evaluation Fixture — PC Interface Board U1, U2 2 XC3042-70 Xilinx For U1, U2 2 LCS-84-02 ITT-Cannon C8, C10 2 503AHL Rogers U5, U6 2 XC1736A/D Xilinx U8, U9, U10 3 TC55257BSPL-10 Toshiba U12, U13 2 74ALS244 Buffers U3, U4, U11 3 74ALS541 Buffers For U5, U6 2 J1 1 86857-325 To connect PC to J1 1 8225-6060 3M 25-Pin Male “D” Wiremount Socket To connect PC to J1 1 8325-6060 3M 25-Pin Female “D” Wiremount Socket J2 1 3431-1202 3M 34-Pin Male Ribbon Connector To connect to DUT board 1 3414-6034 3M LED 1, 2 2 CMD5453 Chicago Miniature LED (2V, 20mA) U7 1 XO-54B 16MHz Dale 16 MHz Crystal P1, P2 2 227161-2 AMP RN1, RN2 2 CSC10A-01-103F PART IDENTIFICATION Programmable Gate Array 84-Pin PLCC Socket Decoupling Capacitors For Xilinx Gate Array Control Prom 8 x 32K Memory 8-Pin Socket (Single-Wide DIP) DuPont 25-Pin Male Right Angle “D” Connector With Hold Down Clip 34-Pin Wiremount Socket BNC Connectors (Right Angle, PC Mount) 10-Pin SIP Resistor Network (10k) (9R, 1C) R1 - R16 16 RN55C4751F 4.7k Resistor, 1% R17, R19, R22 - R25 6 RN55C1002F 10k Resistor, 1% R21 1 RN55C8062F 80.6k Resistor, 1% R20 1 RN55C4022F 40.2k Resistor, 1% R18 1 RN55C2002F 20k Resistor, 1% D1 1 IN5820 C2 - C7, C9, C11 - C14 11 CF114-104 1W Diode C1 1 T110B106K020AS Kermet P3 1 2SV-02 AUGAT/RDI Legs 8 313-6487-016 E.F. Johnson To attach legs 8 0.1 inch spacing 0.1µF Bypass Capacitors 10µF Polarized Capacitors, 20V, 10% Terminal Block 1/2 Inch Hex Spacer 6-32 Thread 0.25 Inch Round Head Screw 6-32 Thread TABLE II. Parts List for the PC Interface Board. ® 19 DEM-DDC101P-C PART IDENTIFICATION NUMBER OF PARTS PER KIT PART NUMBER COMPANY PART DESCRIPTION Burr-Brown DDC101 Evaluation Fixture–DUT Board TE06767 1 TE06767 U2 1 74ALS244 U1 1 74ALS541 P1 1 3431-1202 3M For Cable to P1 1 3414-6034 3M J1, J2 2 227161-2 AMP Buffer Buffer 34-Pin Male Ribbon Connector 34-Pin Wiremount Socket BNC Connector R6, R7, R8 3 RN55C10R0F Dale 10Ω Resistor, 1% R4 1 RN55C1001F Dale 1k Resisitor, 1% R1, R2, R3 3 RN55C1002F Dale 10k Resisitor, 1% R5 1 RN55C2492F Dale 24.9k Resistor, 1% D2, D3, D4 3 IN5820 C1, C2, C3, C4, C5 5 C330C104KR5CA 1W Diode 0.2 in spacing 0.1µF Bypass Capacitors Miniature Spring Sockets Z1, Z2, Z3 (two of each) 6 50863-5 AMP C9, C10 2 T110B106K020AS Kermet 10µF Polarized Capacitors, 20V C6, C7 2 T353E106K020AS Kermet 10µF Dipped Tantalum Capacitors, 20V, 10% P2 1 2SV-03 AUGAT/RDI Terminal Block D1 1 REF1004C-2.5 Burr-Brown SOIC 2.5V Reference 4 legs, 4 to separate bottom ground plane from DUT board 8 313-6487-008 E.F. Johnson To separate top ground 2 555-7003-044 Concord 3/4 Inch Hinged Spacer 6-32 Thread Plane from DUT board 2 542-7612 Concord 3/4 Inch Spacer 6-32 Thread To connect 3 boards 4 To connect top 2 U3 1 1/4 Inch Hex Spacer 6-32 Thread 0.75 Inch Round Head Screw 6-32 Thread 0.25 Inch Round Head Screw 6-32 Thread 223-3345 Textool 28-Pin Socket (Double-Wide DIP) TABLE III. Parts List for the DDC101 DUT Board. KEY RESULTING SOFTWARE ACTION Alt-A Pulls the Analysis menu down. Alt-D Pulls the Data menu down. Alt-R Refresh command to clear PC Interface Board RAM an to re-initialize the DDC101 under test. Alt-S Pulls the Setup menu down. Alt-T Takes existing data in PC RAM and plots in the time domain. Alt-F Takes existing data in PC RAM that had FFT calculations performed and plots in the frequency domain. Alt-X Exit program. Ctrl-Print Screen Used in graphics screen to print plot or save plot to specified file. Esc Escape from existing screen to high level. F1 Retrieve DDC101 test data from the PC Interface Board and store in PC RAM. F2 Save Retrieved data and software set up in disk file. F3 Load disk file containing data and software set up into software. F4 Turn PC numerically generated sinusoidal wave on to test software functionality. TAB Used to move cursor forward through screens. Shift-TAB Used to move cursor backwards through screens. PC SYSTEM REQUIREMENTS DOS-compatible EGA or VGA graphics Parallel interface port Mouse (optional) HP-Laser Jet II (only drive available with software) Math Co-processor (not required but improves computation speeds) TABLE V. PC System Requirements. TABLE IV. Listing of Key Stoke Commands for Software Operation Without a Mouse. ® DEM-DDC101P-C 20