Freescale Semiconductor, Inc. MOTOROLA Semiconductor Product Information DSP56012P/D (Motorola Order Number) Rev. 0, 09/98 Product Preview Freescale Semiconductor, Inc... DSP56012 24-Bit DVD Digital Signal Processor Motorola developed the DSP56012 as a high-performance programmable digital signal processor (DSP) for digital versatile disc (DVD), high-definition television (HDTV), and advanced set-top audio decoding. The DSP56012 is optimized with audio-specific peripherals and customized memory configuration, and may be programmed with Motorola’s certified software for Dolby AC3 5.1 Channel Surround, Dolby Pro Logic, and MPEG1 Layer 2. These applications use Motorola’s 24-bit DSP56000 architecture and are the highest quality solutions available. Flexible peripheral modules and interface software allow simple connection to a wide variety of video/ system decoders. In addition, the DSP56012 offers switchable memory space configuration, a large user-definable program ROM, two independent data RAMs and ROMs, a serial audio interface (SAI), Serial host interface (SHI), parallel host interface (HI) with Direct Memory Access (DMA) for communicating with other processors, dedicated I/O lines, on-chip phaselocked loop (PLL), On-Chip Emulation (OnCE™) port, and an on-chip digital audio transmitter (DAX). Figure 1 shows the functional blocks of the DSP56012. 8 15 Parallel Host Interface (HI) 5 9 Serial Audio Interface (SAI) General Purpose I/O (GPIO) Serial Host Interface (SHI) 16-Bit Bus 24-Bit Bus 2 Digital Audio Transmitter (DAX) Program Memory X Data Memory Y Data Memory Expansion Area 24-Bit DSP56000 Core GDB PDB XDB YDB Internal Data Bus Switch OnCETM Port Program Interrupt Controller Clock PLL Gen. 4 3 EXTAL PAB XAB YAB Address Generation Unit Program Program Decode Address Controller Generator Program Control Unit Data ALU 24 ¥ 24 + 56 Æ 56-Bit MAC Two 56-Bit Accumulators 4 IRQA, IRQB, NMI, RESET Figure 1 DSP56012 Block Diagram This document contains information on a new product. Specifications and information herein are subject to change without notice. © Motorola, Inc., 1998 For More Information On This Product, Go to: www.freescale.com AA1271 Freescale Semiconductor, Inc. Features Features Freescale Semiconductor, Inc... Digital Signal Processing Core • Efficient, object-code compatible, 24-bit DSP56000 family DSP engine • 47.5 million instructions per second (MIPS) with 21.05 ns instruction cycle at 95 MHz • Highly parallel instruction set with unique DSP addressing modes • Two 56-bit accumulators including extension byte • Parallel 24 × 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles) • Double precision 48 × 48-bit multiply with 96-bit result in 6 instruction cycles • 56-bit addition/subtraction in 1 instruction cycle • Fractional and integer arithmetic with support for multi-precision arithmetic • Hardware support for block-floating point fast fourier transforms (FFT) • Hardware nested DO loops • Zero-overhead fast interrupts (2 instruction cycles) • PLL-based clocking with a wide range of frequency multiplications (1 to 4096) and power saving clock divider (2i: i = 0 to 15), which reduces clock noise • Four 24-bit internal data buses and three 16-bit internal address buses for simultaneous accesses to one program and two data memories Memory • Modified Harvard architecture allows simultaneous access to program and data memories • 15360 × 24-bit on-chip program ROM1 • 4096 × 24-bit on-chip X data RAM and 3584 × 24-bit on-chip X data ROM1 • 4352 × 24-bit on-chip Y data RAM and 2048 × 24-bit on-chip Y data ROM1 • 256 × 24-bit on-chip program RAM and 32 × 24-bit bootstrap ROM • As much as 2304 × 24 bits of X and Y data RAM can be switched to program RAM, giving a total of 2560 × 24 bits of program RAM 1. 2 These ROMs may be factory programmed with data/program provided by the application developer. DSP56012 Product Brief For More Information On This Product, Go to: www.freescale.com Motorola Freescale Semiconductor, Inc. Peripheral and Support Circuits Table 1 lists the memory configurations of the DSP56012. Freescale Semiconductor, Inc... Table 1. DSP56012 Internal Memory Configurations Memory Type No Switch (PEA = 0, PEB = 0) Switch A (PEA = 1, PEB = 0) Switch B (PEA = 0, PEB = 1) Switch A+B (PEA = 1, PEB = 1) Program RAM 0.25K 1.0K 1.75K 2.5K X data RAM 4.0K 3.25K 3.25K 2.5K Y data RAM 4.25K 4.25K 3.5K 3.5K Program ROM 15K 15K 15K 15K X data ROM 3.5K 3.5K 3.5K 3.5K Y data ROM 2.0K 2.0K 2.0K 2.0K Peripheral and Support Circuits • • • • • • • • • • • • Motorola SAI includes: — Two receivers and three transmitters — Master or slave capability — I2S, Sony, and Matsushita audio protocol implementations — Two sets of SAI interrupt vectors SHI features: — Single master capability — SPI and I2C protocols — 10-word receive FIFO — Support for 8-, 16- and 24-bit words. Byte-wide parallel host interface with DMA support capable of reconfiguration as 15 general purpose input/output (GPIO) lines DAX features one serial transmitter capable of supporting S/PDIF, IEC958, CP-340, and AES/EBU formats. Eight dedicated, independent, programmable GPIO lines On-chip peripheral registers memory mapped in data memory space OnCE port for unobtrusive, processor speed-independent debugging Software programmable PLL-based frequency synthesizer for the core clock Power saving wait and stop modes Fully static, HCMOS design from specified operating frequency down to dc 100-pin plastic thin quad flat pack (TQFP) surface-mount package 5 V power supply DSP56012 Product Brief For More Information On This Product, Go to: www.freescale.com 3 Freescale Semiconductor, Inc. Documentation Table 2 lists the documents that provide a complete description of the DSP56012 and are required to design properly with the part. Documentation is available from a local Motorola distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center, or through the Motorola DSP home page on the Internet (the source for the latest information). Table 2. Additional DSP56012 Documentation Freescale Semiconductor, Inc... Document Name Description Order Number DSP56000 Family Manual Detailed description of the 56000-family architecture and the 24-bit core processor and instruction set DSP56KFAMUM/AD DSP56012 User’s Manual Detailed description of memory, peripherals, and interfaces DSP56012UM/AD DSP56012 Technical Data Electrical and timing specifications; pin and package descriptions DSP56012/D OnCE and Mfax are registered trademarks of Motorola, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. 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How to reach us: USA/Europe/Locations Not Listed: Motorola Literature Distribution P.O. Box 5405 Denver, Colorado 80217 1 (800) 441-2447 1 (303) 675-2140 Motorola Fax Back System (Mfax™): TOUCHTONE (602) 244-6609 1 (800) 774-1848 [email protected] [email protected] Asia/Pacific: Motorola Semiconductors H.K. Ltd. 8B Tai Ping Industrial Park 51 Ting Kok Road Tai Po, N.T., Hong Kong 852-26629298 Technical Resource Center: 1 (800) 521-6274 Japan: Nippon Motorola Ltd SPD, Strategic Planning Office141 4-32-1, Nishi-Gotanda Shinagawa-ku, Japan 81-3-5487-8488 Internet: http://www.motorola-dsp.com/ DSP Helpline For More Information On This Product, Go to: www.freescale.com