DATA SHEET 128M bits Mobile RAM EDL1216BASA (8M words × 16 bits) Description Pin Configurations The EDL1216BA is a 128M bits Mobile RAM organized as 2,097,152 words × 16 bits × 4 banks. The low power synchronous DRAMs achieved low power consumption and high-speed data transfer using the pipeline architecture. All inputs and outputs are synchronized with the positive edge of the clock. This product is packaged in 54-ball FBGA. /xxx indicates active low signal. Features • Low power supply VDD: 2.5V ± 0.2V VDDQ: 2.5V ± 0.2V • Wide temperature range (−25°C to 85°C) • Programmable partial self refresh • Programmable driver strength • Programmable temperature compensated self refresh (Option) • Deep power down mode • Small package (54-ball FBGA) • Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge • Pulsed interface • Possible to assert random column address in every cycle • Quad internal banks controlled by BA0 (A13) and BA1 (A12) • Byte control by LDQM and UDQM • Wrap sequence = Sequential / Interleave • /CAS latency (CL) = 2, 3 • Automatic precharge and controlled precharge • Auto refresh and self refresh • ×16 organization • 4,096 refresh cycles/64ms • Burst termination by Burst stop command and Precharge command Applications Mobile cellular handset, PDA, wireless PDA, handheld PC, home electronic appliances, and information appliances, etc. 1 2 3 4 5 6 7 8 9 DQ15 VSSQ VDDQ DQ0 VDD DQ14 DQ13 VDDQ VSSQ DQ2 DQ1 DQ12 DQ11 VSSQ VDDQ DQ4 DQ3 DQ10 DQ9 VDDQ VSSQ DQ6 DQ5 DQ8 NC VSS VDD LDQM DQ7 UDQM CLK CKE /CAS /RAS /WE NC A11 A9 BA0 BA1 /CS A8 A7 A6 A0 A1 A10 VSS A5 A4 A3 A2 VDD A VSS B C D E F G H J (Top view) A0 to A11 BA0, BA1 DQ0 to DQ15 CLK CKE /CS /RAS /CAS /WE UDQM LDQM VDD VSS VDDQ VSSQ NC Address inputs Bank Select Data inputs / outputs Clock input Clock enable Chip select Row address strobe Column address strobe Write enable Upper DQ mask enable Lower DQ mask enable Supply voltage Ground Supply voltage for DQ Ground for DQ No connect Document No. E0255E10 (Ver. 1.0) Date Published March 2002 (K) Japan URL: http://www.elpida.com Elpida Memory, Inc. 2002 EDL1216BASA Ordering Information Part number Organization (words × bits) Internal Banks Clock frequency MHz (max.) /CAS latency Package EDL1216BASA-75 8M × 16 4 133 3 54-ball FBGA Data Sheet E0255E10 (Ver. 1.0) 2 EDL1216BASA CONTENTS Description .................................................................................................................................................... 1 Features ........................................................................................................................................................ 1 Applications ................................................................................................................................................... 1 Pin Configurations ......................................................................................................................................... 1 Ordering Information ..................................................................................................................................... 2 Electrical Specifications................................................................................................................................. 4 Pin Function .................................................................................................................................................. 9 Command Operation ................................................................................................................................... 10 Truth Table .................................................................................................................................................. 14 Simplified State Diagram............................................................................................................................. 19 Initialization.................................................................................................................................................. 20 Programming Mode Registers .................................................................................................................... 20 Address Bits of Bank-Select and Precharge ............................................................................................... 24 Operation of the Mobile RAM...................................................................................................................... 25 Timing Waveforms ...................................................................................................................................... 33 Package Drawing ........................................................................................................................................ 56 Recommended Soldering Conditions.......................................................................................................... 57 Revision History .......................................................................................................................................... 60 Data Sheet E0255E10 (Ver. 1.0) 3 EDL1216BASA Electrical Specifications • All voltages are referenced to VSS (GND). • After power up, wait more than 200 µs and then, execute Power on sequence and two Auto Refresh before proper device operation is achieved. Absolute Maximum Ratings Parameter Symbol Rating Unit Voltage on any pin relative to VSS VT –0.5 to +3.6 V Supply voltage relative to VSS VDD, VDDQ –0.5 to +3.6 V Short circuit output current IOS 50 mA Power dissipation PD 1.0 W Operating ambient temperature TA –25 to +85 °C Storage temperature Tstg –55 to +125 °C Note Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions (TA = –25 to +85°°C) Parameter Symbol min. typ. max. Unit Supply voltage VDD 2.3 2.5 2.7 V VSS 0 0 0 V DQ Supply voltage VDDQ 2.3 2.5 2.7 V Input high voltage VIH 0.8 × VDDQ VDDQ + 0.3*1 V Input low voltage VIL –0.3*2 0.3 V Notes: 1. VIH (max.) = VDDQ + 1.5V (pulse width ≤ 5ns). 2. VIL (min.) = –1.5V (pulse width ≤ 5ns). Data Sheet E0255E10 (Ver. 1.0) 4 Notes EDL1216BASA DC Characteristics (TA = –25 to +85°°C, VDD = 2.5V ± 0.2V, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) Parameter /CAS latency Symbol Operating current (CL = 2) max. Unit Test condition Notes IDD1 65 mA 1 (CL = 3) IDD1 65 mA Burst length = 1 tRC ≥ tRC min., IO = 0mA, One bank active Standby current in power down IDD2P 1 mA CKE ≤ VIL max., tCK = 15ns Standby current in power down (input signal stable) IDD2PS 0.6 mA CKE ≤ VIL max., tCK = ∞ Standby current in non power down Standby current in non power down (input signal stable) Active standby current in power down Active standby current in power down (input signal stable) Active standby current in non power down Grade IDD2N 5.5 mA IDD2NS 2 mA IDD3P 1.5 mA IDD3PS 1 mA IDD3N Active standby current in non IDD3NS power down (input signal stable) Burst operating current IDD4 (CL = 2) 17 mA 12 mA 60 mA CKE ≥ VIH min., tCK = 15ns, /CS ≥ VIH min., Input signals are changed one time during 30ns. CKE ≥ VIH min., tCK = ∞, Input signals are stable. CKE ≤ VIL max., tCK = 15ns CKE ≤ VIL max., tCK = ∞ CKE ≥ VIH min., tCK = 15 ns, /CS ≥ VIH min., Input signals are changed one time during 30ns. CKE ≥ VIH min., tCK = ∞, Input signals are stable. tCK ≥ tCK min., 2 IOUT = 0mA, All banks active (CL = 3) IDD4 80 mA Refresh current (CL = 2) IDD5 155 mA (CL = 3) IDD5 155 mA Self refresh current PASR="000" (Full) IDD6 0.35 mA TCSR="00" (Ts*4 ≤ 70°C) 0.25 mA CKE ≤ 0.2V PASR="001" (2BK) tRC ≥ tRC min. PASR="010" (1BK) 0.18 mA PASR="101" (1/2 BK) 0.12 mA PASR="110" (1/4 BK) 0.09 mA 0.20 mA TCSR="01" (Ts*4 ≤ 45°C) PASR="001" (2BK) 0.15 mA CKE ≤ 0.2V PASR="010" (1BK) 0.10 mA PASR="101" (1/2 BK) 0.08 mA PASR="110" (1/4 BK) 0.07 mA 0.60 mA TCSR="11" (Ts*4 ≤ 85°C) CKE ≤ 0.2V PASR="000" (Full) PASR="000" (Full) IDD6 IDD6 PASR="001" (2BK) 0.50 mA PASR="010" (1BK) 0.43 mA PASR="101" (1/2 BK) 0.37 mA PASR="110" (1/4 BK) 0.34 mA 10 µA Standby current in deep power down mode IDD7 Data Sheet E0255E10 (Ver. 1.0) 5 CKE ≤ 0.2V 3 EDL1216BASA Notes: 1. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, IDD1 is measured condition that addresses are changed only one time during tCK (min.). 2. IDD4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, IDD4 is measured condition that addresses are changed only one time during tCK (min.). 3. IDD5 is measured on condition that addresses are changed only one time during tCK (min.). 4. Ts is surface temperature. DC Characteristics 2 (TA = –25 to +85°°C, VDD = 2.5V ± 0.2V, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) Parameter Symbol min. max. Unit Test condition Notes Input leakage current ILI –1.0 1.0 µA 0 ≤ VIN ≤ VDDQ Output leakage current ILO –1.5 1.5 µA 0 ≤ VOUT ≤ VDDQ, DQ = disable Output high voltage VOH VDDQ – 0.2 — V IOH = –0.1 mA Output low voltage VOL — 0.2 V IOL = 0.1 mA Pin Capacitance (TA = 25°C, f = 1MHz) Parameter Symbol Input capacitance Data input/output capacitance Pins min. Typ max. Unit CI1 CLK 2.5 — 3.5 pF CI2 Address, CKE, /CS, /RAS, /CAS, /WE, UDQM, LDQM 2.5 — 3.8 pF CI/O DQ 4 — 6.5 pF Data Sheet E0255E10 (Ver. 1.0) 6 Notes EDL1216BASA AC Characteristics (TA = –25 to +85°°C, VDD = 2.5V ± 0.2V, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) Test Conditions • AC high level input voltage / low level input voltage: 2.3 / 0.2V • Input timing measurement reference level: 1.25V • Transition time (Input rise and fall time): 1ns • Output timing measurement reference level: 1.25V tCK tCH CLK 2.3V 1.25V 0.2V tSETUP tHOLD Input 2.3V 1.25V 0.2V tAC tOH Output Data Sheet E0255E10 (Ver. 1.0) 7 tCL EDL1216BASA Synchronous Characteristics Parameter Symbol min. max. Unit Clock cycle time (CL= 2) tCK2 10 — ns (CL= 3) tCK3 7.5 — ns Access time from CLK (CL= 2) tAC2 — 6 ns 1 (CL= 3) tAC3 — 5.4 ns 1 CLK high level width tCH 2.5 — ns CLK low level width tCL 2.5 — ns Data-out hold time tOH 2.5 — ns Data-out low-impedance time tLZ 0 — ns Data-out high-impedance time (CL= 2) tHZ2 2.5 6 ns (CL= 3) tHZ3 2.5 5.4 ns Data-in setup time tDS 1.5 — ns Data-in hold time tDH 0.8 — ns Address setup time tAS 1.5 — ns Address hold time tAH 0.8 — ns CKE setup time tCKS 1.5 — ns CKE hold time tCKH 0.8 — ns CKE setup time (Power down exit) tCKSP 1.5 — ns tCMS 1.5 — ns tCMH 0.8 — ns Command (/CS, /RAS, /CAS, /WE, UDQM, LDQM) setup time Command (/CS, /RAS, /CAS, /WE, UDQM, LDQM) hold time Note 1 Note: 1. Output load. Z = 50 Ω Output 30 pF Output load Asynchronous Characteristics Parameter Symbol ACT to REF/ACT command period (operation) tRC min. max. Unit 67.5 ns ACT to REF/ACT command period (refresh) tRC1 67.5 ns ACT to PRE command period tRAS 45 120000 ns PRE to ACT command period tRP 20 ns Delay time ACT to READ/WRITE command tRCD 20 ns ACT (one) to ACT (another) command period tRRD 15 ns Data-in to PRE command period tDPL 15 ns Data-in to ACT (REF) command period (Auto precharge) (CL = 2) TDAL2 2CLK + 20 ns (CL = 3) TDAL3 2CLK + 20 ns CLK Mode register set cycle time tRSC 2 Transition time tT 0.5 30 ns Refresh time (4,096 refresh cycles) tREF 64 ms Data Sheet E0255E10 (Ver. 1.0) 8 Notes EDL1216BASA Pin Function CLK (input pin) CLK is the master clock input. Other inputs signals are referenced to the CLK rising edge. CKE (input pins) CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge is valid; otherwise it is invalid. If the CLK rising edge is invalid, the internal clock is not issued and the Mobile RAM suspends operation. When the Mobile RAM is not in burst mode and CKE is negated, the device enters power down mode. During power down mode, CKE must remain low. /CS (input pins) /CS low starts the command input cycle. When /CS is high, commands are ignored but operations continue. /RAS, /CAS, and /WE (input pins) /RAS, /CAS and /WE have the same symbols on conventional DRAM but different functions. For details, refer to the command table. A0 to A11 (input pins) Row Address is determined by A0 to A11 at the CLK (clock) rising edge in the active command cycle. It does not depend on the bit organization. Column Address is determined by A0 to 8 at the CLK rising edge in the read or write command cycle. A10 defines the precharge mode. When A10 is high in the precharge command cycle, all banks are precharged; when A10 is low, only the bank selected by BA0(A13) and BA1(A12) is precharged. When A10 is high in read or write command cycle, the precharge starts automatically after the burst access. BA0 and BA1 (input pin) BA0(A13) and BA1(A12) are bank select signal. (See Bank Select Signal Table) [Bank Select Signal Table] BA0 BA1 Bank A L L Bank B H L Bank C L H Bank D H H Remark: H: VIH. L: VIL. ×: VIH or VIL UDQM and LDQM (input pins) UDQM and LDQM control upper byte and lower byte I/O buffers, respectively. In read mode, DQM controls the output buffers like a conventional /OE pin. DQM high and DQM low turn the output buffers off and on, respectively. The DQM latency for the read is two clocks. In write mode, DQM controls the word mask. Input data is written to the memory cell if DQM is low but not if DQM is high. The DQM latency for the write is zero. DQ0 to DQ15 (input/output pins) DQ pins have the same function as I/O pins on a conventional DRAM. VDD, VSS, VDDQ, VSSQ (Power supply) VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers. Data Sheet E0255E10 (Ver. 1.0) 9 EDL1216BASA Command Operation Extended Mode register set command (/CS, /RAS, /CAS, /WE, BA0 = Low, BA1 = High) The Mobile RAM has an extended mode register that defines low power functions. In this command, A0 through A11 are the data input pins. After power on, the extended mode register set command must be executed to fix low power functions. The extended mode register can be set only when all banks are in idle state. During tRSC following this command, the Mobile RAM can not accept any other commands. CLK CKE H /CS /RAS /CAS /WE BA0(A13) BA1(A12) A10 Add Extended Mode register set command Mode register set command (/CS, /RAS, /CAS, /WE, BA0, BA1 = Low) The Mobile RAM has a mode register that defines how the device operates. In this command, A0 through A11 are the data input pins. After power on, the mode register set command must be executed to initialize the device. The mode register can be set only when all banks are in idle state. During tRSC following this command, the Mobile RAM cannot accept any other commands. CLK CKE H /CS /RAS /CAS /WE BA0(A13) BA1(A12) A10 Add Mode register set command Activate command (/CS, /RAS = Low, /CAS, /WE = High) The Mobile RAM has four banks, each with 4,096 rows. This command activates the bank selected by BA0 (A13) and BA1 (A12) and a row address selected by A0 through A11. This command corresponds to a conventional DRAM's /RAS falling. CLK CKE H /CS /RAS /CAS /WE BA0(A13), BA1(A12) A10 Row Add Row Activate command Data Sheet E0255E10 (Ver. 1.0) 10 EDL1216BASA Precharge command (/CS, /RAS, /WE = Low, /CAS = High) This command begins precharge operation of the bank selected by BA0 (A13) and BA1(A12). When A10 is High, all banks are precharged, regardless of BA0 (A13) and BA1 (A12). When A10 is Low, only the bank selected by BA0 (A13) and BA1 (A12) is precharged. After this command, the Mobile RAM can’t accept the activate command to the precharging bank during tRP (precharge to activate command period). This command corresponds to a conventional DRAM’s /RAS rising. CLK CKE H /CS /RAS /CAS /WE BA0(A13), BA1(A12) A10 (Precharge select) Add Precharge command Write command (/CS, /CAS, /WE = Low, /RAS = High) This command sets the burst start address given by the column address to begin the burst write operation. The first write data in burst mode can input with this command with subsequent data on following clocks. CLK CKE H /CS /RAS /CAS /WE BA0(A13), BA1(A12) A10 Add Col. Write command Read command (/CS, /CAS = Low, /RAS, /WE = High) Read data is available after /CAS latency requirements have been met. This command sets the burst start address given by the column address. CLK CKE H /CS /RAS /CAS /WE BA0(A13), BA1(A12) A10 Add Col. Read command Data Sheet E0255E10 (Ver. 1.0) 11 EDL1216BASA Auto refresh command (/CS, /RAS, /CAS = Low, /WE, CKE = High) This command is a request to begin the Auto refresh operation. The refresh address is generated internally. Before executing Auto refresh, all banks must be precharged. After this cycle, all banks will be in the idle (precharged) state and ready for a row activate command. During tRC1 period (from refresh command to refresh or activate command), the Mobile RAM cannot accept any other command CLK CKE H /CS /RAS /CAS /WE BA0(A13), BA1(A12) A10 Add Auto refresh command Self refresh entry command (/CS, /RAS, /CAS, CKE = Low, /WE = High) After the command execution, self refresh operation continues while CKE remains low. When CKE goes high, the Mobile RAM exits the self refresh mode. During self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control. Before executing self refresh, all banks must be precharged. CLK CKE /CS /RAS /CAS /WE BA0(A13), BA1(A12) A10 Add Self refresh entry command Power down entry command (/CS, CKE = Low, /RAS, /CAS, /WE = High) After the command execution, power down mode continues while CKE remains low. When CKE goes high, the Mobile RAM exits the power down mode. Before executing power down, all banks must be precharged. CLK CKE /CS /RAS /CAS /WE BA0(A13), BA1(A12) A10 Add Power down entry command Data Sheet E0255E10 (Ver. 1.0) 12 EDL1216BASA Deep power down entry command( /CS, CKE, /WE = Low, /RAS, /CAS = High) After the command execution, deep power down mode continues while CKE remains low. When CKE goes high, the Mobile RAM exits the deep power down mode. Before executing deep power down, all banks must be precharged. CLK CKE /CS /RAS /CAS /WE BA0(A13), BA1(A12) A10 Add Deep power down entry command Burst stop command (/CS = /WE = Low, /RAS, /CAS = High) This command can stop the current burst operation. CLK CKE H /CS /RAS /CAS /WE BA0(A13), BA1(A12) A10 Add Burst stop command No operation (/CS = Low, /RAS, /CAS, /WE = High) This command is not an execution command. No operations begin or terminate by this command. CLK CKE H /CS /RAS /CAS /WE BA0(A13), BA1(A12) A10 Add No operation Data Sheet E0255E10 (Ver. 1.0) 13 EDL1216BASA Truth Table Command Truth Table CKE Function Symbol Device deselect No operation Burst stop A11, n–1 n /CS /RAS /CAS /WE BA1 BA0 A10 A9 - A0 DESL H × H × × × × × × × NOP H × L H H H × × × × BST H H L H H L × × × × Read READ H × L H L H V V L V Read with auto precharge READA H × L H L H V V H V Write WRIT H × L H L L V V L V Write with auto precharge WRITA H × L H L L V V H V Bank activate ACT H × L L H H V V V V Precharge select bank PRE H × L L H L V V L × Precharge all banks PALL H × L L H L × × H × Mode register set MRS H × L L L L L L L V Extended mode register set EMRS H × L L L L H L L V Remark: H: VIH. L: VIL. ×: VIH or VIL, V = Valid data DQM Truth Table CKE DQM Function Symbol n–1 n U L Data write / output enable ENB H × L L Data mask / output disable MASK H × H H Upper byte write enable / output enable ENBU H × L × Lower byte write enable / output enable ENBL H × × L Upper byte write inhibit / output disable MASKU H × H × Lower byte write inhibit / output disable MASKL H × × H Remark: H: VIH. L: VIL. ×: VIH or VIL CKE Truth Table CKE Current state Function n–1 n /CS /RAS /CAS /WE Address Activating Clock suspend mode entry H L × × × × × Any Clock suspend mode L L × × × × × Clock suspend Clock suspend mode exit L H × × × × × Idle Auto refresh command H H L L L H × Idle Self refresh entry SELF H L L L L H × Idle Power down entry PD H L L H H H × H L H × × × × Idle Deep power down entry DPD H L L H H L × Self refresh Self refresh exit Power down Power down exit Deep power down Deep power down exit D d Symbol REF L H L H H H × L H H × × × × L H L H H H × L H H × × × × L H × × × × × Remark: H: VIH. L: VIL. ×: VIH or VIL Data Sheet E0255E10 (Ver. 1.0) 14 EDL1216BASA Function Truth Table Current state /CS /RAS /CAS /WE Address Command Action Idle H × × × × DESL Nop L H H H × NOP Nop Row active Read Write Notes L H H L × BST Nop L H L H BA, CA, A10 READ/READA ILLEGAL 2 L H L L BA, CA, A10 WRIT/ WRITA ILLEGAL 2 L L H H BA, RA ACT → Row activating L L H L BA, A10 PRE/PALL Nop L L L H × REF Auto refresh L L L L OC, BA1= L MRS Mode register set L L L L OC, BA1= H EMRS Extended mode register set H × × × × DESL Nop L H H H × NOP Nop L H H L × BST Nop L H L H BA, CA, A10 READ/READA Begin read 3 L H L L BA, CA, A10 WRIT/ WRITA Begin write 3 L L H H BA, RA ACT ILLEGAL 2 L L H L BA, A10 PRE/PALL Precharge/Precharge all banks 4 L L L H × REF ILLEGAL L L L L OC, BA MRS/EMRS ILLEGAL H × × × × DESL Continue burst to end → Row active L H H H × NOP Continue burst to end → Row active L H H L × BST Burst stop → Row active L H L H BA, CA, A10 READ/READA Terminate burst, begin new read 5 L H L L BA, CA, A10 WRIT/WRITA Terminate burst, begin write 5, 6 L L H H BA, RA ACT ILLEGAL 2 L L H L BA, A10 PRE/PALL Terminate burst → Precharging L L L H × REF ILLEGAL L L L L OC, BA MRS/EMRS ILLEGAL H × × × × DESL Continue burst to end → Write recovering L H H H × NOP Continue burst to end → Write recovering L H H L × BST Burst stop → Row active L H L H BA, CA, A10 READ/READA Terminate burst, start read : Determine AP 5, 6 L H L L BA, CA, A10 WRIT/WRITA Terminate burst, new write : Determine AP 5 L L H H BA, RA ACT ILLEGAL 2 L L H L BA, A10 PRE/PALL Terminate burst → Precharging 7 L L L H × REF ILLEGAL L L L L OC, BA MRS/EMRS ILLEGAL Data Sheet E0255E10 (Ver. 1.0) 15 EDL1216BASA Current state /CS /RAS /CAS /WE Address Command Action Read with auto H × × × × DESL Continue burst to end → Precharging precharge L H H H × NOP Continue burst to end → Precharging Write with auto precharge Precharging Row activating Notes L H H L × BST ILLEGAL L H L H BA, CA, A10 READ/READA ILLEGAL 2 L H L L BA, CA, A10 WRIT/ WRITA ILLEGAL 2 L L H H BA, RA ACT ILLEGAL 2 L L H L BA, A10 PRE/PALL ILLEGAL 2 L L L H × REF ILLEGAL L L L L OC, BA MRS/EMRS ILLEGAL H × × × × DESL Continue burst to end → Write recovering with auto precharge L H H H × NOP Continue burst to end → Write recovering with auto precharge L H H L × BST ILLEGAL L H L H BA, CA, A10 READ/READA ILLEGAL 2 L H L L BA, CA, A10 WRIT/ WRITA ILLEGAL 2 L L H H BA, RA ACT ILLEGAL 2 L L H L BA, A10 PRE/PALL ILLEGAL 2 L L L H × REF ILLEGAL L L L L OC, BA MRS/EMRS ILLEGAL H × × × × DESL Nop → Enter idle after tRP L H H H × NOP Nop → Enter idle after tRP L H H L × BST ILLEGAL L H L H BA, CA, A10 READ/READA ILLEGAL 2 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 2 L L H H BA, RA ACT ILLEGAL 2 L L H L BA, A10 PRE/PALL Nop → Enter idle after tRP L L L H × REF ILLEGAL L L L L OC, BA MRS/EMRS ILLEGAL H × × × × DESL Nop → Enter bank active after tRCD L H H H × NOP Nop → Enter bank active after tRCD L H H L × BST ILLEGAL L H L H BA, CA, A10 READ/READA ILLEGAL 2 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 2 L L H H BA, RA ACT ILLEGAL 2, 8 L L H L BA, A10 PRE/PALL ILLEGAL 2 L L L H × REF ILLEGAL L L L L OC, BA MRS/EMRS ILLEGAL Data Sheet E0255E10 (Ver. 1.0) 16 EDL1216BASA Current state Write recovering /CS /RAS /CAS /WE Address Command Action H × × × × DESL Nop → Enter row active after tDPL L H H H × NOP Nop → Enter row active after tDPL L H H L × BST Nop → Enter row active after tDPL L H L H BA, CA, A10 READ/READA Begin read Begin new write Notes 6 L H L L BA, CA, A10 WRIT/ WRITA L L H H BA, RA ACT ILLEGAL 2 L L H L BA, A10 PRE/PALL ILLEGAL 2 L L L H × REF ILLEGAL L L L L OC, BA MRS/EMRS ILLEGAL Write recovering H × × × × DESL Nop → Enter precharge after tDPL with auto L H H H × NOP Nop → Enter precharge after tDPL precharge L H H L × BST Nop → Enter row active after tDPL L H L H BA, CA, A10 READ/READA ILLEGAL L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 2, 6 L L H H BA, RA ACT ILLEGAL 2 L L H L BA, A10 PRE/PALL ILLEGAL 2 L L L H × REF ILLEGAL L L L L OC, BA MRS/EMRS ILLEGAL H × × × × DESL Nop → Enter idle after tRC1 L H H H × NOP Nop → Enter idle after tRC1 Refresh L H H L × BST Nop → Enter idle after tRC1 L H L H BA, CA, A10 READ/READA ILLEGAL L H L L BA, CA, A10 WRIT/WRITA ILLEGAL L L H H BA, RA ACT ILLEGAL L L H L BA, A10 PRE/PALL ILLEGAL L L L H × REF ILLEGAL L L L L OC, BA MRS/EMRS ILLEGAL Mode register H × × × × DESL Nop → Enter idle after tRSC accessing L H H H × NOP Nop → Enter idle after tRSC L H H L × BST Nop → Enter idle after tRSC L H L H BA, CA, A10 READ/READA ILLEGAL L H L L BA, CA, A10 WRIT/WRITA ILLEGAL L L H H BA, RA ACT ILLEGAL L L H L BA, A10 PRE/PALL ILLEGAL L L L H × REF ILLEGAL L L L L OC, BA MRS/EMRS ILLEGAL Data Sheet E0255E10 (Ver. 1.0) 17 EDL1216BASA Current state /CS /RAS /CAS /WE Address Command Action Extended mode H × × × × DESL Nop → Enter idle after tRSC register L H H H × NOP Nop → Enter idle after tRSC accessing L H H L × BST Nop → Enter idle after tRSC L H L H BA, CA, A10 READ/READA ILLEGAL L H L L BA, CA, A10 WRIT/WRITA ILLEGAL L L H H BA, RA ACT ILLEGAL L L H L BA, A10 PRE/PALL ILLEGAL L L L H × REF ILLEGAL L L L L OC, BA0,BA1 MRS/EMRS Notes ILLEGAL Remark: H: VIH. L: VIL. ×: VIH or VIL, V = Valid data BA: Bank Address, CA: Column Address, RA: Row Address, OC: Op-Code Notes: 1. All entries assume that CKE is active (CKEn-1=CKEn=H). 2. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 3. Illegal if tRCD is not satisfied. 4. Illegal if tRAS is not satisfied. 5. Must satisfy burst interrupt condition. 6. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 7. Must mask preceding data which don't satisfy tDPL. 8. Illegal if tRRD is not satisfied. Data Sheet E0255E10 (Ver. 1.0) 18 EDL1216BASA Simplified State Diagram Extended Mode Register Set Self Refresh LF EM SE RS xit Fe L SE MRS Mode Register Set REF IDLE D DP CK E it ex ACT PD CBR (Auto) Refresh D CK E Power Down Deep Power Down CKE ROW ACTIVE CKE ST B e h arg ch pre Wr CKE Read WRITE CKE CKE WRITEA CKE Precharge PR E( Pre cha rge ter min atio n) Write CKE POWER ON Read READ n) atio min ter rge cha Pre E( PR WRITEA SUSPEND Au WRITE SUSPEND to ite wit W T ad h wit e ad rg Re cha pre to PRE r Write BS Re Au ite Active Power Down CKE CKE READA CKE READ SUSPEND READA SUSPEND Precharge Automatic sequence Manual input Data Sheet E0255E10 (Ver. 1.0) 19 EDL1216BASA Initialization The synchronous DRAM is initialized in the power-on sequence according to the following. (1) To stabilize internal circuits, when power is applied, a 200 µs or longer pause must precede any signal toggling. (2) After the pause, all banks must be precharged using the Precharge command (The Precharge all banks command is convenient). (3) Once the precharge is completed and the minimum tRP is satisfied, two or more Auto refresh must be performed. (4) Both the mode register and the extended mode register must be programmed. After the mode register set cycle or the extended mode register set cycle, tRSC (2 CLK minimum) pause must be satisfied. Remarks: 1 The sequence of Auto refresh, mode register programming and extended mode register programming above may be transposed. 2 CKE and DQM must be held high until the Precharge command is issued to ensure data-bus High-Z. Programming Mode Registers The mode register and extended mode register are programmed by the Mode register set command and Extended mode register command, respectively using address bits A11 through A0, BA0 (A13) and BA1 (A12) as data inputs. The registers retain data until they are re-programmed, or the device enters into the deep power down or the device loses power. Mode register The mode register has three fields; Options /CAS latency Wrap type Burst length : : : : A11 through A7 A6 through A4 A3 A2 through A0 Following mode register programming, no command can be issued before at least 2 CLK have elapsed. /CAS Latency /CAS latency is the most critical of the parameters being set. It tells the device how many clocks must elapse before the data will be available. The value is determined by the frequency of the clock and the speed grade of the device. Burst Length Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is completed, the output bus will become High-Z. The burst length is programmable as 1, 2, 4, 8 or full page. Wrap Type (Burst Sequence) The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either “Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system. Some microprocessor cache systems are optimized for sequential addressing and others for interleaved addressing. “Burst Length Sequence” shows the addressing sequence for each burst length using them. Both sequences support bursts of 1, 2, 4 and 8. Additionally, sequence supports the full page length. Data Sheet E0255E10 (Ver. 1.0) 20 EDL1216BASA Extended Mode Register The extended mode register has four fields; Options : A11 through A7 Drive Strength : A6 through A5 Temperature Compensated Self Refresh : A4 through A3 Partial Array Self Refresh : A2 through A0 Following extended mode register programming, no command can be issued before at least 2 CLK have elapsed. Drive Strength Driving capability of data output drivers. Temperature Compensated Self Refresh Programmable refresh rate for self refresh mode to allow the system to control power as a function of temperature. Partial Array Self Refresh Memory array size to be refreshed during self refresh operation is programmable in order to reduce power. Data outside the defined area will not be retained during self refresh. Data Sheet E0255E10 (Ver. 1.0) 21 EDL1216BASA Mode Register Definition BA0 BA1 (A13) (A12) A11 0 0 0 A10 A9 A8 A7 0 0 0 0 Latency mode BA0 BA1 (A13) (A12) A11 0 1 0 Drive Strength Bits6-4 000 001 010 011 100 101 110 111 A10 A9 A8 A7 0 0 0 0 Bits6-5 00 01 10 11 A6 A5 A4 LTMODE A3 A2 WT A1 Mode Register Set /CAS latency R R 2 3 R R R R A6 A5 DS A4 A3 A0 BL A2 TCSR A1 PASR Strength Normal 1/2 strength 1/4 strength R Burst length Bits2-0 000 001 010 011 100 101 110 111 Wrap type 0 1 22 WT = 1 1 2 4 8 R R R R Sequential Interleave A0 Extended Mode Register Set Partial Array Self Refresh Bits2-0 000 001 010 011 100 101 110 111 Refresh Array All banks Bank A & Bank B (BA1=0) Bank A (BA0=BA1=0) R R 1/2 of Bank A (RA11=0) 1/4 of Bank A (RA11=RA10=0) R Temprature Compensated Self Refresh Bits4-3 00 01 10 11 Max Temperature 70°C 45°C 15°C 85°C Remark R : Reserved Data Sheet E0255E10 (Ver. 1.0) WT = 0 1 2 4 8 R R R Full page EDL1216BASA Burst Length and Sequence [Burst of Two] Starting address (column address A0, binary) Sequential addressing sequence (decimal) Interleave addressing sequence (decimal) 0 0, 1 0, 1 1 1, 0 1, 0 Starting address (column address A1−A0, binary) Sequential addressing sequence (decimal) Interleave addressing sequence (decimal) 00 0, 1, 2, 3 0, 1, 2, 3 01 1, 2, 3, 0 1, 0, 3, 2 10 2, 3, 0, 1 2, 3, 0, 1 11 3, 0, 1, 2 3, 2, 1, 0 Starting address (column address A2−A0, binary) Sequential addressing sequence (decimal) Interleave addressing sequence (decimal) 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 [Burst of Four] [Burst of Eight] Full page burst is an extension of the above tables of sequential addressing, with the length being 512. Data Sheet E0255E10 (Ver. 1.0) 23 EDL1216BASA Address Bits of Bank-Select and Precharge Row A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA1 BA0 (A12) (A13) (Activate command) A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA1(A12) BA0(A13) Result Select Bank A “Activate” command Select Bank B “Activate” command 0 0 0 1 1 0 Select Bank C “Activate” command 1 1 Select Bank D “Activate” command BA1 BA0 (A12) (A13) A10 BA1(A12) BA0(A13) 0 0 0 0 1 0 0 0 1 0 1 1 1 x x (Precharge command) Result Precharge Bank A Precharge Bank B Precharge Bank C Precharge Bank D Precharge All Banks x : Don’t care 0 Col. A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA1 BA0 (A12) (A13) 1 disables Auto-Precharge (End of Burst) enables Auto-Precharge (End of Burst) (/CAS strobes) BA1(A12) BA0(A13) Data Sheet E0255E10 (Ver. 1.0) 24 Result enables Read/Write commands for Bank A enables Read/Write commands for Bank B 0 0 0 1 1 0 enables Read/Write commands for Bank C 1 1 enables Read/Write commands for Bank D EDL1216BASA Operation of the Mobile RAM Precharge The precharge command can be issued anytime after tRAS min. is satisfied. Soon after the precharge command is issued, precharge operation performed and the synchronous DRAM enters the idle state after tRP is satisfied. The parameter tRP is the time required to perform the precharge. The earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is as follows. Burst length=4 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK /CAS latency = 2 Command PRE READ Q1 DQ Q2 Q3 Hi-Z Q4 /CAS latency = 3 Command READ PRE DQ Q1 Q2 Q3 Q4 Hi-Z (tRAS must be satisfied) Precharge In order to write all data to the memory cell correctly, the asynchronous parameter tDPL must be satisfied. The tDPL (min.) specification defines the earliest time that a precharge command can be issued. Minimum number of clocks is calculated by dividing tDPL (min.) with clock cycle time. In summary, the precharge command can be issued relative to reference clock that indicates the last data word is valid. In the following table, minus means clocks before the reference; plus means time after the reference. /CAS latency Read Write 2 -1 +tDPL(min.) 3 -2 +tDPL(min.) Data Sheet E0255E10 (Ver. 1.0) 25 EDL1216BASA Auto Precharge During a read or write command cycle, A10 controls whether auto precharge is selected. A10 high in the Read or Write command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is selected and begins automatically. The tRAS must be satisfied with a read with auto precharge or a write with auto precharge operation. In addition, the next activate command to the bank being precharged cannot be executed until the precharge cycle ends. In read cycle, once auto precharge has started, an activate command to the bank can be issued after tRP has been satisfied. In write cycle, the tDAL must be satisfied to issue the next activate command to the bank being precharged. The timing that begins the auto precharge cycle depends on whether read or write cycle. Read with Auto Precharge During a read cycle, the auto precharge begins one clock earlier (/CAS latency of 2) or two clocks earlier (/CAS latency of 3) the last data word output. Burst length = 4 T0 T1 T2 T3 T4 T5 T6 T7 T9 T8 CLK /CAS latency = 2 Auto precharge starts READA B Command Hi-Z DQ QB1 QB2 QB3 QB4 /CAS latency = 3 Command Auto precharge starts READA B Hi-Z DQ QB1 QB2 QB3 QB4 (tRAS must be satisfied) Read with Auto Precharge Remark: READA means Read with Auto precharge Write with Auto Precharge During a write cycle, the auto precharge starts at the timing that is equal to the value of the tDPL (min.) after the last data word input to the device. Burst length = 4 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK Command Auto precharge starts WRITA B Hi-Z DQ DB1 DB2 DB3 DB4 tDPL(MIN.) Write with Auto Precharge Remark: WRITA means Write with Auto Precharge Data Sheet E0255E10 (Ver. 1.0) 26 (tRAS must be satisfied) EDL1216BASA Read / Write Command Interval Read to Read Command Interval During a read cycle, when new Read command is issued, it will be effective after /CAS latency, even if the previous read operation does not completed. READ will be interrupted by another READ. The interval between the commands is 1 cycle minimum. Each Read command can be issued in every clock without any restriction. Burst length = 4, /CAS latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 QA1 QB1 QB2 QB3 QB4 T8 T9 CLK Command READ A READ B Hi-Z DQ 1cycle Read to Read Command Interval Write to Write Command Interval During a write cycle, when a new Write command is issued, the previous burst will terminate and the new burst will begin with a new Write command. WRITE will be interrupted by another WRITE. The interval between the commands is minimum 1 cycle. Each Write command can be issued in every clock without any restriction. Burst length = 4 T0 T1 T2 T3 T4 T5 DB2 DB3 DB4 T6 CLK Command WRITE A WRITE B DA1 DB1 Hi-Z DQ 1cycle Write to Write Command Interval Data Sheet E0255E10 (Ver. 1.0) 27 T7 T8 EDL1216BASA Write to Read Command Interval Write command and Read command interval is also 1 cycle. Only the write data before Read command will be written. The data bus must be High-Z at least one cycle prior to the first DOUT. Burst length = 4 T0 T1 T2 T3 T4 T5 T6 T7 QB1 QB2 QB3 QB4 QB1 QB2 QB3 T8 CLK /CAS latency = 2 Command WRITE A READ B Hi-Z DQ DA1 /CAS latency = 3 Command WRITE A READ B Hi-Z DQ DA1 Write to Read Command Interval Data Sheet E0255E10 (Ver. 1.0) 28 QB4 EDL1216BASA Read to Write Command Interval During a read cycle, READ can be interrupted by WRITE. The Read and Write command interval is 1 cycle minimum. There is a restriction to avoid data conflict. The Data bus must be High-Z using DQM before WRITE. Burst length = 4 T0 T1 T2 T3 T4 T5 D2 D3 D4 T6 T7 T8 CLK Command READ WRITE DQM Hi-Z DQ D1 1cycle Read to Write Command Interval 1 READ can be interrupted by WRITE. DQM must be High at least 3 clocks prior to the Write command. Burst length = 8 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 D2 D3 D2 D3 CLK /CAS latency = 2 Command READ WRITE DQM Q1 DQ Q2 Q3 D1 Hi-Z is necessary /CAS latency = 3 Command READ WRITE DQM DQ Q1 Q2 D1 Hi-Z is necessary Read to Write Command Interval 2 Data Sheet E0255E10 (Ver. 1.0) 29 EDL1216BASA Burst Termination There are two methods to terminate a burst operation other than using a Read or a Write command. One is the burst stop command and the other is the precharge command. Burst Termination in READ Cycle During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus goes to High-Z after the /CAS latency from the burst stop command. Burst length = X T0 T1 T2 T3 T4 T5 T6 T7 CLK Command READ BST /CAS latency = 2 Hi-Z DQ Q1 Q2 Q3 Q1 Q2 /CAS latency = 3 Hi-Z DQ Q3 Burst Termination in READ Cycle Remark: BST: Burst stop command Burst Termination in WRITE Cycle During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes to High-Z at the same clock with the burst stop command. Burst length = X T0 T1 T2 T3 T4 T5 T6 T7 CLK Command WRITE BST Hi-Z DQ D1 D2 D3 D4 Burst Termination in WRITE Cycle Remark: BST: Burst stop command Data Sheet E0255E10 (Ver. 1.0) 30 EDL1216BASA Precharge Termination in READ Cycle During a read cycle, the burst read operation is terminated by a precharge command. When the precharge command is issued, the burst read operation is terminated and precharge starts. The same bank can be activated again after tRP from the precharge command. To issue a precharge command, tRAS must be satisfied. When /CAS latency is 2, the read data will remain valid until one clock after the precharge command. Burst length = X, /CAS latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 CLK READ Command PRE ACT Hi-Z DQ Q1 Q2 Q3 Q4 tRP (tRAS must be satisfied) Precharge Termination in READ Cycle (CL = 2) When /CAS latency is 3, the read data will remain valid until two clocks after the precharge command. Burst length = X, /CAS latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK Command READ PRE ACT Hi-Z DQ Q1 Q2 Q3 Q4 tRP (tRAS must be satisfied) Precharge Termination in READ Cycle (CL = 3) Data Sheet E0255E10 (Ver. 1.0) 31 EDL1216BASA Precharge Termination in WRITE Cycle During a write cycle, the burst write operation is terminated by a precharge command. When the precharge command is issued, the burst write operation is terminated and precharge starts. The same bank can be activated again after tRP from the precharge command. To issue a precharge command, tRAS must be satisfied. The write data written prior to the precharge command will be correctly stored. However, invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM must be high at the same clock as the precharge command. This will mask the invalid data. Burst length = X, /CAS latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK Command WRITE ACT PRE DQM Hi-Z DQ D1 D2 D3 D4 D5 tRP (tRAS must be satisfied) Precharge Termination in WRITE Cycle Data Sheet E0255E10 (Ver. 1.0) 32 EDL1216BASA Timing Waveforms ; ;;; ; ;;; ;; ; ;;; ;;; ;;;; ;;; ;;;; ;; ;;; ;;;; ; ;;; ;;; ;;;; ; ;;; ;;; ;; ;; ;;; ;;;; ; ;; ; ;;; ;;; ;;; ;;; ;;; ;; ; ;;; ;;; ; ;; ;;; ;;;; ;;;;;; ; ;; ; ;; ; ; ; ;;;; AC Parameters for Read Timing with Manual Precharge T0 tCK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 CLK tCH tCL CKE tCKH tCKS tCMS tCMH /CS /RAS /CAS /WE BA0 BA1 A10 ADD tAS tAH DQM L tAC DQ tAC tAC tAC tHZ Hi-Z tLZ tRCD tOH tOH tRAS tOH tOH tRP tRC Activate Command for Bank A Read Command for Bank A Precharge Command for Bank A Activate Command for Bank A [Burst Length = 4, /CAS Latency = 3] Data Sheet E0255E10 (Ver. 1.0) 33 EDL1216BASA ;;; ;;; ;;; ;;; ;; ;;; ;; ;;; ;;; ;; ;;;;; ;;; ;; ;;;;;; ;;;;; ;;; ;;; ;;; ;;; ;; ; ;;; ;;; ;;; ;; ; ; ; ; ;;; ;;; ;;;; ;; ;; ;;; ;; ; ; ; ; ;;; ;;; ;;; ;; ;;;;;;; ;;; ;;; ;;;;;; AC Parameters for Read Timing with Auto Precharge T0 tCK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 CLK tCH tCL CKE tCKS Auto Precharge Start for Bank C tCMS tCMH tCKH /CS /RAS /CAS /WE BA0 BA1 A10 ADD tAS tAH DQM L tAC DQ tAC tAC tAC tHZ Hi-Z tRCD tLZ tOH tOH tOH tOH tRAS tRRD tRC Activate Command for Bank C Read with Auto Precharge Command for Bank C Activate Command for Bank D Activate Command for Bank C [Burst Length = 4, /CAS Latency = 3] Data Sheet E0255E10 (Ver. 1.0) 34 EDL1216BASA ;; ;;;; ;; ;; ;;;; ;; ; ; ;; ;; ;; ;;;; ;; ;; ; ; ;; ;;;;;; ;; ;; ; ; ;; ;;;; ;; ; ; ;; ; ; ;; ;;;; ;; ; ; ; ; ; ;; ; ; ;; ;; ;; ;;;; ;; ; ; ;; ; ; ; ; ; ;; ;;;;;; ;; ;;; ;; ;;;; AC Parameters for Write Timing T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE Auto Precharge Start for Bank C tCKS tCMS tCMH tCKH /CS /RAS ;; /CAS /WE BA0 BA1 A10 ADD tAS tAH DQM L tDS tDH DQ Hi-Z tRCD tDAL tRC tRRD tRCD tDPL tRP tRAS tRC Activate Command for Bank C Write with Activate Auto Precharge Command Command for Bank B for Bank C Write Command for Bank B Activate Precharge Command Command for Bank C for Bank B Activate Command for Bank B [Burst Length = 4] Data Sheet E0255E10 (Ver. 1.0) 35 EDL1216BASA Mode Register Set T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK ;; ;; ;; ;;;;;;;;; ;; ;; ; ;; ; ;;;;;;;;; ; ;;;;;;;; ;;; ;; ;;;;;;;;; ;;; ;; ;;;;;;;; ;;; ;; ;; ; ; ;;;;;;;; ;; ;;; ; ; ;;;;;;;; ;;;;;;;;;;;; CKE H tRSC 2 CLK (MIN.) /CS /RAS /CAS /WE BA0 BA1 A10 ADDRESS KEY ADD DQM Hi-Z DQ Precharge All Banks Command Mode Register Set Command Activate Command is valid tRP Data Sheet E0255E10 (Ver. 1.0) 36 EDL1216BASA Extended Mode Register Set T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK ;; ;; ;; ;;;;;;;;; ;; ;; ; ;; ; ;;;;;;;;; ; ;;;;;;;; ;;; ;; ;;;;;;;;; ;;; ;; ;;;;;;;; ;;; ;; ;; ; ; ;;;;;;;; ;; ;;; ; ; ;;;;;;;; ;;;;;;;;;;;; CKE H tRSC 2 CLK (MIN.) /CS /RAS /CAS /WE BA0 BA1 A10 ADDRESS KEY ADD DQM Hi-Z DQ Precharge All Banks Command Extended Mode Register Set Command Activate Command is valid tRP Power On Sequence ;; ; ; ; ;;; ;;;; ;; ;;; ;; ;;;; ;; ;; ; ; ; ;; ;;; ; ; ; ;;; ;; ;;;; ;; ;;; ;;;;;;;; ;;; ; ;;;;;;;; ; ;; ;;; ;; ;; ; ;;;;;;;; ; ;; ; ; ;;;;;;;;;;;; ;; CLK Clock cycle is necessary CKE tRSC High level is necessary tRSC 2 refresh cycles are necessary /CS /RAS /CAS /WE BA0 BA1 A10 ADDRESS KEY ADDRESS KEY ADD DQM High level is necessary Hi-Z DQ Precharge All Banks Command is necessary Mode Register Set Command is necessary tRP Extended Mode Register Set Command is necessary CBR (Auto) Refresh Command is necessary CBR (Auto) Refresh Command is necessary tRC1 Data Sheet E0255E10 (Ver. 1.0) 37 Activate Command tRC1 EDL1216BASA /CS Function Only /CS signal needs to be issued at minimum rate T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H /CS /RAS /CAS /WE BA0 L BA1 L A10 RAa ADD RAa DQM CAa CAb L Hi-Z QAa1 DQ Activate Command for Bank A QAa2 QAa3 Read Command for Bank A QAa4 DAb1 Write Command for Bank A DAb2 DAb3 DAb4 Precharge Command for Bank A [Burst Length = 4, /CAS Latency = 3] Data Sheet E0255E10 (Ver. 1.0) 38 EDL1216BASA Clock Suspension during Burst Read T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ;; ;; ; ; ;; ;;;;;;;;; ;; ;; ;;;;;;;;;; ; ; ;; ;;;;;;;;; ;; ;; ;;;;;;;;;; ;; ;; ; ;;; ; ;; ;; ;; ;;;;;;;;;; ; ;;;;;;;;; ;; ;; ;;;;;;;;;; ; ;;;;;;;;; ;;;; ;;;;;;;;;; CLK CKE /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa DQM CAa L Hi-Z QAa1 DQ Activate Command for Bank A QAa2 Read Command for Bank A QAa3 1-CLOCK SUSPENDED QAa4 2-CLOCK SUSPENDED 3-CLOCK SUSPENDED Hi-Z (turn off) at the end of burst [Burst Length = 4, /CAS Latency = 3] T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ;; ;; ; ; ;;;;;;;;; ;; ;; ;;;;;;;;;; ; ; ;;;;;;;;; ;;;;;;;;;;;; ;; ;; ;;; ;;;;;;;;;; ;;;; ;;;;;;;;;;;; ;;;;;;;;;;; ;;;;;;;;; ;;;;;;;;;;;; CLK CKE /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa DQM CAa L Hi-Z QAa1 DQ Activate Command for Bank A Read Command for Bank A QAa2 QAa3 1-CLOCK SUSPENDED QAa4 2-CLOCK SUSPENDED 3-CLOCK Hi-Z (turn off) SUSPENDED at the end of burst [Burst Length = 4, /CAS Latency = 2] Data Sheet E0255E10 (Ver. 1.0) 39 EDL1216BASA Clock Suspension during Burst Write T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ;; ;; ; ; ;;;;;;;;; ; ; ;;;;;;;;; ;; ;; ;;;;;;;;;; ;; ;; ;;;;;;;;;; ; ;; ;; ; ;;; ;; ;; ;; ;;;;;;;;;; ; ;;;;;;;;; ;;; ; ;;;;;;;;; ;; ;; ;;;;;;;;;; ;;;;;;;;;;;;;; ;;;;;; CLK CKE /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa DQM CAa L Hi-Z DQ DAa1 Activate Command for Bank A DAa2 Write 1-CLOCK Command SUSPENDED for Bank A DAa3 DAa4 2-CLOCK SUSPENDED 3-CLOCK SUSPENDED Data Sheet E0255E10 (Ver. 1.0) 40 EDL1216BASA Power Down Mode and Clock Mask ;; ; ; ;; ;;; ; ;; ;;; ;;;;; ;;;; ;; ;;; ; ;; ; ;;;;; ; ;;;; ; ;; ;; ;;; ;;;;; ;;;; ;; ;;; ;;;; ;;;;; ;;;; ; ;;; ;;;;; ;;;; ;;;; ; ;;; ;;;;; ; ;;;; ;;; ;;;; ;;;;;;;; T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK tCKSP tCKSP CKE VALID /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa DQM CAa L Hi-Z QAa1 QAa2 QAa3 DQ Activate Command for Bank A QAa4 Read Command for Bank A Power Down Mode Entry Precharge Command for Bank A Power Down Mode Exit Clock Mask Start Power Down Mode Entry Clock Mask End ACTIVE STANDBY Power Down Mode Exit PRECHARGE STANDBY [Burst Length = 4, /CAS Latency = 3] ;; ;; ;;; ;; ;; ;; ;;; ; ;;;;; ;; ;;; ;;;; ;; ; ;; ; ;; ;;; ;;;;; ;;;; ;;;; ;; ;;; ;;;;; ; ;;;;;;;; ;;;; ; ;;; ;;; ; ;;; ;; ;;;;; ;;;; ;;;;; ;;;; ;; ;;; ;;;;;;;; ;; ;;;;;;;;;;; T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK tCKSP tCKSP CKE VALID /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa DQM CAa L Hi-Z QAa1 QAa2 QAa3 DQ Activate Command for Bank A QAa4 Read Command for Bank A Power Down Mode Entry Power Down Mode Exit Precharge Command for Bank A Clock Mask Start Clock Mask End ACTIVE STANDBY Power Down Mode Entry Power Down Mode Exit PRECHARGE STANDBY [Burst Length = 4, /CAS Latency = 2] Data Sheet E0255E10 (Ver. 1.0) 41 EDL1216BASA Auto Refresh T0 T1 T2 T3 T4 T5 T6 Tn Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tm Tm + 1 Tm + 2 Tm + 3 Tm + 4 Tm + 5 Tm + 6 Tm + 7 ;;;; ;;;;; ; ;;; ; ; ;; ; ; ; ;;; ; ; ;; ;;;; ;;;; ;; ;;; ; ;; ; ;;;; ;;;; ;; ;;; ;;;;;;;; ;; ; ;;;;;;;; ;;;;;;;; ;; ; ;;; ;; ;; ;;;;;;;; ;; ;;;;;;;;; ; ;;;;;;;;;;;; CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 ADD DQM DQ L Hi-Z Q1 Precharge CBR (Auto) Refresh Command (if necessary) tRP CBR (Auto) Refresh tRC1 Activate Command tRC1 Data Sheet E0255E10 (Ver. 1.0) 42 Read Command EDL1216BASA ; ; ;;; ;;; ; ;;;;; ; ;;;; ;; ;; ;; ;; ;; ;; ;; ; ;;;;; ; ; ;;;; ;; ;;; ;; ;; ;; ; ;;;;;;;; ;; ;;;;;;;;;;; ;; ;;;;;;;;; ;;; ;;;;;;;;;;; ;; ;;;;;;;;; ;;; Self Refresh (Entry and Exit) T0 T1 T2 T3 T4 Tn Tn + 1 Tn + 2 Tm Tm + 1 Tk Tk + 1 Tk + 2 Tk + 3 Tk + 4 CLK CKE /CS /RAS /CAS /WE BA0 BA1 A10 ADD DQM L Hi-Z DQ Precharge Command (if necessary) Self Refresh Entry Self Refresh Self Refresh Entry Exit (or Activate Command) Self Refresh Exit Activate Command Next Clock Enable tRP tRC1 Next Clock Enable tRC1 Data Sheet E0255E10 (Ver. 1.0) 43 EDL1216BASA Deep Power Down Entry ;;;;;;;;;; ;; ;;;;;;;;;;;; ;; ;;;;;;;;;; ;; ;; ; ;;;;;;;;;; ; ;;;;;;;;;;;; ;;;;;;;;;;;; ;; ;;;;;;;;;;; ;;;;;;;;;;;;; ;;;;;;;;;;;; T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE /CS /RAS /CAS /WE BA0 BA1 A10 ADD DQM L Hi-Z DQ Precharge All Banks Command Deep Power Down Entry tRP Deep Power Down Exit ;;; ; ; ; ;;; ;;;; ;; ;;; ;; ;;;; ;; ;; ; ; ; ;; ;;; ; ; ; ;;; ;; ;;;; ;; ;;; ;;;;;;;; ;;; ; ;;;;;;;; ; ;; ;;; ;; ;; ; ;;;;;;;; ; ;; ; ; ;;;;;;;;;;;; ;; CLK Clock cycle is necessary CKE tRSC High level is necessary tRSC 2 refresh cycles are necessary /CS /RAS /CAS /WE BA0 BA1 A10 ADDRESS KEY ADDRESS KEY ADD DQM High level is necessary Hi-Z DQ Deep Power Down Exit Command Precharge All Banks Command is necessary 200µs Mode Register Set Command is necessary tRP Extended Mode Register Set Command is necessary CBR (Auto) Refresh Command is necessary CBR (Auto) Refresh Command is necessary tRC1 Data Sheet E0255E10 (Ver. 1.0) 44 Activate Command tRC1 EDL1216BASA ;;;;;;;;;;;; ;; ;; ;; ;; ;; ; ;; ;; ;; ; ;; ;; ;;; ; ;; ;; ; ;; ;;;; ;; ;; ; ;; ;; ;; ;; ; ;; ;;;;;;; ;;; ;; ;;; ;; ;; ;;; ;; ;;;; ;;; ;;;; ;; ;; ; ; ; ;; ;; ;;;; ;;; ;; ;;; ;; ;;;; ;;;;;;;;;;;;; ;;;;;;;;;;;;;;;; Random Column Read T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa DQM RAa CAb CAa CAc RAa CAa Activate Command for Bank A Read Command for Bank A L Hi-Z QAa1 QAa2 DQ Activate Command for Bank A QAa3 QAa4 QAc1 Read Command for Bank A Read Command for Bank A Read Command for Bank A QAb1 QAb2 QAc2 QAc3 QAc4 Precharge Command for Bank A [Burst Length = 4, /CAS Latency = 3] ;;;;;;;;;;;;; ; ; ; ;; ;; ;;; ;; ;;; ;; ;; ;;;; ;; ;; ; ; ;; ;;; ;;; ;; ;; ;;;; ;; ; ;; ; ;;; ; ;; ;;; ; ;; ; ;; ;;;; ; ;; ;;;;;; ;; ;;;; ; ; ;;; ;; ; ; ;;;; ;;;;;;; ;; ; ;; ; ; ;;; ;;;; ;; ; ;; ; ; ;;; ;;;;;;;;;;;;; ;;;;;;;;;;; T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK H CKE /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa DQM RAd CAa CAb CAc RAd CAd L Hi-Z QAa1 DQ Activate Command for Bank A Read Command for Bank A QAa2 QAa3 Read Command for Bank A QAa4 QAb1 QAb2 Read Command for Bank A QAc1 QAc2 QAc3 Precharge Command for Bank A QAc4 Activate Command for Bank A QAd1 QAd2 QAd3 Read Command for Bank A [Burst Length = 4, /CAS Latency = 2] Data Sheet E0255E10 (Ver. 1.0) 45 EDL1216BASA Random Column Write ;;;;;;;;;;;;; ;; ;; ;; ;; ; ;; ;; ;; ;; ;; ;; ;; ;; ;; ; ;; ;; ;; ;; ; ;; ;; ;; ; ;; ;; ;; ; ; ;; ;;;; ;; ;;;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;;;;;;;;;;;;;; ;; ;;;; ;; ;;; ;;;; ;; ;; ; ;;; ;; ;;;; ;; ;; ;; ;; ;; ;;; ;; ;;; ;; ;; ;; ;;;;;;;;;;;; T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RDa ADD RDa DQM DQ RDd CDa CDb CDc RDd CDd L Hi-Z Activate Command for Bank D DDa1 Write Command for Bank D DDa2 DDa3 DDa4 DDb1 DDb2 Write Command for Bank D DDc1 Write Command for Bank D DDc2 DDc3 DDc4 Precharge Command for Bank D DDd1 DDd2 Activate Command for Bank D Write Command for Bank D [Burst Length = 4] Data Sheet E0255E10 (Ver. 1.0) 46 EDL1216BASA ;;;;;;;;;;;; ;; ;; ;;;;;; ; ;; ; ; ;; ;;; ;; ;; ;; ;; ;; ;; ; ;; ; ;;; ;; ;; ;; ;; ; ;; ; ;; ; ;; ; ;; ; ;;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ; ;;; ; ; ;;; ; ; ;; ; ; ; ; ;; ; ;; ; ; ; ; ;;;;;;;;;;;;; ;; ;;; ;;; ;;;;;;;; Random Row Read T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RBa ADD RBa DQM DQ RBb RAa CBa RAa CAa RBb CBb L Hi-Z QBa1 QBa2 Activate Command for Bank B Read Command for Bank B QBa3 QBa4 QBa5 QBa6 Activate Command for Bank A QBa7 QBa8 Read Command for Bank A QAa1 QAa2 QAa3 QAa4 Precharge Command for Bank B QAa5 QAa6 QAa7 Activate Command for Bank B Read Command for Bank B Precharge Command for Bank A [Burst Length = 8, /CAS Latency = 3] ;;;;;;;;;;;;; ; ; ;;;;;; ;; ; ; ;; ;;;; ;; ; ;;; ;; ;; ; ; ;;;; ; ;; ; ;; ;;; ;; ;; ;; ;; ; ;; ;;;; ; ; ; ; ;;;; ; ;; ;; ;; ;; ; ;; ;;;; ;; ;; ;;;; ;; ;;;;;;;;;;;; ;; ;;;;;;;;;;;;;;;; T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RDa ADD RDa DQM DQ RBa CDa RDb RBa CBa RDb CDb L Hi-Z Activate Command for Bank D QDa1 QDa2 QDa3 QDa4 QDa5 QDa6 QDa7 QDa8 QBa1 QBa2 QBa3 QBa4 Read Command for Bank D Activate Command for Bank B Read Command for Bank B Activate Command for Bank D QBa5 QBa6 QBa7 QBa8 Read Command for Bank D Precharge Command for Bank D [Burst Length = 8, /CAS Latency = 2] Data Sheet E0255E10 (Ver. 1.0) 47 EDL1216BASA ;;;;;;;;;;;; ; ;; ;; ;;; ;; ;; ;; ; ; ; ;; ;; ;;; ;;;;; ;; ;; ;; ;; ;; ; ; ;; ; ;; ;;; ; ;; ;; ;; ;; ;; ;; ; ; ; ; ; ;; ;;; ;;; ;; ;; ;;; ;; ;; ; ;; ;; ; ;; ;; ;; ;; ; ; ;; ; ;; ;; ;; ;;; ;; ;;; ;; ;; ;;; ;; ;;;;;;;;;;; ;;;;;;; Random Row Write T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa DQM DQ RAb RDa CAa RDa RAb CDa CAb L Hi-Z Activate Command for Bank A DAa1 DAa2 Write Command for Bank A DAa3 DAa4 DAa5 DAa6 DAa7 DAa8 Activate Command for Bank D DDa1 DDa2 Write Command for Bank D DDa3 Precharge Command for Bank A DDa4 DDa5 DDa6 Activate Command for Bank A DDa7 DDa8 DAb1 Write Command for Bank A DAb2 Precharge Command for Bank D [Burst Length = 8] Data Sheet E0255E10 (Ver. 1.0) 48 EDL1216BASA ;;;;;;;;;;;;; ;; ;; ;; ;;;; ;; ;;;; ;; ; ;; ;; ;;;; ;; ;; ;;;; ;; ;; ; ; ; ;;;; ;; ;; ;;;; ;;; ;; ;;;;; ;;; ;;;; ; ; ;;;; ;;;;; ;;; ;;;; ;;;;;;;;;;; ;;;;;;; ;;; Read and Write T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa CAa CAb CAc Write Latency = 0 DQM L Word Masking DQ Hi-Z QAa1 QAa2 Activate Command for Bank A QAa3 QAa4 DAb1 Read Command for Bank A DAb2 DAb4 Write Command for Bank A QAc1 QAc2 Read Command for Bank A 0-Clock Latency Hi-Z at the end of wrap function 2-Clock Latency [Burst Length = 4, /CAS Latency = 3] T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK ;;;;;;;; ;;; ;;;;; ; ;;;; ;;; ;;;;; ; ; ; ;;;; ; ;;; ;;;;; ;; ;; ;;;; ;; ;;;;; ;;;;; ;; ;;;; ;; ;;;;; ;; ;;;;;;;;;;;;;;; CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa CAa CAb CAc Write Latency = 0 DQM L Word Masking DQ Hi-Z Activate Command for Bank A QAa1 QAa2 Read Command for Bank A QAa3 QAa4 DAb1 DAb2 DAb4 Write Command for Bank A Hi-Z at the end of wrap function QAc1 QAc2 QAc4 Read Command for Bank A 0-Clock Latency 2-Clock Latency [Burst Length = 4, /CAS Latency = 2] Data Sheet E0255E10 (Ver. 1.0) 49 EDL1216BASA Interleaved Column Read Cycle ;;;;;;;;;;;; ;; ;; ;; ;; ;; ; ;; ; ; ;; ;;; ;; ;; ; ; ; ;;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;;; ;; ;;;;;;;;;;;;; ;; ;; ;; ;; ;; ;;;; ;; ; ;; ;; ; ;; ; ; ;; ; ; ;;; ;;; ;;;;;;;;;;;;; ;;;;;;;;;;;;; ;;;; T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK H CKE /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa RDa CAa RDa CDa CDb CAb CDc L DQM Hi-Z DQ Aa1 Activate Command for Bank A Aa2 Aa3 Read Command for Bank D Read Command for Bank A Aa4 Da1 Read Command for Bank D Da2 Db1 Read Command for Bank D Db2 Dc1 Dc2 Ab1 Ab2 Ab3 Ab4 Read Command for Bank A Precharge Command for Bank D Activate Command for Bank D Precharge Command for Bank A [Burst Length = 4, /CAS Latency = 3] T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK ; ; ; ; ;;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;; ;;;; ;; ;; ;; ; ;; ; ;; ;; ; ;;; ;; ;;;;;; ;; ;; ;; ;; ;; ; ; ;; ;; ; ; ;;; ; ;; ; ; ;; ;;; ; ; ; ; ; ;; ;;;;;;;; ;;;;;; ;; ;;; CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa DQM RDa CAa CDa RDa CDb CDc CAb CDd L Hi-Z Aa1 DQ Activate Command for Bank A Read Command for Bank A Activate Command for bank D Aa2 Aa3 Read Command for Bank D Aa4 Da1 Read Command for Bank D Da2 Db1 Read Command for Bank D Db2 Dc1 Read Command for Bank A Dc2 Ab1 Ab2 Read Command for Bank D Precharge Command for Bank A Dd1 Dd2 Dd3 Dd4 Precharge Command for Bank D [Burst Length = 4, /CAS Latency = 2] Data Sheet E0255E10 (Ver. 1.0) 50 EDL1216BASA ;;;;;;;;;;;; ;; ;; ;; ;; ;; ;; ;; ;; ; ; ; ; ;; ; ; ;; ;; ;; ;; ;; ;; ;; ;; ;; ; ; ; ;; ;; ;; ;;;; ;; ;; ;; ; ;; ; ; ;; ;; ; ;; ; ; ; ; ; ; ; ; ;; ; ;; ;; ;; ;;;; ;; ;; ;; ; ; ; ; ; ; ; ; ; ;; ;; ;; ; ; ;; ; ;; ; ; ; ; ; ;;;;;;;;;;;; Interleaved Column Write Cycle T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H /CS /RAS ; ; /CAS /WE BA0 BA1 A10 RAa ADD RAa DQM DQ RBa CAa RBa Aa1 Aa2 CBa CBb CAb CBc CBd L Hi-Z Activate Command for Bank A Write Command for Bank A Activate Command for Bank B Aa3 Aa4 Ba1 Write Command for Bank B Ba2 Bb1 Write Command for Bank B Bb2 Bc1 Write Command for Bank B Bc2 Ab1 Write Command for Bank A Ab2 Bd1 Bd2 Bd3 Bd4 Write Command for Bank B Precharge Command for Bank A Precharge Command for Bank B [Burst Length = 4] Data Sheet E0255E10 (Ver. 1.0) 51 EDL1216BASA ;;;;;;;;;;;; ;;; ;;;; ;;; ;;; ; ;;; ;;;;;; ;;; ; ;;; ; ;;; ;; ;; ;; ;; ;; ;; ;;; ;;; ; ;; ;; ; ;; ;; ;; ;; ;; ;;;; ;; ;;;; ;; ;;; ;; ;;;; ;; ;;; ;; ;; ;; ;;;; ;; ;;;;;;;;;;;; ;;;;;;;;;;;; Auto Precharge after Read Burst T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa DQM DQ RDa CAa RDb RDa CDa CAb RDb CDb L Hi-Z Activate Command for Bank A Activate Command for Bank D Read Command for Bank A Read with Auto Precharge Command for Bank A Read with Auto Precharge Command for Bank D Activate Command for Bank D Auto Precharge Start for Bank D Read with Auto Precharge Command for Bank D Auto Precharge Start for Bank A [Burst Length = 4, /CAS Latency = 3] ;;;;;;;;;;; ;; ;;;; ;; ;;; ; ;; ; ; ; ; ; ;; ;; ;; ;; ;; ;; ;; ; ;;;; ;; ; ; ;;; ; ;; ; ; ; ; ; ;; ; ;; ;; ;; ;;; ;; ; ;;;; ; ;; ;; ;; ;;; ;; ;; ;; ;; ;; ; ;; ; ;;; ;;; ;; ;; ; ; ;; ; ;;; ;;;;;;;;;;;; ;;; ;; ;;; ;; ;; ;; ;; ;;;;;;;;;;;; T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa DQM DQ RDa CAa RDa RDb CDa CAb RDb RAc CDb RAc CAc L Hi-Z Activate Command for Bank A Read Command for Bank A Activate Command for Bank D Read with Auto Precharge Command for Bank D Activate Command Read with for Bank D Auto Precharge Command for Bank A Auto Precharge Start for Bank D Activate Command Read with Read with for Bank A Auto Precharge Auto Precharge Command Command for Bank A for Bank D Auto Precharge Auto Precharge Start for Bank A Start for Bank D [Burst Length = 4, /CAS Latency = 2] Data Sheet E0255E10 (Ver. 1.0) 52 EDL1216BASA ;;;;;;;;;;;;; ;;;; ;;;; ; ;; ;; ;; ;; ;; ;; ;; ;;; ;; ;; ;;;; ;; ;; ;; ;;;; ;; ;;; ; ;; ;; ;; ;; ;;;; ;; ;; ; ;; ;;; ;; ;; ;; ;;; ;;; ;; ;; ;; ;; ;; ;;; ; ;;; ; ;; ;; ;;; ;;; ;;;; ;;;;;; ;;;;;;;;;;;; ; ;;;;;;;;; Auto Precharge after Write Burst T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa DQM DQ RDa CAa RDa RDb CDa CAb RDb CDb L Hi-Z Activate Command for Bank A Activate Command for Bank D Write Command for Bank A Write with Auto Precharge Command for Bank D Write with Auto Precharge Command for Bank A Auto Precharge Start for Bank D Activate Command for bank D Auto Precharge Start for Bank A Write with Auto Precharge Command for Bank D [Burst Length = 4] Data Sheet E0255E10 (Ver. 1.0) 53 EDL1216BASA Burst Write Operation ;;; ;;;;; ;;; ;;;;; ;;;;;;;;; ;; ;;; ;;;;; ;;;;; ; ;;;; ;;; ; ;; ;;;;; ; ;;;; ;;;;;;; ;; ;;;;; ;;; ;;;;; ; ;; ; ;;;; ; ;; ;;;;; ;;; ; ;; ;;;;; ; ;;;; ;;;;;;;;;;;; ;;; ;; ; ;; ;;;;;;;;;;;; ;;; ;; ; ;; T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE /CS /RAS /CAS /WE BA0 BA1 A10 ADD LDQM UDQM DQ (lower) DQ (upper) Activate Command for Bank D Read Command for Bank D Upper Byte not Read Lower Byte not Read Lower Byte not Write Upper Byte not Write Lower Byte not Write Read Command for Bank D Lower Byte not Read Lower Byte not Read [Burst Length = 4] Data Sheet E0255E10 (Ver. 1.0) 54 EDL1216BASA ;;;;;;;;;;;; ;; ;; ;;; ;; ;; ;;; ;;; ;; ; ;; ;; ;;; ;; ;; ;;; ;; ; ;; ;; ; ;;; ; ;; ;; ;;; ; ;; ;;; ;; ;; ;;; ; ; ;; ; ;; ;; ;;; ;; ;; ;; ;; ;; ; ; ;;; ;; ;; ;; ;; ;; ;;;; ;;;;; ;;; ;;;;;;;;;;;;;; ;;;;;;;;;;;;; Precharge Termination T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa DQM RAb CAa RAc RAb CAb RAc Write Masking L Hi-Z DAa1 DQ DAa2 DAa3 DAa4 Hi-Z DAa5 Write Command for Bank A Activate Command for Bank A QAb1 QAb2 QAb3 QAb4 Read Command for Bank A Precharge Command for Bank A PRE Termination of Burst tRCD Activate Command for Bank A tDPL Activate Command for Bank A Precharge Command for Bank A PRE Termination of Burst tRAS tRP tRAS [Burst Length = 8, /CAS Latency = 3] ;;;;;;;;;;;; ;; ;; ;;; ;; ;; ;;; ;; ; ;; ;; ;; ;;; ;; ;; ;;; ; ;; ;; ; ; ;;; ;; ;; ;; ;;; ;; ; ;; ;; ;;;;; ; ; ;;; ;; ; ; ;; ; ; ;;; ;;; ;; ;;;;;;;;;;;;; ;;; ;;;;; ;;;;; ;;;;; ;;;; T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 CLK CKE H /CS /RAS /CAS /WE BA0 BA1 A10 RAa ADD RAa DQM DQ RAb CAa RAc CAb RAb RAc Write Masking L Hi-Z DAa1 Activate Command for Bank A DAa2 DAa3 DAa4 DAa5 QAb1 QAb2 Write Command for Bank A QAb3 QAb4 QAb5 Activate Command for Bank A Read Command for Bank A PRE Termination of Burst tRCD Precharge Command for Bank A tDPL Activate Command for Bank A PRE Termination of Burst tRP Hi-Z Precharge Command for Bank A tRAS tRAS [Burst Length = 8, /CAS Latency = 2] Data Sheet E0255E10 (Ver. 1.0) 55 EDL1216BASA Package Drawing Unit: mm S A 8.0±0.1 0.2 S B 8.0±0.1 0.2 INDEX AREA ⁄⁄ 0.2 1.0 max S S S 0.35±0.05 B 0.1 2 7 3 8 9 F G H J 1 0.8 A B C D E INDEX MARK A 0.8 0.8 1.6 0.8 54-φ0.45±0.05 φ0.08 M S A B ECA-TS2-0017-04 Data Sheet E0255E10 (Ver. 1.0) 56 EDL1216BASA Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the EDL1216BA. Type of Surface Mount Device EDL1216BASA: 54-ball FBGA Data Sheet E0255E10 (Ver. 1.0) 57 EDL1216BASA NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR MOS DEVICES Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. CME0107 Data Sheet E0255E10 (Ver. 1.0) 58 EDL1216BASA The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. M01E0107 Data Sheet E0255E10 (Ver. 1.0) 59