HY51V17800C,HY51V16800C 2Mx8, Fast Page mode DESCRIPTION This family is a 16M bit dynamic RAM organized 2,097,152 x 8-bit configuration with Fast Page mode CMOS DRAMs. Fast Page mode is a kind of page mode which is useful for the read operation. The circuit and process design allow this device to achieve high performance and low power dissipation. Optional features are access time(60, 70 or 80ns) and refresh cycle(2K ref. or 4K ref.) and power consumption (Normal or Low power with self refresh). Hyundai’s advanced circuit design and process technology allow this device to achieve high bandwidth, low power consumption and high reliability. FEATURES Ÿ Fast Page mode operation Ÿ Read-modify-write Capability Ÿ LVTTL compatible inputs and outputs Ÿ /CAS-before-/RAS, /RAS-only, Hidden and Self refresh capability Ÿ JEDEC standard pinout Ÿ 28-pin Plastic SOJ (300mil) 28-pin plastic TSOP-II (300mil) Ÿ Single power supply of 3.3V ± 0.3V Ÿ Early write or output enable controlled write Ÿ Max. Active power dissipation Ÿ Fast access time and cycle time Speed 2K refresh 4K refresh Speed tRAC tCAC tPC 60 432mW 360mW 60 60ns 15ns 40ns 70 360mW 324mW 70 70ns 20ns 45ns 80 324mW 288mW 80 80ns 20ns 50ns Ÿ Refresh cycle Part number Refresh Normal HY51V17800B 2K 16ms HY51V16800B 4K 64ms SL-part 256ms ORDERING INFORMATION Part Name Refresh HY51V17800CJ 2K HY51V17800CSLJ 2K HY51V17800CT 2K HY51V17800CSLT 2K HY51V16800CJ 4K HY51V16800CSLJ 4K HY51V16800CT 4K HY51V16800CSLT 4K Power Package 28Pin SOJ SL-part 28Pin SOJ 28Pin TSOP-II SL-part 28Pin TSOP-II 28Pin SOJ SL-part 28Pin SOJ 28Pin TSOP-II SL-part 28Pin TSOP-II *SL : Low power with self refresh This document is a general product description and is subject to change without notice. Hyundai electronics does not assume any responsibility for use of circuits described. No patent licences are implied Hyundai Semiconductor Rev.00 / Sep.97 1 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HY51V17800C,HY51V16800C FUNCTIONAL BLOCK DIAGRAM *(A10) and *(A11) for 4K refresh part (2K Refresh / 4K Refresh)* 2Mx8,Fast Page DRAM Rev.00 / Sep.97 2 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HY51V17800C,HY51V16800C PIN CONFIGURATION (Marking Side) 28Pin Plastic SOJ (300mil) 28Pin Plastic TSOP- II (300mil) *(N.C) : For 2K Refresh product PIN DESCRIPTION Pin Name Parameter /RAS Row Address Strobe /CAS Column Address Strobe /WE Write Enable /OE Output Enable A0~A11 Address Input (4K Refresh Product) A0~A10 Address Input (2K Refresh Product) DQ0~DQ7 Data In/Out Vcc Power (3.3V) Vss Ground NC No Connection 2Mx8,Fast Page DRAM Rev.00 / Sep.97 3 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HY51V17800C,HY51V16800C ABSOLUTE MAXIMUM RATING Symbol Parameter Rating Unit TA Ambient Temperature 0 to 70 °C TSTG Storage Temperature -55 to 150 °C VIN, VOUT Voltage on Any Pin relative to VSS -0.5 to 4.6 V VCC Voltage on VCC relative to VSS -0.5 to 4.6 V IOS Short Circuit Output Current 50 mA PD Power Dissipation 1 W TSOLDER Soldering Temperature Ÿ Time 260 Ÿ 10 °C Ÿ sec Note : Operation at or above Absolute Maximum Ratings can adversely affect device reliability RECOMMENDED DC OPERATING CONDITIONS (TA = 0°C to 70°C ) Symbol Parameter Min Typ Max UNIT VCC Power Supply Voltage 3.0 3.3 3.6 V VIH Input High Voltage 2.0 - Vcc+0.3 V VIL Input Low Voltage -0.3 - 0.8 V Note : All voltages are referenced to VSS. DC OPERATING CHARACTERISTIC Symbol Parameter Test condition Min Max Unit ILI Input Leakage Current (Any input) VSS ≤ VIN ≤ VCC + 0.3 All other pins not under test = VSS -10 10 µA ILO Output Leakage Current (Any input) VSS ≤ VOUT ≤ VCC /RAS & /CAS at VIH -10 10 µA VOL Output Low Voltage IOL = 2.0mA - 0.4 V VOH Output High Voltage IOH = -2.0mA 2.4 - V 2Mx8,Fast Page DRAM Rev.00 / Sep.97 4 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HY51V17800C,HY51V16800C DC CHARACTERISTICS (TA = 0°C to 70°C , VCC = 3.3V ± 0.3V, VSS = 0V, unless otherwise noted.) Symbol Parameter Test condition Speed Max. Current Unit 2K Ref 4K Ref 60 70 80 120 100 90 100 90 80 mA SL-part 2 1 2 1 mA ICC1 Operating Current /RAS, /CAS Cycling tRC = tRC(min.) ICC2 LVTTL Standby Current /RAS, /CAS ≥ VIH Other inputs ≥ VSS ICC3 /RAS-only Refresh Current /RAS Cycling,/CAS = VIH tRC = tRC(min.) 60 70 80 120 100 90 100 90 80 mA ICC4 Fast Page Mode Current /CAS Cycling, /RAS = VIL tPC = tPC(min.) 60 70 80 80 70 60 70 60 50 mA ICC5 CMOS Standby Current /RAS = /CAS ≥ VCC - 0.2V SL-part 1 200 1 200 mA mA ICC6 /CAS-before-/RAS Refresh Current /RAS & /CAS = 0.2V tRC = tRC(min.) 60 70 80 120 100 90 100 90 80 mA ICC7 Battery Back-up Current (SL-part) tRC=250µs (2K Ref), 62.5µs (4K Ref) /CAS = 0.2V /OE & /WE = VCC - 0.2V Address = Vcc-0.2V or 0.2V DQ0~DQ7 = Vcc-0.2, 0.2V or Open tRAS ≤ 300ns 300 300 ICC8 Self Refresh Current (SL-part) tRAS ≤ 1µs /RAS & /CAS = 0.2V Other pins are same as ICC7 µA 400 400 300 300 µA Note 1. ICC1, ICC3, ICC4 and ICC6 depend on output loading and cycle rates(tRC and tPC). 2. Specified values are obtained with output unloaded. 3. ICC is specified as an average current. In ICC1, ICC3, ICC6, address can be changed only once while /RAS=VIL. In ICC4, address can be changed maximum once while /CAS=VIH within one Fast Page mode cycle time tPC. 4. Only /RAS(max.)=1µs is applied to refresh of battery backup but tRAS(max.) = 10 µs is to applied to normal functional operation. 5. Icc5(max.) = 200 µA, Icc7 and Icc8 are applied to SL-part only. 2Mx8,Fast Page DRAM Rev.00 / Sep.97 5 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HY51V17800C,HY51V16800C AC CHARACTERISTICS (TA = 0 °C to 70 °C, VCC = 3.3V ± 0.3V, VSS = 0V, unless otherwise noted.) 60ns Symbol 70ns 80ns Parameter Unit Min Max Min Max Min Max Note tRC Random read or write cycle time 110 - 130 - 150 - ns tRWC Read-modify-write cycle time 155 - 170 - 200 - ns tPC Fast Page mode cycle time 40 - 45 - 50 - ns tPRWC Fast Page mode read-modify-write cycle time 80 - 95 - 105 - ns tRAC Access time from /RAS - 60 - 70 - 80 ns 4,5,6 tCAC Access time from /CAS - 15 - 20 - 20 ns 4,5 tAA Access time from column address - 30 - 35 - 40 ns 4,6 tCPA Access time from /CAS precharge - 35 - 40 - 45 ns 4 tCLZ /CAS to output low impedance 0 - 0 - 0 - ns 4 tOFF Output buffer turn-off delay from /CAS 0 15 0 15 0 15 ns 7 tT Transition time(rise and fall) 3 50 3 50 3 50 ns 2 tRP /RAS precharge time 40 - 50 - 50 - ns tRAS /RAS pulse width 60 10K 70 10K 80 10K ns tRASP /RAS pulse width(Fast Page cycle) 60 100K 70 100K 80 100K ns tRSH /RAS hold time 15 - 20 - 20 - ns tCSH /CAS hold time 60 - 70 - 80 - ns tCAS /CAS pulse width 15 10K 15 10K 20 10K ns tRCD /RAS to /CAS delay time 20 45 20 50 20 60 ns 5 tRAD /RAS to column address delay time 15 30 15 35 15 40 ns 6 tCRP /CAS to /RAS precharge time 5 - 5 - 5 - ns 10 tCP /CAS precharge time 10 - 10 - 10 - ns 14 tASR Row address set-up time 0 - 0 - 0 - ns tRAH Row address hold time 10 - 10 - 10 - ns tASC Column address set-up time 0 - 0 - 0 - ns tCAH Column address hold time 10 - 15 - 15 - ns tRAL Column address to /RAS lead time 30 - 35 - 40 - ns tRCS Read command set-up time 0 - 0 - 0 - ns tRCH Read command hold time referenced to /CAS 0 - 0 - 0 - ns 8 tRRH Read command hold time referenced to /RAS 0 - 0 - 0 - ns 8 tWCH Write command hold time 15 - 15 - 15 - ns tWP Write command pulse width 10 - 10 - 10 - ns tRWL Write command to /RAS lead time 20 - 20 - 20 - ns tCWL Write command to /CAS lead time 20 - 20 - 20 - ns 2Mx8,Fast Page DRAM Rev.00 / Sep.97 6 Powered by ICminer.com Electronic-Library Service CopyRight 2003 14 HY51V17800C,HY51V16800C AC CHARACTERISTICS Continued 60ns Symbol 70ns 80ns Parameter Min Max Min Max Min Max Unit Note tDS Data-in set-up time 0 - 0 - 0 - ns 9 tDH Data-in hold time 15 - 15 - 15 - ns 9 Refresh period(2048 cycles) - 32 - 32 - 32 ms Refresh period(4096 cycles) - 64 - 64 - 64 ms Refresh period(SL-part) - 256 - 256 - 256 ms tWCS Write command set-up time 0 - 0 - 0 - ns 10 tCWD /CAS to /WE delay time 45 - 50 - 50 - ns 10,13 tRWD /RAS to /WE delay time 85 - 95 - 105 - ns 10 tAWD Column address to /WE delay time 55 - 60 - 65 - ns 10 tCSR /CAS set-up time(CBR cycle) 5 - 5 - 5 - ns 15 tCHR /CAS hold time(CBR cycle) 10 - 10 - 10 - ns 16 tRPC /RAS to /CAS precharge time 5 - 5 - 5 - ns tCPT /CAS precharge time(CBR counter test) 30 - 35 - 40 - ns tROH /RAS hold time referenced to /OE 10 - 10 - 10 - ns tOEA /OE access time - 15 - 20 - 20 ns tOED /OE to data delay Time 15 - 20 - 20 - ns tOEZ Output buffer turn-off delay time from /OE 0 15 0 15 0 15 ns tOEH /OE command hold time 15 - 20 - 20 - ns tCPWD /WE delay time from /CAS precharge 55 - 65 - 75 - ns tRHCP /RAS hold time from /CAS precharge 40 - 40 - 50 - ns tWRP /WE to /RAS precharge time(CBR cycle) 10 - 10 - 10 - ns tWRH /WE to /RAS hold time(CBR cycle) 10 - 10 - 10 - ns tRASS /RAS pulse width(self refresh) 100K - 100K - 100K - ns tRPS /RAS Precharge Time (Self refresh) 110 - 130 - 150 - ns tCHS /CAS Hold Time (Self refresh) -50 - -50 - -50 - ns tREF 2Mx8,Fast Page DRAM Rev.00 / Sep.97 7 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12 7 10 HY51V17800C,HY51V16800C NOTE 1. An initial pause of 200µs is required after power-up followed by 8 /RAS only refresh cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CBR refresh cycles instead of 8 /RAS-only refresh cycles are required. 2. VIH(min.) and VIL(max.) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min.) and VIL(max.) 3. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (TA=0 to 70¡ ÆC) is assured. 4. Measured at VOH=2.0V and VOL=0.8V with a load equivalent to 1TTL loads and 100pF. 5. Operation within the tRCD(max.) limit ensures that tRAC(max.) can be met. tRCD(max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(max.) limit, then access time is controlled by tCAC. 6. Operation within the tRAD(max.) limit ensures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(max.) limit, then access time is controlled by tAA. 7. t OFF and t OEZ define the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to /CAS leading edge in early write cycles and to /WE leading edge in read-modify-write cycles and late write cycle. 10.tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS(min.), the cycle is an early write cycle and data out pin will remain open circuit (high impedance) through the entire cycle. If tRWD ≥ tRWD(min.), tCWD ≥ tCWD(min.), tAWD ≥ tAWD(min), and tCPWD ≥ tCPWD(min.), the cycle is a read-modify-write cycle and data out will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11.tASC,tCAH are referenced to the earlier /CAS falling edge. 12.tCP and tCPT are measured when /CAS is high state. 13.tCWD is referenced to the later /CAS falling edge at word read-modifiy-write cycle. 14.tCWL must be satisfied by /CAS for 8-bit access cycles. 15.tCSR is referenced to the earlier /CAS falling before /RAS transition low. 16.tCHR is referenced to the later /CAS rising high after /RAS transition low. CAPACITANCE (TA = 25°C, VCC = 3.3V ± 0.3V, VSS = 0V and f=1MHz, unless otherwise noted.) Symbol Parameter Typ. Max Unit CIN1 Input Capacitance (A0~A11) - 5 pF CIN2 Input Capacitance (/RAS, /CAS, /WE, /OE) - 7 pF CDQ Data Input / Output Capacitance (DQ0~DQ7) - 7 pF 2Mx8,Fast Page DRAM Rev.00 / Sep.97 8 Powered by ICminer.com Electronic-Library Service CopyRight 2003