ETC ICE2B165

y
ICE2B165/265/365
D
CoolSET™-F2
at
a
Datasheet, Version 2.0, Novem ber 2001
re
li
m
in
ar
Off-Line SMPS Current Mode
C o n t ro l l e r w i t h i n t e g ra t e d 6 5 0 V
CoolMOS™
P
P o w e r M a n a g em e n t & S u p p l y
N e v e r
s t o p
t h i n k i n g .
CoolSET™-F2
Revision History:
2001-11-21
Previous Version:
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Datasheet
Subjects (major changes since last revision)
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Edition 2001-11-21
Published by Infineon Technologies AG,
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D-81541 München
© Infineon Technologies AG 1999.
All Rights Reserved.
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For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list).
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be endangered.
CoolSET™-F2
Preliminary Specification
ICE2B165/265/365
Off-Line SMPS Current Mode Controller
with integrated 650V CoolMOS™
Product Highlights
•
•
•
•
Best of Class in DIP8 Package
No Heatsink required
Lowest Standby Power Dissipation
Enhanced Protection Functions all
with Auto Restart Mode
P-DIP-8-6
Features
Description
•
•
•
•
•
•
The second generation COOLSET™-F2 provides several
special enhancements to satisfy the needs for low power
standby and protection features. In standby mode
frequency reduction is used to lower the power
consumption and support a stable output voltage in this
mode. The frequency reduction is limited to 20 kHz to avoid
audible noise. In case of failure modes like open loop,
overvoltage or overload due to short circuit the device
switches in Auto Restart Mode which is controlled by the
internal protection unit. By means of the internal precise
peak current limitation the dimension of the transformer and
the secondary diode can be lower which leads to more cost
efficiency.
•
•
•
•
•
•
•
•
650V Avalanche Rugged CoolMOS™
Only few external Components required
Input Undervoltage Lockout
67kHz Switching Frequency
Max Duty Cycle 72%
Low Power Standby Mode to support
“Blue Angle” Norm
Thermal Shut Down with Auto Restart
Overload and Open Loop Protection
Overvoltage Protection during Auto Restart
Adjustable Peak Current Limitation via
External Resistor
Overall Tolerance of Current Limiting < ±5%
Internal Leading Edge Blanking
User defined Soft Start
Soft Switching for Low EMI
Typical Application
+
RStart-up
85 ... 270 VAC
Converter
DC Output
Snubber
-
CVCC
VCC
Drain
Feedback
Low Power
StandBy
Power
Management
SoftS
PWM Controller
Current Mode
Soft-Start Control
CSoft Start
CoolMOS™
Isense
Precise Low Tolerance
Peak Current Limitation
RSense
FB
Protection Unit
GND
PWM-Controller
Feedback
CoolSET™-F2
Type
Ordering Code
Package
UDS
FOSC
RDSon1)
230VAC ±15%2)
85-265 VAC2)
ICE2B165
Q67040-S4489-A001
P-DIP-8-6
650V
67kHz
3.0Ω
31W
18W
ICE2B265
Q67040-S4478-A001
P-DIP-8-6
650V
67kHz
0.9Ω
52W
32W
ICE2B365
Q67040-S4490-A001
P-DIP-8-6
650V
67kHz
0.45Ω
73W
45W
1)
typ @ T=25°C
2)
Maximum practical continous power in an open frame design at 75°C ambient with copper area on PCB = 6cm², Tj=125°C
Datasheet
Preliminary Data
3
November 2001
Preliminary Specification
Table of Contents
CoolSET™-F2
ICE2B165/265/365
Page
1
1.1
1.2
Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2
Representative Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3
3.1
3.2
3.2.1
3.2.2
3.3
3.4
3.4.1
3.4.2
3.5
3.5.1
3.5.2
3.6
3.7
3.8
3.8.1
3.8.2
3.8.3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Improved Current Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
PWM-OP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
PWM-Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Oscillator and Frequency Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Frequency Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Leading Edge Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Propagation Delay Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
PWM-Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Protection Unit (Auto Restart Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Overload & Open loop with normal load . . . . . . . . . . . . . . . . . . . . . . . . .12
Overvoltage due to open loop with no load . . . . . . . . . . . . . . . . . . . . . . .13
Thermal Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Control Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Protection Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
CoolMOS™ Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
5
Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .18
6
Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Datasheet
Preliminary Data
4
November 2001
Preliminary Specification
CoolSET™-F2
ICE2B165/265/365
Pin Configuration and Functionality
1
Pin Configuration and Functionality
1.1
Pin Configuration
Pin
1.2
SoftS (Soft Start & Auto Restart Control)
This pin combines the function of Soft Start in case of
Start Up and Auto Restart Mode and the controlling of
the Auto Restart Mode in case of an error detection.
Symbol
Function
1
SoftS
Soft-Start
2
FB
Feedback
3
Isense
Controller Current Sense Input,
CoolMOS™ Source Output
4
Drain
650V1) CoolMOS™ Drain
5
Drain
650V1) CoolMOS™ Drain
6
N.C.
Not connected
7
VCC
Controller Supply Voltage
8
GND
Controller Ground
1)
FB (Feedback)
The information about the regulation is provided by the
FB Pin to the internal Protection Unit and to the internal
PWM-Comparator to control the duty cycle.
Isense (Current Sense)
The Current Sense pin senses the voltage developed
on the series resistor inserted in the source of the
integrated CoolMOS™. When Isense reaches the
internal threshold of the Current Limit Comparator, the
Driver output is disabled. By this means the Over
Current Detection is realized.
Furthermore the current information is provided for the
PWM-Comparator to realize the Current Mode.
at Tj = 110°C
Package P-DIP-8-6
8
GND
FB
2
7
VCC
Isense
3
6
N.C
4
5
Drain
(see Note)
Figure 1
Note:
Drain (Drain of integrated CoolMOS™)
Pin Drain is the connection to the Drain of the internal
CoolMOSTM.
1
SoftS
Pin Functionality
VCC (Power supply)
This pin is the positiv supply of the IC. The operating
range is between 8.5V and 21V.
To provide overvoltage protection the driver gets
disabled when the voltage becomes higher than 16.5V
during Start Up Phase.
GND (Ground)
This pin is the ground of the primary side of the SMPS.
Drain
Pin Configuration (top view)
To provide a larger creepage distance on the
PCB the Drain Pin 4 should not be connected.
Datasheet
Preliminary Data
5
November 2001
Figure 2
Datasheet
Preliminary Data
FB
CSoft-Start
T1
6
Thermal
Shutdown
C3
C4
C2
C1
GND
Protection Unit
Tj >140°C
4.8V
5.3V
4.0V
CoolSET™-F2
RFB
6.5V
5.6V
RSoft-Start
6.5V
16.5V
VCC
RStart-up
G2
G1
8.5V
67kHz
20kHz
R
S
Q
Q
fosc
UFB
Error-Latch
Spike
Blanking
5µs
Power-Up
Reset
Power-Down
Reset
13.5V
x3.65
C5
PWM
Comparator
Soft-Start
Comparator
6.5V
5.3V
4.8V
4.0V
Improved Current Mode
PWM OP
0.8V
0.3V
Soft Start
Voltage
Reference
Internal
Bias
Power Management
Undervoltage
Lockout
Standby Unit
G3
CVCC
CLine
G4
Current Limiting
R
S
Vcsth
Q
Q
PWM-Latch
0.72
Propagation-Delay
Compensation
Current-Limit
Comparator
20-67kHz
Clock
Duty Cycle
max
Oscillator
Leading Edge
Blanking
200ns
Gate
Driver
D1
10kΩ
CoolMOS™
Drain
Optocoupler
Isense
RSense
+
Converter
DC Output
VOUT
-
2
SoftS
85 ... 270 VAC
Snubber
Preliminary Specification
CoolSET™-F2
ICE2B165/265/365
Representative Blockdiagram
Representative Blockdiagram
Representative Blockdiagram
November 2001
CoolSET™-F2
ICE2B165/265/365
Preliminary Specification
Functional Description
3
Functional Description
3.1
Power Management
3.2
M ain L in e (1 00 V -3 80 V )
Improved Current Mode
S o ft-S ta rt C o m p a ra to r
R S tart-U p
P rim ary W in ding
P W M -L a tch
FB
C VC C
R
Q
D rive r
VCC
P W M C o m p a ra to r
Pow er M anagem ent
S
U n de rvolta g e
Q
In te rn a l
L o ckou t
B ias
0 .8V
1 3 .5V
8 .5 V
P o w er-D ow n
6.5 V
R e set
5.3 V
V o lta g e
PW M OP
x3 .6 5
4.8 V
R efe ren ce
4.0 V
P o w er-U p
Ise n se
Im proved
C urrent M ode
R e se t
R
Q
P W M -L atch
Figure 4
6 .5 V
S
R Soft-Sta rt
S o ftS
Q
Current Mode means that the duty cycle is controlled
by the slope of the primary current. This is done by
comparison the FB signal with the amplified current
sense signal.
E rro r-L a tch
S o ft-S ta rt C om p ara tor
C S oft-Start
T1
Current Mode
E rror-D ete ctio n
A m p lified C u rren t S ig n al
Figure 3
Power Management
FB
The Undervoltage Lockout monitors the external
supply voltage VVCC. In case the IC is inactive the
current consumption is max. 55µA. When the SMPS is
plugged to the main line the current through RStart-up
charges the external Capacitor CVCC. When VVCC
exceeds the on-threshold VCCon=13.5V the internal bias
circuit and the voltage reference are switched on. After
it the internal bandgap generates a reference voltage
VREF=6.5V to supply the internal circuits. To avoid
uncontrolled ringing at switch-on a hysteresis is
implemented which means that switch-off is only after
active mode when Vcc falls below 8.5V.
In case of switch-on a Power Up Reset is done by
reseting the internal error-latch in the protection unit.
When VVCC falls below the off-threshold VCCoff=8.5V the
internal reference is switched off and the Power Down
reset let T1 discharging the soft-start capacitor CSoft-Start
at pin SoftS. Thus it is ensured that at every switch-on
the voltage ramp at pin SoftS starts at zero.
Datasheet
Preliminary Data
0 .8 V
D rive r
t
T on
t
Figure 5
Pulse Width Modulation
In case the amplified current sense signal exceeds the
FB signal the on-time Ton of the driver is finished by
reseting the PWM-Latch (see Figure 5).
7
November 2001
CoolSET™-F2
ICE2B165/265/365
Preliminary Specification
Functional Description
The primary current is sensed by the external series
resistor RSense inserted in the source of the integrated
CoolMOS™. By means of Current Mode the regulation
of the secondary voltage is insensitive on line
variations. Line variation causes varition of the
increasing current slope which controls the duty cycle.
The external RSense allows an individual adjustment of
the maximum source current of the integrated
CoolMOS™.
V OSC
m a x.
D u ty C yc le
V olta ge R a m p
t
S oft-S tart C o m p ara to r
P W M C o m pa ra to r
0 .8 V
FB
FB
0 .3 V
P W M -La tch
O s cilla to r
G a te D rive r
0.3V
t
C5
G a te D rive r
V O SC
0.8V
1 0 kΩ
x3 .6 5
R1
T2
C1
V1
2 0p F
t
PW M OP
Figure 7
3.2.1
V oltage Ram p
Figure 6
PWM-OP
The input of the PWM-OP is applied over the internal
leading edge blanking to the external sense resistor
RSense connected to pin ISense. RSense converts the
source current into a sense voltage. The sense voltage
is amplified with a gain of 3.65 by PWM OP. The output
of the PWM-OP is connected to the voltage source V1.
The voltage ramp with the superimposed amplified
current singal is fed into the positive inputs of the PWMComparator, C5 and the Soft-Start-Comparator.
Improved Current Mode
To improve the Current Mode during light load
conditions the amplified current ramp of the PWM-OP
is superimposed on a voltage ramp, which is built by
the switch T2, the voltage source V1 and the 1st order
low pass filter composed of R1 and C1(see Figure 6,
Figure 7). Every time the oscillator shuts down for max.
duty cycle limitation the switch T2 is closed by VOSC.
When the oscillator triggers the Gate Driver T2 is
opened so that the voltage ramp can start.
In case of light load the amplified current ramp is to
small to ensure a stable regulation. In that case the
Voltage Ramp is a well defined signal for the
comparison with the FB-signal. The duty cycle is then
controlled by the slope of the Voltage Ramp.
By means of the C5 Comparator the Gate Driver is
switched-off until the voltage ramp exceeds 0.3V. It
allows the duty cycle to be reduced continously till 0%
by decreasing VFB below that threshold.
Datasheet
Preliminary Data
Light Load Conditions
3.2.2
PWM-Comparator
The PWM-Comparator compares the sensed current
signal of the integrated CoolMOSTM with the feedback
signal VFB (see Figure 8). VFB is created by an external
optocoupler or external transistor in combination with
the internal pullup resistor RFB and provides the load
information of the feedback circuitry. When the
amplified current signal of the integrated CoolMOS™
exceeds the signal VFB the PWM-Comparator switches
off the Gate Driver.
8
November 2001
CoolSET™-F2
ICE2B165/265/365
Preliminary Specification
Functional Description
pullup resistor RSoft-Start. The Soft-Start-Comparator
compares the voltage at pin SoftS at the negative input
with the ramp signal of the PWM-OP at the positive
input. When Soft-Start voltage VSoftS is less than
Feedback voltage VFB the Soft-Start-Comparator limits
the pulse width by reseting the PWM-Latch (see Figure
9). In addition to Start-Up, Soft-Start is also activated at
each restart attempt during Auto Restart. By means of
the above mentioned CSoft-Start the Soft-Start can be
defined by the user. The Soft-Start is finished when
VSoftS exceeds 5.3V. At that time the Protection Unit is
activated by Comparator C4 and senses the FB by
Comparator C3 wether the voltage is below 4.8V which
means that the voltage on the secondary side of the
SMPS is settled. The internal Zener Diode at SoftS with
breaktrough voltage of 5.6V is to prevent the internal
circuit from saturation (see Figure 10).
6 .5 V
S o ft-S ta rt C o m p ara to r
R FB
FB
P W M -L atch
P W M C o m p a rato r
0 .8 V
O p to co u p le r
PW M OP
Ise n se
6 .5 V
x3 .65
R S o ft-S ta rt
Im proved
Current M ode
3.3
E rro r-L a tc h
S o ftS
6 .5 V
5 .3 V
Figure 8
P o w e r-U p R e s e t
5 .6 V
C4
G2
R
Q
S
Q
R
Q
PWM Controlling
4 .8 V
R FB
Soft-Start
FB
C3
G a te
D riv e r
C lo c k
V S oftS
S
Q
P W M -L a tc h
Figure 10
5 .6 V
5 .3 V
The Start-Up time TStart-Up within the converter output
voltage VOUT is settled must be shorter than the SoftStart Phase TSoft-Start (see Figure 11).
T S oft-S tart
G a te D rive r
Activation of Protection Unit
C Soft − Start =
t
T Soft − Start
R Soft − Start × 1, 69
By means of Soft-Start there is an effective
minimization of current and voltage stresses on the
integrated CoolMOS™, the clamp circuit and the output
overshoot and prevents saturation of the transformer
during Start-Up.
t
Figure 9
Soft-Start Phase
The Soft-Start is realized by the internal pullup resistor
RSoft-Start and the external Capacitor CSoft-Start (see
Figure 2). The Soft-Start voltage VSoftS is generated by
charging the external capacitor CSoft-Start by the internal
Datasheet
Preliminary Data
9
November 2001
CoolSET™-F2
ICE2B165/265/365
Preliminary Specification
Functional Description
V S o ftS
kHz
67
f OSC
5 .3 V
T S oft-S ta rt
V FB
20
t
1,0
1,1
1,2
1,3
1,4
1,5
1,6
1,7
1,8
1,9
2
V
V FB
4 .8 V
Figure 12
3.5
V OUT
T S ta rt-U p
t
Start Up Phase
3.4
Oscillator and Frequency
Reduction
3.4.1
Oscillator
3.5.1
The oscillator generates a frequency fswitch = 67kHz. A
resistor, a capacitor and a current source and current
sink which determine the frequency are integrated. The
charging and discharging current of the implemented
oscillator capacitor are internally trimmed, in order to
achieve a very accurate switching frequency. The ratio
of controlled charge to discharge current is adjusted to
reach a max. duty cycle limitation of Dmax=0.72.
3.4.2
Current Limiting
There is a cycle by cycle current limiting realised by the
Current-Limit Comparator to provide an overcurrent
detection. The source current of the integrated
CoolMOSTM is sensed via an external sense resistor
RSense . By means of RSense the source current is
transformed to a sense voltage VSense. When the
voltage VSense exceeds the internal threshold voltage
Vcsth the Current-Limit-Comparator immediately turns
off the gate drive. To prevent the Current Limiting from
distortions caused by leading edge spikes a Leading
Edge Blanking is integrated at the Current Sense.
Furthermore a Propagation Delay Compensation is
added to support the immedeate shut down of the
CoolMOS™ in case of overcurrent.
t
V O UT
Figure 11
Frequency Dependence
Leading Edge Blanking
V S en s e
V c s th
t L E B = 22 0 ns
Frequency Reduction
The frequency of the oscillator is depending on the
voltage at pin FB. The dependence is shown in Figure
12. This feature allows a power supply to operate at
lower frequency at light loads thus lowering the
switching losses while maintaining good cross
regulation performance and low output ripple. In case
of low power the power consumption of the whole
SMPS can now be reduced very effective. The minimal
reachable frequency is limited to 20 kHz to avoid
audible noise in any case.
Datasheet
Preliminary Data
t
Figure 13
Leading Edge Blanking
Each time when CoolMOS™ is switched on a leading
spike is generated due to the primary-side
capacitances and secondary-side rectifier reverse
recovery time. To avoid a premature termination of the
switching pulse this spike is blanked out with a time
constant of tLEB = 220ns. During that time the output of
the Current-Limit Comparator cannot switch off the
gate drive.
10
November 2001
CoolSET™-F2
ICE2B165/265/365
Preliminary Specification
Functional Description
3.5.2
The propagation delay compensation is done by
means of a dynamic threshold voltage Vcsth (see Figure
15). In case of a steeper slope the switch off of the
driver is earlier to compensate the delay.
E.g. Ipeak = 0.5A with RSense = 2 . Without propagation
delay compensation the current sense threshold is set
to a static voltage level Vcsth=1V. A current ramp of
dI/dt = 0.4A/µs, that means dVSense/dt = 0.8V/µs, and a
propagation delay time of i.e. tPropagation Delay =180ns
leads then to a Ipeak overshoot of 12%. By means of
propagation delay compensation the overshoot is only
about 2% (see Figure 16).
Propagation Delay Compensation
In case of overcurrent detection by ILimit the shut down
of CoolMOS™ is delayed due to the propagation delay
of the circuit. This delay causes an overshoot of the
peak current Ipeak which depends on the ratio of dI/dt of
the peak current (see Figure 14).
.
S ig n a l2
S ig n a l1
t P ro pa ga tion D e la y
I S e ns e
I O v ers h oo t2
I p ea k 2
I p ea k 1
I L im it
with compensation
without compensation
V
I O v e rs ho ot1
1,3
1,25
VSense
1,2
t
Figure 14
Current Limiting
dI
peak
dt
1
≤ 1
0,95
0,9
0
Figure 16
3.6
dV Sense
dt
3.7
t
Vcsth
Signal1
Signal2
t
Figure 15
0,6
0,8
1
1,2
1,4
1,6
1,8
2
V
µs
Overcurrent Shutdown
PWM-Latch
Driver
The driver-stage drives the gate of the CoolMOS™
and is optimized to minimize EMI and to provide high
circuit efficiency. This is done by reducing the switch on
slope when reaching the CoolMOS™ threshold. This is
achieved by a slope control of the rising edge at the
driver’s output (see Figure 17).
Thus the leading switch on spike is minimized. When
CoolMOS™ is switched off, the falling shape of the
driver is slowed down when reaching 2V to prevent an
overshoot below ground. Furthermore the driver circuit
is designed to eliminate cross conduction of the output
stage. At voltages below the undervoltage lockout
threshold VVCCoff the gate drive is active low.
off time
Propagation Delay
0,4
The oscillator clock output applies a set pulse to the
PWM-Latch when initiating CoolMOS™ conduction.
After setting the PWM-Latch can be reset by the PWMOP, the Soft-Start-Comparator, the Current-LimitComparator, Comparator C3 or the Error-Latch of the
Protection Unit. In case of reseting the driver is shut
down immediately.
max. Duty Cycle
VSense
0,2
dVSense
dt
So current limiting is now capable in a very accurate
way (see Figure 16).
VOSC
1,1
1,05
The overshoot of Signal2 is bigger than of Signal1 due
to the steeper rising waveform.
A propagation delay compensation is integrated to
bound the overshoot dependent on dI/dt of the rising
primary current. That means the propagation delay
time between exceeding the current sense threshold
Vcsth and the switch off of CoolMOS™ is compensated
over temperature within a range of at least.
0 ≤ R Sense ×
1,15
Dynamic Voltage Threshold Vcsth
Datasheet
Preliminary Data
11
November 2001
CoolSET™-F2
ICE2B165/265/365
Preliminary Specification
Functional Description
V G a te
ca . t = 1 3 0 n s
O verload & O pen loop/norm al load
5µ s B la n king
FB
4 .8 V
F a ilu re
D e te ctio n
5V
t
S o ftS
t
5 .3 V
Figure 17
3.8
Gate Rising Slope
S o ft-S ta rt P h a se
Protection Unit (Auto Restart Mode)
An overload, open loop and overvoltage detection is
integrated within the Protection Unit. These three
failure modes are latched by an Error-Latch. Additional
thermal shutdown is latched by the Error-Latch. In case
of those failure modes the Error-Latch is set after a
blanking time of 5µs and the CoolMOS™ is shut down.
That blanking prevents the Error-Latch from distortions
caused by spikes during operation mode.
3.8.1
t
T B u rs t1
D rive r
T R e s tart
t
Overload & Open loop with normal
load
VC C
1 3 .5 V
Figure 18 shows the Auto Restart Mode in case of
overload or open loop with normal load. The detection
of open loop or overload is provided by the Comparator
C3, C4 and the AND-gate G2 (see Figure19). The
detection is activated by C4 when the voltage at pin
SoftS exceeds 5.3V. Till this time the IC operates in the
Soft-Start Phase. After this phase the comparator C3
can set the Error-Latch in case of open loop or overload
which leads the feedback voltage VFB to exceed the
threshold of 4.8V. After latching VCC decreases till
8.5V and inactivates the IC. At this time the external
Soft-Start capacitor is discharged by the internal
transistor T1 due to Power Down Reset. When the IC
is inactive VVCC increases till VCCon = 13.5V by charging
the Capacitor CVCC by means of the Start-Up Resistor
RStart-Up. Then the Error-Latch is reset by Power Up
Reset and the external Soft-Start capacitor CSoft-Start is
charged by the internal pullup resistor RSoft-Start . During
the Soft-Start Phase which ends when the voltage at
pin SoftS exceeds 5.3V the detection of overload and
open loop by C3 and G2 is inactive. In this way the Start
Up Phase is not detected as an overload.
8 .5 V
t
Figure 18
Auto Restart Mode
6.5 V
P o w e r U p R e se t
S o ftS
R S oft-S tart
C S oft-S tart
C4
5 .3 V
E rro r-L a tch
G2
T1
4 .8V
C3
FB
R FB
6 .5 V
Figure 19
Datasheet
Preliminary Data
12
FB-Detection
November 2001
Preliminary Specification
CoolSET™-F2
ICE2B165/265/365
Functional Description
detection due to varying of VCC concerning the
regulation of the converter output. When the voltage
VSoftS is above 4.0V the overvoltage detection by C1 is
deactivated.
But the Soft-Start Phase must be finished within the
Start Up Phase to force the voltage at pin FB below the
failure detection threshold of 4.8V.
3.8.2
Overvoltage due to open loop with
no load
VCC
O pen loop & no load conditio n
FB
5 µs B la n kin g
6 .5 V
4 .0 V
C2
S o ftS
t
S o ft-S ta rt P ha se
S o ftS
E rro r L a tch
G1
R S o ft-S ta rt
F ailure
D ete ction
C S o ft-S ta rt
T1
5 .3V
4 .0V
C1
1 6 .5 V
4 .8V
P o w e r U p R e se t
O v erv olta g e
D e te ction P ha se
Figure 21
D rive r
Overvoltage Detection
t
T B urs t2
3.8.3
T R es ta rt
Thermal Shut Down
Thermal Shut Down is latched by the Error-Latch when
junction temperature Tj of the pwm controller is
exceeding an internal threshold of 140°C. In that case
the IC switches in Auto Restart Mode.
O ve rvo ltag e D ete ctio n
t
VCC
1 6.5 V
1 3.5 V
8.5 V
t
Figure 20
Auto Restart Mode
Figure 20 shows the Auto Restart Mode for open loop
and no load condition. In case of this failure mode the
converter output voltage increases and also VCC. An
additional protection by the comparators C1, C2 and
the AND-gate G1 is implemented to consider this
failure mode (see Figure 21).The overvoltage detection
is provided by Comparator C1 only in the first time
during the Soft-Start Phase till the Soft-Start voltage
exceeds the threshold of the Comparator C2 at 4.0V
and the voltage at pin FB is above 4.8V. When VCC
exceeds 16.5V during the overvoltage detection phase
C1 can set the Error-Latch and the Burst Phase during
Auto Restart Mode is finished earlier. In that case
TBurst2 is shorter than TSoft-Start . By means of C2 the
normal operation mode is prevented from overvoltage
Datasheet
Preliminary Data
Note:
13
All the values which are mentioned in the
functional description are typical. Please refer
to Electrical Characteristics for min/max limit
values.
November 2001
CoolSET™-F2
ICE2B165/265/365
Preliminary Specification
Electrical Characteristics
4
Electrical Characteristics
4.1
Absolute Maximum Ratings
Note:
Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction
of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 6
(VCC) is discharged before assembling the application circuit.
Parameter
Symbol
Limit Values
min.
max.
Unit
Remarks
Tj=110°C
Drain Source Voltage
VDS
-
650
V
ICE2B165
Avalanche energy,
repetitive tAR limited by
ICE2B265
max. Tj=150°C1)
ICE2B365
EAR1
-
0.1
mJ
EAR2
-
0.4
mJ
EAR3
-
0.5
mJ
ICE2B165
Avalanche current,
repetitive tAR limited by
ICE2B265
max. Tj=150°C1)
ICE2B365
IAR1
-
1
A
IAR2
-
2
A
IAR3
-
3
A
VCC Supply Voltage
VCC
-0.3
22
V
FB Voltage
VFB
-0.3
6.5
V
SoftS Voltage
VSoftS
-0.3
6.5
V
ISense
ISense
-0.3
3
V
Junction Temperature
Tj
-40
150
°C
Storage Temperature
TS
-50
150
°C
Thermal Resistance
Junction-Ambient
RthJA
-
90
K/W
P-DIP-8-6
ESD Capability2)
VESD
-
2
kV
Human Body Model
Controller & CoolMOS™
1)
Repetetive avalanche causes additional power losses that can be calculated as PAV=EAR*f
2)
Equivalent to discharging a 100pF capacitor through a 1.5 kΩ series resistor
4.2
Note:
Operating Range
Within the operating range the IC operates as described in the functional description.
Parameter
Symbol
Limit Values
min.
max.
Unit
VCC Supply Voltage
VCC
VCCoff
21
V
Junction Temperature of
Controller
TJCon
-25
130
°C
Junction Temperature of
CoolMOS™
TJCoolMOS
-25
150
°C
Datasheet
Preliminary Data
14
Remarks
limited due to thermal shut down of
controller
November 2001
CoolSET™-F2
ICE2B165/265/365
Preliminary Specification
Electrical Characteristics
4.3
Note:
4.3.1
Characteristics
The electrical characteristics involve the spread of values guaranteed within the specified supply voltage
and junction temperature range TJ from – 25 °C to 125 °C.Typical values represent the median values,
which are related to 25°C. If not otherwise stated, a supply voltage of VCC = 15 V is assumed.
Supply Section
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
Start Up Current
IVCC1
-
27
55
µA
VCC=VCCon -0.1V
Supply Current with Inactiv
Gate
IVCC2
-
5.0
6.6
mA
VSoftS = 0
IFB = 0
Supply Current
with Activ Gate
ICE2B165
IVCC3
-
5.5
7.0
mA
VSoftS = 5V
IFB = 0
ICE2B265
IVCC3
-
6.1
7.3
mA
VSoftS = 5V
IFB = 0
ICE2B365
IVCC3
-
7.1
8.3
mA
VSoftS = 5V
IFB = 0
VCCon
VCCoff
VCCHY
13
4.5
13.5
8.5
5
14
5.5
V
V
V
VCC Turn-On Threshold
VCC Turn-Off Threshold
VCC Turn-On/Off Hysteresis
4.3.2
Internal Voltage Reference
Parameter
Trimmed Reference Voltage
4.3.3
Symbol
VREF
Limit Values
min.
typ.
max.
6.37
6.50
6.63
Unit
Test Condition
V
measured at pin FB
Unit
Test Condition
Control Section
Parameter
Symbol
Limit Values
min.
typ.
max.
Oscillator Frequency
fOSC1
62
67
72
kHz
VFB = 4V
Reduced Osc. Frequency
fOSC2
-
20
-
kHz
VFB = 1V
3.18
3.35
3.53
Frequency Ratio fosc1/fosc2
Max Duty Cycle
Dmax
0.67
0.72
0.77
Min Duty Cycle
Dmin
0
-
-
PWM-OP Gain
AV
3.45
3.65
3.85
Datasheet
Preliminary Data
15
VFB < 0.3V
November 2001
CoolSET™-F2
ICE2B165/265/365
Preliminary Specification
Electrical Characteristics
Max. Level of Voltage Ramp
-
0.80
-
V
VFB Operating Range Min Level VFBmin
0.3
-
-
V
VFB Operating Range Max level VFBmax
-
-
4.6
V
Feedback Resistance
RFB
3.0
3.7
4.9
kΩ
Soft-Start Resistance
RSoft-Start
42
50
62
kΩ
4.3.4
VMax-Ramp
Protection Unit
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
Over Load & Open Loop
Detection Limit
VFB2
4.65
4.8
4.95
V
VSoftS > 5.5V
Activation Limit of Overload &
Open Loop Detection
VSoftS1
5.15
5.3
5.46
V
VFB > 5V
Deactivation Limit of
Overvoltage Detection
VSoftS2
3.88
4.0
4.12
V
VFB > 5V
VCC > 17.5V
Overvoltage Detection Limit
VVCC1
16
16.5
17.2
V
VSoftS < 3.8V
VFB
> 5V
Latched Thermal Shutdown
TjSD
130
140
150
°C
guaranteed by design
Spike Blanking
tSpike
-
5
-
µs
4.3.5
Current Limiting
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Condition
dVsense / dt = 0.6V/µs
Peak Current Limitation (incl.
Propagation Delay Time)
(see Figure 7)
Vcsth
0.95
1.00
1.05
V
Leading Edge Blanking
tLEB
-
220
-
ns
4.3.6
CoolMOS™ Section
Parameter
Symbol
Drain Source Breakdown Voltage V(BR)DSS
Datasheet
Preliminary Data
Limit Values
min.
typ.
max.
600
650
-
-
16
Unit
Test Condition
V
V
Tj=25°C
Tj=110°C
November 2001
CoolSET™-F2
ICE2B165/265/365
Preliminary Specification
Electrical Characteristics
ICE2B165
RDSon1
-
3
6.6
3.3
7.3
Ω
Ω
Tj=25°C
Tj=125°C
ICE2B265
RDSon2
-
0.9
1.9
1.08
2.28
Ω
Ω
Tj=25°C
Tj=125°C
ICE2B365
RDSon3
-
0.45
0.95
0.54
1.14
Ω
Ω
Tj=25°C
Tj=125°C
ICE2B165
Effective output
capacitance, energy
ICE2B265
related
ICE2B365
Co(er)1
-
7
-
pF
VDS =0V to 480V
Co(er)2
-
21
-
pF
VDS =0V to 480V
Co(er)3
-
30
-
Zero Gate Voltage Drain Current
IDSS
-
0.5
Drain Source
On-Resistance
Rise Time
Fall Time
1)
trise
tfall
-
-
µA
1)
-
ns
1)
-
ns
30
-
VDS =0V to 480V
30
VVCC=0V
Measured in a Typical Flyback Converter Application
Datasheet
Preliminary Data
17
November 2001
CoolSET™-F2
ICE2B165/265/365
Preliminary Specification
Typical Performance Characteristics
Typical Performance Characteristics
40
VCC Turn-On Threshold V CCon [V]
13,58
36
34
32
PI-001-190101
Start Up Current I VCC1 [µA]
38
30
28
26
24
22
-25 -15
-5
5
15
25
35
45
55
65
75
85
95
13,56
13,54
13,52
13,50
13,48
13,46
13,44
13,42
-25 -15
105 115 125
PI-004-190101
5
-5
5
Start Up Current IVCC1 vs. Tj
Figure 25
VCC Turn-Off Threshold V VCCoff [V]
5,7
5,4
5,1
4,8
-5
5
15
25
35
45
55
65
75
85
95 105 115 125
65
75
85
95 105 115 125
8,64
8,61
8,58
8,55
8,52
8,49
8,46
8,43
8,40
-25 -15
Figure 26
-5
5
ICE2B365
8,2
7,8
PI-002-190101
7,4
7,0
ICE2B265
6,6
ICE2B165
6,2
5,8
5,4
-25 -15 -5
5
15 25 35 45 55 65 75 85 95 105 115 125
25
35
45
55
65
75
85
95 105 115 125
VCC Turn-Off Threshold VVCCoff vs. Tj
5,10
5,07
5,04
5,01
4,98
4,95
4,92
4,89
4,86
4,83
-25 -15
Junction Temperature [°C]
-5
5
15
25
35
45
55
65
75
85
95 105 115 125
Junction Temperature [°C]
Figure 27
Supply Current IVCC3 vs. Tj
Datasheet
Preliminary Data
15
PI-006-190101
VCC Turn-On/Off Hysteresis V CCHY [V]
Static Supply Current IVCC2 vs. Tj
8,6
Supply Current I VCC3 [mA]
55
Junction Temperature [°C]
9,0
Figure 24
45
VCC Turn-On Threshold VVCCon vs. Tj
Junction Temperature [°C]
Figure 23
35
8,67
PI-003-190101
Supply Current IVCC2 [mA]
6,0
4,5
-25 -15
25
PI-005-190101
Figure 22
15
Junction Temperature [°C]
Junction Temperature [°C]
18
VCC Turn-On/Off HysteresisVVCCHY vs. Tj
November 2001
CoolSET™-F2
ICE2B165/265/365
Preliminary Specification
3,45
6,54
3,43
6,53
6,52
6,51
6,50
6,49
6,48
6,47
6,46
6,45
-25 -15
-5
5
15
25
35
45
55
65
75
85
3,41
3,39
3,37
3,35
3,33
3,31
3,29
3,27
3,25
-25 -15
95 105 115 125
PI-010a-190101
Frequency Ratio f OSC1/fOSC2
6,55
PI-007-190101
Trimmed Reference Voltage V REF [V]
Typical Performance Characteristics
-5
5
Junction Temperature [°C]
Trimmed Reference VREF vs. Tj
Figure 31
70,0
0,730
69,5
0,728
69,0
35
45
55
65
75
85
95 105 115 125
Frequency Ratio fOSC1 / fOSC2 vs. Tj
0,726
67,5
67,0
66,5
66,0
65,5
0,724
0,722
PI-011-190101
Max. Duty Cycle
68,0
0,720
0,718
0,716
0,714
65,0
0,712
64,5
64,0
-25 -15
-5
5
15
25
35
45
55
65
75
85
0,710
-25 -15
95 105 115 125
-5
5
Oscillator Frequency fOSC1 vs. Tj
Figure 32
3,70
20,8
3,69
20,6
3,68
20,4
3,67
PWM-OP Gain AV
21,0
PI-009a-190101
20,2
20,0
19,8
19,6
25
35
45
55
65
75
85
3,60
-25 -15
95 105 115 125
Reduced Osc. Frequency fOSC2 vs. Tj
Datasheet
Preliminary Data
75
85
95 105 115 125
85
95 105 115 125
Max. Duty Cycle vs. Tj
-5
5
15
25
35
45
55
65
75
Junction Temperature [°C]
Junction Temperature [°C]
Figure 30
65
3,63
3,61
15
55
3,64
3,62
5
45
3,65
19,2
-5
35
3,66
19,4
19,0
-25 -15
25
PI-012-190101
Figure 29
15
Junction Temperature [°C]
Junction Temperature [°C]
Reduced Osc. Frequency f OSC2 [kHz]
25
68,5
PI-008a-190101
Oscillator Frequency f OSC1 [kHz]
Figure 28
15
Junction Temperature [°C]
Figure 33
19
PWM-OP Gain AV vs. Tj
November 2001
CoolSET™-F2
ICE2B165/265/365
Preliminary Specification
Typical Performance Characteristics
5,31
[V]
3,95
3,85
3,80
3,70
Detection Limit V
3,75
3,65
3,60
3,55
3,50
-25 -15
-5
5
15
25
35
45
55
65
75
85
PI-016-190101
Soft-Start1
3,90
PI-013-190101
Feedback Resistance R FB [kOhm]
4,00
5,30
5,29
-25 -15 -5
95 105 115 125
5
Feedback Resistance RFB vs. Tj
Figure 37
58
[V]
52
50
Detection Limit V
48
46
44
42
-5
5
15
25
35
45
55
65
75
85
95
PI-017-190101
Soft-Start2
54
40
-25 -15
Detection Limit VSoft-Start1 vs. Tj
4,01
56
PI-014-190101
Soft-Start Resistance R Soft-Start [kOhm]
Figure 34
4,00
3,99
-25 -15 -5
105 115 125
5
Figure 38
Overvoltage Detection Limit V VCC1 [V]
4,83
4,82
4,81
PI-015-190101
Detection Limit V FB2 [V]
4,84
4,80
4,79
4,78
4,77
4,76
-5
5
15
25
35
45
55
65
75
85
95 105 115 125
16,80
16,75
16,70
16,65
16,60
16,55
16,50
16,45
16,40
16,35
16,30
16,25
16,20
-25 -15
Detection Limit VFB2 vs. Tj
Datasheet
Preliminary Data
-5
5
15
25
35
45
55
65
75
85
95 105 115 125
Junction Temperature [°C]
Junction Temperature [°C]
Figure 36
Detection Limit VSoft-Start2 vs. Tj
PI-018-190101
Soft-Start Resistance RSoft-Start vs. Tj
4,85
4,75
-25 -15
15 25 35 45 55 65 75 85 95 105 115 125
Junction Temperature [°C]
Junction Temperature [°C]
Figure 35
15 25 35 45 55 65 75 85 95 105 115 125
Junction Temperature [°C]
Junction Temperature [°C]
Figure 39
20
Overvoltage Detection Limit VVCC1 vs. Tj
November 2001
CoolSET™-F2
ICE2B165/265/365
Preliminary Specification
Typical Performance Characteristics
800
1,006
1,004
1,002
1,000
0,998
0,996
0,994
0,992
0,990
-25 -15
-5
5
15
25
35
45
55
65
75
85
750
700
650
550
500
450
-5
5
15
25
35
45
55
65
75
85
95 105 115 125
Junction Temperature [°C]
Junction Temperature [°C]
Figure 40
ICE2B165
ICE2B265
ICE2B365
600
400
-25 -15
95 105 115 125
PI-025-190101
Breakdown Voltage V(BR)DSS [V]
1,008
PI-019-190101
Peak Current Limitation V csth [V]
1,010
Peak Current Limitation Vcsth vs. Tj
Figure 43
Breakdown Voltage VBR(DSS) vs. Tj
270
260
250
240
PI-020-190101
Leading Edge Blanking t LEB [ns]
280
230
220
210
200
190
180
-25 -15
-5
5
15
25
35
45
55
65
75
85
95 105 115 125
Junction Temperature [°C]
Figure 41
Leading Edge Blanking VVCC1 vs. Tj
3,0
ICE2B165
2,7
2,4
2,1
PI-022-190101
On-Resistance R dson [Ohm]
3,3
1,8
1,5
1,2
ICE2B265
0,9
0,6
ICE2B365
0,3
0,0
-25 -15
-5
5
15
25
35
45
55
65
75
85
95 105 115 125
Junction Temperature [°C]
Figure 42
Drain Source On-Resistance RDSon vs. Tj
Datasheet
Preliminary Data
21
November 2001
Preliminary Specification
CoolSET™-F2
ICE2B165/265/365
Outline Dimension
6
Outline Dimension
P-DIP-8-6
(Plastic Dual In-line
Package)
Figure 44
Dimensions in mm
Datasheet
Preliminary Data
22
November 2001
Total Quality Management
Qualität hat für uns eine umfassende
Bedeutung. Wir wollen allen Ihren
Ansprüchen in der bestmöglichen
Weise gerecht werden. Es geht uns also
nicht nur um die Produktqualität –
unsere
Anstrengungen
gelten
gleichermaßen der Lieferqualität und
Logistik, dem Service und Support
sowie allen sonstigen Beratungs- und
Betreuungsleistungen.
Dazu
gehört
eine
bestimmte
Geisteshaltung unserer Mitarbeiter.
Total Quality im Denken und Handeln
gegenüber Kollegen, Lieferanten und
Ihnen, unserem Kunden. Unsere
Leitlinie ist jede Aufgabe mit „Null
Fehlern“ zu lösen – in offener
Sichtweise auch über den eigenen
Arbeitsplatz hinaus – und uns ständig
zu verbessern.
Unternehmensweit orientieren wir uns
dabei auch an „top“ (Time Optimized
Processes), um Ihnen durch größere
Schnelligkeit
den
entscheidenden
Wettbewerbsvorsprung zu verschaffen.
Geben Sie uns die Chance, hohe
Leistung durch umfassende Qualität zu
beweisen.
Wir werden Sie überzeugen.
http://www.infineon.com
Published by Infineon Technologies AG
Quality takes on an allencompassing
significance at Semiconductor Group.
For us it means living up to each and
every one of your demands in the best
possible way. So we are not only
concerned with product quality. We
direct our efforts equally at quality of
supply and logistics, service and
support, as well as all the other ways in
which we advise and attend to you.
Part of this is the very special attitude of
our staff. Total Quality in thought and
deed, towards co-workers, suppliers
and you, our customer. Our guideline is
“do everything with zero defects”, in an
open manner that is demonstrated
beyond your immediate workplace, and
to constantly improve.
Throughout the corporation we also
think in terms of Time Optimized
Processes (top), greater speed on our
part to give you that decisive
competitive edge.
Give us the chance to prove the best of
performance through the best of quality
– you will be convinced.