SC652 Clock Generator for Pentium Based Designs W/2 DIMM Support Approved Product FREQUENCY TABLE PRODUCT FEATURES SEL1 SEL0 CPU PCI n Supports Pentium series, 6X86 and K6 CPUs. 0 0 55.0 27.5 n Supports Intel VIA, SiS and Opti chipset 0 1 75.0 37.5 requirements. 1 0 60.0 30.0 n Supports Sychronous DRAM designs 1 1 66.6 33.3 n 4 host (CPU/AGP) clocks & 8 SDRAM clocks. n Optional common or mixed supply mode : CONNECTION DIAGRAM (Vdd = Vddq3 = Vddq4 = Vddq2 = 3.3V) (Vdd = Vddq3 = Vddq4 = 3.3V, Vddq2 = 2.5V) n < 250 pS skew on CPU buffers n < 250 pS skew on PCI buffers n Supports Single Pin Power Management. n 48 Pin SSOP package for minimum board space BLOCK DIAGRAM Buffers Xin Xout REF OSC 3 REF0,1,2 Vddq2 IOAPIC Buffer Vddq2 4 PWR_DWN# SEL0,1 CPUCLK0~3 PLL1 dly 8 Buffers 6 1 48 REF0 2 47 REF2 Vss 3 46 Vddq2 Vdd Xin 4 45 IOAPIC Xout 5 44 PWR_DWN# N/C 6 43 Vss Vddq4 7 42 CPUCLK0 PCICLK_F 8 41 CPUCLK1 PCICLK0 9 40 Vddq2 Vss 10 39 CPUCLK2 PCICLK1 11 38 CPUCLK3 PCICLK2 12 37 Vss PCICLK3 13 36 SDRAM0 PCICLK4 14 35 SDRAM1 Vddq4 15 34 Vddq3 PCICLK5 16 33 SDRAM2 Vss 17 32 SDRAM3 SEL0 18 31 Vss SDRAM0~7 SEL1 19 30 SDRAM4 N/C 20 29 SDRAM5 PCICLK0~5 Vddq4 21 28 Vddq3 48MHZ 22 27 SDRAM6 24MHZ 23 26 SDRAM7 Vss 24 25 Vdd Buffers Vddq3 REF1 Buffers PCICLK_F Buffer Vddq4 Buffer 48MHZ PLL2 Buffer 24MHZ INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.2 4/24/97 Page 1 of 6 SC652 Clock Generator for Pentium Based Designs W/2 DIMM Support Approved Product PIN DESCRIPTION Xin, Xout - These pins form an on-chip reference REF(0:2) - Buffered outputs of reference 14.3MHZ. oscillator when connected to terminals of an external parallel resonant crystal (nominally 14.318 MHz). Xin IOAPIC - Buffered output of 14.3MHZ may also serve as input for an externally generated multiprocessor support. It is powered by Vddq2. for reference signal. 48MHz - Frequency output for USB. SEL(0:1) - Standard frequency select inputs. They have 24MHz - Frequency output for super I/O. internal pull-ups. CPUCLK(0:3) - Low skew (<250 pS) clock outputs for PWR_DWN# - Power down pin to turn the power of the host frequencies such as CPU, Chipset, Cache. Vddq2 whole chip down including the VCOs and the PCICLK_F is the supply voltage for these outputs. output pin. It has an internal pull-up SDRAM(0:7) - Synchronous DRAM DIMs clocks. They Vss - Ground pins for the chip. are powered by Vddq3. Vdd - Power supply pins for analog circuit and core PCICLK(0:5) - Low skew (<250pS) clock outputs for PCI frequencies. logic. These buffers voltage level is controlled by Vddq3. Vddq3 - Power supply pins for 3.3V IO pins. PCICLK_F - A PCI clock output that does not stop until Vddq2 - Power supply pins for 2.5V/3.3V IO pins. in power down mode. It is synchronous with other PCI clocks. N/C - No connection pins. POWER MANAGEMENT FUNCTIONS The IMISC652 clocks may be disabled using the PWR_DWN# pin in order to reduce power consumption. All clocks are stopped in the low state. All clocks maintain a valid high period on transitions from running to stopped. When powered down, the reference oscillator and VCOs are stopped. On low to high transitions of PWR_DWN#, external circuitry should allow 3 mS for the VCOs to stabilize prior to assuming the pulse widths are correct. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.2 4/24/97 Page 2 of 6 SC652 Clock Generator for Pentium Based Designs W/2 DIMM Support Approved Product MAXIMUM RATINGS This device contains circuitry to protect the inputs against damage due to high static voltages or electric Voltage Relative to VSS: Voltage Relative to VDD: -0.3V field; however, precautions should be taken to avoid 0.3V application of any voltage higher than the maximum Storage Temperature: -65ºC to + 150ºC rated voltages to this circuit. For proper operation, Vin Ambient Temperature: -55ºC to +125ºC and Vout should be constrained to the range: Maximum Power Supply: 7V VSS<(Vin or Vout)<VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). ELECTRICAL CHARACTERISTICS Characteristic Symbol Min Typ Max Units Conditions Input Low Voltage VIL - - 0.8 Vdc - Input High Voltage VIH 2.0 - Input Low Current IIL - Vdc - -66 µA Input High Current IIH 5 µA Output Low Current IOL1 61 - - mA VOL1 = 1.6V (@ CPU, SDRAM, PCI, IOAPIC and REF0 clocks) Output High Current IOH1 61 - - mA VOH1 = 1.0V (@ CPU, SDRAM, PCI, IOAPIC and REF0 clocks) Output Low Current IOL2 42 - - mA VOL2 = 1.9V (@ 48Mhz, 24 Mhz, REF2 and REF1 clocks) Output High Current IOH2 40 - - mA VOH2 = 1.0V (@ 48Mhz, 24 Mhz, REF2 and REF1 clocks) Tri-State leakage Current Ioz - - 10 µA Dynamic Supply Current Idd - 40 - mA CPU = 66.6 Mhz, No Load Static Supply Current Idd - 200 - µA PWR_DWN# = Low Short Circuit Current ISC 25 - - mA 1 output at a time - 30 seconds VDD = VDDq2 = VDDq3 = 3.3V+5%, TA = 0ºC to +70ºC Contact IMI for IBIS models. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.2 4/24/97 Page 3 of 6 SC652 Clock Generator for Pentium Based Designs W/2 DIMM Support Approved Product SWITCHING CHARACTERISTICS Characteristic Output Rise (0.4V - 2.0V) and Fall (2.0V-0.4V) time Output Duty Cycle Symbol Min Typ Max tTLH, tTHL - - 1.6 Units ns Conditions 22 pf Load CPU and PCI outputs - 45 50 55 % Measured at 1.5V tOFF 1 - 4 ns 15 pf Load Measured at 1.5V Skew (CPU-CPU), (PCIPCI), (SDRAM-SDRAM) tSKEW1 - - 250 ps 15 pf Load Measured at 1.5V Skew (CPU-SDRAM) tSKEW2 - - 500 ps 15 pf Load Measured at 1.5V ∆P - - +250 ps - 500 ps - 1.5 V 22 ohms @ source of 8 inch PCB run to 15 pf load 2.1 V note1 CPU/SDRAM to PCI Offset ∆Period Cycles, CPU Jitter Absolute, CPU tjab - Overshoot/Undershoot Beyond Power Rails Vover - Ring Back Exclusion VRBE 0.7 - VDD = VDDq2 = VDDq3 = 3.3V+5%, TA = 0ºC to +70ºC note 1: Ring Back must not enter this range. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.2 4/24/97 Page 4 of 6 SC652 Clock Generator for Pentium Based Designs W/2 DIMM Support Approved Product PCB LAYOUT RECOMMENDATION Via to VDD Island Via to GND plane Via to VCC plane VCC1 IMISC652 FB1 C3 10µF C4 C5 C6 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 C12 C11 FB2 VCC2 C10 C13 10µF C9 C8 C7 This is only a layout recommendation for best performance and lower EMI. The designer may choose a differnent approach but C4, C5, C6, C7, C8, C9, C10, C11and C12 (all are 0.1µf) should always be used and placed close to their VDD pins. PACKAGE DRAWING AND DIMENSIONS INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.2 4/24/97 Page 5 of 6 SC652 Clock Generator for Pentium Based Designs W/2 DIMM Support Approved Product 48 PIN SSOP OUTLINE DIMENSIONS INCHES C SYMBOL L H E D a A2 A1 e B NOM MAX MIN NOM MAX A 0.095 0.102 0.110 2.41 2.59 2.79 A1 0.008 0.012 0.016 0.20 0.31 0.41 A2 0.088 0.090 0.092 2.24 2.29 2.34 B 0.008 0.010 0.0135 0.203 0.254 0.343 C 0.005 - 0.010 0.127 - 0.254 D 0.620 0.625 0.630 15.75 15.88 16.00 E 0.292 0.296 0.299 7.42 7.52 7.59 e A MILLIMETERS MIN 0.025 BSC 0.635 BSC H 0.400 0.406 0.410 10.16 10.31 10.41 a 0.10 0.013 0.016 0.25 0.33 0.41 L 0.024 0.032 0.040 0.61 0.81 1.02 a 0º 5º 8º 0º 5º 8º X 0.085 0.093 0.100 2.16 2.36 2.54 ORDERING INFORMATION Part Number Package Type IMISC652EYB 48 PIN SSOP Note: Production Flow Commercial, 0ºC to +70ºC The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Marking: Example: IMI SC652EYB Date Code, Lot # IMISC652EYB Flow B = Commercial, 0ºC to + 70ºC Package Y = SSOP Revision IMI Device Number INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.2 4/24/97 Page 6 of 6