Pentium II, System Clock Generator with 2 DIMM Support and SSCG Approved Product FREQUENCY TABLE (MHz) PRODUCT FEATURES SELECTORS n Supports Pentium, Pentium II, Pentium-Pro, AMD and Cyrix CPUs. n Supports Intel chipset requirements. n Supports Sychronous DRAM designs n 4 host (CPU/AGP) clocks & 8 SDRAM clocks. n Optional common or mixed supply mode : n (Vdd = Vdd3 = Vdd4 = Vdd2 = 3.3V) (Vdd = Vdd3 = Vdd4 = 3.3V, Vdd2 = 2.5V) < 250 pS skew on CPU buffers n < 250 pS skew on PCI buffers n Supports Single Pin Power Management. n Integrates Spread Spectrum Technology for reduced EMI. n 48 Pin SSOP package for minimum board space BLOCK DIAGRAM XIN B REF(1:3) 3 REF XOUT IOAPIC Vdd2 S1 S0 SSon B Spread Spectrum PLL1 B 4 8 CPUCLK(1:4) SDRAM (1:8) PCICLK_F dly B 6 OUTPUTS (MHz) S1 S0 CPU PCI 0 0 1 1 0 1 0 1 55.00 75.01 59.99 66.60 27.50 37.50 30.00 33.30 CONNECTION DIAGRAM REF2 REF1 Vss Xin Xout Test Vdd4 PCICLK_F PCICLK1 Vss PCICLK2 PCICLK3 PCICLK4 PCICLK5 Vdd4 PCICLK6 Vss S0 S1 SSon Vdd4 48 MHz 24 Mhz Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Vdd REF3 Vdd2 IOAPIC PWR_DWN# Vss CPUCLK1 CPUCLK2 Vdd2 CPUCLK3 CPUCLK4 Vss SDRAM1 SDRAM2 Vdd3 SDRAM3 SDRAM4 Vss SDRAM5 SDRAM6 Vdd3 SDRAM7 SDRAM8 Vdd PCICLK(1:6) PWR_DWN# PLL2 24 MHz 48 MHz INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.3 4/8/97 Page 1 of 8 SG552 Pentium II, System Clock Generator with 2 DIMM Support and SSCG Approved Product PIN DESCRIPTION PIN No. Pin Name Power I/O TYPE Description 4 Xin Vdd I OSC1 5 Xout Vdd O OSC1 18, 19 42, 41, 39, 38 36, 35, 33, 32, 30, 29, 27, 26 43, 37, 31, 24, 17, 10. 3 48, 25 46, 40 34, 28 21, 15, 7 23 22 1,2,47 20 S(0:1) CPU(1:4) Vdd2 I O pullup Type1 SDRAM(1:8) Vdd3 O Type4 On-chip reference oscillator input pin. Requires either an external parallel resonant crystal (nominally 14.318 MHz) or externally generated reference signal On chip reference oscillator output pin. Drives an external parallel resonant crystal. When an externally generated reference signal is used, this pin is left unconnected Frequency select input pins. See page 1 for frequency selection. Clock outputs. CPU frequency table specified. Power is applied by Vdd2 pin. Synchronous Dynamic RAM clocks. Same Frequency as CPU clocks. GND - P Ground pins for the device. Vdd Vdd2 Vdd3 Vdd4 24MHz 48MHZ REF(1:3) SSon Vdd4 Vdd4 Vdd4 Vdd4 P P P Power supply pins for analog circuit , Fixed clocks and core logic Power supply pins for 2.5V/3.3V CPU pins. Power supply pins for 3.3V PCI and SDRAM pins. O O O I Type3 Type3 Type4 pullup 9, 11, 12, 13, 14, 16 8 45 PCICLK(1:6) Vdd4 O Type5 PCICLK_F IOAPIC Vdd4 Vdd2 O O Type5 Type2 44 PWR_DWN# - I 6 TEST Pullup inside Pulllow Inside 1 Frequency output for super I/O. Frequency output for USB. Buffered output of on-chip 14.31818 Mhz reference oscillator. Spread Spectrum enable pin. When this pin is High (default), it enables the Spread Spectrum of 3% down modulation. When Low, spread spectrum is dsabled. This pin has an internal pull-up. PCI clock outputs. See frequency table PCI clock outputs. See frequency table. - Buffered output of 14.3MHZ for multiprocessor support. It is powered by Vdd2 Power down pin to turn the power of the whole chip down including the VCOs. This pin is reserved for IMI testing. It is active High. It has an internal pull down. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.3 4/8/97 Page 2 of 8 SG552 Pentium II, System Clock Generator with 2 DIMM Support and SSCG Approved Product POWER MANAGEMENT FUNCTION The device clocks may be disabled using the PWR_DWN# pin in order to reduce power consumption. All clocks are stopped in the low state. All clocks maintain a valid high period on transitions from running to stopped. When powered down, the reference oscillator and VCOs are stopped. On low to high transitions of PWR_DWN#, external circuitry should allow 2 mS for the VCOs to stabilize prior to assuming the pulse widths are correct. SPREAD SPECTRUM (SSCG) The device integrates a Spread Spectrum Clock Generation (SSCG) technology for the purpose of reducing EMI at the fundamental frequency and its harmonics. SSCG utilizes a modulation technique for redistributing the energy generated by a repetitive signal (a clock). Generally, the energy is accumulated at the center of the clock frequency, consequently disseminating Electro-Magnetic Interference (EMI) from the system. The Spread Spectrum technique reduces EMI by distributing this energy over a small bandwidth as shown in fig.2. The bandwidth size of this modulation is -3.0 percent of the resting frequency. Spectrum Analysis Amplitude (dB) Without Spread Spectrum With Spread Spectrum Modulation Bandwidth Down Spread Frequency(MHz) Center, without SSCG Shifted Center, with SSCG INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.3 4/8/97 Page 3 of 8 SG552 Pentium II, System Clock Generator with 2 DIMM Support and SSCG Approved Product MAXIMUM RATINGS Voltage Relative to VSS: Voltage Relative to VDD: Storage Temperature: Ambient Temperature: Maximum Power Supply: This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS<(Vin or Vout)<VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). -0.3V 0.3V -65ºC to + 150ºC -55ºC to +125ºC 7V SWITCHING CHARACTERISTICS Characteristic Symbol Output Duty Cycle CPU to PCI Offset Buffer out Skew All CPU and PCI Buffer Outputs ∆Period Adjacent Cycles Jitter Spectrum 20 dB Bandwidth from Center Min Typ Max Units Conditions tOFF tSKEW 45 1 - 50 - 55 4 250 % ns ps Measured at 1.5V 15 pf Load Measured at 1.5V 15 pf Load Measured at 1.5V ∆P BWJ - - +250 ps - 500 KHz VDD = VDD3 =3.3V ±5%, VDD2 = 2.375V to 2.9V, TA = 0ºC to +70ºC note 1: Ring Back must not enter this range. TYPE 1 BUFFER CHARACTERISTICS FOR CPUCLK(1:4) Characteristic Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise Time Between 0.4 V and 2.0 V Fall Time Between 0.4 V and 2.0 V Symbol Min IOHmin IOHmax IOLmin IOLmax TR TF -27 27 0.4 0.4 Typ Max Units - -36 27 1.6 1.6 mA mA mA mA nS nS Conditions Vout = 1.0 V Vout = 2.5 V Vout = 1.2 V Vout = 0.3 V 20 pF Load 20 pF Load VDD = VDD3 =3.3V ±5%, VDD2 = 2.5V +/-5%, TA = 0ºC to +70ºC INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.3 4/8/97 Page 4 of 8 SG552 Pentium II, System Clock Generator with 2 DIMM Support and SSCG Approved Product TYPE 2 BUFFER CHARACTERISTICS FOR IOAPIC Characteristic Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise Time Between 0.4 V and 2.0 V Fall TimeBetween 0.4 V and 2.0 V Symbol Min IOHmin IOHmax IOLmin IOLmax TR TF -36 36 0.4 0,4 Typ Max Units - -29 28 1.6 1.6 mA mA mA mA nS nS Conditions Vout = 1.4 V Vout = 2.7 V Vout = 1.0 V Vout = 0.2 V 20 pF Load 20 pF Load VDD = VDD3 =3.3V ±5%, VDD2 = 2.5V +/-5%, TA = 0ºC to +70ºC TYPE 3 BUFFER CHARACTERISTICS FOR REF(2:3) and 48/24 MHz Characteristic Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise Time Between 0.4 V and 2.4 V Fall Time Between 0.4 V and 2.4 V Symbol Min IOHmin IOHmax IOLmin IOLmax TR TF -29 29 1.0 1.0 Typ Max Units - -23 27 4.0 4.0 mA mA mA mA nS nS Conditions Vout = 1.0 V Vout = 3.135 V Vout = 1.95 V Vout = 0.4 V 20 pF Load 20 pF Load VDD = VDD3 =3.3V ±5%, VDD2 = 2.5V +/-5%, TA = 0ºC to +70ºC TYPE 4 BUFFER CHARACTERISTICS FOR REF1, SDRAM(1:8) Characteristic Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max Rise Time Between 0.4 V and 2.4 V Fall Time Between 0.4 V and 2.4 V Rise Time Between 0.4 V and 2.4 V Fall Time Between 0.4 V and 2.4 V Symbol Min Typ Max Units IOHmin IOHmax IOLmin IOLmax TR TF TR TF -54 49 0.5 0.5 0.5 0.5 - -46 53 2.0 2.0 1.3 1.3 mA mA mA mA nS nS nS nS VDD = VDD3 =3.3V ±5%, VDD2 =2.5V +/-5%, INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Conditions Vout = 2.0 V Vout = 3.135 V Vout = 1.0 V Vout = 0.4 V 45 pF Load, REF1 45 pF Load, REF1 30 pF Load, SDRAM(1:8) 30 pF Load, SDRAM(1:8) TA = 0ºC to +70ºC Rev.1.3 4/8/97 Page 5 of 8 SG552 Pentium II, System Clock Generator with 2 DIMM Support and SSCG Approved Product TYPE 5 BUFFER CHARACTERISTICS FOR PCICLK(1:6,F) Characteristic Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max RiseTime Between 0.4 V and 2.4 V Fall Time Between 0.4 V and 2.4 V Symbol Min Typ Max Units IOHmin IOHmax IOLmin IOLmax TR TF -33 30 0.5 0.5 - -33 38 2.0 2.0 mA mA mA mA nS nS Conditions Vout = 1.0 V Vout = 3.135 V Vout = 1.95 V Vout = 0.4 V 30 pF Load 30 pF Load VDD = VDD3 =3.3V ±5%, VDD2 = 2.5V +/-5%,, TA = 0ºC to +70ºC INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.3 4/8/97 Page 6 of 8 SG552 Pentium II, System Clock Generator with 2 DIMM Support and SSCG Approved Product PCB LAYOUT RECOMMENDATION Via to GND plane Via to VDD Island Via to VCC plane VCC3.3V IMISG552 FB1 C3 22µF C4 C5 C6 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 C12 VCC2.5V C11 FB1 C10 C13 22µF C9 C8 C7 This is only a layout recommendation for best performance and lower EMI. The designer may choose a differnent approach but C4, C5, C6, C7, C8, C9, C10, C11and C12 (all are 0.1µf) should always be used and placed close to their VDD pins. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.3 4/8/97 Page 7 of 8 SG552 Pentium II, System Clock Generator with 2 DIMM Support and SSCG Approved Product PACKAGE DRAWING AND DIMENSIONS 48 PIN SSOP OUTLINE DIMENSIONS INCHES SYMBOL C L H E D a A2 A1 B NOM MAX MIN NOM MAX A 0.095 0.102 0.110 2.41 2.59 2.79 A1 0.008 0.012 0.016 0.20 0.31 0.41 A2 0.088 0.090 0.092 2.24 2.29 2.34 B 0.008 0.010 0.0135 0.203 0.254 0.343 C 0.005 - 0.010 0.127 - 0.254 D 0.620 0.625 0.630 15.75 15.88 16.00 E 0.292 0.296 0.299 7.42 7.52 7.59 e A e MILLIMETERS MIN 0.025 BSC 0.635 BSC H 0.400 0.406 0.410 10.16 10.31 a 0.10 0.013 0.016 0.25 0.33 10.41 0.41 L 0.024 0.032 0.040 0.61 0.81 1.02 a 0º 5º 8º 0º 5º 8º X 0.085 0.093 0.100 2.16 2.36 2.54 ORDERING INFORMATION Part Number Package Type IMISG552BYB 48 PIN SSOP Note: Production Flow Commercial, 0ºC to +70ºC The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. IMISG552AYB Flow B = Commercial, 0ºC to + 70ºC Package Y = SSOP Revision IMI Device Number INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571 Rev.1.3 4/8/97 Page 8 of 8