IRF830 Power Field Effect Transistor N–Channel Enhancement Mode Silicon Gate TMOS This TMOS Power FET is designed for high voltage, high speed power switching applications such as switching regulators, converters, solenoid and relay drivers. http://onsemi.com • Silicon Gate for Fast Switching Speeds • Low RDS(on) to Minimize On–Losses, Specified at Elevated TMOS POWER FET 4.5 AMPERES 500 VOLTS RDS(on) = 1.5 Ω Temperature • Rugged — SOA is Power Dissipation Limited • Source–to–Drain Diode Characterized for Use with Inductive Loads N–Channel MAXIMUM RATINGS Rating D Symbol Value Unit Drain–Source Voltage VDSS 500 Vdc Drain–Gate Voltage (RGS = 1.0 MΩ) VDGR 500 Vdc Gate–Source Voltage VGS "20 Drain Current Continuous, TC = 25°C Continuous, TC = 100°C Peak, TC = 25°C ID Total Power Dissipation @ TC = 25°C Derate above 25°C PD 75 0.6 Watts W/°C TJ, Tstg – 55 to 150 °C RθJC RθJA 1.67 62.5 TL 300 Operating and Storage Temperature Range G Vdc S Adc 4.5 3.0 18 4 THERMAL CHARACTERISTICS Thermal Resistance — Junction–to–Case — Junction–to–Ambient Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 5 Seconds °C/W 1 °C 2 3 TO–220AB CASE 221A STYLE 5 PIN ASSIGNMENT 1 Gate 2 Drain 3 Source 4 Drain ORDERING INFORMATION Device IRF830 Package Shipping TO–220AB 50 Units/Rail See the MTM4N45 Data Sheet for a complete set of design curves for the product on this data sheet. Design curves of the MTP4N45 are applicable for this product. Semiconductor Components Industries, LLC, 2000 April, 2000 – Rev. 0 1 Publication Order Number: IRF830/D IRF830 ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Symbol Characteristic Min Max 500 — — — 0.2 1.0 — 100 — 100 2.0 4.0 — 1.5 4.5 — 2.5 — Ciss — 800 Coss — 200 Crss — 60 td(on) — 30 tr — 30 td(off) — 55 tf — 30 Qg 22 (Typ) 30 Qgs 12 (Typ) — Qgd 10 (Typ) — VSD 1.1 (Typ) 1.6 Unit OFF CHARACTERISTICS Drain–to–Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) V(BR)DSS Zero Gate Voltage Drain Current (VDS = Rated VDSS, VGS = 0 Vdc) (VDS = 0.8 Rated VDSS, VGS = 0 Vdc, TJ = 125°C) Vdc IDSS Gate–Body Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0) IGSS(f) Gate–Body Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0) IGSS(r) mAdc nAdc nAdc ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS, ID = 0.25 mA) VGS(th) Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 2.5 Adc) RDS(on) On–State Drain Current (VGS = 10 V) (VDS ≥ 6.75 Vdc) Vdc Ohm ID(on) Forward Transconductance (VDS ≥ 6.75 Vdc, ID = 2.5 Adc) Adc gFS mhos DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, Vd VGS = 0 Vdc, Vd f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance pF SWITCHING CHARACTERISTICS (1) Turn–On Delay Time Rise Time ((VDD = 200 Vdc, ID = 2.5 Apk, RG = 15 Ω) Turn–Off Delay Time Fall Time Total Gate Charge (VDS = 0 0.8 8R Rated t d VDSS, VGS = 10 Vdc, ID = Rated ID) Gate–Source Charge Gate–Drain Charge SOURCE–DRAIN DIODE CHARACTERISTICS ns nC (1) Forward On–Voltage Forward Turn–On Time (IS = Rated R t d ID , VGS = 0) Reverse Recovery Time ton trr Vdc Limited by stray inductance 450 (Typ) — 3.5 (Typ) 4.5 (Typ) — — 7.5 (Typ) — ns INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the contact screw on tab to center of die) (Measured from the drain lead 0.25″ from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25″ from package to source bond pad) LS (1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%. http://onsemi.com 2 nH IRF830 PACKAGE DIMENSIONS TO–220AB CASE 221A–09 ISSUE Z –T– SEATING PLANE C T S 4 DIM A B C D F G H J K L N Q R S T U V Z A Q 1 2 3 U H K Z L R V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. J G D N INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 ––– ––– 0.080 STYLE 5: PIN 1. 2. 3. 4. http://onsemi.com 3 GATE DRAIN SOURCE DRAIN MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 ––– ––– 2.04 IRF830 E–FET is a trademark of Semiconductor Components Industries, LLC. TMOS is a registered trademark of Semiconductor Components Industries, LLC. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: [email protected] Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada N. American Technical Support: 800–282–9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor – European Support German Phone: (+1) 303–308–7140 (M–F 1:00pm to 5:00pm Munich Time) Email: ONlit–[email protected] French Phone: (+1) 303–308–7141 (M–F 1:00pm to 5:00pm Toulouse Time) Email: ONlit–[email protected] English Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK Time) Email: [email protected] EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781 *Available from Germany, France, Italy, England, Ireland CENTRAL/SOUTH AMERICA: Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST) Email: ONlit–[email protected] ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support Phone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: 001–800–4422–3781 Email: ONlit–[email protected] JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031 Phone: 81–3–5740–2745 Email: [email protected] ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 4 IRF830/D