P R E L I M I N A R Y Dual SLIC Dual Subscriber Line Interface Circuit Le57D11 Device APPLICATIONS DESCRIPTION Ideal for low cost, high performance line card applications (CO, DLC) Meets requirements for countries such as: China, Korea, Japan, Taiwan, and Australia Fulfills the following China specifications: GF0029002.1 FEATURES Dual Channel SLIC device with small footprint On-chip Thermal Management (TMG) feature in normal and reverse polarity Control states: Active (normal and reversal polarity), Standby, and Disconnect On-hook transmission Low standby power –39 V to –58 V battery operation Two-wire impedance set by single external impedance Per channel fault detection Device level thermal shutdown Programmable constant-current feed (Range TBD) Programmable loop-detect threshold Programmable ring-trip detect threshold Only +5 V and battery supply required Current Gain = 500 The innovative Le57D11 Dual Channel SLIC device was designed for high-density POTS applications requiring a small footprint SLIC device with significant power savings. By combining the line interface of two channels into one SLIC device, the Le57D11 device enables the design of a low cost, high performance, and fully programmable line interface for multiple country applications worldwide. The on-chip Thermal Management (TMG) feature allows for significantly reduced power dissipation on the device. Another benefit is that it is offered in space-saving package types 44-pin eTQFP and 32pin PLCC. The small footprint of the SLIC device allows designers to save board space, increasing the density of lines on the board. The Le57D11 device is also designed to significantly reduce the number of external components required for line card design. Legerity offers a range of compatible SLAC devices that perform the codec function in a line card. In particular, the Legerity Quad SLAC device combined with the Le57D11 device provides a programmable line circuit that can be configured for varying requirements. RELATED LITERATURE 080147 Am79Q02/021/031 Quad SLAC Data Sheet 080753 Le58QL02/021/031 QLSLAC™ Data Sheet 080748 Le57D11 Evaluation Board User’s Guide CH2 Fault Detector A 2 (TIP) ORDERING INFORMATION 32-Pin PLCC HP 2 44-pin eTQFP CH2 2-W Interface TMG 1 CFLT 1 C1 1 C2 1 DET 1 CAS IREF DET 2 C1 2 C2 2 TMG 2 CFLT 2 BLOCK DIAGRAM CH1 Fault Detector CH2 Input Decoder and Control Common Bias CH1 Input Decoder and Control A 1 (TIP) CH1 2-W Interface B 1 (RING) Ring Trip Detector Power Feed Controller Off-Hook Detector Signal Transmission VTX 1 RSN 1 AGND VCC BGND 1 CDC 1 44-pin eTQFP, 48 dB No Polarity Reversal BGND 2 DB 1 Le57D113TC CH1 DAC 44-pin eTQFP, 48 dB Polarity Reversal CH1 Ring Trip Detector 32-pin PLCC, 48 dB No Polarity Reversal Le57D111TC CH1 DB 2 Le57D113JC RSN 2 CH1 Power Feed Controller 32-pin PLCC, 48 dB Polarity Reversal CH2 CDC 2 Le57D111JC CH2 Off-Hook Detector Performance Grade CH2 VBAT Device CH2 Signal Transmission B 2 (RING) VTX 2 HP 1 Publication# 080676 Rev: A Version: 1.0 Date: Nov 16, 2001 Le57D11 Data Sheet P R E L I M I N A R Y Table of Contents APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ORDERING INFORMATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 RELATED LITERATURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 BLOCK DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 FAULT DETECTOR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 TWO-WIRE INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 SIGNAL TRANSMISSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 POWER FEED CONTROLLER AND COMMON BIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 INPUT DECODER AND CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 OFF-HOOK DETECTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 RING-TRIP DETECTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 CONNECTION DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 PIN DESCRIPTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Environmental Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Electrical Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 TRANSMISSION PERFORMANCE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 CROSSTALK BETWEEN CHANNELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 LONGITUDINAL CAPABILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 INSERTION LOSS AND BALANCE RETURN SIGNAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 LINE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 POWER SUPPLY REJECTION RATIO, ACTIVE NORMAL STATE. . . . . . . . . . . . . . . . . . . . . . . .9 POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 SUPPLY CURRENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 RFI REJECTION (SEE FIGURE 9.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 LOGIC INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 LOGIC OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 RING-TRIP DETECTOR INPUT (DA, DB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 CFLT1, CFLT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 CFLT TOGGLE RANGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 LOOP DETECTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 SLIC DECODING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 USER-PROGRAMMABLE COMPONENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 DC FEED CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 TEST CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 APPLICATION CIRCUIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 LINE CARD PARTS LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 PHYSICAL DIMENSIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 PL032 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 eTQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 2 Le57D11 Data Sheet P R E L I M I N A R Y PRODUCT DESCRIPTION The Le57D11 device is designed for long loop high-density POTS applications requiring a power saving, small footprint SLIC. The Le57D11 device increases line card density by integrating two SLIC devices into a single 32 pin package. This reduction in board space allows for higher density linecard, which allows for amortizing common hardware across more channels. The Le57D11 device gives line card designers a simple control interface that supports four states: Active, Polarity Reversal, Standby, and Disconnect (Ringing). The Le57D11 device is low cost and high performance, providing key features required for POTS markets requiring only loop start. The device includes a thermal management resistor option. BLOCK DESCRIPTIONS Fault Detector These blocks provide fault detection on a per channel basis for short to ground, short to battery, or certain AC faults. The Le57D11 device provides fault detection by having one fault detector in each channel. Under fault conditions — either a short to ground, a short to battery, or specified AC power cross faults — the Le57D11 device detects the longitudinal unbalance and trips the detector. Once the detector is tripped, the CFLT pin is pulled low and keeps toggling between Vth1 and Vth2 (refer Figure 2) until the fault is removed. An external 0.1µF capacitor is connected between the CFLT pin and AGND, which provides a fault trigger delay of about 4 mS (T1) and release delay of 24 mS (T2). During release delay, the affected channel is shutdown which sets Tip and Ring to a Disconnect state. The trigger delay prevents short transients on Tip and Ring from triggering the channel shutdown when a fault is not present. Figure 1. Fault Detector TIP Fault CFLT Vlong RING C FLT Vlb Release Fault Detector Bias Block Figure 2. Bias Shutdown Control Fault Detection Waveform VCFLT 5V Fault Trigger Vth1 T1 Release T2 Fault Trigger T1 Release T2 Vth2 Time CFLT ( Vth1 – V th2 ) T1 = ----------------------------------------------------Itrigger CFLT ( Vth1 – V th2 ) T2 = ----------------------------------------------------I release Le57D11 Data Sheet 3 P R E L I M I N A R Y Two-Wire Interface The two-wire interfaces provide DC current and send voice signals to a telephone apparatus connected to the line card with a two-wire line. The two-wire interface also receives the returning voice signals from the telephone transmitter. Signal Transmission The AC line voltage is sensed by a differential amplifier between the Ai (TIP) and HPi leads. The output of this amplifier is equal to the AC metallic components of the line voltages and is output at VTXi. The transmission circuit also contains a longitudinal feedback circuit to shunt longitudinal signals to a DC bias voltage. The longitudinal feedback does not affect metallic signals. Power Feed Controller and Common Bias The power feed controllers have three sections: (1) the battery feed circuit, (2) the polarity reversal circuit, and (3) the common bias circuit. The battery feed circuit regulates the amount of DC current and voltage supplied to the telephone over a wide range of loop resistance. The polarity reversal circuit provides the capability to reverse the loop current for pay telephone key pad disable and other applications. The bias circuit provides a filtered reference voltage, which is offset from the subscriber line voltage, and a signal which sets the current limit. Input Decoder and Control The input decoder and control block provides a means for a microprocessor or SLAC IC to control such system states as Active, Standby, Disconnect (Ringing), and Polarity Reversal. The input decoder and control block has TTL-compatible inputs, which set the operating states of the SLIC device. Off-Hook Detector The most important loop monitoring function is off-hook detection. Loop current is programmed for both channels by a single resistor. Loop detect threshold is typically 1/3 of the programmed Loop current in the Active and Reverse Polarity states. Ring-Trip Detector In the Disconnect state, the ring-trip detector is active. While the DBi pin is more negative than the DAC pin, the DET pin will be high to indicate on hook. When an off hook condition occurs, the DBi pin becomes more positive than the DAC pin, and the DET pin will go low to indicate off hook during ringing (ring-trip) has been detected. The system implements the Ringing state using external control of a ring relay in combination with the Disconnect SLIC state, which enables the ring-trip detector. 4 Le57D11 Data Sheet P R E L I M I N A R Y RSN1 VTX1 CFLT1 3 2 1 32 31 TMG1 CDC1 4 HP1 DET1 CONNECTION DIAGRAMS 30 C2 1 5 29 BGND 1 C1 1 AGND/ DGND VCC 6 28 B 1 (RING) 7 27 A 1 (TIP) 26 DB 1 25 DAC 8 Le57D11JC 32-Pin PLCC 24 VBAT C1 2 11 23 DB 2 C2 2 12 22 A 2 (TIP) DET 2 13 21 B 2 (RING) NC TMG 2 CFLT 1 CFLT 2 HP 2 NC NC VTX 1 VTX 2 NC RSN 1 CDC 1 RSN 2 20 DET 1 14 15 16 17 18 19 TMG 1 10 HP 1 IREF BGND 2 9 CDC 2 CAS 44 43 42 41 40 39 38 37 36 35 34 C21 1 33 BGND 1 C11 2 32 B 1 (RING) NC 3 31 A 1 (TIP) AGND 4 30 DB 1 VCC 5 29 DAC NC 6 28 NC 27 VBAT Le57D11TC 44-Pin eTQFP CAS 7 IREF 8 26 DB 2 C12 9 25 A 2 (TIP) C22 10 24 B 2 (RING) DET 2 11 23 BGND 2 HP 2 TMG 2 NC CFLT 2 NC NC VTX 2 NC RSN 2 NC CDC 2 12 13 14 15 16 17 18 19 20 21 22 Note: 1. Pin 1 is marked for orientation. 2. NC = No Connect 3. e = exposed pad Le57D11 Data Sheet 5 P R E L I M I N A R Y PIN DESCRIPTIONS 6 Pin Name Type A1 (TIP) Input/Output Output of A (TIP) power amplifier of channel 1. Description A2 (TIP) Input/Output Output of A (TIP) power amplifier of channel 2. AGND Ground B1 (RING) Input/Output Output of B (RING) power amplifier of channel 1. B2 (RING) Input/Output Output of B (RING) power amplifier of channel 2. BGND1 Ground Battery (power) ground of channel 1 BGND2 Ground Battery (power) ground of channel 2. C11 Input C21 Input C12 Input C22 Input Analog and digital ground. State decoder inputs of channel 1. State decoder inputs of channel 2. CAS Capacitor Pin for capacitor to filter reference voltage when operating in anti-saturation region. CDC1 Capacitor DC feed filter capacitor and DC feed programming pin of channel 1. CDC2 Capacitor DC feed filter capacitor and DC feed programming pin of channel 2. CFLT1 Input/Output Fault detector output of channel 1. Connect a capacitor from CFLT1 to AGND to set fault detector timing. CFLT2 Input/Output Fault detector output of channel 2. Connect a capacitor from CFLT2 to AGND to set fault detector timing. DAC Input Ring-trip negative of both channels. Negative input to ring-trip comparator. DB1 Input Ring-trip positive of channel 1. Positive input to ring-trip comparator. DB2 Input Ring-trip positive of channel 2. Positive input to ring-trip comparator. DET1 Output Switch-hook/Ring-trip detector output of channel1. Logic low indicates that a detector is tripped. DET2 Output Switch-hook/Ring-trip detector output of channel 2. Logic low indicates that a detector is tripped. HP1 Capacitor Connect High-pass filter capacitor from HP1 to B1 (RING). HP2 Capacitor Connect High-pass filter capacitor from HP2 to B2 (RING). IREF Resistor RSN1 Input Receive Summing Node of channel 1. The metallic current (both AC and DC) between A1 (TIP) and B1 (RING) is equal to 500 times the current into this pin. The networks that program receive gain and two-wire impedance of channel 1 connect to this node. RSN2 Input Receive Summing Node of channel 2. The metallic current (both AC and DC) between A2 (TIP) and B2 (RING) is equal to 500 times the current into this pin. The networks that program receive gain and two-wire impedance of channel 2 connect to this node. TMG1 Output Thermal management of channel 1. External resistor connects from TMG1 to VBAT to offload power from the SLIC device. TMG2 Output Thermal management of channel 2. External resistor connects from TMG2 to VBAT to offload power from the SLIC device. VBAT Battery Battery supply and connection to substrate. VCC Power +5 V power supply. VTX1 Output Transmit audio signal of channel 1. This output is a scaled version of the A and B metallic voltage. VTX also sources the two-wire input impedance programming network. VTX2 Output Transmit audio signal of channel 2. This output is a scaled version of the A and B metallic voltage. VTX2 also sources the two-wire input impedance programming network. Connection for reference resistor that programs loop detector threshold and DC feed current of both channels. Le57D11 Data Sheet P R E L I M I N A R Y ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Stresses greater than those listed under Absolute Maximum Ratings can cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods can affect device reliability Storage temperature VCC with respect to AGND –55 to +150º C –0.4 to +7.0 V VBAT with respect to AGND: Continuous 10 ms BGND1, BGND2 with respect to AGND +0.4 to –70 V +0.4 to –75 V +3 to –3 V A1 (TIP), A2 (TIP), B1 (RING), B2 (RING) to BGND: Continuous 10 ms (F = 0.1 Hz) 1 µs (F = 0.1 Hz) 250 ns (F = 0.1 Hz) Current from A1 (TIP), A2 (TIP), B1 (RING), B2 (RING) DB1, DB2, and DAC inputs: –70 to +5 V –80 to +8 V –90 to +12 V Voltage on ring-trip inputs Current into ring-trip inputs C11, C21, C12, C22, CFLT1, CFLT2 ±10 mA VBAT to + 1 V ±150 mA VBAT to 0 V Input Voltage Maximum power dissipation, continuous: TA = 70º C, No heat sink (see note) –0.4 to VCC + 0.4 V In 32-pin PLCC package In 44-pin eTQFP 1.7 W 3.3 W Thermal Data (Junction to Ambient): θJA In 32-pin PLCC package In 44-pin eTQFP 43º C/W typ 22.7º C/W typ Thermal Data (Junction to Case): θJC In 32-pin PLCC package In 44-pin eTQFP ESD immunity/pin (Human Body Model) ESD immunity/pin (Charge Device Model) 16º C/W typ 9.2º C/W typ 1.5 kV 1 kV Note: 1. Thermal limiting circuitry on-chip will shut down the circuit at a junction temperature of about 165º C. The device should never see this temperature, and operation above 145º C junction temperature may degrade device reliability. See the SLIC Packaging Considerations for more information. 2. Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. Operating Ranges Legerity guarantees the performance of this device over commercial (0° to 70° C) and industrial (−40° to 85° C) temperature ranges by conducting electrical characterization over each range, and by conducting a production test with single insertion coupled to periodic sampling. These characterization and test procedures comply with section 4.6.2 of Bellcore TR-TSY-000357 Component Reliability Assurance Requirements for Telecommunications Equipment. Le57D11 Data Sheet 7 P R E L I M I N A R Y Environmental Ranges −40° to 85° C Ambient Temperature Electrical Ranges VCC 4.75 to 5.25 V VBAT –39 to –58 V DB1, DB2, and DAC VBAT to –2 V AGND 0V BGND1, BGND2 with respect to AGND –100 to + 100 mV Load resistance on VTX to ground 20 kΩ minimum Note: The operating ranges define those limits between which the functionality of the device is guaranteed. SPECIFICATIONS Transmission Performance Description 2-wire return loss Test Conditions (See Note 1) Min 200 Hz to 3.4 kHz (See Figure 8) 26 Analog output (VTX) impedance Typ 3 Analog (VTX) output offset voltage –50 Max Unit Note dB 1, 4 20 Ω 4 +50 mV Overload level, 2-wire Active state 2.5 Vpk 2a Overload level On hook, RLAC = 600 Ω 0.77 Vrms 2b dB 5 –36 dB 5 Max Unit Note dB 4 Unit Note THD (Total Harmonic Distortion) 0 dBm –64 –50 +7 dBm –55 –40 0dBm, RLAC = 600 Ω THD, On hook Crosstalk Between Channels Description Crosstalk coupling loss Test Conditions (See Note 1) Min F = 200 Hz to 3.4 kHz Typ 80 Longitudinal Capability (See Figure 7.) Description Min Typ Max 200 Hz to 3.4 kHz, 0º C to +70º C 48 Longitudinal signal generation 4-L 200 Hz to 3.4 kHz 40 Longitudinal current per pin (A or B) Active state (off hook) 8.5 Longitudinal impedance at A or B 0 to 100 Hz C-Message, RL = 600 Ω 7 12 dBrnc –83 –78 dBmP Idle Channel Noise 8 Test Conditions (See Note 1) Longitudinal to metallic L-T, L-4 balance Psophometric, 600 Ω Le57D11 Data Sheet dB 4 20 mArms 8 25 Ω/pin 4 P R E L I M I N A R Y Insertion Loss and Balance Return Signal (See Figure 5 and Figure 6.) Description Test Conditions (See Note 1) Min Typ Max +0.20 Gain accuracy, 4- to 2-wire 0 dBm, 1 kHz –0.20 0 Gain accuracy, 2- to 4-wire 0 dBm, 1 kHz –9.64 –9.54 Gain accuracy, 4- to 2-wire On hook –0.35 +0.35 Gain accuracy over frequency 300 to 3.4 kHz relative to 1 kHz –0.15 +0.15 Gain tracking +3 dBm to –55 dBm relative to 0 dBm –0.15 +0.15 Gain tracking On hook 0 dBm to –37 dBm +3 dBm to 0 dBm –0.15 –0.35 +0.15 +0.35 Group delay 0 dBm, 1 kHz Unit Note –9.44 4 4 dB µs 4, 7 Unit Note Line Characteristics Description Test Conditions (See Note 1) Min Typ Max 26.4 30 33.6 RLDC = 1930 Ω, BAT = –42.75 V, TA = 25°C 18 19 VBAT – 3V I L = æ ------------------------------ö , T A = 25°C è ( R L + 5K ) ø 0.7IL IL +38.3 +40.3 Min Typ IL, Short Loops, Active state RLDC = 600 Ω IL, Long Loops, Active state IL, Accuracy, Standby state IL, Loop current, Disconnect state RL = 0 VAB, Open Circuit voltage VBAT = –48 V mA 1.3IL 100 µA V Power Supply Rejection Ratio, Active Normal State Description Test Conditions (See Note 1) Max Unit Note dB 5 VCC 50 Hz to 3.4 kHzVRIPPLE = 100 mVrms 30 40 VBAT 50 Hz to 3.4 kHzVRIPPLE = 500 mVPP 28 50 Effective internal resistance CAS pin to VBAT 85 170 255 kΩ 4 Min Unit Note Power Dissipation Typ Max On hook, Standby state (both Stdby) Description Test Conditions (See Note 1) 40 100 On hook, Active state (Active) 200 400 Off hook, Active state (Active) RL = 300 Ω, RTMG = 1600 Ω 1400 2000 One channel, Active/ One channel, Stdby RL = 300 Ω, RTMG = 1600 Ω 720 1050 Typ Max mW Supply Currents Battery = – 48 V Description ICC, On-hook VCC supply current IBAT, On-hook VBAT supply current Test Conditions (See Note 1) Min Standby state (both Stdby) 4.4 Active state, BAT = –48 V (both active) 12.6 Standby state (both Stdby) 0.4 Active state, BAT = –48 V (both active) 5.6 Le57D11 Data Sheet Unit Note mA 9 P R E L I M I N A R Y RFI Rejection (See Figure 9.) Description Test Conditions VTX1 or VTX2 Min Typ Max Unit Note f = .01 MHz to 100 MHz HF gen output = 1.5 Vrms CAX = CBX = 33 nF 1 mVrms 4 CAX = CBX = 2.2 nF 3 Unit Note Logic Inputs (Applies to C11, C12, C21, and C22.) Description Test Conditions VIH, Input High voltage Min Typ Max 2.0 VIL, Input Low voltage 0.8 IIH, Input High current –75 IIL, Input Low current –400 40 V µA Logic Output (Applies to DET1, DET2, CFLT1, and CFLT2.) Description Test Conditions (See Note 1) VOL, Output Low voltage IOUT = 0.3 mA, 15 kΩ to VCC VOH, Output High voltage IOUT = –0.1 mA, 15 kΩ to VCC Min Typ Max 0.40 2.4 Unit Note V Ring-Trip Detector Input (Applies to DAC, DB1, and DB2.) Description Test Conditions (See Note 1) Bias Current Offset voltage Source resistance = 2 MΩ Min Typ –500 –50 Max Unit Note –50 0 +50 mV 6 Min Typ Max Unit Note nA CFLT1, CFLT2 Description Test Conditions (See Note 1) Sinking Current (ITrigger) 60 Sourcing Current (IRelease) 10 µA CFLT Toggle Range Typ Max Vth1 Description Test Conditions (See Note 1) Min 3.0 3.3 Vth2 0.8 1.1 Typ Max Unit Note V Loop Detector Description Test Conditions (See Note 1) Active 9 11 On-hook threshold Active 8.5 10.5 Off-hook threshold Standby 4 6 On-hook threshold Standby 3.8 5.8 0 2 Hysteresis 10 Min Off-hook threshold Le57D11 Data Sheet Unit mA Note P R E L I M I N A R Y Note: 1. Unless otherwise noted, test conditions are BAT = –52 V; VCC = +5 V; RL1, RL2= 600 Ω; RTMG1, RTMG2 = 1600 Ω; no fuse resistors; CHP1, CHP2= 100 nF; CDC1,CDC2= 1.5 µF; CCAS = 0.33 µF; RREF=15 K; two-wire AC input impedance is a 600 Ω resistance synthesized by the programming network shown below. Figure 3. AC Input Impedance Programming Network VTX RT1 = 41.7 k CT1 = 120 pF RT2 = 41.7 k RSN RRX = 124 k VRX 2. a. Z when THD = 1%. b. Overload level is defined when THD = 1.5%. 3. Balance return signal is the signal generated at VTX by VRX. This specification assumes that the two-wire, AC-load impedance matches the programmed impedance. 4. Not tested in production. This parameter is guaranteed by characterization or correlation to other tests. 5. This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization. 6. Tested with 0 Ω source impedance. 2 MΩ is specified for system design only. 7. Group delay can be greatly reduced by using a ZT network such as that shown in Note 1. The network reduces the group delay to less than 2 µs and increases 2WRL. The effect of group delay on linecard performance also may be compensated for by synthesizing complex impedance with the QSLAC™ or DSLAC™ device. 8. Minimum current level guaranteed not to cause a false loop detect. SLIC Decoding (For X, Channel = 1 or 2) State C2x C1x 0 0 0 Disconnect Two-Wire Status 1 0 1 Active Loop Detector 2 1 1 Polarity Reversed Loop Detector 3 1 0 Standby Loop Detector Le57D11 Data Sheet DETx output Ring-Trip Detector 11 P R E L I M I N A R Y User-Programmable Components Z T = 166.7 ( Z 2WIN – 2R F ) ZT is connected between the VTX and RSN pins. The fuse resistors are RF, and Z2WIN is the desired 2-wire AC input impedance. When computing ZT, the internal current amplifier pole and any external stray capacitance between VTX and RSN must be taken into account. 500ZT ZL Z RX = ------------- • --------------------------------------------------------G 42L ZT + 166.7 ( Z L + 2R F ) ZRX is connected from VRX to RSN. ZT is defined above, and G42L is the desired receive gain. 450 R REF = --------------I LOOP ILOOP is the desired loop current in the constant-current region. Loop detect threshold is typically 1/3 of programmed Loop current. C DC = 1.5 µF 1 C CAS = ------------------------------5 3.4 • 10 πf c CCAS is the regulator filter capacitor and fc is the desired filter cut-off frequency. V BAT – 3 V I STANDBY = ------------------------------5000Ω + R L Standby loop current (resistive region). Thermal Management Equations (Normal, Active, and Polarity Reverse States) æ V BAT – 6 V ö R TMG ≥ ç ------------------------------- – 70 Ω÷ è ILOOP ø RTMG is connected from TMG to VBAT and limits power within the SLIC in Active and Off-Hook states. 2 ( V BAT – 6 V – ( IL • R L ) ) P RTMG = ---------------------------------------------------------------------- • R TMG 2 ( R TMG + 70 Ω ) 2 P SLIC = V BAT • I L – P RTMG – R L ( I L ) + 0.12 W 12 Power dissipated in the TMG resistor, RTMG during Active and OffHook states. Power dissipated in the SLIC while in Active state. Le57D11 Data Sheet P R E L I M I N A R Y DC Feed Characteristics Load Line (Typical) Vbat = -48V 2a 2b 3b 3a Vbat = -42V On-Hook R FEED = 26.7K Internal Vbat = -38V 1 Off-Hook 150 I SWTH = -------------R REF R REF = 15 K Note: 1. Constant current region: 2a. Battery-independent anti-sat (Off-hook): ( 450 ) V AB1 = I L R L' = -------------- R L' , where R L' = R L + 2RF R REF R FEED V AB2a = 43.6 V – I L ----------------88 2b. Battery tracking anti-sat (On-hook): V AB2b = V AB2a – 3.5 3a. Battery tracking anti-sat (Off-hook): R FEED VAB3a = V BAT – 1.8 – I L -----------------240 3b. Battery tracking anti-sat (On-hook): VAB3b = V AB3a – 0.33 ⋅ VBAT + 10.8 Le57D11 Data Sheet 13 P R E L I M I N A R Y Figure 4. Feed Programming IREF A (TIP) RREF a RL IL SLIC RSN b RDC CDC B (RING) CDC Note: To choose the correct value for RDC, please contact the manufacturer. Test Circuits Figure 5. Two-to-Four Wire Insertion Loss VTX 1 VTX 2 A 1, A 2 (TIP) RL SLIC 2 V AB VL RT AGND RL RRX 2 B 1, B 2 (RING) RSN 1 RSN 2 IL2-4 = 20 log(V TX / V AB ) Figure 6. Four-to-Two Wire Insertion Loss and Balance Return Signals A 1, A 2 (TIP) VTX 1 VTX 2 SLIC V AB RT RL AGND RRX B 1, B 2 (RING) RSN 1 RSN 2 IL4-2 = 20 log(V AB / V RX ) BRS = 20 log(V TX / V RX ) 14 Le57D11 Data Sheet V RX P R E L I M I N A R Y Figure 7. 1 ωC A 1, A 2 (TIP) << RL RL 2 S1 Longitudinal Balance VTX 1 VTX 2 SLIC C VL RT V AB AGND VL RL S2 2 RRX RSN 1 B 1, B 2 (RING) RSN 2 V RX S2 Open, S1 Closed S2 Closed, S1Open L-T Long. Bal. = 20 log(V AB / V L) 4-L Long. Sig. Gen. = 20 log(V L / V RX ) L-4 Long. Bal. = 20 log(V TX / V L) Figure 8. Two-Wire Return Loss Test Circuit ZD = 600 VTX 1 VTX 2 A 1, A 2 (TIP) RTA R 41.7 K SLIC 300 VM VS AGND R CT = 120 pF ZIN = 600 300 RTB 41.7 K RSN 1 B 1, B 2 (RING) RSN 2 ZD : The desired impedance; eg., the characteristic impedance of the line RRX = 124 K Return loss = –20 log (2V M / V S) Figure 9. RFI Test Circuit L1 200Ω C1 50Ω A 1, A 2 (TIP) RF 1 200Ω HF GEN 50 Ω CAX RF 2 50Ω C2 L2 80% amplitude modulated Modulation frequency = 1 kHz Le57D11 Data Sheet B 1, B 2 (RING) CBX VTX 1 VTX 2 SLIC under test 15 P R E L I M I N A R Y Figure 10. Le57D11 Test Circuit +5V BGND DB 1 DB 1 VCC AGND Le57D11 CA1 TIP 1 CH1 CHP1 B 1 (RING) RTMG1 C21 VBAT CAS DAC DAC DET 1 C21 IREF DB 2 CFLT1 CDC1 C11 TMG 1 DB 2 VRX 1 C11 RREF CCAS TMG 2 VTX 2 RT2 RSN 2 CA2 CH2 A 2 (TIP) TIP 2 RRX1 DET 1 CB1 RTMG2 VTX 1 CFLT 1 CDC 1 HP 1 DVBH BAT RT1 RSN 1 A 1 (TIP) RING 1 VTX 1 VTX 2 RRX2 VRX 2 CFLT 2 CDC 2 CFLT2 CDC2 HP 2 CHP2 RING 2 B 2 (RING) CB2 16 Le57D11 Data Sheet DET 2 DET 2 C12 C12 C22 C22 P R E L I M I N A R Y APPLICATION CIRCUIT +5V BGND DB 1 DB 1 RR1 50 A 1 (TIP) RR1 CHP1 RF1B 100 nF 50 CDC 1 HP 1 CH1 B 1 (RING) 1.6 K RTMG2 1.6 K C1 1 C2 1 VBAT CAS TIP 2 BAT C P2 RING 2 R R2 50 CH2 RT2 83.3 K RRX2 124 K VTX 2 VRX 2 CFLT 2 CDC 2 A 2 (TIP) CFLT2 CDC2 100 nF 1.5 µF U3 CHP2 100 nF RR2 RSN 2 CA2 2.2nF RF2A 15 K 330 nF VTX 2 DAC RREF CCAS TMG 2 DAC DET 1 C2 1 IREF DB 2 CDC1 C1 1 TMG 1 DB 2 VRX 1 CFLT1 100 nF DET 1 RTMG1 DVBH BAT 124 K VTX 1 1.5 µF CB1 2.2nF RS 1 83.3 K RRX1 CFLT 1 U2 100 nF RR1 RT1 RSN 1 TIP 1 RING 1 VTX 1 U1 Le57D11 CA1 C P1 AGND 2.2nF RF1A BAT VCC RF2B 50 HP 2 100 nF B 2 (RING) CB2 2.2nF DET 2 DET 2 C1 2 C1 2 C2 2 C2 2 RS 2 RING_SOURCE BATTERY GROUND ANALOG GROUND DIGITAL GROUND R R2 400 R R1 400 R SR3 909 K R SR1 909 K R RTH1 1M DAC R SR4 1M C RT2 100 nF R SR2 1M R RTH2 909 K C TH 100 nF C RT1 100 nF RS 1 DB 1 RS 2 DB 2 Le57D11 Data Sheet 17 P R E L I M I N A R Y LINE CARD PARTS LIST The following list defines the parts and part values required to meet target specification limits for channel i of the line card (i = 1,2). 18 Item Quantity CA1, CB1, CA2, CB2 4 CHP1, CHP2, CP1, CP2, CRT1, CRT2, CTH Type Value Tol. Rating Capacitor (X7R) 2200 pF 20% 100 V 7 Capacitor (X7R) 100 nF 20% 100 V CFLT1, CFLT2 2 Capacitor (X7R) 100 nF 20% 16 V CDC1, CDC2 2 Capacitor (X7R) 1.5 µF 10% 16 V RF1A, RF1B, RF2A, RF2B 2 Resistor Hybrid 50 1% RREF 1 SMT 15 k 1% 1/10 W RT1, RT2 2 SMT 83.3 k 1% 1/10 W RRX1, RRX2 2 SMT 124 k 1% 1/10 W DVBH 1 MURS 120 (D0-41) DIODE RR1, RR2 2 Resistor Hybrid 400 1% U2, U3 2 TISP61089 RRTH1, RSR2, RSR4 3 SMT 1M 1% 1/4 W RSR1, RSR3, RRTH2 3 SMT 909 k 1% 1/4 W U1 1 Le57D11 RTMG1 RTMG2 2 SMT 1.6 k 1% 2W CCAS 1 Capacitor (X7R) 330 nF 20% 50 V Le57D11 Data Sheet Comments Note P R E L I M I N A R Y PHYSICAL DIMENSIONS PL032 Dwg rev AH; 08/00 Le57D11 Data Sheet 19 P R E L I M I N A R Y eTQFP 20 Le57D11 Data Sheet P R E L I M I N A R Y The contents of this document are provided in connection with Legerity, Inc. products. Legerity makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in Legerity's Standard Terms and Conditions of Sale, Legerity assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. Legerity's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of Legerity's product could create a situation where personal injury, death, or severe property or environmental damage may occur. Legerity reserves the right to discontinue or make changes to its products at any time without notice. © 2001 Legerity, Inc. All rights reserved. Trademarks Legerity, the Legerity logo and combinations thereof, are trademarks of Legerity, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Le57D11 Data Sheet 21 Americas Mailing: P.O. Box 18200 Austin, TX 78760-8200 Shipping: 4509 Freidrich Lane Austin, TX 78744-1812 ATLANTA 6465 East Johns Crossing, Suite 400 Duluth, GA USA 30097 MainLine: 770-814-4252 Fax: 770-814-4253 AUSTIN 4509 Freidrich Lane Austin, TX USA 78744-1812 MainLine: 512-228-5400 Fax: 512-228-5510 BOSTON 6 New England Executive Park Suite 400 Burlington, MA USA 01803 MainLine: 781-229-7320 Fax: 781-272-3706 CHICAGO 8770 W. Bryn Mawr, Suite 1300 Chicago, IL USA 60631 MainLine: 773-867-8034 Fax: 773-867-2910 DALLAS 4965 Preston Park Blvd., Suite 280 Plano, TX USA 75093 MainLine: 972-985-5474 Fax: 972-985-5475 HUNTSVILLE 600 Boulevard South, Suite 104 Huntsville, AL USA 35802 MainLine: 256-705-3504 Fax: 256-705-3505 IRVINE 1114 Pacifica Court, Suite 250 Irvine, CA USA 92618 MainLine: 949-753-2712 Fax: 949-753-2713 NEW JERSEY 3000 Atrium Way, Suite 270 Mt. Laurel, NJ USA 08054 MainLine: 856-273-6912 Fax: 856-273-6914 OTTAWA 600 Terry Fox Drive Ottawa, Ontario, Canada K26 4B6 MainLine: 613-599-2000 Fax: 613-599-2002 RALEIGH 2500 Regency Parkway, Suite 226 Cary, NC USA 27511 MainLine: 919-654-6843 Fax: 919-654-6781 SAN JOSE 1740 Technology Drive, Suite 290 San Jose, CA USA 95110 MainLine: 408-573-0650 Fax: 408-573-0402 Telephone: (512) 228-5400 Fax: (512) 228-5510 North America Toll Free: (800) 432-4009 Worldwide Sales Offices Europe Asia BELGIUM Baron Ruzettelaan 27 8310 Brugge Belgium MainLine: 32-50-28-88-10 Fax: 32-50-27-06-44 HONG KONG Units 2401-2, 24th Floor Jubilee Centre, 18 Fenwick Street Wanchai, Hong Kong MainLine: 852-2864-8300 Fax: 852-2866-1323 FRANCE 7, Avenue G. Pompidou Suite 402 92300 Levallois-Perret, France MainLine: 33-1-47-48-2206 Fax: 33-1-47-48-2568 KOREA 135-090 18th Fl., Kyoung Am Bldg 157-26, Samsung-dong, Kangnam-ku Seoul, Korea MainLine: 82-2-565-5951 Fax: 82-2-565-3788 GERMANY Freisinger Str. 1 85737 Ismaning, Germany MainLine: 49-89-1893-99-0 Fax: 49-89-1893-99-44 SHENZHEN Room 703, Block D1 Fu Yuan Garden Futian Free Trade Zone Shenzhen, PR China 518031 MainLine: 86-755-3567-008 Fax: 86-755-3567-191 ITALY Via F. Rosselli 3/2 20019 Settimo Mse, Milano Italy MainLine: 39-02-3355521 Fax: 39-02-33555232 SWEDEN Frösundaviks Allé 15, 4tr SE-16970 Solna Sweden MainLine: 46-8-509-045-45 Fax: 46-8-509-046-36 TOKYO Shinjuku NS Bldg. 5F 2-4-1 Nishi Shinjuku, Shinjuku-ku Tokyo, Japan 163-0805 MainLine: 81-3-5339-2011 Fax: 81-3-5339-2012 UK Regus House, Windmill Hill Business Park Whitehill Way SN5 6QR Swindon Wiltshire UK MainLine: 44-(0)1793-441408 Fax: 44-(0)1793-441608 To download or order product literature, visit our website at www.legerity.com. To order literature in North America, call: (800) 572-4859 or 512-349-3193 or email: [email protected] To order literature in Europe or Asia, call: 44-0-1179-341607 or email: Europe — [email protected] Asia — [email protected]