SaRonix Crystal Clock Oscillator 1.8V, LVCMOS, Tri-State Technical Data NTH Series Frequency Range: 20 MHz to 70 MHz Frequency Stability: ±50 or ±100 ppm over all conditions: calibration tolerance, operating temperature, input voltage change, load change, aging, shock and vibration. Temperature Range: Operating: Storage: 0 to +70°C -55 to +125°C Supply Voltage: Recommended Operating: 1.8V ±5% Supply Current: ACTUAL SIZE Output Drive: Description A 1.8V LVDS, crystal controlled, low current, low jitter oscillator with precise rise and fall times demanded in networking applications, such as Gigabit Ethernet and Fibre Channel. The Tri-State function enables the output to go high impedance. Device is packaged in an 8pin DIP compatible resistance welded, all metal grounded case, to reduce EMI. Applications & Features • • • • • • 6mA max 20 to 50 MHz, output enabled 10mA max 50+ to 70MHz, output enabled 10µA max 20 to 70MHz, output disabled Fibre Channel Gigabit Ethernet 32 Bit Microprocessors Tri-State output standard LVCMOS / HCMOS compatible Grounded, all metal half size case 45/55% max @ 50% VDD 2.5ns max 10% VDD max 90% VDD min 15 pF max 8ps max Mechanical: Shock: Solderability: Terminal Strength: Vibration: Solvent Resistance: Resistance to Soldering Heat: MIL-STD-883, MIL-STD-883, MIL-STD-883, MIL-STD-883, MIL-STD-202, MIL-STD-202, Method 2002, Condition B Method 2003 Method 2004, Conditions B2 Method 2007, Condition A Method 215 Method 210, Condition A, B or C Environmental: Gross Leak Test: Fine Leak Test: Thermal Shock: Moisture Resistance: MIL-STD-883, MIL-STD-883, MIL-STD-883, MIL-STD-883, Method Method Method Method 1014, Condition C 1014, Condition A2 1011, Condition A 1004 Tri-State Output Waveform Logic Table: CMOS Tr Symmetry: Rise and Fall Times: Logic 0: Logic 1: Load: Period Jitter RMS: Tf 1 Level Pin 1 Input Pin 5 Output Logic 1 or NC Oscillation Logic 0 or GND High Impedance V DD 80% VDD 50% VDD 20% VDD 0 Level GND SYMMETRY Control Characteristics: Output: Output: Internal Pullup Resistance: Control Input: Control Input: Oscillation @ VIN, 2.2V min High Impedance @ VIN, 0.8V max 50KΩ min Disable Output Delay: 100ns max Enable Output Delay: 10ms max DS-206 SaRonix REV A 141 Jefferson Drive • Menlo Park, CA 94303 • USA • 650-470-7700 • 800-227-8974 • Fax 650-462-9894 SaRonix Crystal Clock Oscillator 1.8V, LVCMOS, Tri-State Technical Data NTH Series Package Details Part Numbering Guide NTH HALF SIZE PACKAGE A 3 9 B 2 – 50.0000 Frequency (MHz) 13.0 max .510 10.87 max .428 Series 0.9 max .036 Supply Voltage 2 = 1.8V 5.08 max .200 .46±.051 .018±.002 Pin 1 Tri-State 7.62±.20 .300±.008 1.5 .059 Stability Tolerance B = ±50 ppm C = ±100 ppm Package 9 = Half Size, Thru-Hole Symmetry / Temperature Range A = 45/55%, 0 to +70°C, HCMOS/LVCMOS 6.35±.51 .250±.020 Frequency Range 3 = 20 to 50 MHz 6 = 50+ to 70 MHz Pin 4 GND 120° 13.0 .510 max Pin 8 +1.8VDC 120° 7.62±.20 .300±.008 120° 1.5 .059 6.0 .236 Example PN: NTHA39B2 - 60.0000 Pin 5 Output Test Circuits Marking Format ** TEST POINT Includes Date Code, Frequency & Model mA M SARONIX Pin 5 Pin 8 V CC Denotes Pin 1 POWER SUPPLY ** Exact locations of items may vary mm Scale: None (Dimensions in ) inches OUT CL = 15pF (Note A) OSCILLATOR VM GND Pin 1 Pin 4 TRI-STATE INPUT NOTE A: CL includes probe and fixture capacitance HCMOS (Used at SaRonix) All specifications are subject to change without notice. DS-206 SaRonix REV A 141 Jefferson Drive • Menlo Park, CA 94025 • USA • 650-470-7700 • 800-227-8974 • Fax 650-462-9894