P4C174 P4C174 HIGH SPEED 8K x 8 CACHE TAG STATIC RAM FEATURES High Speed Address-To-Match - 8 ns Maximum Access Time Data Retention at 2V for Battery Backup Operation Advanced CMOS Technology High-Speed Read-Access Time Low Power Operation — Active: 750 mW Typical at 25 ns — Standby: 500 µW Typical – 8/10/12/15/20/25 ns (Commercial) Open Drain MATCH Output Reset Function Package Styles Available — 28 Pin 300 mil Plastic DIP — 28 Pin 300 mil Plastic SOJ 8-Bit Tag Comparison Logic Automatic Powerdown During Long Cycles Single Power Supply — 5V±10% DESCRIPTION the addressed memory location. 8K Cache lines can be mapped into 1M-Byte address spaces by comparing 20 address bits organized as 13-line address bits and 7-page address bits. The P4C174 is a 65,536 bit high speed cache tag static RAM organized as 8K x 8. The CMOS memory has equal access and cycle times. Inputs are fully TTL-compatible. The cache tag RAMs operate from a single 5V±10% power supply. An 8-bit data comparator with a MATCH output is included for use as an address tag comparator in high speed cache applications. The reset function provides the capability to reset all memory locations to a LOW level. Low power operation of the P4C174 is enhanced by automatic powerdown when the memory is deselected or during long cycle times. Also, data retention is maintained down to VCC = 2.0. Typical battery backup applications consume only 30 µW at VCC = 3.0V. The MATCH output of the P4C174 reflects the comparison result between the 8-bit data on the I/O pins and PIN CONFIGURATION FUNCTIONAL BLOCK DIAGRAM ROW ADDRESS 8 256 x 32 x 8 MEMORY ARRAY ROW SELECT RESET 8 8 COLUMN SELECT & COLUMN SENSE 8 DATA I/O 8 COMPARATOR 1 (IF MATCH) 5 COLUMN ADDRESS 8 WE RESET 1 28 A 12 2 27 A7 3 26 Vcc WE MATCH A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 OE A2 8 21 A10 A1 9 20 CE A0 10 19 I/07 I/00 11 18 I/06 I/01 12 17 I/05 I/02 13 16 I/04 GND 14 15 I/03 OE DIP (P5), SOJ (J5) TOP VIEW CE MATCH (OPEN DRAIN) 174.1 Means Quality, Service and Speed 1Q97 99 P4C174 MAXIMUM RATINGS(1) Symbol Parameter Value Unit VCC Power Supply Pin with Respect to GND –0.5 to +7 V VTERM Terminal Voltage with Respect to GND (up to 7.0V) –0.5 to VCC +0.5 V TA Operating Temperature –55 to +125 °C Symbol Ambient Temperature GND VCC Commercial 0°C to +70°C 0V 5.0V ± 10% Value Unit TBIAS Temperature Under Bias –55 to +125 °C TSTG Storage Temperature –65 to +150 °C PT Power Dissipation 1.0 W IOUT DC Output Current 50 mA CAPACITANCES(4) RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade(2) Parameter VCC = 5.0V, TA = 25°C, f = 1.0MHz Symbol Parameter Conditions Typ. Unit CIN Input Capacitance VIN = 0V 5 pF COUT Output Capacitance VOUT = 0V 7 pF DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol Parameter Test Conditions P4C174 Min Max Unit VIH Input High Voltage 2.2 VCC +0.5 V VIL Input Low Voltage –0.5(3) 0.8 V VHC CMOS Input High Voltage VLC CMOS Input Low Voltage VCD VOL VOH ILI VCC –0.2 VCC +0.5 –0.5(3) V 0.2 V Input Clamp Diode Voltage VCC = Min., IIN = 18 mA –1.2 V Output Low Voltage (TTL Load) Output High Voltage (TTL Load) Input Leakage Current 0.4 V IOL = +8 mA, VCC = Min. IOH = –4 mA, VCC = Min. 2.4 VCC = Max. –5 +5 µA –5 +5 µA ___ 25 mA ___ 5 mA V VIN = GND to VCC ILO Output Leakage Current VCC = Max., CE = VIH, VOUT = GND to VCC ISB CE ≥ VIH Standby Power Supply Current (TTL Input Levels) VCC = Max ., f = Max., Outputs Open ISB1 Standby Power Supply Current (CMOS Input Levels) CE ≥ VHC VCC = Max., f = 0, Outputs Open VIN ≤ VLC or VIN ≥ VHC n/a = Not Applicable Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. 4. This parameter is sampled and not 100% tested. 100 P4C174 POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol ICC Temperature Range Dynamic Operating Current* Commercial Parameter –8 –10 –12 –15 –20 –25 Unit 200 180 170 160 155 150 mA *VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH. DATA RETENTION CHARACTERISTICS (P4C174 Military Temperature Only) Symbol Parameter Test Conditons VDR VCC for Data Retention ICCDR Data Retention Current CE ≥ VCC –0.2V, tCDR Chip Deselect to Data Retention Time VIN ≥ VCC –0.2V tR† Operation Recovery Time Min Typ.* VCC = 2.0V 3.0V 10 or VIN ≤ 0.2V 15 ns (4) tRC ADDRESS t AA OE t OH (1) t OLZ (1) t AC tOHZ (1) tHZ DATA OUT 101 µA tRC§ OE CONTROLLED)(2,3) READ CYCLE NO. 1 (OE t LZ 900 ns This parameter is guaranteed but not tested. CE 600 0 §tRC = Read Cycle Time t OE Unit V 2.0 *TA = +25˙C † Max VCC = 2.0V 3.0V (1) P4C174 AC CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Symbol Parameter –8 Min –12 –10 Max Min 8 Max Min 10 –15 Max 12 –20 –25 Min Max Min Max Min Max 15 20 25 Unit ns tRC Read Cycle Time tAA Address Access Time tOH Address Change to Output Change tAC Chip Enable LOW to Output Valid tLZ Chip Enable LOW to Output LOW-Z (1) tHZ Chip Enable HIGH to Output HIGH -Z (1) 5 5 5 8 8 10 ns tOE Output Enable LOW to Output Valid 5 6 6 8 10 12 ns tOLZ Output Enable LOW to Output LOW-Z (1) tOHZ Output Enable HIGH to Output HIGH -Z (1) tPU Chip Enable LOW or Address Change to Powerup tpUPD Powerup to Powerdown 8 10 3 3 12 3 8 10 3 3 0 3 12 5 0 5 20 20 20 8 0 20 20 READ CYCLE NO. 1 (OE CONTROLLED)(2, 3) (4) tRC ADDRESS t AA OE t OH (1) t OLZ CE (1) t AC t LZ tOHZ (1) tHZ DATA OUT 102 (1) ns ns ns 10 0 Note: 1. Transition is measured ± 200 mV from steady state voltage with Output Load B. t OE 25 0 5 ns ns 3 0 0 25 3 3 0 0 20 3 3 0 5 20 15 3 0 0 15 ns ns 25 ns P4C174 READ CYCLE NO. 2 (ADDRESS CONTROLLED)(2) (4) t RC ADDRESS tAA tOH PREVIOUS DATA VALID DATA OUT DATA VALID CE CONTROLLED)(2, 3) READ CYCLE NO. 3 (CE (4) t RC CE (1) (1) t HZ tAC t LZ DATA OUT DATA VALID t PU HIGH IMPEDANCE t PUPD VCC SUPPLY CURRENT(5) Notes: 1. Transition is measured ±200 mV from steady state voltage with Output Load B. This parameter is sampled, not 100% tested. 2. CE is LOW, OE is LOW, WE is HIGH for READ cycle. CE or WE must be HIGH during address transitions. 3. All address lines are valid no later than the transition of CE to LOW. 4. READ cycle time is measured from the last valid address to the first transitioning address. 5. Powerup occurs as a result of any of the following conditions: a) Falling edge of CE. b) Falling edge of WE (CE active). c) Any address line transition (CE active). d) Any Data line transition (CE and WE active). This device automatically powers down after TPUPD has elapsed from any of the prior conditions. Power dissipatio is therefore a function of cycle rate, not CE pulse width. 6. CE is LOW, WE is LOW for WRITE cycle. CE or WE must be HIGH during address transitions. 7. WRITE cycle time is measured from the last valid address to the first transitioning address. 8. OE is LOW for this WRITE cycle to show TWZ and TOW. 103 P4C174 AC CHARACTERISTICS - WRITE CYCLE (VCC = 5V ± 10%, 0°C to +70°C) Symbol Parameter –8 –10 –12 –15 –20 –25 Min Max Min Max Min Max Min Max Min Max Min Max Unit tWC Write Cycle Time 8 10 12 15 20 20 ns tCW Chip Enable LOW to End of Write Address Valid to Beginning of Write Address Valid to End of Write End of Write to Address Change 7 9 10 12 15 15 ns 0 0 0 0 0 0 ns 7 9 10 12 15 15 ns 0 0 0 0 0 0 ns tWP Write Pulse Width 7 9 10 12 15 15 ns tDW Data Valid to End of Write 6 6 6 7 10 10 ns tDH End of Write to Data Change 0 0 0 0 0 0 ns tOW Write Enable HIGH to Output LOW-Z (1) Write Enable LOW to Output HIGH-Z (1) 0 0 0 0 0 0 ns tAS tAW tAH tWZ 4 4 4 5 WE CONTROLLED)(6) WRITE CYCLE NO. 1 (WE tWC (7) ADDRESS tCW CE tAW t WP tAH WE tAS t DW DATA IN DATA VALID (1) (1) tOW tWZ (8) DATA OUT tDH DATA UNDEFINED HIGH IMPEDANCE 104 7 7 ns P4C174 CE CONTROLLED)(6) WRITE CYCLE NO. 2 (CE tWC (7) ADDRESS tAS tCW CE tAH tAW tWP WE tDW DATA IN tDH DATA VALID DATA OUT HIGH IMPEDANCE AC CHARACTERISTICS - MARCH CYCLE (VCC = 5.0V ± 10%, 0°C to +70°C) Parameter Symbol tMC Match Cycle Time tADM Address Valid to MATCH Valid Address Change to MATCH Change Chip Enable LOW to MATCH Valid Chip Enable HIGH to MATCH HIGH tADMH tCEM tCEMHI tOEMHI tWEMHI –8 Data Valid to MATCH Valid tDAMH Data Change to MATCH Change –12 –15 –20 8 10 12 8 10 3 3 15 12 3 20 25 15 3 20 3 ns ns 8 8 10 10 15 ns 7 8 8 10 10 15 ns 7 9 10 12 15 20 ns 7 9 10 12 15 20 ns 7 9 10 13 15 15 ns 0 0 0 0 0 0 t ADMH ADDRESS t ADM CE tCEM tCEMHI t OE t OEMHI WE tWEMHI RESET tRMHI MATCH 25 7 tMC VALID READ DATA OUT Unit ns 3 MATCH TIMING DATA –25 Min Max Min Max Min Max Min Max Min Max Min Max Output Enable LOW to MATCH HIGH Write Enable LOW to MATCH HIGH tDAM –10 VALID MATCH DATA IN tDAM tDAMH MATCH MATCH VALID NO MATCH 105 ns P4C174 AC CHARACTERISTICS - RESET CYCLE (VCC = 5.0V ± 10%, 0°C to +70°C) –8 Parameter Symbol –10 –12 –15 –20 –25 Min Max Min Max Min Max Min Max Min Max Min Max Unit tRRC Reset Cycle Time 35 40 45 50 50 60 ns tRP Reset Pulse Width 8 10 12 12 15 15 ns tRPU Reset LOW to Powerup 0 0 0 0 0 0 ns tRPD Reset LOW to Powerdown tRMHI Reset LOW to MATCH HIGH 0 tRIX Reset LOW to Inputs Ignored Reset LOW to inputs Recognized 0 Powerup to RESET LOW 8 tRIR tPUR 35 8 40 0 10 0 45 0 10 0 35 40 10 50 0 12 0 0 45 12 50 15 0 0 50 20 ns 20 ns ns 0 50 15 60 60 25 ns ns RESET TIMING t PUR VCC POWERUP 4.5 V t RRC t RP RESET t RIR t RIX INPUTS (A, D, CE, OE, WE) PRIOR CYCLE NEXT CYCLE t RPD t RPU VCC SUPPLY CURENT t RMHI MATCH AC TEST CONDITIONS TRUTH TABLE CE WE Output Power Standby H X High Z Standby 1.5V Read L H DOUT Active Output Timing Reference Level 1.5V Write L L High Z Active Input Pulse Levels GND to 3.0V Mode Input Rise and Fall Times < 3ns Input Timing Reference Level Output Load Outputs Loads A, B & C 106 P4C174 R1 480Ω R1 480Ω R1 200Ω +5V +5V +5V MATCH OUT OUTPUT OUTPUT INCLUDING JIG AND SCOPE INCLUDING JIG AND SCOPE R2 255Ω 30 pF OUTPUT LOAD A OUTPUT LOAD B PACKAGE SUFFIX Package Suffix P J INCLUDING JIG AND SCOPE R2 255Ω 5 pF OUTPUT LOAD C TEMPERATURE RANGE SUFFIX Temperature Range Suffix Description Plastic DIP, 300 mil wide standard Plastic SOJ, 300 mil wide standard C Description Commercial Temp. Range, 0°C to +70°C. ORDERING INFORMATION Performance Semiconductor's part numbering scheme is as follows: P4C 174 — ss p t Temperature Range Package Code Speed (Access/Cycle Time) Device Number Static RAM Prefix SS = Speed (access/cycle time in ns), e.g., 10, 12, 15 P = Package code, i.e., P, J. T = Temperature range, i.e., C. SELECTION GUIDE The P4C174 is available in the following temperature, speed and package options. Temperature Range Commercial 30 pF Speed (ns) Package Plastic DIP (300 mil) Plastic SOJ (300 mil) 8 10 12 15 20 25 -8PC -8JC -10PC -10JC -12PC -12JC -15PC -15JC -20PC -20JC -25PC -25JC 107 P4C174 108