ETC PEB3081

Da ta S he et , D S 1 , F eb . 2 00 3
SBCX-X
S/T Bus Interface Circuit Extended
PEB 3081, Version 1.4
Wired
Communications
N e v e r
s t o p
t h i n k i n g .
ABM®, ACE®, AOP®, ARCOFI®, ASM®, ASP®, DigiTape®, DuSLIC®, EPIC®, ELIC®,
FALC®, GEMINAX®, IDEC®, INCA®, IOM®, IPAT®-2, ISAC®, ITAC®, IWE®, IWORX®,
MUSAC®, MuSLIC®, OCTAT®, OptiPort®, POTSWIRE®, QUAT®, QuadFALC®,
SCOUT®, SICAT®, SICOFI®, SIDEC®, SLICOFI®, SMINT®, SOCRATES®, VINETIC®,
10BaseV®, 10BaseVX® are registered trademarks of Infineon Technologies AG.
10BaseS™, EasyPort™, VDSLite™ are trademarks of Infineon Technologies AG.
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trademark of Linus Torvalds.
The information in this document is subject to change without notice.
Edition 2003-02-04
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2003.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide
(www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Data Sheet
Revision History:
2003-02-04
Previous Version:
Data Sheet, DS1, V1.3, 2000-07-21
Page
Subjects (major changes since last revision)
Chapter 1 Comparison SBCX/SBCX-X
Chapter
3.3.6.2
S- Transceiver Synchronization New
Chapter
3.3.10
Test Functions extended
Chapter
3.7.1.1
CDA Handler Description extended
Chapter
3.7.5.1
TIC Bus Access Control: Note added
Chapter
5.6
IOM-2 Interface Timing: Explanation added
Chapter
5.9
S-Transceiver
Chapter
5.10
Recommended Transformer Specification: Changed
Chapter
5.11
Line Overload Protection added
Chapter
5.12
EMC/ESD added
DS 1
SBCX-X
PEB 3081
Table of Contents
Page
1
1.1
1.2
1.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3
3.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.6.1
3.3.6.2
3.3.7
3.3.8
3.3.9
3.3.10
3.4
3.4.1
3.4.2
3.4.3
3.5
3.5.1
3.5.1.1
3.5.1.2
3.5.1.3
3.5.1.4
3.5.2
3.5.2.1
3.5.2.2
3.5.2.3
Description of Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Functions and Device Architecture . . . . . . . . . . . . . . . . . . . . . . .
Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Control Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Activation Indication via Pin ACL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S/T-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S/T-Interface Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S/T-Interface Multiframing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Transfer and Delay between IOM-2 and S/T . . . . . . . . . . . . . . . .
Transmitter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S/T Interface Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Protection Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S-Transceiver Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S/T Interface Delay Compensation (TE/LT-T Mode) . . . . . . . . . . . . . . .
Level Detection Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transceiver Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description of the Receive PLL (DPLL) . . . . . . . . . . . . . . . . . . . . . . . . .
Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator Clock Output C768 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control of Layer-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
State Machine TE and LT-T Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
State Transition Diagram (TE, LT-T) . . . . . . . . . . . . . . . . . . . . . . . . .
States (TE, LT-T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C/I Codes (TE, LT-T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Infos on S/T (TE, LT-T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
State Machine LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
State Transition Diagram (LT-S) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
States (LT-S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C/I Codes (LT-S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Sheet
4
11
14
15
16
23
23
25
26
27
29
31
33
35
36
38
40
42
45
46
47
47
49
50
50
50
51
53
56
56
57
58
60
60
62
64
66
67
67
68
69
2003-02-04
SBCX-X
PEB 3081
Table of Contents
Page
3.5.2.4
3.5.3
3.5.3.1
3.5.3.2
3.5.3.3
3.5.4
3.6
3.6.1
3.6.2
3.6.3
3.7
3.7.1
3.7.1.1
3.7.2
3.7.2.1
3.7.2.2
3.7.3
3.7.3.1
3.7.3.2
3.7.3.3
3.7.3.4
3.7.3.5
3.7.3.6
3.7.4
3.7.5
3.7.5.1
3.7.5.2
3.7.5.3
3.7.5.4
3.7.6
3.8
Infos on S/T (LT-S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
State Machine NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
State Transition Diagram (NT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
States (NT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
C/I Codes (NT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Command / Indicate Channel Codes (C/I0) - Overview . . . . . . . . . . . . . 75
Control Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Example of Activation/Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Activation initiated by the Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Activation initiated by the Network Termination NT . . . . . . . . . . . . . . . . 78
IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
IOM-2 Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Controller Data Access (CDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Serial Data Strobe Signal and Strobed Data Clock . . . . . . . . . . . . . . . 94
Serial Data Strobe Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Strobed IOM-2 Bit Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
IOM-2 Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Handshake Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Error Treatment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
MONITOR Channel Programming as a Master Device . . . . . . . . . . 103
MONITOR Channel Programming as a Slave Device . . . . . . . . . . . 103
MONITOR Time-Out Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
MONITOR Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
C/I Channel Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
D-Channel Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
TIC Bus D-Channel Access Control . . . . . . . . . . . . . . . . . . . . . . . . 108
S-Bus Priority Mechanism for D-Channel . . . . . . . . . . . . . . . . . . . . 110
S-Bus D-Channel Control in LT-T . . . . . . . . . . . . . . . . . . . . . . . . . . 112
D-Channel Control in the Intelligent NT (TIC- and S-Bus) . . . . . . . . 112
Activation/Deactivation of IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . 116
Auxiliary Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
4
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
4.1.8
4.1.9
Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transceiver and C/I Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TR_MODE2 - Transceiver Mode Register 2 . . . . . . . . . . . . . . . . . . . .
CIR0 - Command/Indication Receive 0 . . . . . . . . . . . . . . . . . . . . . . .
CIX0 - Command/Indication Transmit 0 . . . . . . . . . . . . . . . . . . . . . . .
CIR1 - Command/Indication Receive 1 . . . . . . . . . . . . . . . . . . . . . . .
CIX1 - Command/Indication Transmit 1 . . . . . . . . . . . . . . . . . . . . . . .
TR_CONF0 - Transceiver Configuration Register 0 . . . . . . . . . . . . . .
TR_CONF1 - Transceiver Configuration Register 1 . . . . . . . . . . . . . .
TR_CONF2 - Transmitter Configuration Register 2 . . . . . . . . . . . . . .
TR_STA - Transceiver Status Register . . . . . . . . . . . . . . . . . . . . . . .
Data Sheet
5
120
126
126
127
128
128
129
129
131
131
133
2003-02-04
SBCX-X
PEB 3081
Table of Contents
4.1.10
4.1.11
4.1.12
4.1.13
4.1.14
4.1.15
4.1.16
4.1.17
4.1.18
4.1.19
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
4.3.10
4.3.11
4.3.12
4.3.13
4.3.14
4.3.15
4.3.16
4.3.17
4.3.18
4.3.19
4.3.20
4.3.21
4.4
4.4.1
4.4.2
4.4.3
Page
TR_CMD - Transceiver Command Register . . . . . . . . . . . . . . . . . . . .
SQRR1 - S/Q-Channel Receive Register 1 . . . . . . . . . . . . . . . . . . . .
SQXR1- S/Q-Channel TX Register 1 . . . . . . . . . . . . . . . . . . . . . . . . .
SQRR2 - S/Q-Channel Receive Register 2 . . . . . . . . . . . . . . . . . . . . .
SQXR2 - S/Q-Channel TX Register 2 . . . . . . . . . . . . . . . . . . . . . . . . .
SQRR3 - S/Q-Channel Receive Register 3 . . . . . . . . . . . . . . . . . . . .
SQXR3 - S/Q-Channel TX Register 3 . . . . . . . . . . . . . . . . . . . . . . . . .
ISTATR - Interrupt Status Register Transceiver . . . . . . . . . . . . . . . . .
MASKTR - Mask Transceiver Interrupt . . . . . . . . . . . . . . . . . . . . . . . .
TR_MODE - Transceiver Mode Register 1 . . . . . . . . . . . . . . . . . . . . .
Auxiliary Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ACFG1 - Auxiliary Configuration Register 1 . . . . . . . . . . . . . . . . . . . .
ACFG2 - Auxiliary Configuration Register 2 . . . . . . . . . . . . . . . . . . . .
AOE - Auxiliary Output Enable Register . . . . . . . . . . . . . . . . . . . . . . .
ARX - Auxiliary Interface Receive Register . . . . . . . . . . . . . . . . . . . .
ATX - Auxiliary Interface Transmit Register . . . . . . . . . . . . . . . . . . . .
IOM-2 and MONITOR Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CDAxy - Controller Data Access Register xy . . . . . . . . . . . . . . . . . . .
XXX_TSDPxy - Time Slot and Data Port Selection for CHxy . . . . . . .
CDAx_CR - Control Register Controller Data Access CH1x . . . . . . .
TR_CR - Control Register Transceiver Data (IOM_CR.CI_CS=0) . . .
TRC_CR - Control Register Transceiver C/I0 (IOM_CR.CI_CS=1) . . .
DCI_CR - Control Register for CI1 Handler (IOM_CR.CI_CS=0) . . . .
DCIC_CR - Control Register for CI0 Handler (IOM_CR.CI_CS=1) . . .
MON_CR - Control Register Monitor Data . . . . . . . . . . . . . . . . . . . . .
SDSx_CR - Control Register Serial Data Strobe x . . . . . . . . . . . . . . .
IOM_CR - Control Register IOM Data . . . . . . . . . . . . . . . . . . . . . . . .
STI - Synchronous Transfer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .
ASTI - Acknowledge Synchronous Transfer Interrupt . . . . . . . . . . . .
MSTI - Mask Synchronous Transfer Interrupt . . . . . . . . . . . . . . . . . . .
SDS_CONF - Configuration Register for Serial Data Strobes . . . . . .
MCDA - Monitoring CDA Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MOR - MONITOR Receive Channel . . . . . . . . . . . . . . . . . . . . . . . . . .
MOX - MONITOR Transmit Channel . . . . . . . . . . . . . . . . . . . . . . . . .
MOSR - MONITOR Interrupt Status Register . . . . . . . . . . . . . . . . . . .
MOCR - MONITOR Control Register . . . . . . . . . . . . . . . . . . . . . . . . .
MSTA - MONITOR Status Register . . . . . . . . . . . . . . . . . . . . . . . . . .
MCONF - MONITOR Configuration Register . . . . . . . . . . . . . . . . . . .
Interrupt and General Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISTA - Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MASK - Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AUXI - Auxiliary Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . .
Data Sheet
6
134
135
136
136
137
137
137
137
138
139
140
140
140
141
141
142
142
142
143
144
145
146
146
147
148
149
150
152
153
153
154
155
155
155
156
156
157
157
158
158
159
159
2003-02-04
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PEB 3081
Table of Contents
Page
4.4.4
4.4.5
4.4.6
4.4.7
4.4.8
4.4.9
AUXM - Auxiliary Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODE1 - Mode1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MODE2 - Mode2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ID - Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRES - Software Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMR - Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
160
160
162
163
163
164
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IOM-2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Control Interface (SCI) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S-Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Transformer Specification . . . . . . . . . . . . . . . . . . . . . . .
Line Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMC / ESD Aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
165
165
166
166
168
169
169
172
173
174
175
176
177
6
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
7
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Data Sheet
7
2003-02-04
SBCX-X
PEB 3081
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Data Sheet
Page
Logic Symbol of the SBCX-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Applications of the SBCX-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Pin Configuration of the SBCX-X (P-MQFP-44) . . . . . . . . . . . . . . . . . 17
Pin Configuration of the SBCX-X (P-TQFP-48) . . . . . . . . . . . . . . . . . . 18
Functional Block Diagram of the SBCX-X . . . . . . . . . . . . . . . . . . . . . . 24
Serial Control Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Serial Control Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Interrupt Status and Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Reset Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Timer Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
ACL Indication of Activated Layer 1 on TE Side . . . . . . . . . . . . . . . . . 35
ACL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Wiring Configurations in User Premises . . . . . . . . . . . . . . . . . . . . . . . 37
S/T-Interface Line Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Frame Structure at Reference Points S and T (ITU I.430). . . . . . . . . . 39
Data Delay between IOM-2 and S/T Interface (TE mode only) . . . . . . 42
Data Delay between IOM-2 and S/T Interface with S/G Bit Evaluation
(TE mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Data Delay between IOM-2 and S/T Interface with 8 IOM Channels
(LT-S/NT mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Data Delay between IOM-2 and S/T Interface with 3 IOM Channels and
Maximum Receive Delay (LT-S/NT mode only). . . . . . . . . . . . . . . . . . 44
Equivalent Internal Circuit of the Transmitter Stage . . . . . . . . . . . . . . 45
Equivalent Internal Circuit of the Receiver Stage . . . . . . . . . . . . . . . . 46
Connection of Line Transformers and Power Supply to the SBCX-X . 47
External Circuitry for Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
External Circuitry for Symmetrical Receivers. . . . . . . . . . . . . . . . . . . . 48
External Circuitry for Symmetrical Receivers. . . . . . . . . . . . . . . . . . . . 49
Disabling of S/T Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
External Loop at the S/T-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Clock System of the SBCX-X. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Phase Relationships of SBCX-X Clock Signals . . . . . . . . . . . . . . . . . . 56
Buffered Oscillator Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Layer-1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
State Diagram Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
State Transition Diagram (TE, LT-T) . . . . . . . . . . . . . . . . . . . . . . . . . . 61
State Transition Diagram of Unconditional Transitions (TE, LT-T) . . . 62
State Transition Diagram (LT-S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
State Transition Diagram (NT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Example of Activation/Deactivation Initiated by the Terminal . . . . . . . 76
8
2003-02-04
SBCX-X
PEB 3081
List of Figures
Figure 39
Figure 40
Figure 41
Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
Figure 48
Figure 49
Figure 50
Figure 51
Figure 52
Figure 53
Figure 54
Figure 55
Figure 56
Figure 57
Figure 58
Figure 59
Figure 60
Figure 61
Figure 62
Figure 63
Figure 64
Figure 65
Figure 66
Figure 67
Figure 68
Figure 69
Figure 70
Figure 71
Figure 72
Figure 73
Figure 74
Figure 75
Figure 76
Data Sheet
Page
Example of Activation/Deactivation initiated by the Terminal (TE).
Activation/Deactivation completely under Software Control . . . . . . . . 77
Example of Activation/Deactivation initiated by the Network Termination
(NT). Activation/Deactivation completely under Software Control . . . . 78
IOM“-2 Frame Structure in Terminal Mode. . . . . . . . . . . . . . . . . . . . . . 80
Multiplexed Frame Structure of the IOM-2 Interface
in Non-TE Timing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Architecture of the IOM Handler (Example Configuration). . . . . . . . . . 83
Data Access via CDAx1 and CDAx2 Register Pairs . . . . . . . . . . . . . . 85
Examples for Data Access via CDAxy Registers . . . . . . . . . . . . . . . . . 86
Data Access when Looping TSa from DU to DD . . . . . . . . . . . . . . . . . 87
Data Access when Shifting TSa to TSb on DU (DD) . . . . . . . . . . . . . . 88
Example for Monitoring Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Interrupt Structure of the Synchronous Data Transfer . . . . . . . . . . . . . 91
Examples for the Synchronous Transfer Interrupt Control with one
Enabled STIxy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Data Strobe Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Strobed IOM-2 Bit Clock. Register SDS_CONF Programmed to 01H . 96
Examples of MONITOR Channel Applications in IOM-2 TE Mode . . . 97
MONITOR Channel Protocol (IOM-2) . . . . . . . . . . . . . . . . . . . . . . . . . 99
Monitor Channel, Transmission Abort Requested by the Receiver . . 102
Monitor Channel, Transmission Abort Requested by the Transmitter 102
Monitor Channel, Normal End of Transmission . . . . . . . . . . . . . . . . . 102
MONITOR Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
CIC Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Applications of TIC Bus in IOM-2 Bus Configuration . . . . . . . . . . . . . 108
Structure of Last Octet of Ch2 on DU . . . . . . . . . . . . . . . . . . . . . . . . 109
Structure of Last Octet of Ch2 on DD . . . . . . . . . . . . . . . . . . . . . . . . 110
D-Channel Access Control on the S-Interface . . . . . . . . . . . . . . . . . . 111
Data Flow for Collision Resolution Procedure in Intelligent NT . . . . . 115
Deactivation of the IOM-2 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Activation of the IOM-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Register Mapping of the SBCX-X . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Oscillator Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Input/Output Waveform for AC Tests . . . . . . . . . . . . . . . . . . . . . . . . . 169
IOM-2 Timing (TE mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
IOM-2 Timing (LT-S, LT-T, NT mode) . . . . . . . . . . . . . . . . . . . . . . . . 170
Definition of Clock Period and Width . . . . . . . . . . . . . . . . . . . . . . . . . 171
SCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Reset Signal RES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Maximum Line Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Transformer Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
9
2003-02-04
SBCX-X
PEB 3081
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Data Sheet
Page
Comparison of the SBCX-X with the Previous Version SBCX . . . . . . . 11
SBCX-X Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . 19
Host Interface Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Header Byte Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Reset Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
SBCX-X Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
S/Q-Bit Position Identification and Multiframe Structure . . . . . . . . . . . 40
Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Examples for Synchronous Transfer Interrupts . . . . . . . . . . . . . . . . . . 91
CDA Register Combinations with Correct Read/Write Access . . . . . . 93
Transmit Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Receive Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
SBCX-X Configuration Settings in Intelligent NT Applications . . . . . . 113
AUX Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
IOM-2 Channel Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
10
2003-02-04
SBCX-X
PEB 3081
Overview
1
Overview
The S/T Bus Interface Circuit Extended (SBCX-X) implements the four-wire S/T interface
used to link voice/data ISDN terminals, network terminators and PBX trunk lines to a
central office. It is based on the SBCX PEB 2081, and provides enhanced features and
functionality.
The SBCX-X provides the electrical and functional link between the analog S/T interface
(compliant to the ITU recommendation I.430) and the IOM-2 interface.
It provides an S/T interface operating in TE, LT-T, LT-S, NT and intelligent NT modes, a
serial control interface (SCI) for host programming, three general purpose I/O pins and
one LED output which is capable to indicate the activation status of the S-interface
automatically or can be programmed by the host.
The SBCX-X is produced in advanced CMOS technology.
Table 1
Comparison of the SBCX-X with the Previous Version SBCX
SBCX-X PEB 3081
SBCX PEB 2081
Operating modes
TE, LT-T, LT-S, NT, Int. NT TE, LT-T, LT-S, NT
Supply voltage
3.3 V ± 5%
5 V ± 5%
Technology
CMOS
CMOS
Package
P-MQFP-44 / P-TQFP-48
P-LCC-28 / P-DIP-28
Transceiver
Transformer ratio for the
transmitter
receiver
1:1
1:1
2:1
2:1
Test Functions
- Analog loop (LP_A - bit
EXLP - bit, ARL)
- Analog loop (ARL)
Microcontroller Interface
Serial interface (SCI)
Not provided
Host programming
SCI or MON channel
(MONITOR slave mode)
MON channel
(MONITOR slave mode)
Command structure of the
register access
Header/address/data
Address/data
Crystal
7.68 MHz
7.68 MHz
Buffered 7.68 MHz output
Provided
Not provided
Data Sheet
11
2003-02-04
SBCX-X
PEB 3081
Overview
Table 1
Comparison of the SBCX-X with the Previous Version SBCX (cont’d)
SBCX-X PEB 3081
SBCX PEB 2081
Controller data access to
IOM-2 timeslots
All timeslots;
Not provided
various possibilities of data
access
Data control and
manipulation
Various possibilities of data Shifting B-channel to
control and data
channel 0 and direction
manipulation
control
(enable/disable, shifting,
looping, switching)
Auxiliary Interface
AUX0-2
(general purpose I/Os)
MAI0-7
(general purpose I/Os and
several mode dependent
functions)
IOM channel select
(LT modes)
Channel select pins
multiplexed on AUX0-2
X0-2
LED pin
ACL (host controlled or
automatic indication of
layer 1 activated state)
Not provided
Output pin for D-channel
active indication
Provided
Not provided
Control input pin for
D-channel inhibit
Provided
Not provided
Stop/Go bit output pin
Provided
Provided
IOM-2
IOM-2 Interface
Double clock (DCL),
Double clock (DCL),
bit clock (BCL),
bit clock (BCL)
serial data strobe 1 (SDS1)
serial data strobe 2 (SDS2)
Monitor channel
programming
Provided
(MON0, 1, 2, ..., 7)
Provided
(MON0 or 1)
C/I channels
CI0 (4 bit),
CI1 (4/6 bit)
CI0 (4 bit),
CI1 (6 bit)
Data Sheet
12
2003-02-04
SBCX-X
PEB 3081
Overview
Table 1
Comparison of the SBCX-X with the Previous Version SBCX (cont’d)
SBCX-X PEB 3081
SBCX PEB 2081
Layer 1 state machine
With changes for
correspondence with the
actual ITU specification
Layer 1 state machine
in software
Possible
Not possible
Reset Signals
RES input signal
RSTO output signal
RST input signal
Reset Sources
RES Input
Watchdog
C/I Code Change
EAW Pin
Software Reset
RST Input
C/I Code Change
Interrupt Output Signals
INT
Not provided
low active (open drain) by
default, reprogrammable to
high active (push-pull)
Pin SCLK
1.536 MHz
Data Sheet
512 kHz
13
2003-02-04
S/T Bus Interface Circuit Extended
SBCX-X
PEB 3081
Version 1.4
1.1
Features
• Full duplex 2B + D S/T interface transceiver according
to ITU-T I.430
• Successor of SBCX PEB 2081 in 3.3 V technology
• Conversion of the frame structure between the
S/T-interface and IOM-2
P-MQFP-44-2
• IOM-2 interface supporting TE, LT-T, LT-S, NT and
intelligent NT modes
P-MQFP-44
• Single and double clocks on IOM-2
• Two serial data strobe signals
• Serial control interface (SCI)
• Microcontroller access to all IOM-2 timeslots
• Monitor channel handler (master/slave)
• IOM-2 MONITOR and C/I-channel protocol to control
peripheral devices
• Receive timing recovery
• D-channel access control
• Activation and deactivation procedures with automatic P-TQFP-48
activation from power down state
• Access to S and Q bits of S/T-interface
• Adaptively switched receive thresholds
• 3 general purpose I/O pins multiplexed with channel select pins
• Three pins for D-channel active indication, Stop/Go bit output and E-bit control on S
• One programmable timer
• Watchdog timer
• Software Reset
• One LED pin automatically indicating layer 1 activated state
• Test loops
• Sophisticated power management for restricted power mode
Type
Package
PEB 3081 H
P-MQFP-44
PEB 3081 F
P-TQFP-48
Data Sheet
14
2003-02-04
SBCX-X
PEB 3081
Overview
• Power supply 3.3 V
• 3.3 V output drivers, inputs are 5 V safe
• Advanced CMOS technology
1.2
Logic Symbol
The logic symbol gives an overview of the SBCX-X functions. It must be noted that not
all functions are available simultaneously, but depend on the selected mode.
Pins which are marked with a “ * “ are multiplexed and not available in all modes.
IOM-2 Interface
+3.3V 0V
0V
2
DU
DD
FSC
DCL
BCL/ SDS1/2 VDD VSS TP
VDDA VSSA
SCLK
SCL
C768
SDR
Host
Interface
(SCI)
SDX
XTAL2
CS
XTAL1
INT
7.68 MHz output
7.68 MHz ± 100ppm
SR1
RES
SR2
RSTO
S Interface
SX1
SX2
D-channel
Active Indication
DCA
D-channel Inhibit
DCI
S/G Bit Output
SGO
MODE0
Mode
Setting
MODE1 / EAW
AUX0...2 *
CH0...2 *
General
purpose I/O
IOM channel
select
ACL
LED Output
3081_17
Auxiliary Interface
Figure 1
Data Sheet
Logic Symbol of the SBCX-X
15
2003-02-04
SBCX-X
PEB 3081
Overview
1.3
Typical Applications
The SBCX-X is designed for the user area of the ISDN basic access. By programming
the corresponding operating mode it may be used at both ends of these interfaces.
Figure 2 illustrates the general application fields of the SBCX-X:
•
•
•
•
ISDN terminals (TE mode)
ISDN network termination (NT) for a link between the S/T interface and the U interface
ISDN subscriber line termination (LT-S)
ISDN trunk line termination (LT-T), i.e. PBX connection to central office
S
TE(1)
LT-S
TE(8)
Network Terminator (NT)
S
U
TE (1)
NT 1
NT
T
TE(8)
NT 2
LT-S
NT 1
LT-T
NT
ITS04492
= SBCX-X
Figure 2
Data Sheet
Applications of the SBCX-X
16
2003-02-04
SBCX-X
PEB 3081
Pin Configuration
2
Pin Configuration
VDD
VSS
XTAL1
VSS
XTAL2
SX2
SX1
VDDA
VSSA
SR2
SR1
P-MQFP-44
33 32 31 30 29 28 27 26 25 24 23
BCL / SCLK
DU
34
35
22
21
DD
FSC
36
20
37
38
19
18
SDS1
17
C768
SGO
13
44
12
VSS
Data Sheet
SDX
9 10 11
SCL
SDR
2 3 4 5 6 7 8
INT
n.c.
1
Figure 3
SDS2
43
VDD
MODE1 / EAW
ACL
16
15
14
AUX1
AUX0
DCI
DCA
VDD
VSS
MODE0
40
41
42
RES
RSTO
VSS
VDD
SBCX-X
PEB 3081
39
CS
TP
DCL
VSS
AUX2
3081_02.vsd
Pin Configuration of the SBCX-X (P-MQFP-44)
17
2003-02-04
SBCX-X
PEB 3081
Pin Configuration
VSS
VDD
XTAL2
XTAL1
n.c.
VSS
SX2
SX1
VDDA
VSSA
SR2
SR1
P-TQFP-48
36 35 34 33 32 31 30 29 28 27 26 25
AUX1
AUX0
40
21
SDS1
20
19
18
SDS2
17
16
DCI
DCA
46
15
47
48
14
13
n.c.
VDD
41
42
43
SBCX-X
PEB 3081
2 3 4 5 6 7 8
INT
n.c.
1
Figure 4
Data Sheet
C768
SGO
VSS
9 10 11 12
SDX
44
45
SCL
SDR
MODE1 / EAW
ACL
n.c.
23
22
n.c.
MODE0
38
39
VDD
VSS
VDD
AUX2
VSS
DCL
VSS
24
RES
RSTO
DD
FSC
37
CS
TP
BCL / SCLK
DU
3081_01.vsd
Pin Configuration of the SBCX-X (P-TQFP-48)
18
2003-02-04
SBCX-X
PEB 3081
Pin Configuration
Table 2
SBCX-X Pin Definitions and Functions
Pin No.
MQFP44
Symbol
Input (I)
Function
Output (O)
Open
Drain (OD)
TQFP48
Host Interface
9
10
SCL
I
SCL - Serial Clock
Clock signal of the SCI interface if a
serial interface is selected.
10
11
SDR
I
SDR - Serial Data Receive
Receive data line of the SCI interface if a
serial interface is selected.
11
12
SDX
OD
SDX - Serial Data Transmit
Transmit data line of the SCI interface if
a serial interface is selected.
3
3
CS
I
Chip Select
A low level indicates a microcontroller
access to the SBCX-X.
1
1
INT
O (OD)
Interrupt Request
INT becomes active (low) if the SBCX-X
requests an interrupt (open drain
characteristic).
The polarity can be reprogrammed to
high active with push-pull characteristic.
5
5
RES
I
Reset
A LOW on this input forces the SBCX-X
into a reset state.
IOM-2 Interface
37
40
FSC
I/O
Frame Sync
8-kHz frame synchronization signal.
38
41
DCL
I/O
Data Clock
IOM-2 interface clock signal (double
clock, e.g. 1.536 MHz in TE mode).
Data Sheet
19
2003-02-04
SBCX-X
PEB 3081
Pin Configuration
Table 2
SBCX-X Pin Definitions and Functions (cont’d)
Pin No.
Symbol
Input (I)
Function
Output (O)
Open
Drain (OD)
MQFP44
TQFP48
34
37
BCL/
SCLK
O
Bit Clock/S-Clock
TE-Mode:
Bit clock output, identical to IOM-2 data
rate (DCL/2).
LT-T Mode:
1.536 MHz output synchronous to
S-interface.
NT / LT-S Mode:
Bit clock output derived from the DCL
input clock divided by 2.
36
39
DD
I/O (OD)
Data Downstream
IOM-2 data signal in downstream
direction.
35
38
DU
I/O (OD)
Data Upstream
IOM-2 data signal in upstream direction.
19
21
SDS1
O
Serial Data Strobe 1
Programmable strobe signal for time slot
and/or D-channel indication on IOM-2.
18
20
SDS2
O
Serial Data Strobe 2
Programmable strobe signal for time slot
and/or D-channel indication on IOM-2.
Miscellaneous
28
29
31
32
SX1
SX2
O
O
S-Bus Transmitter Output (positive)
S-Bus Transmitter Output (negative)
32
33
35
36
SR1
SR2
I
I
S-Bus Receiver Input
S-Bus Receiver Input
25
27
XTAL1
I
26
28
XTAL2
O
Crystal 1
Connection for a crystal or used as
external clock input. 7.68 MHz clock or
crystal required.
Crystal 2
Connection for a crystal. Not connected if
an external clock is supplied to XTAL1
Data Sheet
20
2003-02-04
SBCX-X
PEB 3081
Pin Configuration
Table 2
SBCX-X Pin Definitions and Functions (cont’d)
Pin No.
Symbol
Input (I)
Function
Output (O)
Open
Drain (OD)
MQFP44
TQFP48
20
21
22
22
23
24
AUX0
AUX1
AUX2
I/O (OD)
I/O (OD)
I/O (OD)
TE-Mode:
Auxiliary Port 0 - 2 (input/output)
These pins are individually
programmable as general input/output.
The state of the pin can be read from
(input) / written to (output) a register.
LT-T/LT-S/NT Mode:
CH0-2 - IOM-2 Channel Select (input)
These pins select one of eight channels
on the IOM-2 interface.
42
45
MODE0
I
Mode 0 Select
A LOW selects TE-mode and a HIGH
selects LT-T / LT-S mode (see MODE1/
EAW).
43
46
MODE1
I
EAW
I
The pin function depends on the setting
of MODE0.
If MODE0=1: Mode 1 Select
A LOW selects LT-T mode and a HIGH
selects LT-S mode.
If MODE0=0: External Awake
If a falling edge on this input is detected,
the SBCX-X generates an interrupt and,
if enabled, a reset pulse.
6
6
RSTO
OD
Reset Output
Low active reset output, either from a
watchdog timeout or programmed by the
host.
17
19
C768
O
Clock Output
A 7.68 MHz clock is output to support
other devices. This clock is not
synchronous to the S interface.
14
16
DCA
O
DCA - D-Channel Active Indication
This pin provides an output of the
D-channel bits on the S-bus receive line.
Data Sheet
21
2003-02-04
SBCX-X
PEB 3081
Pin Configuration
Table 2
SBCX-X Pin Definitions and Functions (cont’d)
Pin No.
Symbol
Function
Input (I)
Output (O)
Open
Drain (OD)
MQFP44
TQFP48
15
17
DCI
I
DCI - D-Channel Inhibit
If this bit is set to ’1’ the E-bits are
inverted, i.e. the D-channel is blocked
(only in NT/LT-S mode). This pin has the
same function as the D-channel inhibit bit
(see TR_MODE.DCH_INH).
16
18
SGO
O
SGO - Stop/Go Bit Output
A S/G bit output with programmable
polarity and length (TR_CONF2 register)
is provided.
44
47
ACL
O
Activation LED
This pin can either function as a
programmable output or it can
automatically indicate the activated state
of the S interface by a logic ’0’.
An LED with pre-resistance may directly
be connected to ACL.
4
4
TP
I
Test Pin
Must be connected to VSS.
2
2, 9, 15, n.c.
30, 48
Not Connected
Power Supply
8, 13, 23, 8, 14,
41
25, 44
VDD
–
Digital Power Supply Voltage
(3.3 V ± 5 %)
31
VDDA
–
Analog Power Supply Voltage
(3.3 V ± 5 %)
7, 12, 24, 7, 13,
27, 39,
26, 29,
40
42, 43
VSS
–
Digital Ground
(0 V)
30
VSSA
–
Analog Ground
(0 V)
Data Sheet
34
33
22
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3
Description of Functional Blocks
3.1
General Functions and Device Architecture
Figure 5 shows the architecture of the SBCX-X containing the following functions:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
S/T-interface transceiver supporting TE, LT-T, LT-S, NT and intelligent NT modes
Serial Control Interface (SCI)
IOM-2 interface for terminal, linecard and NT applications, with single/double clock
Two serial data strobe signals
IOM handler with controller data access registers (CDA) allows flexible access to IOM
timeslots for reading/writing, looping and shifting data
Synchronous transfer interrupts (STI) allow controlled access to IOM timeslots
MONITOR channel handler on IOM-2 for master mode, slave mode or data exchange
C/I-Channel handler
D-channel access mechanism
3-pin auxiliary port for general purpose I/O pins or channel select pins
LED connected to pin ACL indicates S-interface activation status automatically or can
be controlled by the host
Output for D-channel active indication (output of received D-bits on S)
Stop/Go bit output with programmable polarity and length
D-channel inhibit input pin to control inversion of E-bits on S to block other terminals
Level detect circuit on the S interface reduces power consumption in power down
mode
Timer for periodic or single interrupts
Clock and timing generation
Digital PLL to synchronize the transceiver to the S/T interface
Buffered 7.68 MHz oscillator clock output allows connection of further devices and
saves another crystal on the system board
Reset generation (watchdog timer)
Data Sheet
23
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
Peripheral Devices
IOM-2 Interface
IOM-2 Handler
S Transceiver
General
Purpose
I/Os
Auxiliary
Interface
MONITOR
Handler
TIC
C/I
DPLL
Serial Host Interface
(SCI)
Reset
Interrupt
generation
OSC
3081_18
Host
Figure 5
Data Sheet
Functional Block Diagram of the SBCX-X
24
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.2
Microcontroller Interface
The SBCX-X supports a serial micrcontroller interface. For applications where no
controller is connected to the SBCX-X programming is done via the IOM-2 MONITOR
channel from a master device. In such applications the SBCX-X operates in the IOM-2
slave mode (refer to the corresponding chapter of the IOM-2 MONITOR handler). This
mode is suitable for control functions (e.g. programming registers of the S/T transceiver),
but the bandwidth is not sufficient to transfer B- and D-channel data.
The interface selection is done by pinstrapping of the chip select signal CS (see
Table 3). The selection pins are evaluated when the reset input RES is active. For the
pin levels stated in the table the following is defined:
’High’: dynamic pin; value must be ’High’ only during reset
VSS: static pin; pin must statically be strapped to ’Low’ level
Table 3
Host Interface Selection
CS
Interface Mode
’High’
Serial Control Interface (SCI)
VSS
IOM-2 MONITOR Channel (Slave Mode)
The interfaces contain all circuitry necessary for the access to programmable registers.
The mapping of all these registers can be found in Chapter 4.
The microcontroller interface also provides an interrupt request at pin INT which is low
active by default but can be reprogrammed to high active, a reset input pin RES and a
reset output pin RSTO.
The interrupt request pin INT becomes active if the SBCX-X requests an interrupt and
this can occur at any time.
Data Sheet
25
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.2.1
Serial Control Interface (SCI)
The serial control interface (SCI) is compatible to the SPI interface of Motorola or
Siemens C510 family of microcontrollers.
The SCI consists of 4 lines: SCL, SDX, SDR and CS. Data is transferred via the lines
SDR and SDX at the rate given by SCL. The falling edge of CS indicates the beginning
of a serial access to the registers. The SBCX-X latches incoming data at the rising edge
of SCL and shifts out at the falling edge of SCL. Each access must be terminated by a
rising edge of CS. Data is transferred in groups of 8 bits with the MSB first.
Figure 6 shows the timing of a one byte read/write access via the serial control interface.
Write Access
CS
SCL
Header
SDR
Address
Data
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
'0'
write
SDX
Read Access
CS
SCL
Header
SDR
Address
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
'1'
read
Data
7 6 5 4 3 2 1 0
SDX
21150_19
Figure 6
Data Sheet
Serial Control Interface Timing
26
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.2.2
Programming Sequences
The basic structure of a read/write access to the SBCX-X registers via the serial control
interface is shown in Figure 7.
write sequence:
write
byte 2
0
header
SDR
7
address
0 7 6
read sequence:
byte 3
write data
0 7
0
read
byte 2
header
SDR
7
1
address
0 7 6
0 7
SDX
Figure 7
byte 3
0
read data
Serial Control Interface Timing
A new programming sequence starts with the transfer of a header byte. The header byte
specifies different programming sequences allowing a flexible and optimized access to
the individual functional blocks of the SBCX-X.
The possible sequences for access to the complete address range 00H-7FH are listed in
Table 4 and described after that.
Table 4
Header
Byte
Header Byte Code
Sequence
40H/44H
48H/4CH
Alternating Read/Write (non-interleaved)
Adr-Data-Adr-Data
43H/47H
41H/45H
49H/4DH
Sequence Type
Alternating Read/Write (interleaved)
Read-only/Write-only (constant address)
Adr-Data-Data-Data
Read and following Write-only (non-interleaved)
Read and following Write-only (interleaved)
Note: In order to access the address range 00H-7FH bit 2 of the header byte must be set
to ’0’ (header bytes 40H, 48H, 43H, 41H, 49H), and for the addresses 80H-FFH bit 2
must be set to ’1’ (header bytes 44H, 4CH, 47H, 45H, 4DH).
Data Sheet
27
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
Header 40H: Non-interleaved A-D-A-D Sequences
The non-interleaved A-D-A-D sequence gives direct read/write access to the complete
address range and can have any length. In this mode SDX and SDR can be connected
together allowing data transmission on one line.
Example for a read/write access with header 40H:
SDR header wradr wrdata
rdadr
SDX
rdadr
rddata
wradr wrdata
rdata
Header 48H: Interleaved A-D-A-D Sequences
The interleaved A-D-A-D sequence gives direct read/write access to the complete
address range and can have any length. This mode allows a time optimized access to
the registers by interleaving the data on SDX and SDR (SDR and SDX must not be
connected together).
Example for a read/write access with header 48H:
SDR header wradr wrdata
rdadr
SDX
rdadr
wradr wrdata
rddata rddata
Header 43H: Read-/Write- only A-D-D-D Sequence (Constant Address)
This mode can be used for a fast access to the HDLC FIFO data. Any address (rdadr,
wradr) in the range 00H-1FH and 6AH/7AH gives access to the current FIFO location
selected by an internal pointer which is automatically incremented with every data byte
following the first address byte. The sequence can have any length and is terminated by
the rising edge of CS.
Example for a write access with header 43H:
SDR header wradr wrdata wrdata wrdata wrdata wrdata wrdata wrdata
(wradr)
(wradr)
(wradr)
(wradr)
(wradr)
(wradr)
(wradr)
SDX
Example for a read access with header 43H:
SDR header rdadr
SDX
rddata rddata rddata rddata rddata rddata rddata
(rdadr)
Data Sheet
(rdadr)
(rdadr)
28
(rdadr)
(rdadr)
(rdadr)
(rdadr)
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
Header 41H: Non-interleaved A-D-D-D Sequence
This sequence allows in front of the A-D-D-D write access a non-interleaved A-D-A-D
read access. This mode is useful for reading status information before writing to the
HDLC XFIFO. The termination condition of the read access is the reception of the wradr.
The sequence can have any length and is terminated by the rising edge of CS.
Example for a read/write access with header 41H:
SDR header rdadr
wradr wrdata wrdata wrdata
rdadr
(wradr)
SDX
rddata
(wradr)
(wradr)
rddata
Header 49H: Interleaved A-D-D-D Sequence
This sequence allows in front of the A-D-D-D write access an interleaved A-D-A-D read
access. This mode is useful for reading status information before writing to the HDLC
XFIFO. The termination condition of the read access is the reception of the wradr. The
sequence can have any length and is terminated by the rising edge of the CS line.
Example for a read/write access with header 49H:
SDR header rdadr
rdadr
wradr wrdata wrdata wrdata
(wradr)
SDX
3.2.3
(wradr)
(wradr)
rddata rddata
Interrupt Structure
Special events in the device are indicated by means of a single interrupt output, which
requests the host to read status information from the device or transfer data from/to the
device.
Since only one interrupt request pin (INT) is provided, the cause of an interrupt must be
determined by the host reading the interrupt status registers of the device.
The structure of the interrupt status registers is shown in Figure 8.
Data Sheet
29
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
MASK
ISTA
ST
ST
CIC
CIC
AUX
AUX
TRAN
TRAN
MOS
MOS
MSTI
STI
STOV21
STOV21
ASTI
STOV20
STOV20
STOV11
STOV11
STOV10
STOV10
STI21
STI21
ACK21
STI20
STI20
ACK20
STI11
STI11
ACK11
STI10
STI10
ACK10
CIR0
CIC0
CI1E
CIC1
EAW
EAW
LD
WOV
WOV
RIC
RIC
SQC
SQC
TIN
AUXM
TIN
AUXI
LD
SQW
MASKTR
Interrupt
CIX1
MRE
SQW
ISTATR
MDR
MER
Figure 8
MIE
MDA
MOCR
MAB
MOSR
3081_16.vsd
Interrupt Status and Mask Registers
All five interrupt bits in the ISTA register point at interrupt sources in the Monitor handler
(MOS), C/I handler (CIC), the transceiver (TRAN), the synchronous transfer (ST) and the
auxiliary interrupts (AUXI).
All these interrupt sources are described in the corresponding chapters. After the device
has requested an interrupt activating the interrupt pin (INT), the host must read first the
device interrupt status register (ISTA) in the associated interrupt service routine. The
interrupt pin of the device remains active until all interrupt sources are cleared by reading
the corresponding interrupt register. Therefore it is possible that the interrupt pin is still
active when the interrupt service routine is finished.
Each interrupt indication of the interrupt status registers can selectively be masked by
setting the respective bit in the MASK register.
For some interrupt controllers or hosts it might be necessary to generate a new edge on
the interrupt line to recognize pending interrupts. This can be done by masking all
interrupts at the end of the interrupt service routine (writing FFH into the MASK register)
and write back the old mask to the MASK register.
Data Sheet
30
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.2.4
Reset Generation
Figure 9 shows the organization of the reset generation of the device.
.
C/I Code Change
(Exchange Awake)
RSS1
125µs £ t £ 250µs
³1
EAW
(Subscriber Awake)
125µs £ t £ 250µs
'0'
'1x'
'1'
'01'
'00'
³1
Software Reset
Register (SRES)
' 01 '
RSS2,1
125µs £ t £ 250µs
Watchdog
(reserved)
RSS2,1
³1
Pin
RSTO
125µs £ t £ 250µs
Transceiver, C/I (22H-3FH)
Reset
IOM-2 (40H-5BH)
Functional
MON-channel (5CH-5FH)
Block
General Config (60H-6FH)
Reset MODE1 Register
Pin
RES
Internal Reset of all Registers
3081_21
Figure 9
Reset Generation
Reset Source Selection
The internal reset sources C/I code change, EAW and Watchdog can be output at the
low active reset pin RSTO. The selection of these reset sources can be done with the
RSS2,1 bits in the MODE1 register according Table 5.
The setting RSS2,1 = ’01’ is reserved for further use. In this case no reset except
software reset (SRES.RSTO) is output on RSTO. The internal reset sources set the
MODE1 register to its reset value.
Data Sheet
31
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
Table 5
Reset Source Selection
RSS2
Bit 1
RSS1
Bit 0
C/I Code
Change
EAW
Watchdog
Timer
0
0
--
--
--
0
1
1
0
x
x
--
1
1
--
--
x
reserved
• C/I Code Change (Exchange Awake)
A change in the downstream C/I channel (C/I0) generates an external reset pulse of
125 µs £ t £ 250 µs.
• EAW (Subscriber Awake)
A low level on the EAW input starts the oscillator from the power down state and
generates a reset pulse of 125 µs £ t £ 250 µs.
• Watchdog Timer
After the selection of the watchdog timer (RSS = ’11’) an internal timer is reset and
started. During every time period of 128 ms the microcontroller has to program the
WTC1- and WTC2 bits in the following sequence to reset and restart the watchdog timer:
1.
2.
WTC1
WTC2
1
0
0
1
If not, the timer expires and a WOV-interrupt (ISTA Register) together with a reset pulse
of 125 µs is generated.
Deactivation of the watchdog timer is only possible with a hardware reset.
External Reset Input
At the RES input an external reset can be applied forcing the device in the reset state.
This external reset signal is additionally fed to the RSTO output. The length of the reset
signal is specified in Chapter 5.8.
After an external reset from the RES pin all registers of the device are set to its reset
values (see register description in Chapter 4).
Software Reset Register (SRES)
Every main functional block of the device can be reset separately by software setting the
corresponding bit in the SRES register. A reset to external devices can also be controlled
in this way. The reset state is activated by setting the corresponding bit to ’1’ and onchip
Data Sheet
32
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
logic resets this bit again automatically after 4 BCL clock cycles. The address range of
the registers which will be reset at each SRES bit is listed in Figure 9.
3.2.5
Timer Modes
The SBCX-X provides one timer which can be used for various purposes. It provides two
modes (Table 6), a count down timer interrupt, i.e. an interrupt is generated only once
after expiration of the selected period, and a periodic timer interrupt, which means an
interrupt is generated continuously after every expiration of that period.
Table 6
Address
65H
SBCX-X Timer
Register
TIMR
Modes
Period
Periodic
1 ... 63 ms
Count Down
1 ... 63 ms
When the programmed period has expired an interrupt is generated and indicated in the
auxiliary interrupt status ISTA.AUX. The source of the interrupt can be read from
AUXI.TIN and masked in AUXM.
MASK
ST
CIC
AUX
TRAN
MOS
ISTA
AUXM
EAW
WOV
TIN
ST
CIC
AUX
TRAN
MOS
AUXI
EAW
WOV
TIN
Interrupt
Figure 10
Data Sheet
Timer Interrupt Status Registers
33
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
The host starts and stops the timer in TIMR.CNT (Figure 11). If TIMR.TMD=0 the timer
is operating in count down mode, for TIMR.TMD=1 a periodic interrupt AUXI.TIN is
generated. The timer length (for count down timer) or the timer period (for periodic timer),
respectively, can be configured to a value between 1 - 63 ms (TIMR.CNT).
Timer Mode
0 : Count Down Timer
1 : Periodic Timer
Timer Count
0 : Timer off
1 ... 63 : 1 ... 63 ms
7
TIMR
Figure 11
Data Sheet
6
5
TMD 0
4
3
2
1
0
65H
CNT
3081_14
Timer Register
34
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.2.6
Activation Indication via Pin ACL
The activated state of the S-interface is directly indicated via pin ACL (Activation LED).
An LED with pre-resistance may directly be connected to this pin and a low level is driven
on ACL as soon as the layer 1 state machine reaches the activated state (see
Figure 12).
Figure 12
ACL Indication of Activated Layer 1 on TE Side
By default (ACFG2.ACL=0) the state of layer 1 is indicated at pin ACL. If the automatic
indication of the activated layer 1 is not required, the state on pin ACL can also be
controlled by the host (see Figure 13).
If ACFG2.ACL=1 the LED on pin ACL can be switched on (ACFG2.LED=1) and off
(ACFG2.LED=0) by the host.
+3.3V
'1'
ACL
ACFG2:LED
0 : off
1 : on
'0'
Layer 1
S Interface
ACFG2:ACL
3086_15
Figure 13
Data Sheet
ACL Configuration
35
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.3
S/T-Interface
The layer-1 functions for the S/T interface of the SBCX-X are:
– line transceiver functions for the S/T interface according to the electrical specifications
of ITU-T I.430;
– conversion of the frame structure between IOM-2 and S/T interface;
– conversion from/to binary to/from pseudo-ternary code;
– level detection;
– receive timing recovery for point-to-point, passive bus and extended passive bus
configuration;
– S/T timing generation using IOM-2 timing synchronous to system, or vice versa;
– D-channel access control and priority handling;
– D-channel echo bit generation by handling of the global echo bit;
– activation/deactivation procedures, triggered by primitives received over the IOM-2
interface or by INFOs received from the line;
– execution of test loops.
The wiring configurations in user premises, in which the SBCX-X can be used, are
illustrated in Figure 14.
Data Sheet
36
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
£ 1000 m 1)
SBCX-X
TR
TR
TE
SBCX-X
LT-S
£ 1000 m 1)
SBCX-X
TR
TR
SBCX-X
LT-T
Point-to-Point
Configurations
NT
1) The maximum line attenuation tolerated by the SBCX-X is 7 dB at 96 kHz.
£ 100 m
TR
TR
£ 10 m
SBCX-X
....
TE1
SBCX-X
Short
Passive Bus
NT / LT-S
SBCX-X
TE8
£ 500 m
£ 25 m
TR
TR
£ 10 m
SBCX-X
TE1
Figure 14
Data Sheet
....
SBCX-X
Extended
Passive Bus
NT / LT-S
TR: Terminating Resistor
SBCX-X
TE8
3081_20
Wiring Configurations in User Premises
37
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.3.1
S/T-Interface Coding
Transmission over the S/T-interface is performed at a rate of 192 kbit/s. 144 kbit/s are
used for user data (B1+B2+D), 48 kbit/s are used for framing and maintenance
information.
Line Coding
The following figure illustrates the line code. A binary ONE is represented by no line
signal. Binary ZEROs are coded with alternating positive and negative pulses with two
exceptions:
For the required frame structure a code violation is indicated by two consecutive pulses
of the same polarity. These two pulses can be adjacent or separated by binary ONEs.
In bus configurations a binary ZERO always overwrites a binary ONE.
0 1 1
code violation
Figure 15
S/T-Interface Line Code
Frame Structure
Each S/T frame consists of 48 bits at a nominal bit rate of 192 kbit/s. For user data
(B1+B2+D) the frame structure applies to a data rate of 144 kbit/s (see Figure 16).
In the direction TE ® NT the frame is transmitted with a two bit offset. For details on the
framing rules please refer to ITU I.430 section 6.3. The following figure illustrates the
standard frame structure for both directions (NT ® TE and TE ® NT) with all framing
and maintenance bits.
Data Sheet
38
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
Figure 16
Frame Structure at Reference Points S and T (ITU I.430)
– F
Framing Bit
F = (0b) ® identifies new frame (always
positive pulse, always code violation)
– L.
D.C. Balancing Bit
L. = (0b) ® number of binary ZEROs sent
after the last L. bit was odd
– D
D-Channel Data Bit
Signaling data specified by user
– E
D-Channel Echo Bit
E = D ® received E-bit is equal to transmitted
D-bit
– FA
Auxiliary Framing Bit
See section 6.3 in ITU I.430
– N
N = FA
– B1
B1-Channel Data Bit
User data
– B2
B2-Channel Data Bit
User data
– A
Activation Bit
A = (0b) ® INFO 2 transmitted
A = (1b) ® INFO 4 transmitted
– S
S-Channel Data Bit
S1 channel data (see note below)
– M
Multiframing Bit
M = (1b) ® Start of new multiframe
Note: The ITU I.430 standard specifies S1 - S5 for optional use.
Data Sheet
39
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.3.2
S/T-Interface Multiframing
According to ITU recommendation I.430 a multiframe provides extra layer 1 capacity in
the TE-to-NT direction by using an extra channel between the TE and NT (Q-channel).
The Q bits are defined to be the bits in the FA bit position.
In the NT-to-TE direction the S-channel bits are used for information transmission. One
S channel (S1) out of five possible S-channels can be accessed by the SBCX-X.
In the NT-to-TE direction the S-channel bits are used for information transmission.
The S and Q channels are accessed via the µC interface or the IOM-2 MONITOR
channel, respectively, by reading/writing the SQR or SQX bits in the S/Q channel
registers (SQRRx, SQXRx).
Table 7 shows the S and Q bit positions within the multiframe.
Table 7
S/Q-Bit Position Identification and Multiframe Structure
Frame Number
NT-to-TE
NT-to-TE
FA Bit Position M Bit
NT-to-TE
S Bit
TE-to-NT
FA Bit Position
1
2
3
4
5
ONE
ZERO
ZERO
ZERO
ZERO
ONE
ZERO
ZERO
ZERO
ZERO
S11
S21
S31
S41
S51
Q1
ZERO
ZERO
ZERO
ZERO
6
7
8
9
10
ONE
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
S12
S22
S32
S42
S52
Q2
ZERO
ZERO
ZERO
ZERO
11
12
13
14
15
ONE
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
S13
S23
S33
S43
S53
Q3
ZERO
ZERO
ZERO
ZERO
16
17
18
19
20
ONE
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
S14
S24
S34
S44
S54
Q4
ZERO
ZERO
ZERO
ZERO
1
2
ONE
ZERO
ONE
ZERO
S11
S21
Q1
ZERO
Data Sheet
40
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
TE Mode
After multiframe synchronization has been established, the Q data will be inserted at the
upstream (TE ® NT) FA bit position in each 5th S/T frame (see Table 7).
When synchronization is not achieved or lost, each received FA bit is mirrored to the next
transmitted FA bit.
Multiframe synchronization is achieved after two complete multiframes have been
detected with reference to FA/N bit and M bit positions. Multiframe synchronization is lost
if bit errors in FA/N bit or M bit positions have been detected in two consecutive
multiframes. The synchronization state is indicated by the MSYN bit in the S/Q-channel
receive register (SQRR1).
The multiframe synchronization can be enabled or disabled by programming the MFEN
bit in the S/Q-channel transmit register (SQXR1).
NT Mode
The transceiver in NT mode starts multiframing if SQXR1.MFEN is set.
After multiframe synchronization has been established in the TE, the Q data will be
inserted at the upstream (TE ® NT) FA bit position by the TE in each 5th S/T frame, the
S data will be inserted at the downstream (NT ® TE) S bit position in each S/T frame
(see Table 7).
Interrupt Handling for Multiframing
To trigger the microcontroller for a multiframe access an interrupt can be generated once
per multiframe (SQW) or if the received S-channels (TE) or Q-channel (NT) have
changed (SQC).
In both cases the microcontroller has access to the multiframe within the duration of one
multiframe (5 ms).
Data Sheet
41
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.3.3
Data Transfer and Delay between IOM-2 and S/T
TE mode
In the state F7 (Activated) or if the internal layer-1 statemachine is disabled and XINF of
register TR_CMD is programmed to ’011’ the B1, B2, D and E bits are transferred
transparently from the S/T to the IOM-2 interface. In all other states ’1’s are transmitted
to the IOM-2 interface.
To transfer data transparently to the S/T interface any activation request C/I command
(AR8, AR10 or ARL) is additionally necessary or if the internal layer-1 statemachine is
disabled, bit TDDIS of register TR_CMD has additionally to be programmed to ’0’.
Figure 17 shows the data delay between the IOM-2 and the S/T interface and vice
versa.
For the D channel the delay from the IOM-2 to the S/T interface is only valid if S/G
evaluation is disabled (TR_MODE2.DIM0=0). If S/G evaluation is enabled
(TR_MODE2.DIM2-0=0x1) the delay depends on the selected priority and the relation
between the echo bits on S and the D channel bits on the IOM-2, e.g. for priority 8 the
timing relation between the 8th D-bit on S bus and the D-channel on IOM-2.
E
NT -> TE
F
D
E
B1
B2
D
TE -> NT
F
B1
B2
D
E
D
E
B1
B2
D
D
B1
D
E
F
E
B1
D
B2
D
F
B2
D
B1
B2
D
E
D
E
B1
B2
D
D
B1
D
D
B2
FSC
DU
B1 B2 D
B1 B2 D
B1 B2 D
B1 B2 D
DD
B1 B2 D
Figure 17
Data Sheet
E
B1 B2 D
E
B1 B2 D
E
B1 B2 D
E
line_iom_s.vsd
Data Delay between IOM-2 and S/T Interface (TE mode only)
42
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
E
NT -> TE
F
D
E
B1
B2
D
TE -> NT
F
B1
B2
D
E
D
E
B1
B2
D
D
B1
D
E
F
E
B1
D
B2
D
F
B2
D
B1
D
E
D
E
B1
B2
D
D
B2
B1
D
D
B2
FSC
DU
B1 B2 D
B1 B2 D
B1 B2 D
B1 B2 D
DD
B1 B2 D
E
B1 B2 D
E
B1 B2 D
E
B1 B2 D
Mapping of B-Channel Timeslots
Mapping of a 4-bit group of D-bits on S and IOM depends on prehistory (e.g. priority control):
1. Possibility
2. Possibility
Figure 18
E
line_iom_s_dch.vsd
Data Delay between IOM-2 and S/T Interface with S/G Bit Evaluation
(TE mode only)
LT-T mode
In this mode the frame relation between S/T interface and IOM-2 is flexible.
LT-S/NT mode
In the state F7 (Activated) or if the internal layer-1 statemachine is disabled and XINF of
register TR_CMD is programmed to ’011’ the B1, B2 and D bits are transferred
transparently from the S/T to the IOM-2 interface. In all other states ’1’s are transmitted
to the IOM-2 interface.
Note: In intelligent NT the D-channel access can be blocked by the IOM-2 D-channel
handler.
Data Sheet
43
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
E
NT -> TE
F
D
E
B1
D
B2
D
F
TE -> NT
B1
E
D
E
B1
B2
D
D
B2
B1
D
E
F
D
B1
D
B2
D
B2
E
D
F
B1
E
D
E
B1
B2
D
D
B2
B1
D
D
B2
FSC
DD
B1 B2
D
B1 B2
D
B1 B2
D
B1 B2
D
B1 B2
D
B1 B2
D
B1 B2
D
B1 B2
D
DU
Figure 19
Data Delay between IOM-2 and S/T Interface with 8 IOM Channels
(LT-S/NT mode only)
E
NT -> TE
F
D
E
B1
D
B2
D
F
TE -> NT
line_iom_s4nt.vsd
B1
B2
E
F
B1
E
B1
B2
D
D
B1
D
TE -> NT (42µs)
D
E
F
D
B2
F
D
B2
D
B1
B2
D
D
D
B1
E
B1
D
D
B2
D
B2
F
B1
E
D
E
B1
B2
D
D
B1
D
B2
D
B2
D
D
B1
D
B2
FSC
DU
B1 B2 D
B1 B2 D
B1 B2 D
B1 B2 D
DD
B1 B2 D
Figure 20
Data Sheet
E
B1 B2 D
E
B1 B2 D
E
B1 B2 D
E
line_iom_s4nt_dly.vsd
Data Delay between IOM-2 and S/T Interface with 3 IOM Channels and
Maximum Receive Delay (LT-S/NT mode only)
44
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.3.4
Transmitter Characteristics
The full-bauded pseudo-ternary pulse shaping is achieved with the integrated transmitter
which is realized as a symmetrical current limited voltage source (VSX1/SX2 = +/-1.05 V;
Imax = 26 mA). The equivalent circuit of the transmitter is shown in Figure 21.
The nominal pulse amplitude on the S-interface of 750 mV (zero-peak) is adjusted with
external resistors (see Chapter 3.3.6.1).
VCM+0.525V
VCM
VCM-0.525V
'+0'
'1'
'-0'
+
SX1
V=1
-
Level
VCM-0.525V
VCM
VCM+0.525V
Figure 21
Data Sheet
'+0'
'1'
VCM
TR_CONF2.DIS_TX
'+0' '1' '-0'
-
SX2
V=1
+
'-0'
21150_28
Equivalent Internal Circuit of the Transmitter Stage
45
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.3.5
Receiver Characteristics
The receiver consists of a differential input stage, a peak detector and a set of
comparators. Additional noise immunity is achieved by digital oversampling after the
comparators. A simplified equivalent circuit of the receiver is shown in Figure 22.
100 kW
10 kW
SR1
40 kW
VrefLD
Level detected
Vrefmin
10 kW
SR2
40 kW
VCM
Vref+
Positive detected
Peak
Detector Vref-
Negative detected
reccirc
Figure 22
Equivalent Internal Circuit of the Receiver Stage
The input stage works together with external 10 kW resistors to match the input voltage
to the internal thresholds. The data detection threshold Vref is continuously adapted
between a maximal (Vrefmax) and a minimal (Vrefmin) reference level related to the line
level. The peak detector requires maximum 2 ms to reach the peak value while storing
the peak level for at least 250 ms (RC > 1 ms).
The additional level detector for power up/down control works with a fixed threshold
VrefLD. The level detector monitors the line input signals to detect whether an INFO is
present. When closing an analog loop it is therefore possible to indicate an incoming
signal during activated loop.
Data Sheet
46
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.3.6
S/T Interface Circuitry
For both, receive and transmit direction a 1:1 transformer is used to connect the SBCXX transceiver to the 4 wire S/T interface. Typical transformer characteristics can be found
in the chapter on electrical characteristics. The connections of the line transformers is
shown in Figure 23.
3.3 V
1:1
SX1
VDD
Protection
Circuit
Transmit
Pair
SX2
10 µF
1:1
SR1
Protection
Circuit
VSS
GND
Receive
Pair
SR2
21150_05
Figure 23
Connection of Line Transformers and Power Supply to the SBCX-X
For the transmit direction an external transformer is required to provide isolation and
pulse shape according to the ITU-T recommendations.
3.3.6.1
External Protection Circuitry
The ITU-T I.430 specification for both transmitter and receiver impedances in TEs results
in a conflict with respect to external S-protection circuitry requirements:
– To avoid destruction or malfunction of the S-device it is desirable to drain off even
small overvoltages reliably.
– To meet the 96 kHz impedance test specified for transmitters and receivers (for TEs
only, ITU-T I.430 sections 8.5.1.2a and 8.6.1.1) the protection circuit must be
dimensioned such that voltages below 1.2 V (ITU-T I.430 amplitude) x transformer
ratio are not affected.
This requirement results from the fact that this test is also to be performed with no supply
voltage being connected to the TE. Therefore the second reference point for
overvoltages VDD, is tied to GND. Then, if the amplitude of the 96 kHz test signal is
greater than the combined forward voltages of the diodes, a current exceeding the
specified one may pass the protection circuit.
The following recommendations aim at achieving the highest possible device protection
against overvoltages while still fulfilling the 96 kHz impedance tests.
Data Sheet
47
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
Protection Circuit for Transmitter
SX1
1:1
R
S Bus
Vdd
SX2
R
3081_23
Figure 24
External Circuitry for Transmitter
Figure 24 illustrates the secondary protection circuit recommended for the transmitter.
The external resistors (R = 5 .... 10 W) are required in order to adjust the output voltage
to the pulse mask on the one hand and in order to meet the output impedance of
minimum 20 W (transmission of a binary zero according to ITU-T I.430) on the other
hand.
Two mutually reversed diode paths protect the device against positive or negative
overvoltages on both lines.
An ideal protection circuit should limit the voltage at the SX pins from – 0.4 V to VDD
+ 0.4 V. With the circuit in Figure 24 the pin voltage range is increased from – 1.4 V to
VDD + 0.7 V. The resulting forward voltage of 1.4 V will prevent the protection circuit from
becoming active if the 96 kHz test signal is applied while no supply voltage is present.
Protection Circuit for Receiver
Figure 25 illustrates the external circuitry used in combination with a symmetrical
receiver. Protection of symmetrical receivers is rather simple.
1:1
S Bus
Note: up to 10 pF capacitors are optional for noise reduction
Figure 25
Data Sheet
External Circuitry for Symmetrical Receivers
48
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
Between each receive line and the transformer a 10 kW resistor is used. This value is
split into two resistors: one between transformer and protection diodes for current limiting
during the 96 kHz test, and the second one between input pin and protection diodes to
limit the maximum input current of the chip.
With symmetrical receivers no difficulties regarding LCL measurements are observed;
compensation networks thus are obsolete.
In order to comply to the physical requirements of ITU-T recommendation I.430 and
considering the national requirements concerning overvoltage protection and
electromagnetic compatibility (EMC), the SBCX-X may need additional circuitry.
3.3.6.2
S-Transceiver Synchronization
Synchronization problems can occur on a S-Bus that is not terminated properly.
Therefore, it is recommended to change the resistor values in the receive path. The sum
of both resistors is increased from 10 kW (1.8 + 8.2) to e.g. 34 kW (6.8 + 27) for either
receiver line. This change is possible but not necessary for a S-Bus that is terminated
properly.
R1
R2
SR2
GND
VDD
1:1
S Bus
SR1
R1
R2
21150_33
Note: Capacitors (up to 10 pF) are optional for noise reduction.
Figure 26
External Circuitry for Symmetrical Receivers
Note: Lower or higher values than 34 kW may be used as well, however for values above
34 kW the additional delay must be compensated by setting TR_CONF2.PDS=1
(compensates 260 ns) so the allowed input phase delay is not violated.
Data Sheet
49
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.3.7
S/T Interface Delay Compensation (TE/LT-T Mode)
The S/T transmitter is shifted by two S/T bits minus 7 oscillator periods (plus analog
delay plus delay of the external circuitry) with respect to the received frame. To
compensate additional delay introduced into the receive and transmit path by the
external circuit the delay of the transmit data can be reduced by another two oscillator
periods (2 x 130 ns). Therefore PDS of the TR_CONF2 register must be programmed to
’1’. This delay compensation might be necessary in order to comply with the "total phase
deviation input to output" requirement of ITU-T recommendation I.430 which specifies a
phase deviation in the range of – 7% to + 15% of a bit period.
3.3.8
Level Detection Power Down
If MODE1.CFS is set to ’0’, the clocks are also provided in power down state, whereas
if CFS is set to ’1’ only the analog level detector is active in power down state. All clocks,
including the IOM-2 interface, are stopped (DD, DU are ’high’, DCL and BCL are ’low’).
An activation initiated from the exchange side will have the consequence that a clock
signal is provided automatically if TR_CONF0.LDD is set to ’0’. If TR_CONF0.LDD is set
to ’1’ the microcontroller has to take care of an interrupt caused by the level detect circuit
(ISTATR.LD)
From the terminal side an activation must be started by setting and resetting the SPU-bit
in the IOM_CR register and writing TIM to the CIX0 register or by resetting
MODE1.CFS=0.
3.3.9
Transceiver Enable/Disable
The layer-1 part of the SBCX-X can be enabled/disabled by configuration (see
Figure 27) with the two bits TR_CONF0.DIS_TR and TR_CONF2.DIS_TX .
By default all layer-1 functions with the exception of the transmitter buffer is enabled
(DIS_TR = ’0’, DIS_TX = ’1’). With several terminals connected to the S/T interface,
another terminal may keep the interface activated although the SBCX-X does not
establish a connection. The receiver will monitor for incoming calls in this configuration.
If the transceiver is disabled (DIS_TR = ’1’) all layer-1 functions are disabled including
the level detection circuit of the receiver. In this case the power consumption of the
Layer-1 is reduced to a minimum. The DCL and FSC pins become input.
Data Sheet
50
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
TR_CONF0.DIS_TR
TR_CONF2.DIS_TX
’1’
’0’
Figure 27
3.3.10
Disabling of S/T Transmitter
Test Functions
The SBCX-X provides test and diagnostic functions for the S/T interface:
Note: For more details please refer to the application note “Test Function of new STransceiver family”
– The internal local loop (internal Loop A) is activated by a C/I command ARL or by
setting the bit LP_A (Loop Analog) in the TR_CMD register if the layer-1 statemachine
is disabled.
The transmit data of the transmitter is looped back internally to the receiver. The data
of the IOM-2 input B- and D-channels are looped back to the output B- and Dchannels.
The S/T interface level detector is enabled, i.e. if a level is detected this will be
reported by the Resynchronization Indication (RSY) but the loop function is not
affected.
Depending on the DIS_TX bit in the TR_CONF2 register the internal local loop can be
transparent or non transparent to the S/T line.
– The external local loop (external Loop A) is activated in the same way as the internal
local loop described above. Additionally the EXLP bit in the TR_CONF0 register has
to be programmed and the loop has to be closed externally as described in Figure 28.
The S/T interface level detector is disabled.
This allows complete system diagnostics.
– In remote line loop (RLP) received data is looped back to the S/T interface. The Dchannel information received from the line card is transparently forwarded to the
output IOM-2 D-channel. The output B-channel information on IOM-2 is fixed to ‘FF’H
while this test loop is active. The remote loop is programmable in TR_CONF2.RLP.
Data Sheet
51
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
SX1
100 W
SX2
SCOUT-S(X)
SR1
100 W
SR2
Figure 28
External Loop at the S/T-Interface
– transmission of special test signals on the S/T interface according to the modified AMI
code are initiated via a C/I command written in CIX0 register (see Chapter 3.5.4)
Two kinds of test signals may be transmitted by the SBCX-X:
– The single pulses are of alternating polarity. One pulse is transmitted in each frame
resulting in a frequency of the fundamental mode of 2 kHz. The corresponding C/I
command is SSP (Send Single Pulses).
– The continuous pulses are of alternating polarity. 48 pulses are transmitted in each
frame resulting in a frequency of the fundamental mode of 96 kHz. The corresponding
C/I command is SCP (Send Continuous Pulses).
Data Sheet
52
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.4
Clock Generation
Figure 29 shows the clock system of the SBCX-X. The oscillator is used to generate a
7.68 MHz clock signal (fXTAL). In TE mode the DPLL generates the IOM-2 clocks FSC
(8 kHz), DCL (1536 kHz) and BCL (768 kHz) synchronous to the received S/T frames.
In LT modes these pins are input and in LT-T mode an 1536 kHz clock synchronous to
S is output at SCLK which can be used for DCL input.
The FSC signal is used to generate the pulse lengths of the different reset sources C/I
Code, EAW pin and Watchdog (see Chapter 3.2.4).
FSC (TE mode)
XTAL
f XTAL
7.68 MHz
OSC
DCL (TE mode)
DPLL
BCL (TE mode)
SCLK (LT-T mode)
SW Reset
C/I
EAW
Watchdog
Pin RSTO
Reset
Generation
125 µs £ t £ 250 µs
125 µs £ t £ 250 µs
125 µs £ t £ 250 µs
125 µs £ t £ 250 µs
3081_06
Figure 29
Clock System of the SBCX-X
Data Sheet
53
2003-02-04
Data Sheet
54
o
general purpose
I/O pins
AUX0-2
o:768 kHz
(BCL)
BCL/SCLK
DD
o:1536 kHz
DCL
i
o:8 kHz
FSC
DU *4)
pin: MODE0=0
TE
Clock Modes
Selected via
Table 8
CH0-2:
strap pins for IOM
channel select *2)
o
i
o:1536 kHz
(SCLK) *3)
i:1536 kHz
(from SCLK)
or 4096 kHz
(from ext. PLL)
i:8 kHz
pin:MODE1=0
MODE0=1
LT-T
i
CH0-2:
strap pins for IOM
channel select *2)
CH0-2:
strap pins for IOM
channel select *2)
o
o:256 kHz or
768 kHz or
2048 kHz
(derived from
DCL/2)
i:512 kHz or
1536 kHz or
4096 kHz
i
o
o:256 kHz or
768 kHz or
2048 kHz
(derived from
DCL/2)
i:512 kHz or
1536 kHz or
4096 kHz
i:8 kHz
bit:MODE2=0
MODE1=1
MODE0=0
pin:MODE1=1
MODE0=1
i:8 kHz
NT
LT-S
general purpose
I/O pins
i
o
o:768 kHz
(derived from
DCL/2)
i:1536 kHz
i:8 kHz
bit:MODE2=1
MODE1=1
MODE0=1 or
MODE0=0 *1)
Int. NT
SBCX-X
PEB 3081
Description of Functional Blocks
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
Note: The IOM-2 interface is adaptive. This means in LT-S/NT and LT-T mode other
frequencies for BCL and DCL are possible in the range of 512-4096 kHz
(DCL) and 256-2048 kHz (BCL). For details please refer to the application
note “Reconfigurable PBX”.
Note: i = input; o = output;
For all input clocks typical values are given although other clock frequencies may
be used, too.
1) The modes TE, LT-T and LT-S can directly be selected by strapping the pins
MODE1 and MODE0. The mode can be reprogrammed in TR_MODE.MODE2-0
where NT and intelligent NT can be selected additionally. In int. NT mode MODE0
selects between NT state machine (0) and LT-S state machine (1).
2) The number of IOM channels depends on the DCL clock, e.g. with
DCL=1536 kHz 3 IOM channels and with DCL=4096 kHz 8 channels are
available.
3) In LT-T mode the 1536 kHz output clock on SCLK is synchronous to the S
interface and can be used as input for the DCL clock.
4) The direction input/output refers to the direction of the B- and D-channel data
stream across the S-transceiver. Due to the capabilites of the IOM-2 handler the
direction of some other timeslots may be different if this is programmed by the host
(e.g. for data exchange between different devices connected to IOM-2).
Data Sheet
55
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.4.1
Description of the Receive PLL (DPLL)
The receive PLL performs phase tracking between the F/L transition of the receive signal
and the recovered clock. Phase adjustment is done by adding or subtracting 0.5 or 1
XTAL period to or from a 1.536-MHz clock cycle. The 1.536-MHz clock is than used to
generate any other clock synchronized to the line.
During (re)synchronization an internal reset condition may effect the 1.536-MHz clock to
have high or low times as short as 130 ns. After the S/T interface frame has achieved
the synchronized state (after three consecutive valid pairs of code violations) the FSC
output in TE mode is set to a specific phase relationship, thus causing once an irregular
FSC timing.
The phase relationships of the clocks are shown in Figure 30.
7.68 MHz
F-bit
1536 kHz *
* Synchronous to receive S/T. Duty Ratio 1:1 Normally
768 kHz
ITD09664
FSC
Figure 30
3.4.2
Phase Relationships of SBCX-X Clock Signals
Jitter
The timing extraction jitter of the SBCX-X conforms to ITU-T Recommendation I.430
(– 7% to + 7% of the S-interface bit period).
Data Sheet
56
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.4.3
Oscillator Clock Output C768
The SBCX-X derives its system clocks from an external clock connected to XTAL1 (while
XTAL2 is not connected) or from a 7.68 MHz crystal connected across XTAL1 and
XTAL2.
At pin C768 a buffered 7.68 MHz output clock is provided to drive further devices, which
is suitable in multiline applications for example (see Figure 31). This clock is not
synchronized to the S-interface.
In power down mode the C768 output is disabled (low signal).
7.68
MHz
XTAL1
XTAL2
C768
XTAL1
n.c.
n.c.
XTAL2
C768
XTAL1
n.c.
n.c.
XTAL2
C768
3086_12
Figure 31
Data Sheet
Buffered Oscillator Clock Output
57
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.5
Control of Layer-1
The layer-1 activation / deactivation can be controlled by an internal state machine via
the IOM-2 C/I0 channel or by software via the microcontroller interface directly. In the
default state the internal layer-1 state machine of the SBCX-X is used.
By setting the L1SW bit in the TR_CONF0 register the internal state machine can be
disabled and the layer-1 commands, which are normally generated by the internal state
machine are written directly in the TR_CMD register or indications read from the
TR_STA register respectively.The SBCX-X layer-1 control flow is shown in Figure 32.
Figure 32
Layer-1 Control
In the following sections the layer-1 control by the SBCX-X state machine will be
described. For the description of the IOM-2 C/I0 channel see also Chapter 3.7.4.
The layer-1 functions are controlled by commands issued via the CIX0 register. These
commands, sent over the IOM-2 C/I channel 0 to layer-1, trigger certain procedures,
such as activation/deactivation, switching of test loops and transmission of special pulse
patterns. These procedures are governed by layer-1 state diagrams. Responses from
layer 1 are obtained by reading the CIR0 register after a CIC interrupt (ISTA).
The state diagrams of the SBCX-X are shown in Figure 34 and Figure 35. The
activation/deactivation implemented by the SBCX-X agrees with the requirements set
forth in ITU recommendations. State identifiers F1-F8 are in accordance with ITU I.430.
Data Sheet
58
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
State machines are the key to understanding the transceiver part of the SBCX-X. They
include all information relevant to the user and enable him to understand and predict the
behaviour of the SBCX-X. The state diagram notation is given in Figure 33. The
informations contained in the state diagrams are:
–
–
–
–
–
–
state name (based on ITU I.430)
S/T signal received (INFO)
S/T signal transmitted (INFO)
C/I code received
C/I code transmitted
transition criteria
The coding of the C/I commands and indications are described in detail in Chapter 3.5.4.
SBCX-X
IPAC
IPAC
OUT
IN
IOM-2 Interface
C /Ι
Ind.
Cmd.
Unconditional
Transition
State
S / T Interface
INFO
ix
ir
ITD09657
Figure 33
State Diagram Notation
The following example illustrates the use of a state diagram with an extract of the TE
state diagram. The state explained is “F3 deactivated”.
The state may be entered:
– from the unconditional states (ARL, RES, TM)
– from state “F3 pending deactivation”, “F3 power up”, “F4 pending activation” or “F5
unsynchronized” after the C/I command “DI” has been received.
The following informations are transmitted:
– INFO 0 (no signal) is sent on the S/T-interface.
– C/I message “DC” is issued on the IOM-2 interface.
Data Sheet
59
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
The state may be left by either of the following methods:
– Leave for the state “F3 power up” in case C/I = “TIM” code is received.
– Leave for state “F4 pending activation” in case C/I = AR8 or AR10 is received.
– Leave for the state “F6 synchronized” after INFO 2 has been recognized on the S/Tinterface.
– Leave for the state “F7 activated” after INFO 4 has been recognized on the S/Tinterface.
– Leave for any unconditional state if any unconditional C/I command is received.
As can be seen from the transition criteria, combinations of multiple conditions are
possible as well. A “*” stands for a logical AND combination. And a “+” indicates a logical
OR combination.
The sections following the state diagram contain detailed information on all states and
signals used.
3.5.1
State Machine TE and LT-T Mode
3.5.1.1
State Transition Diagram (TE, LT-T)
Figure 34 shows the state transition diagram of the SBCX-X state machine. Figure 35
shows this for the unconditional transitions (Reset, Loop, Test Mode i).
Data Sheet
60
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
DC
i4
DI
F3
Deactivated
i0
TIM
i0
AR i2
DI
PU AR2)
AR
F4
Pending Act.
TIM
i0
i1
DI
RSY
i0
i2
i4
X
TIM
F5
Unsynchronized DI
i0
TIM
F3
Power Up
i0
i0
i4
PU
X
DI
Uncond. State
TIM
ix
i2
AR
X
X4)
F6
Synchronized
i0*TO1
i2
i3
ix
i4
RSY
i2
i4
X
F8
Lost Framing
i2
i0
i0
DI
TIM
i0*TO1
i2
DI*TO2
ix
AI3) AR2)
F7
Activated
i3
TO1:
TO2:
i4
i0*TO1
i4
DR1)
X
F3
Pending Deact.
i0
TIM*TO2
i0
16 ms
0.5 ms
1)
DR for transition from F7 or F8
DR6 for transition from F6
AR stands for AR8 or AR10
3)
AI stands for AI8 or AI10
4)
X stands for commands initiating unconditional
transitions (RES, ARL, SSP or SCP)
2)
Figure 34
Data Sheet
statem_te_s.vsd
State Transition Diagram (TE, LT-T)
61
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
SSP
SCP
ARL
TIM
SSP
TMA SCP
TIM
ARL ARL
DI
Test Mode i
DI
iti
RST
*
Loop A Closed
i3
TIM
DI
RES RES
Reset
i0
*
*
i3
i3
RES
TIM
DI
AIL ARL
RSY
Any
State
Loop A Activated
i3
*
statem_te_aloop_s.vsd
Figure 35
3.5.1.2
State Transition Diagram of Unconditional Transitions (TE, LT-T)
States (TE, LT-T)
F3 Pending Deactivation
State after deactivation from the S/T interface by INFO 0. Note that no activation from
the terminal side is possible starting from this state. A ’DI’ command has to be issued to
enter the state ’Deactivated State’.
F3 Deactivated State
The S/T interface is deactivated and the clocks are deactivated 500 µs after entering this
state and receiving INFO 0 if the CFS bit of the SBCX-X Configuration Register is set to
“0“. Activation is possible from the S/T interface and from the IOM-2 interface. The bit
TR_CMD.PD is set and the analog part is powered down.
F3 Power Up
The S/T interface is deactivated (INFO 0 on the line) and the clocks are running.
F4 Pending Activation
The SBCX-X transmits INFO 1 towards the network, waiting for INFO 2.
Data Sheet
62
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
F5 Unsynchronized
Any signal except INFO 2 or 4 detected on the S/T interface.
F6 Synchronized
The receiver has synchronized and detects INFO 2. INFO 3 is transmitted to
synchronize the NT.
F7 Activated
The receiver has synchronized and detects INFO 4. All user channels are now conveyed
transparently to the IOM-2 interface.
To transfer user channels transparently to the S/T interface either the command AR8 or
AR10 has to be issued and TR_STA.FSYN must be “1” (signal from remote side must
be synchronous).
F8 Lost Framing
The receiver has lost synchronization in the states F6 or F7 respectively.
Unconditional States
Loop A Closed (internal or external)
The SBCX-X loops back the transmitter to the receiver and activates by transmission of
INFO 3. The receiver has not yet synchronized.
For a non transparent internal loop the DIS_TX bit of register TR_CONF2 has to be set
to ’1’.
Loop A Activated (internal or external)
The receiver has synchronized to INFO 3. Data may be sent. The indication “AIL” is
output to indicate the activated state. If the loop is closed internally and the S/T line
awake detector detects any signal on the S/T interface, this is indicated by “RSY”.
Test Mode - SSP
Single alternating pulses are transmitted to the S/T-interface resulting in a frequency of
the fundamental mode of 2 kHz.
Test Mode - SCP
Continuous alternating pulses are transmitted to the S/T-interface resulting in a
frequency of the fundamental mode of 96 kHz.
Data Sheet
63
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.5.1.3
C/I Codes (TE, LT-T)
Command
Abbr. Code Remark
Activation Request with
priority class 8
AR8
Activation Request with
priority class 10
AR10 1001 Activation requested by the SBCX-X,
D-channel priority set to 10 (see note)
Activation Request Loop
ARL
1010 Activation requested for the internal or
external Loop A (see note).
For a non transparent internal loop bit
DIS_TX of register TR_CONF2 has to be set
to ’1’ additionally.
Deactivation Indication
DI
1111 Deactivation Indication
Reset
RES
0001 Reset of the layer-1 statemachine
Timing
TIM
0000 Layer-2 device requires clocks to be
activated
Test mode SSP
SSP
0010 One AMI-coded pulse transmitted in each
frame, resulting in a frequency of the
fundamental mode of 2 kHz
Test mode SCP
SCP
0011 AMI-coded pulses transmitted continuously,
resulting in a frequency of the fundamental
mode of 96 kHz
1000 Activation requested by the SBCX-X,
D-channel priority set to 8 (see note)
Note: In the activated states (AI8, AI10 or AIL indication) the 2B+D channels are only
transferred transparently to the S/T interface if one of the three “Activation
Request” commands is permanently issued.
Data Sheet
64
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
Indication
Abbr. Code Remark
Deactivation Request
DR
0000
Deactivation request via S/T-interface if left
from F7/F8
Reset
RES
0001
Reset acknowledge
Test Mode
Acknowledge
TMA
0010
Acknowledge for both SSP and SCP
Slip Detected
SLD
0011
Resynchronization
during level detect
RSY
0100
Signal received, receiver not synchronous
Deactivation Request
from F6
DR6
0101
Deactivation Request from state F6
Power up
PU
0111
IOM-2 interface clocking is provided
Activation request
AR
1000
INFO 2 received
Activation request loop
ARL
1010
Internal or external loop A closed
Illegal Code Violation
CVR
1011
Illegal code violation received. This function
has to be enabled by setting the EN_ICV bit of
register TR_CONF0.
Activation indication
loop
AIL
1110
Internal or external loop A activated
Activation indication
with priority class 8
AI8
1100
INFO 4 received,
D-channel priority is 8 or 9.
Activation indication
with priority class 10
AI10
1101
INFO 4 received,
D-channel priority is 10 or 11.
Deactivation
confirmation
DC
1111
Clocks are disabled if CFS bit of register
MODE1 is set to ’1’, quiescent state
Data Sheet
65
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.5.1.4
Infos on S/T (TE, LT-T)
Receive Infos on S/T (Downstream)
Name
Abbr. Description
INFO 0
i0
No signal on S/T
INFO 2
i2
4 kHz frame
A=’0’
INFO 4
i4
4 kHz frame
A=’1’
INFO X
ix
Any signal except INFO 2 or INFO 4
Transmit Infos on S/T (Upstream)
Name
Abbr. Description
INFO 0
i0
No signal on S/T
INFO 1
i1
Continuous bit sequence of the form ’00111111’
INFO 3
i3
4 kHz frame
Test INFO 1
it1
SSP - Send Single Pulses
Test INFO 2
it2
SCP - Send Continuous Pulses
Data Sheet
66
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.5.2
State Machine LT-S Mode
3.5.2.1
State Transition Diagram (LT-S)
RST
TIM RES
TIM
DR
Reset
i0
RES
DR
G4 Pend. Deact.
1)
ARD
*
DR
i0
DC
DI
ARD1)
Test Mode i
i0
it
(i0*16ms)+32ms
Any
State
SSP
TIM SCP
DC
*
SSP
SCP
Any
State
DR
G4 Wait for DR
i0
*
DC
DI DC
TIM 2)
DR
G1 Deactivated
i0
i0
(i0*8ms)+ARD1)
DC
AR ARD
G2 Pend. Act.
i2
DR
i3
i3
DC
RSY ARD
G2 Lost
Framing S/T
i2
i3
i3
AI
i3
DC
ARD
G3 Activated
i4
DR
i3
DR
1)
ARD = AR or ARL
2)
DI if i0
TIM if i0
s tatem_lts _s .v s d
Figure 36
State Transition Diagram (LT-S)
Note: State ’Test Mode’ can be entered from any state except from state ’Test Mode’
itself , i.e. C/I-code ’SSP/SCP’ must not be followed by C/I-code ’SCP/SSP’
directly.
Data Sheet
67
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.5.2.2
States (LT-S)
G1 Deactivated
The transceiver is not transmitting. There is no signal detected on the S/T interface, and
no activation command is received in the C/I channel. The clocks are deactivated if
MODE1.CFS is set to 1. Activation is possible from the S/T interface and from the IOM2 interface.
G2 Pending Activation
As a result of an INFO 0 detected on the S/T line or an ARD command, the transceiver
begins transmitting INFO 2 and waits for reception of INFO 3. The timer to supervise
reception of INFO 3 is to be implemented in software. In case of an ARL command, loop
2 is closed.
G3 Activated
Normal state where INFO 4 is transmitted to the S/T-interface. The transceiver remains
in this state as long as neither a deactivation nor a test mode is requested, nor the
receiver looses synchronism.
When receiver synchronism is lost, INFO 2 is sent automatically. After reception of
INFO 3, the transmitter keeps on sending INFO 4.
G2 Lost Framing
This state is reached when the transceiver has lost synchronism in the state G3
activated.
G4 Pending Deactivation
This state is triggered by a deactivation request DR. It is an unstable state: indication DI
(state “G4 Wait for DR.”) is issued by the transceiver when:
either INFO 0 is received for a duration of 16 ms,
or an internal timer of 32 ms expires.
G4 Wait for DR
Final state after a deactivation request. The transceiver remains in this state until DC is
issued.
Unconditional States
Test mode - SSP
Single alternating pulses are sent on the S/T-interface.
Data Sheet
68
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
Test mode - SCP
Continuous alternating pulses are sent on the S/T-interface.
3.5.2.3
C/I Codes (LT-S)
Command
Abbr.
Code
Remark
Deactivation
Request
DR
0000
DR - Deactivation Request. Initiates a complete
deactivation from the exchange side by
transmitting INFO 0.
Reset
RES
0001
Reset of state machine. Transmission of
INFO 0. No reaction to incoming infos. RES is
an unconditional command.
Send Single Pulses
SSP
0010
Send Single Pulses.
Send Continuous
Pulses
SCP
0011
Send Continuous Pulses.
Activation Request
AR
1000
Activation Request. This command is used to
start an exchange initiated activation.
Activation Request
Loop
ARL
1010
Activation request loop. The transceiver is
requested to operate an analog loop-back close
to the S/T-interface.
Deactivation
Confirmation
DC
1111
Deactivation Confirmation. Transfers the
transceiver into a deactivated state in which it
can be activated from a terminal (detection of
INFO 0 enabled).
Indication
Abbr.
Code
Remark
Timing
TIM
0000
Interim indication during activation procedure in
G1.
Receiver not
Synchronous
RSY
0100
Receiver is not synchronous
Activation Request
AR
1000
INFO 0 received from terminal. Activation
proceeds.
Illegal Code
Violation
CVR
1011
Illegal code violation received. This function
has to be enabled in TR_CONF0.EN_ICV.
Data Sheet
69
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SBCX-X
PEB 3081
Description of Functional Blocks
Indication
Code
Remark
Activation Indication AI
1100
Synchronous receiver, i.e. activation
completed.
Deactivation
Indication
1111
Timer (32 ms) expired or INFO 0 received for a
duration of 16 ms after deactivation request
3.5.2.4
Abbr.
DI
Infos on S/T (LT-S)
Receive Infos on S/T (Downstream)
I0
INFO 0 detected
I0
Level detected (signal different to I0)
I3
INFO 3 detected
I3
Any INFO other than INFO 3
Transmit Infos on S/T (Upstream)
I0
INFO 0
I2
INFO 2
I4
INFO 4
It
Send Single Pulses (SSP).
Send Continuous Pulses (SCP).
Data Sheet
70
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SBCX-X
PEB 3081
Description of Functional Blocks
3.5.3
State Machine NT Mode
3.5.3.1
State Transition Diagram (NT)
RST
TIM RES
TIM
DR
Reset
i0
ARD
i0
DI
Any
State
ARD1)
SSP
TIM SCP
Test Mode i
i0
it
(i0*16ms)+32ms
DC
RES
DR
G4 Pend. Deact.
1)
*
DR
DC
DR
*
SSP
SCP
Any
State
G4 Wait for DR
i0
*
DC
DR
DI DC
TIM 3)
G1 Deactivated
ARD1)
i0
i0
(i0*8ms)
AR
DC
G1 i0 Detected
i0
DR
*
ARD1)
AR ARD
G2 Pend. Act
i2
DR
i3
i3
AID
RSY ARD
G2 Lost
Framing S/T
i2
i3
i3*ARD
AI
i3*ARD1)
i3*AID2)
ARD
G2 Wait for AID
RSY
i2
DR
i3
1)
AID2)
RSY
DR
RSY RSY
G3 Lost
Framing U
i2
*
ARD1)
AID2)
i3*AID2)
ARD1)
AI
AID
G3 Activated
RSY
ARD = AR or ARL
AID =AI or AIL
3)
DI if i0
TIM if i0
2)
i4
DR
i3
s tatem_n t_ s .v s d
Figure 37
Data Sheet
State Transition Diagram (NT)
71
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SBCX-X
PEB 3081
Description of Functional Blocks
Note: State ’Test Mode’ can be entered from any state except from state ’Test Mode’
itself , i.e. C/I-code ’SSP/SCP’ must not be followed by C/I-code ’SCP/SSP’
directly.
3.5.3.2
States (NT)
G1 Deactivated
The transceiver is not transmitting. There is no signal detected on the S/T-interface, and
no activation command is received in the C/I channel. The clocks are deactivated if the
bit MODE1.CFS is set to 1. Activation is possible from the S/T interface and from the
IOM-2 interface.
G1 I0 Detected
An INFO 0 is detected on the S/T-interface, translated to an “Activation Request”
indication in the C/I channel. The transceiver is waiting for an AR command, which
normally indicates that the transmission line upstream (usually a two-wire U interface) is
synchronized.
G2 Pending Activation
As a result of the ARD command, an INFO 2 is sent on the S/T-interface. INFO 3 is not
yet received. In case of ARL command, loop 2 is closed.
G2 wait for AID
INFO 3 was received, INFO 2 continues to be transmitted while the transceiver waits for
a “switch-through” command AID from the device upstream.
G3 Activated
INFO 4 is sent on the S/T-interface as a result of the “switch through” command AID: the
B and D-channels are transparent. On the command AIL, loop 2 is closed.
G2 Lost Framing S/T
This state is reached when the transceiver has lost synchronism in the state G3
activated.
G3 Lost Framing U
On receiving an RSY command which usually indicates that synchronization has been
lost on the two-wire U interface, the transceiver transmits INFO 2.
Data Sheet
72
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
G4 Pending Deactivation
This state is triggered by a deactivation request DR, and is an unstable state. Indication
DI (state “G4 wait for DR”) is issued by the transceiver when:
either INFO 0 is received for a duration of 16 ms
or an internal timer of 32 ms expires.
G4 wait for DR
Final state after a deactivation request. The transceiver remains in this state until DC is
issued.
Unconditional States
Test Mode SSP
Send Single Pulses
Test Mode SCP
Send Continuous Pulses
3.5.3.3
C/I Codes (NT)
Command
Abbr.
Code
Remark
Deactivation
Request
DR
0000
DR - Deactivation Request. Initiates a complete
deactivation from the exchange side by
transmitting INFO 0. Unconditional command.
Reset
RES
0001
Reset of state machine. Transmission of
INFO 0. No reaction to incoming infos. RES is
an unconditional command.
Send Single Pulses
SSP
0010
Send Single Pulses.
Send Continuous
Pulses
SCP
0011
Send Continuous Pulses.
Receiver not
Synchronous
RSY
0100
Receiver is not synchronous
Activation Request
AR
1000
Activation Request. This command is used to
start an exchange initiated activation.
Activation Request
Loop
ARL
1010
Activation request loop. The transceiver is
requested to operate an analog loop-back close
to the S/T-interface.
Data Sheet
73
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
Command
Code
Remark
Activation Indication AI
1100
Synchronous receiver, i.e. activation
completed.
Activation Indication AIL
Loop
1110
Activation Indication Loop
Deactivation
Confirmation
DC
1111
Deactivation Confirmation. Transfers the
transceiver into a deactivated state in which it
can be activated from a terminal (detection of
INFO 0 enabled).
Indication
Abbr.
Code
Remark
Timing
TIM
0000
Receiver not
Synchronous
RSY
0100
Receiver is not synchronous
Activation Request
AR
1000
INFO 0 received from terminal. Activation
proceeds.
Illegal Code
Violation
CVR
1011
Illegal code violation received. This function
has to be enabled in TR_CONF0.EN_ICV.
Activation Indication AI
1100
Synchronous receiver, i.e. activation
completed.
Deactivation
Indication
1111
Timer (32 ms) expired or INFO 0 received for a
duration of 16 ms after deactivation request
Data Sheet
Abbr.
DI
Interim indication during deactivation procedure
74
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SBCX-X
PEB 3081
Description of Functional Blocks
3.5.4
Command / Indicate Channel Codes (C/I0) - Overview
The table below presents all defined C/I0 codes. A command needs to be applied
continuously until the desired action has been initiated. Indications are strictly state
orientated. Refer to the state diagrams in the previous sections for commands and
indications applicable in various states.
Code
TE/LT-T
LT-S
NT
Cmd
Ind
Cmd
Ind
Cmd
Ind
0
0
0
0
TIM
DR
DR
TIM
DR
TIM
0
0
0
1
RES
RES
RES
–
RES
–
0
0
1
0
SSP
TMA
SSP
–
SSP
–
0
0
1
1
SCP
SLD
SCP
–
SCP
–
0
1
0
0
–
RSY
–
RSY
RSY
RSY
0
1
0
1
–
DR6
–
–
–
–
0
1
1
0
–
–
–
–
–
–
0
1
1
1
–
PU
–
–
–
–
1
0
0
0
AR8
AR
AR
AR
AR
AR
1
0
0
1
AR10
–
–
–
–
–
1
0
1
0
ARL
ARL
ARL
–
ARL
–
1
0
1
1
–
CVR
–
CVR
–
CVR
1
1
0
0
–
AI8
–
AI
AI
AI
1
1
0
1
–
AI10
–
–
–
–
1
1
1
0
–
AIL
–
–
AIL
–
1
1
1
1
DI
DC
DC
DI
DC
DI
Data Sheet
75
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.6
Control Procedures
3.6.1
Example of Activation/Deactivation
An example of an activation/deactivation of the S/T interface initiated by the terminal with
the time relationships mentioned in the previous chapters is shown in Figure 38.
NT/Linecard
TE
INFO 0
INFO 1
RSY
max. 6 ms
AR
INFO 2
INFO 3
AR
0.5 ms
INFO 4
AI
DR
16 ms
INFO 0
INFO 0
A_DEACT.DRW
Figure 38
Data Sheet
Example of Activation/Deactivation Initiated by the Terminal
76
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SBCX-X
PEB 3081
Description of Functional Blocks
3.6.2
Activation initiated by the Terminal
INFO 1 has to be transmitted as long as INFO 0 is received.
INFO 0 has to be transmitted thereafter as long as no valid INFO (INFO 2 or INFO 4) is
received.
After reception of INFO 2 or INFO 4 transmission of INFO 3 has to be started.
Data can be transmitted if INFO 4 has been received.
µC Interface
TE
S/T Interface
NT
INFO 0
TDDIS='1', XINF='010'
INFO 1
INFO 2
RINF='01'
XINF='000'
T1TE
INFO 0
RINF='10'
INFO 3
XINF='011'
INFO 4
RINF='11'
T2TE
TDDIS='0'
INFO 0
RINF='00'
TDDIS='1', XINF='000'
T3TE
INFO 0
INFO 0
T1TE: 2 to 6 frames (0.5 ms to 1.5 ms)
T2TE:
2 frames (0.5 ms)
4 frames (1 ms)
T3TE:
act_deac_te-ext_s.vsd
Figure 39
Example of Activation/Deactivation initiated by the Terminal (TE).
Activation/Deactivation completely under Software Control
Note: RINF and XINF are Receive- and Transmit-INFOs of the registers TR_STA
TR_CMD.
Data Sheet
77
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.6.3
Activation initiated by the Network Termination NT
INFO 0 has to be transmitted as long as no valid INFO (INFO 2 or INFO 4) is received.
After reception of INFO 2 or INFO 4 transmission of INFO 3 has to be started.
Data can be transmitted if INFO 4 has been received.
µC Interface
TE
S/T Interface
NT
INFO 0
RINF='01'
INFO 2
T1TE
RINF='10'
TDDIS='1', XINF='011'
INFO 3
INFO 4
RINF='11'
T2TE
TDDIS='0'
INFO 0
RINF='00'
T3TE
TDDIS='1', XINF='000'
INFO 0
INFO 0
T1TE: 2 to 6 S/T frames (0.5 ms to 1.5 ms)
2 S/T frames (0.5 ms)
T2TE:
4 S/T frames (1 ms)
T3TE:
act_deac_lt_ext_s.vsd
Figure 40
Example of Activation/Deactivation initiated by the Network
Termination (NT).
Activation/Deactivation completely under Software Control
Note: RINF and XINF are Receive- and Transmit-INFOs of the registers TR_STA
TR_CMD.
Data Sheet
78
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.7
IOM-2 Interface
The SBCX-X supports the IOM-2 interface in linecard mode and in terminal mode with
single clock and double clock. The IOM-2 interface consists of four lines: FSC, DCL, DD
and DU. The rising edge of FSC indicates the start of an IOM-2 frame. The DCL and the
BCL clock signals synchronize the data transfer on both data lines DU and DD. The DCL
is twice the bit rate, the BCL rate is equal to the bit rate. The bits are shifted out with the
rising edge of the first DCL clock cycle and sampled at the falling edge of the second
clock cycle.
The IOM-2 interface can be enabled/disabled with the DIS_IOM bit in the IOM_CR
register.
TE Mode
A DCL signal and BCL signal (pin BCL/SCLK) output is provided and the FSC signal is
generated by the receive DPLL which synchronizes it to the received S/T frame.
The BCL clock together with the two serial data strobe signals (SDS1, SDS2) can be
used to connect time slot oriented standard devices to the IOM-2 interface. If the
transceiver is disabled (TR_CON.DIS_TR) the DCL and FSC pins become input. In this
case the clock mode bit (IOM_CR.CLKM) selects between a double clock and a single
clock input for DCL.
The clock rate/frequency of the IOM-2 signals in TE mode are:
DD, DU:
768 kbit/s
FSC (o):
8 kHz
DCL (o):
1536 kHz (double clock rate)
BCL (o):
768 kHz (single clock rate)
Option - Transceiver disabled (DIS_TR = ’1’):
FSC (i):
8 kHz
DCL (i):
1536 ... 4096 kHz, in steps of 512 kHz (double clock rate)
LT-S, LT-T, NT, iNT Mode
The IOM-2 clock signals FSC and BCL are input.
In LT-T mode a 1536 kHz output clock synchronous to S is provided at pin SCLK which
can directly be connected to the DCL input.
DD, DU:
FSC (i):
DCL (i):
SCLK (o):
data rate = DCL/2 kbit/s (LT-T mode)
8 kHz
512 ... 4096 kHz, in steps of 512 kHz (double clock rate)
1536 kHz (LT-T mode), BCL derived via DCL/2 (LT-S/NT mode)
Note: In all modes the direction of the data lines DU and DD is not fix but depending on
the timeslot which can be seen in the figures below.
Data Sheet
79
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
IOM-2 Frame Structure (TE Mode)
The frame structure on the IOM-2 data ports (DU, DD) of a master device in IOM-2
terminal mode is shown in Figure 41.
Figure 41
IOMÒ-2 Frame Structure in Terminal Mode
The frame is composed of three channels
• Channel 0 contains 144-kbit/s of user and signaling data (2B + D), a MONITOR
programming channel (MON0) and a command/indication channel (CI0) for control
and programming of the layer-1 transceiver.
• Channel 1 contains two 64-kbit/s intercommunication channels (IC) plus a MONITOR
and command/indicate channel (MON1, CI1) to program or transfer data to other
IOM-2 devices.
• Channel 2 is used for the TlC-bus access. Only the command/indicate bits are
specified in this channel.
Data Sheet
80
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
IOM-2 Frame Structure (LT-S, LT-T Modes)
This mode is used in LT-S and LT-T applications. The frame is a multiplex of up to eight
IOM-2 channels (DCL = 4096 kHz, see Figure 42), each of which has the structure
described above.
The reset value for assignment to one of the eight channels (0 to 7) is done via pin
strapping (CH0-2), however the host can reprogram the selected timeslot in
DCH_TSDP.TSS.
125 µ s
FSC
DCL
DD
IOM R CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH0
DU
IOM CH0
R
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH0
B1
Figure 42
B2
MONITOR
D
C/I
MM
RX
ITD09635
Multiplexed Frame Structure of the IOM-2 Interface
in Non-TE Timing Mode
IOM-2 Frame Structure (NT Mode)
In NT mode one IOM-2 channel is used (DCL=512 kHz). The channel structure is the
same as described above.
Data Sheet
81
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.7.1
IOM-2 Handler
The IOM-2 handler offers a great flexibility for handling the data transfer between the
different functional units of the SBCX-X and voice/data devices connected to the IOM-2
interface. Additionally it provides a microcontroller access to all timeslots of the IOM-2
interface via the four controller data access registers (CDA). Figure 43 shows the
architecture of the IOM-2 handler. For illustrating the functional description it contains all
configuration and control registers of the IOM-2 handler. A detailed register description
can be found in Chapter 4.3.
The PCM data of the functional units
• Transceiver (TR) and the
• Controller data access (CDA)
can be configured by programming the time slot and data port selection registers
(TSDP). With the TSS bits (Time Slot Selection) the PCM data of the functional units can
be assigned to each of the 32 PCM time slots of the IOM-2 frame. With the DPS bit (Data
Port Selection) the output of each functional unit is assigned to DU or DD respectively.
The input is assigned vice versa. With the data control registers (xxx_CR) the access to
the data of the functional units can be controlled by setting the corresponding control bits
(EN, SWAP).
The IOM-2 handler also provides access to the
• MONITOR channel (MON)
• C/I channels (C/I0, C/I1) and
• TIC bus (TIC)
The access to these channels is controlled by the register MON_CR and DCI_CR.
The IOM-2 interface with the two Serial Data Strobes (SDS1,2) is controlled by the
control registers IOM_CR, SDS1_CR and SDS2_CR.
The reset configuration of the SBCX-X IOM-2 handler corresponds to the defined frame
structure and data ports of a master device in IOM-2 terminal mode (see Figure 41).
Data Sheet
82
2003-02-04
83
CDA_TSDPxy
CDAx_CRx
MCDA
STI
MSTI
ASTI
( DPS, TSS,
EN_TBM, SWAP,
EN_I1/0, EN_O1/0,
MCDAxy, STIxy,
STOVxy, ACKxy )
CDA Control
CDA Data
BCL / SCLK
FSC
DD
DU
MON Handler
IOM-2 Interface
Microcontroller Interface
C/I0
Data
TIC
C/I1
DCI_CR
(DPS_CI1,
EN_CI1)
(CS2-0)
DCIC_CR
C/I1
C/I Data Control
C/I0
IOM_CR
(TIC_DIS)
(DPS, CS2-0,
EN_MON)
MON_CR
TIC Bus
Disable
Monitor Data
EN_BCL, CLKM, DIS_OD, DIS_IOM,
DIOM_INV, DIOM_SDS
DCL
TIC Bus Data
Control
Monitor Data
Note: The registers shown above are used to control
the corresponding functional block (e.g. programming
of timeslot, data port, enabling/disabling, etc.)
CDA10
CDA11
CDA20
CDA21
CDA Registers
Controller Data Access (CDA)
IOM_CR
SDS1_CR
SDS2_CR
C/I0 Data
Data Sheet
C/I1 Data
Figure 43
SDS2
SDS1
( ENS_TSS, ENS_TSS+1,
ENS_TSS+3, TSS, SDS_BCL
TR_TSDP_BC1
TR_TSDP_BC2
TRC_CR
(DPS, TSS,
CS2-0, EN_D,
EN_B1R,
EN_B1X,
EN_B2R,
EN_B2X )
Control
Transceiver
Data Access
D, B1, B2, C/I0 Data
IOM-2 Handler
3186_07
D-channel RX/TX
B1-channel RX
B1-channel TX
B2-channel RX
B2-channel TX
Transceiver
Data TR
SBCX-X
PEB 3081
Description of Functional Blocks
.
Architecture of the IOM Handler (Example Configuration)
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.7.1.1
Controller Data Access (CDA)
With its four controller data access registers (CDA10, CDA11, CDA20, CDA21) the
SBCX-X IOM-2 handler provides a very flexible solution for the host access to up to 32
IOM-2 time slots.
The functional unit CDA (controller data access) allows with its control and configuration
registers
• looping of up to four independent PCM channels from DU to DD or vice versa over the
four CDA registers
• shifting of two independent PCM channels to another two independent PCM channels
on both data ports (DU, DD). Between reading and writing the data can be
manipulated (processed with an algorithm) by the microcontroller. If this is not the
case a switching function is performed
• monitoring of up to four time slots on the IOM-2 interface simultaneously
• microcontroller read and write access to each PCM timeslot
The access principle which is identical for the two channel register pairs CDA10/11 and
CDA20/21 is illustrated in Figure 44. Each of the index variables x,y used in the following
description can be 1 or 2 for x and 0 or 1 for y. The prefix ’CDA_’ from the register names
has been omitted for simplification.
To each of the four CDAxy data registers a TSDPxy register is assigned by which the
time slot and the data port can be determined. With the TSS (Time Slot Selection) bits a
time slot from 0...31 can be selected. With the DPS (Data Port Selection) bit the output
of the CDAxy register can be assigned to DU or DD respectively. The time slot and data
port for the output of CDAxy is always defined by its own TSDPxy register. The input of
CDAxy depends on the SWAP bit in the control registers CRx.
• If the SWAP bit = ’0’ (swap is disabled) the time slot and data port for the input and
output of the CDAxy register is defined by its own TSDPxy register.
• If the SWAP bit = ’1’ (swap is enabled) the input port and timeslot of the CDAx0 is
defined by the TSDP register of CDAx1 and the input port and timeslot of CDAx1 is
defined by the TSDP register of CDAx0. The input definition for timeslot and data port
CDAx0 are thus swapped to CDAx1 and for CDAx1 swapped to CDAx0. The output
timeslots are not affected by SWAP.
The input and output of every CDAxy register can be enabled or disabled by setting the
corresponding EN (-able) bit in the control register CDAx_CR. If the input of a register is
disabled the output value in the register is retained.
Usually one input and one output of a functional unit (transceiver, HDLC controller, CDA
register) is programmed to a timeslot on IOM-2 (e.g. for B-channel transmission in
upstream direction the HDLC controller writes data onto IOM and the transceiver reads
data from IOM). For monitoring data in such cases a CDA register is programmed as
described below under “Monitoring Data”. Besides that none of the IOM timeslots must
be assigned more than one input and output of any functional unit.
Data Sheet
84
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
.
TSa
TSb
DU
Control
Register
1
CDAx0
0
1
1
1
1
1
CDAx1
1
1
0
CDA_TSDPx1
Enable
input *
output
(EN_I1)
(EN_O1)
Input
Swap
(SWAP)
input *
(EN_I0)
1
Time Slot
Selection (TSS)
0
Data Port
Selection (DPS)
Time Slot
Selection (TSS)
CDA_CRx
0
Enable
output
(EN_O0)
Data Port
Selection (DPS)
CDA_TSDPx0
1
DD
TSa
TSb
IOM_HAND.FM4
x = 1 or 2; a,b = 0...31
*) In the normal mode (SWAP=0) the input of CDAx0 and CDAx1 is enabled via EN_I0 and
EN_I1, respectively. If SWAP=1 EN_I0 controls the input of CDAx1 and EN_I1 controls the
input of CDAx0. The output control (EN_O0 and EN_O1) is not affected by SWAP.
Figure 44
Data Access via CDAx1 and CDAx2 Register Pairs
Looping and Shifting Data
Figure 45 gives examples for typical configurations with the above explained control and
configuration possibilities with the bits TSS, DPS, EN and SWAP in the registers
TSDPxy or CDAx_CR:
a) looping IOM-2 time slot data from DU to DD or vice versa (SWAP = 0)
b) shifting data from TSa to TSb and TSc to TSd in both transmission directions (SWAP
= 1)
c) switching data from TSa to TSb and looping from DU to DD or TSc to TSd and looping
from DD to DU respectively
TSa is programmed in TSDP10, TSb in TSDP11, TSc in TSDP20 and TSd in TSDP21.
It should also be noted that the input control of CDA registers is swapped if SWAP=1
while the output control is not affected (e.g. for CDA11 in example a: EN_I1=1 and
EN_O1=1, whereas for CDA11 in example b: EN_I0=1 and EN_O1=1).
Data Sheet
85
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
a) Looping Data
TSa
TSb
TSc
TSd
CDA10
CDA11
CDA20
CDA21
TSc
’1’
TSd
’1’
DU
DD
.TSS: TSa
TSb
.DPS ’0’
’0’
.SWAP
’0’
’0’
b) Shifting Data
TSa
TSb
TSc
TSd
CDA10
CDA11
CDA20
CDA21
DU
DD
.TSS: TSa
TSb
.DPS ’0’
’1’
.SWAP
’1’
c) Switching Data
TSa
TSb
CDA10
CDA11
TSc
’0’
TSd
’1’
’1’
TSc
TSd
CDA20
CDA21
DU
DD
.TSS: TSa
TSb
.DPS ’0’
’0’
.SWAP
’1’
Figure 45
TSc
’1’
TSd
’1’
’1’
Examples for Data Access via CDAxy Registers
a) Looping Data
b) Shifting (Switching) Data
c) Switching and Looping Data
Data Sheet
86
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
Figure 46 shows the timing of looping TSa from DU to DD (a = 0...31) via CDAxy
register. TSa is read in the CDAxy register from DU and is written one frame later on DD.
.
a = 0...31
FSC
DU
TSa
TSa
µC *)
DD
TSa
STOV
ACK
WR
RD
STI
CDAxy
TSa
*) if access by the µC is required
Figure 46
Data Access when Looping TSa from DU to DD
Figure 47 shows the timing of shifting data from TSa to TSb on DU (DD). In Figure 47a)
shifting is done in one frame because TSa and TSb didn’t succeed direct one another (a,
b = 0...29 and b ³ a+2. In Figure 47b) shifting is done from one frame to the following
frame. This is the case when the time slots succeed one other (b = a+1) or b is smaller
than a (b < a).
At looping and shifting the data can be accessed by the controller between the
synchronous transfer interrupt (STI) and the status overflow interrupt (STOV). STI and
STOV are explained in the section ’Synchronous Transfer’. If there is no controller
intervention the looping and shifting is done autonomous.
Data Sheet
87
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
a) Shifting TSa ® TSb within one frame
(a,b: 0...31 and b ³ a+2)
FSC
DU
(DD)
TSa
TSa
TSb
µC *)
STI
STOV
ACK
WR
RD
STI
CDAxy
b) Shifting TSa ® TSb in the next frame
(a,b: 0...31 and (b = a+1 or b <a)
FSC
DU
(DD)
TSa TSb
TSa TSb
µC *)
STOV
WR
RD
STI
CDAxy
ACK
*) if access by the µC is required
Figure 47
Data Sheet
Data Access when Shifting TSa to TSb on DU (DD)
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PEB 3081
Description of Functional Blocks
Monitoring Data
Figure 48 gives an example for monitoring of two IOM-2 time slots each on DU or DD
simultaneously. For monitoring on DU and/or DD the channel registers with even
numbers (CDA10, CDA20) are assigned to time slots with even numbers TS(2n) and the
channel registers with odd numbers (CDA11, CDA21) are assigned to time slots with odd
numbers TS(2n+1). The user has to take care of this restriction by programming the
appropriate time slots.
However, this rule is only valid if two blocks (e.g. transceiver and HDLC controller) are
programmed to these timeslots and are communicating via IOM-2. If only one block is
programmed to this timeslot, the timeslots for CDAx0 and CDAx1 can programmed
completely independently.
.
EN_O: ’0’
CDA_CR1. EN_I: ’1’
DPS: ’0’
TSS: TS(2n)
’0’
’1’
’0’
TS(2n+1)
DU
CDA10
CDA11
CDA20
CDA21
TSS: TS(2n)
CDA_CR2. DPS: ’1’
EN_I: ’1’
EN_O: ’0’
Figure 48
TS(2n+1)
’1’
’1’
’0’
DD
Example for Monitoring Data
Monitoring TIC Bus (TE mode)
Monitoring the TIC bus (TS11) is handled as a special case. The TIC bus can be
monitored with the registers CDAx0 by setting the EN_TBM (Enable TIC Bus Monitoring)
bit in the control registers CRx. In this special case the TSDPx0 must be set to 08h for
monitoring from DU or 88h for monitoring from DD respectively. By this it is possible to
monitor the TIC bus (TS11) and the odd numbered D-channel (TS3) simultaneously on
DU and DD.
Data Sheet
89
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
Synchronous Transfer
While looping, shifting and switching the data can be accessed by the controller between
the synchronous transfer interrupt (STI) and the status overflow interrupt (STOV).
The microcontroller access to the CDAxy registers can be synchronized by means of
four programmable synchronous transfer interrupts (STIxy)1) and synchronous transfer
overflow interrupts (STOVxy) 2) in the STI register.
Depending on the DPS bit in the corresponding CDA_TSDPxy register the STIxy is
generated two (for DPS=’0’) or one (for DPS=’1’) BCL clock after the selected time slot
(CDA_TSDPxy.TSS). One BCL clock is equivalent to two DCL clocks.
In the following description the index xy0 and xy1 are used to refer to two different
interrupt pairs (STI/STOV) out of the four CDA interrupt pairs (STI10/STOV10, STI11/
STOV11, STI20/STOV20, STI21/STOV21).
An STOVxy0 is related to its STIxy0 and is only generated if STIxy0 is enabled and not
acknowledged. However, if STIxy0 is masked, the STOVxy0 is generated for any other
STIxy1 which is enabled and not acknowledged.
Table 9 gives some examples for that. It is assumed that an STOV interrupt is only
generated because an STI interrupt was not acknowledged before.
In example 1 only the STIxy0 is enabled and thus STIxy0 is only generated. If no STI is
enabled, no interrupt will be generated even if STOV is enabled (example 2).
In example 3 STIxy0 is enabled and generated and the corresponding STOVxy0 is
disabled. STIxy1 is disabled but its STOVxy1 is enabled, and therefore STOVxy1 is
generated due to STIxy0. In example 4 additionally the corresponding STOVxy0 is
enabled, so STOVxy0 and STOVxy1 are both generated due to STIxy0.
In example 5 additionally the STIxy1 is enabled with the result that STOVxy0 is only
generated due to STIxy0 and STOVxy1 is only generated due to STIxy1.
Compared to the previous example STOVxy0 is disabled in example 6, so STOVxy0 is
not generated and STOVxy1 is only generated for STIxy1 but not for STIxy0.
Compared to example 5 in example 7 a third STOVxy2 is enabled and thus STOVxy2 is
generated additionally for both STIxy0 and STIxy1.
1)
In order to enable the STI interrupts the input of the corresponding CDA register has to be enabled. This is also
valid if only a synchronous write access is wanted. The enabling of the output alone does not effect an STI
interrupt.
2) In order to enable the STOV interrupts the output of the corresponding CDA register has to be enabled. This
is also valid if only a synchronous read access is wanted. The enabling of the input alone does not effect an
interrupt.
Data Sheet
90
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
Table 9
Examples for Synchronous Transfer Interrupts
Enabled Interrupts
(Register MSTI)
Generated Interrupts
(Register STI)
STI
STOV
STI
STOV
xy0
-
xy0
-
Example 1
-
xy0
-
-
Example 2
xy0
xy1
xy0
xy1
Example 3
xy0
xy0 ; xy1
xy0
xy0 ; xy1
Example 4
xy0 ; xy1
xy0 ; xy1
xy0
xy1
xy0
xy1
Example 5
xy0 ; xy1
xy1
xy0
xy1
xy1
Example 6
xy0 ; xy1
xy0 ; xy1 ; xy2
xy0
xy1
xy0 ; xy2
xy1 ; xy2
Example 7
An STOV interrupt is not generated if all stimulating STI interrupts are acknowledged.
An STIxy must be acknowledged by setting the ACKxy bit in the ASTI register until two
BCL clocks (for DPS=’0’) or one BCL clocks (for DPS=’1’) before the time slot which is
selected for the appropriate STIxy.
The interrupt structure of the synchronous transfer is shown in Figure 49.
.
MASK
ISTA
ST
CIC
WOV
TRAN
MOS
ST
CIC
WOV
TRAN
MOS
MSTI
STOV21
STOV20
STOV11
STOV10
STI21
STI20
STI11
STI10
STI
STOV21
STOV20
STOV11
STOV10
STI21
STI20
STI11
STI10
ASTI
ACK21
ACK20
ACK11
ACK10
Interrupt
Figure 49
Data Sheet
Interrupt Structure of the Synchronous Data Transfer
91
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SBCX-X
PEB 3081
Description of Functional Blocks
Figure 50 shows some examples based on the timeslot structure. Figure a) shows at
which point in time an STI and STOV interrrupt is generated for a specific timeslot. Figure
b) is identical to example 3 above, figure c) corresponds to example 5 and figure d)
shows example 4.
.
: STI interrupt generated
: STOV interrupt generated for a not acknowledged STI interrupt
a) Interrupts for data access to time slot 0 (B1 after reset), MSTI.STI10 and MSTI.STOV10 enabled
xy:
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
10
TS0
'0'
'0'
11
TS1
'1'
'1'
TS11 TS0 TS1
21
TS5
'1'
'1'
TS2 TS3
TS4 TS5 TS6
20
TS11
'1'
'1'
TS7 TS8
TS9 TS10 TS11 TS0
b) Interrupts for data access to time slot 0 (B1 after reset), STOV interrupt used as flag for "intermediate CDA
access"; MSTI.STI10 and MSTI.STOV21 enabled
xy:
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
10
TS0
'0'
'1'
11
TS1
'1'
'1'
TS11 TS0 TS1
21
TS5
'1'
'0'
TS2 TS3
TS4 TS5 TS6
20
TS11
'1'
'1'
TS7 TS8
TS9 TS10 TS11 TS0
c) Interrupts for data access to time slot 0 and 5, MSTI.STI10, MSTI.STOV10,
MSTI.STI21 and MSTI.STOV21 enabled
xy:
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
10
TS0
'0'
'0'
11
TS1
'1'
'1'
TS11 TS0 TS1
21
TS5
'0'
'0'
TS2 TS3
TS4 TS5 TS6
20
TS11
'1'
'1'
TS7 TS8
TS9 TS10 TS11 TS0
d) Interrupts for data access to time slot 0 (B1 after reset), STOV21 interrupt used as flag for "intermiediate CDA
access", STOV10 interrupt used as flag for "CDA access failed"; MSTI.STI10, MSTI.STOV10 and
MSTI.STOV21 enabled
xy:
CDA_TDSPxy.TSS:
MSTI.STIxy:
MSTI.STOVxy:
10
TS0
'0'
'0'
11
TS1
'1'
'1'
TS11 TS0 TS1
21
TS5
'1'
'0'
TS2 TS3
TS4 TS5 TS6
20
TS11
'1'
'1'
TS7 TS8
TS9 TS10 TS11 TS0
sti_stov.vsd
Figure 50
Data Sheet
Examples for the Synchronous Transfer Interrupt Control with one
Enabled STIxy
92
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PEB 3081
Description of Functional Blocks
Restrictions Concerning Monitoring and Shifting Data
Due to the hardware design, there are some restrictions for the CDA shifting data
function and for the CDA monitoring data function. The selection of the CDA registers is
restricted if other functional blocks of the SBCX-X (transceiver cores, CI handler, Monitor
handler, TIC bus etc.) access the corresponding timeslot.
If no functional block is assigned to a certain timeslot, any CDA register can be used for
monitoring or shifting it.
If a timeslot is already occupied by a functional block in a certain transmission direction,
only CDA registers with odd numbers (CDA11/21) can be assigned to odd timeslots and
CDA registers with even numbers (CDA10/20) can be assigned to even timeslots in the
same transmission direction. For the other transmission direction every CDA register can
be used. (Example: If TS 5 is already occupied in DD direction, only CDA11 and 21 can
be used for monitoring it. For monitoring TS 5 in DU direction, also CDA10 or CDA20
could be used.)
If above guideline is not considered, data can be overwritten in corresponding timeslots.
In this context no general rules can be derived in which way the data are overwritten.
The usage of the looping data and switching data functions are unrestricted.
Restrictions Concerning Read/Write Access
If data shall be read out from a certain transmission direction and other data shall be
written in the opposite transmission direction in the same timeslot, only special CDA
register combinations can be used. The correct behavior can be achieved with the
following CDA register combinations:
Table 10
CDA Register Combinations with Correct Read/Write Access
CDA Register Combination
1
2
3
4
Data of the downstream timeslot is read by CDA10
CDA11
CDA20
CDA21
Data is written to the upstream timeslot from CDA20
CDA21
CDA10
CDA11
With other register combinations unintended loops or erroneous monitorings can occur
or wrong data is written to the IOM interface.
Unexpected Write/Read Behavior of CDA Registers
If inputs and outputs are disabled, the programmed values of CDA10/11/20/21 registers
cannot be read back. Instead of the expected value the content of the previous
programming can be read out. The programmed value (5AH in the following example)
will be fetched if the output is enabled.
Data Sheet
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SBCX-X
PEB 3081
Description of Functional Blocks
Example:
w CDA1_CR = 00H (inputs and outputs are disabled)
w CDA10 = 5AH (example)
r CDA10 = FFH (old value of previous programming)
w CDA1_CR = 02H (output of CDA10 is enabled)
r CDA10 = 5AH (the programmed value can be read back)
3.7.2
Serial Data Strobe Signal and Strobed Data Clock
For time slot oriented standard devices connected to the IOM-2 interface the SBCX-X
provides two independent data strobe signals SDS1 and SDS2. Instead of a data strobe
signal a strobed IOM-2 bit clock can be provided on pin SDS1 and SDS2.
3.7.2.1
Serial Data Strobe Signal
The two strobe signals can be generated with every 8-kHz frame and are controlled by
the registers SDS1/2_CR. By programming the TSS bits and three enable bits
(ENS_TSS, ENS_TSS+1, ENS_TSS+3) a data strobe can be generated for the IOM-2
time slots TS, TS+1 and TS+3 and any combination of them.
The data strobes for TS and TS+1 are always 8 bits long (bit7 to bit0) whereas the data
strobe for TS+3 is always 2 bits long (bit7, bit6).
Figure 51 shows three examples for the generation of a strobe signal. In example 1 the
SDS is active during channel B2 on IOM-2 whereas in the second example during IC2
and MON1. The third example shows a strobe signal for 2B+D channels which can be
used e.g. for an IDSL (144kbit/s) transmission.
Data Sheet
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SBCX-X
PEB 3081
Description of Functional Blocks
FSC
DD,DU
B1
B2
MON0
TS0
TS1
TS2
D CI0
MM
RX
TS3
IC1
IC2 MON1
TS4
TS5
TS6
CI1
MM
RX
TS7
TS8
TS9
TS10 TS11
TS0
TS1
SDS1,2
(Example1)
SDS1,2
(Example2)
SDS1,2
(Example3)
Example 1:
TSS
ENS_TSS
ENS_TSS+1
ENS_TSS+3
= '0H'
= '0'
= '1'
= '0'
Example 2:
TSS
ENS_TSS
ENS_TSS+1
ENS_TSS+3
= '5H'
= '1'
= '1'
= '0'
Example 3:
TSS
ENS_TSS
ENS_TSS+1
ENS_TSS+3
= '0H'
= '1'
= '1'
= '1'
strobe.vsd
For all examples SDS_CONF.SDS1/2_BCL must be set to “0”.
Figure 51
Data Sheet
Data Strobe Signal
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PEB 3081
Description of Functional Blocks
3.7.2.2
Strobed IOM-2 Bit Clock
The strobed IOM-2 bit clock is active during the programmed window. Outside the
programmed window a ’0’ is driven. Two examples are shown in Figure 52.
FSC
DD,DU
B1
B2
TS0
TS1
MM
MON0 D CI0 R X IC1
TS2
TS3
TS4
IC2 MON1
TS5
TS6
CI1
MM
RX
TS7
TS8
TS9
TS10 TS11
TS0
TS1
SDS1
(Example1)
SDS1
(Example2)
Setting of SDS1_CR:
Example 1:
TSS
ENS_TSS
ENS_TSS+1
ENS_TSS+3
= '0H'
= '0'
= '0'
= '1'
Example 2:
TSS
ENS_TSS
ENS_TSS+1
ENS_TSS+3
= '5H'
= '1'
= '1'
= '0'
bcl_strobed.vsd
For all examples SDS_CONF.SDS1_BCL must be set to “1”.
Figure 52
Strobed IOM-2 Bit Clock. Register SDS_CONF Programmed to 01H
The strobed bit clock can be enabled in SDS_CONF.SDS1/2_BCL.
Data Sheet
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2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.7.3
IOM-2 Monitor Channel
The IOM-2 MONITOR channel (see Figure 53) is utilized for information exchange in the
MONITOR channel between a master mode device and a slave mode device.
The MONTIOR channel data can be controlled by the bits in the MONITOR control
register (MON_CR). For the transmission of the MONITOR data one of the IOM-2
channels (3 IOM-2 channels in TE mode, 8 channels in non TE mode) can be selected
by setting the MONITOR channel selection bits (MCS) in the MONITOR control register
(MON_CR).
The DPS bit in the same register selects between an output on DU or DD respectively
and with EN_MON the MONITOR data can be enabled/disabled. The default value is
MONITOR channel 0 (MON0) enabled and transmission on DD.
IOM-2 MONITOR Channel
V/D Module
(e.g. ARCOFI-BA)
IOM-2 MONITOR Channel
V/D Module
(e.g. ISAR34)
MONITOR Handler
MONITOR Handler
Layer 1
Layer 1
Master
Device
Slave
Device
µC
µC
IOM-2 MONITOR Channel
V/D Module
(e.g. ISAR34)
MONITOR Handler
Layer 1
µC
Data Exchange between
two µC Systems
Figure 53
µC
3086_08
Examples of MONITOR Channel Applications in IOM-2 TE Mode
The MONITOR channel of the SBCX-X can be used in following applications which are
illustrated in Figure 53:
• As a master device the SBCX-X can program and control other devices attached to
the IOM-2 which do not need a parallel microcontroller interface e.g. ARCOFI-BA
PSB 2161. This facilitates redesigning existing terminal designs in which e.g. an
interface of an expansion slot is realized with IOM-2 interface and monitor
programming.
Data Sheet
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SBCX-X
PEB 3081
Description of Functional Blocks
• As a slave device the transceiver part of the SBCX-X is programmed and controlled
from a master device on IOM-2 (e.g. ISAR 34 PSB 7115). This is used in applications
where no microcontroller is connected directly to the SBCX-X in order to simplify host
interface connection. The HDLC controlling is processed by the master device
therefore the HDLC data is transferred via IOM-2 interface directly to the master
device.
• For data exchange between two microcontroller systems attached to two different
devices on one IOM-2 backplane. Use of the MONITOR channel avoids the necessity
of a dedicated serial communication path between the two systems. This simplifies the
system design of terminal equipment.
3.7.3.1
Handshake Procedure
The MONITOR channel operates on an asynchronous basis. While data transfers on the
bus take place synchronized to frame sync (FSC), the flow of data is controlled by a
handshake procedure using the MONITOR Channel Receive (MR) and MONITOR
Channel Transmit (MX) bits. Data is placed onto the MONITOR channel and the MX bit
is activated. This data will be transmitted once per 8-kHz frame until the transfer is
acknowledged via the MR bit.
The MONITOR channel protocol is described in the following section and Figure 54
illustrates this. The relevant control and status bits for transmission and reception are
listed in Table 11 and Table 12.
Table 11
Transmit Direction
Control/
Status Bit
Register
Bit
Function
Control
MOCR
MXC
MX Bit Control
MIE
Transmit Interrupt Enable
MDA
Data Acknowledged
MAB
Data Abort
MAC
Transmission Active
Status
MOSR
MSTA
Table 12
Receive Direction
Control/
Status Bit
Register
Bit
Function
Control
MOCR
MRC
MR Bit Control
MRE
Receive Interrupt Enable
MDR
Data Received
MER
End of Reception
Status
Data Sheet
MOSR
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SBCX-X
PEB 3081
Description of Functional Blocks
µP
Transmitter
MIE = 1
MOX = ADR
MXC = 1
MAC = 1
MDA Int.
MOX = DATA1
MDA Int.
MOX = DATA2
MDA Int.
MXC = 0
µP
Receiver
MON
MX
MR
FF
FF
ADR
1
1
0
1
1
1
ADR
DATA1
DATA1
0
1
0
0
0
0
DATA1
DATA1
0
0
1
0
DATA2
DATA2
1
0
0
0
DATA2
DATA2
0
0
1
0
FF
FF
1
1
0
0
FF
FF
1
1
1
1
125 µ s
MDR Int.
RD MOR (=ADR)
MRC = 1
MDR Int.
RD MOR (=DATA1)
MDR Int.
RD MOR (=DATA2)
MER Int.
MRC = 0
MAC = 0
ITD10032
Figure 54
MONITOR Channel Protocol (IOM-2)
Before starting a transmission, the microprocessor should verify that the transmitter is
inactive, i.e. that a possible previous transmission has been terminated. This is indicated
by a ’0’ in the MONITOR Channel Active MAC status bit.
After having written the MONITOR Data Transmit (MOX) register, the microprocessor
sets the MONITOR Transmit Control bit MXC to ’1’. This enables the MX bit to go active
(’0’), indicating the presence of valid MONITOR data (contents of MOX) in the
corresponding frame. As a result, the receiving device stores the MONITOR byte in its
MONITOR Receive MOR register and generates an MDR interrupt status.
Alerted by the MDR interrupt, the microprocessor reads the MONITOR Receive (MOR)
register. When it is ready to accept data (e.g. based on the value in MOR, which in a
point-to-multipoint application might be the address of the destination device), it sets the
MR control bit MRC to ’1’ to enable the receiver to store succeeding MONITOR channel
bytes and acknowledge them according to the MONITOR channel protocol. In addition,
it enables other MONITOR channel interrupts by setting MONITOR Interrupt Enable
(MIE) to ’1’.
Data Sheet
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2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
As a result, the first MONITOR byte is acknowledged by the receiving device setting the
MR bit to ’0’. This causes a MONITOR Data Acknowledge MDA interrupt status at the
transmitter.
A new MONITOR data byte can now be written by the microprocessor in MOX. The MX
bit is still in the active (0) state. The transmitter indicates a new byte in the MONITOR
channel by returning the MX bit active after sending it once in the inactive state. As a
result, the receiver stores the MONITOR byte in MOR and generates a new MDR
interrupt status. When the microprocessor has read the MOR register, the receiver
acknowledges the data by returning the MR bit active after sending it once in the inactive
state. This in turn causes the transmitter to generate an MDA interrupt status.
This "MDA interrupt – write data – MDR interrupt – read data – MDA interrupt"
handshake is repeated as long as the transmitter has data to send. Note that the
MONITOR channel protocol imposes no maximum reaction times to the microprocessor.
When the last byte has been acknowledged by the receiver (MDA interrupt status), the
microprocessor sets the MONITOR Transmit Control bit MXC to ’0’. This enforces an
inactive (’1’) state in the MX bit. Two frames of MX inactive signifies the end of a
message. Thus, a MONITOR Channel End of Reception MER interrupt status is
generated by the receiver when the MX bit is received in the inactive state in two
consecutive frames. As a result, the microprocessor sets the MR control bit MRC to 0,
which in turn enforces an inactive state in the MR bit. This marks the end of the
transmission, making the MONITOR Channel Active MAC bit return to ’0’.
During a transmission process, it is possible for the receiver to ask a transmission to be
aborted by sending an inactive MR bit value in two consecutive frames. This is effected
by the microprocessor writing the MR control bit MRC to ’0’. An aborted transmission is
indicated by a MONITOR Channel Data Abort MAB interrupt status at the transmitter.
The MONITOR transfer protocol rules are summarized in the following section:
• A pair of MX and MR in the inactive state for two or more consecutive frames indicates
an idle state or an end of transmission.
• A start of a transmission is initiated by the transmitter by setting the MXC bit to ’1’
enabling the internal MX control. The receiver acknowledges the received first byte by
setting the MR control bit to ’1’ enabling the internal MR control.
• The internal MX,MR control indicates or acknowledges a new byte in the MON slot by
toggling MX,MR from the active to the inactive state for one frame.
• Two frames with the MR-bit set to inactive indicate a receiver request for abort.
• The transmitter can delay a transmission sequence by sending the same byte
continuously. In that case the MX-bit remains active in the IOM-2 frame following the
first byte occurrence. Delaying a transmission sequence is only possible while the
receiver MR-bit and the transmitter MX-bit are active.
• Since a double last-look criterion is implemented the receiver is able to receive the
MON slot data at least twice (in two consecutive frames), the receiver waits for the
acknowledge of the reception of two identical bytes in two successive frames.
Data Sheet
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SBCX-X
PEB 3081
Description of Functional Blocks
• To control this handshake procedure a collision detection mechanism is implemented
in the transmitter. This is done by making a collision check per bit on the transmitted
MONITOR data and the MX bit.
• Monitor data will be transmitted repeatedly until its reception is acknowledged or the
transmission time-out timer expires.
• Two frames with the MX bit in the inactive state indicates the end of a message
(EOM).
• Transmission and reception of monitor messages can be performed simultaneously.
This feature is used by the SBCX-X to send back the response before the
transmission from the controller is completed (the SBCX-X does not wait for EOM
from controller).
3.7.3.2
Error Treatment
In case the SBCX-X does not detect identical monitor messages in two successive
frames, transmission is not aborted. Instead the SBCX-X will wait until two identical bytes
are received in succession.
A transmission is aborted of the SBCX-X if
• an error in the MR handshaking occurs
• a collision on the IOM-2 bus of the MONITOR data or MX bit occurs
• the transmission time-out timer expires
A reception is aborted by the device if
• an error in the MX handshaking occurs or
• an abort request from the opposite device occurs
MX/MR Treatment in Error Case
In the master mode the MX/MR bits are under control of the microcontroller through MXC
or MRC, respectively. An abort is indicated by an MAB interrupt or MER interrupt,
respectively.
In the slave mode the MX/MR bits are under control of the device. An abort is always
indicated by setting the MX/MR bit inactive for two or more IOM-2 frames. The controller
must react with EOM.
Figure 55 shows an example for an abort requested by the receiver, Figure 56 shows
an example for an abort requested by the transmitter and Figure 57 shows an example
for a successful transmission.
Data Sheet
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SBCX-X
PEB 3081
Description of Functional Blocks
IOM -2 Frame No.
1
2
3
4
5
6
7
1
MX (DU)
EOM
0
1
MR (DD)
0
Abort Request from Receiver
mon_rec-abort.vsd
Figure 55
Monitor Channel, Transmission Abort Requested by the Receiver
IOM -2 Frame No.
1
3
2
4
5
6
7
1
MR (DU)
EOM
0
1
MX (DD)
0
Abort Request from Transmitter
mon_tx-abort.vsd
Figure 56
Monitor Channel, Transmission Abort Requested by the Transmitter
IOM -2 Frame No.
MR (DU)
1
2
3
4
5
6
8
1
EOM
0
MX (DD)
7
1
0
mon_norm.vsd
Figure 57
Data Sheet
Monitor Channel, Normal End of Transmission
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Description of Functional Blocks
3.7.3.3
MONITOR Channel Programming as a Master Device
As a master device the SBCX-X can program and control other devices attached to the
IOM-2 interface. The master mode is selected by default if the serial control interface
(SCI) is used by the host. The monitor data is written by the microprocessor in the MOX
register and transmitted via IOM-2 DD (DU) line to the programmed/controlled device
e.g. ARCOFI-BA PSB 2161 or IEC-Q TE PSB 21911. The transfer of the commands in
the MON channel is regulated by the handshake protocol mechanism with MX, MR
which is described in the previous chapter Chapter 3.7.3.1.
If the transmitted command was a read command the slave device responds by sending
the requested data.
The data structure of the transmitted monitor message depends on the device which is
programmed. Therefore the first byte of the message is a specific address code which
contains in the higher nibble a MONITOR channel address to identify different devices.
The length of the messages depends on the accessed device and the type of MONITOR
command.
3.7.3.4
MONITOR Channel Programming as a Slave Device
In applications without direct host controller connection the SBCX-X must operate in the
MONITOR slave mode which can be selected by pinstrapping the microcontroller
interface pins according Table 3 respectively in Chapter 3.2. As a slave device the
transceiver part of the SBCX-X is programmed and controlled by a master device at the
IOM-2 interface. All programming data required by the SBCX-X is received in the
MONITOR time slot on the IOM-2 and is transferred in the MOR register. The transfer of
the commands in the MON channel is regulated by the handshake protocol mechanism
with MX, MR which is described in the previous Chapter 3.7.3.1.
The first byte of the MONITOR message must contain in the higher nibble the MONITOR
channel address code which is ’1010’ for the SBCX-X. The lower nibble distinguishes
between a programming command or an identification command.
Identification Command
In order to be able to identify unambiguously different hardware designs of the SBCX-X
by software, the following identification command is used:
DD 1st byte value
1
0
1
0
0
0
0
0
DD 2nd byte value
0
0
0
0
0
0
0
0
The SBCX-X responds to this DD identification sequence by sending a DU identification
sequence:
DESIGN: six bit code, specific for each device in order to identify differences in operation
e.g.
000001 SBCX-X PEB 3081 Version 1.4
Data Sheet
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2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
DU 1st byte value
1
0
DU 2nd byte value
0
1
1
0
0
0
0
0
DESIGN
<IDENT>
This identification sequence is usually done once, when the terminal is connected for the
first time. This function is used so that the software can distinguish between different
possible hardware configurations. However this sequence is not compulsory.
Programming Sequence
The programming sequence is characterized by a ’1’ being sent in the lower nibble of the
received address code. The data structure after this first byte and the principle of a read/
write access to a register is similar to the structure of the serial control interface
described in Chapter 3.2.2. For write access the header 43H/47H can be used and for
read access the header 40H/44H.
DD 1st byte value
1
0
1
DD 2nd byte value
DD 3rd byte value
0
0
0
0
1
Header Byte
R/W
Register Address
DD 4th byte value
Data 1
DD (nth + 3) byte value
Data n
All registers can be read back when setting the R/W bit in the byte for the command/
register address. The SBCX-X responds by sending its IOM-2 specific address byte
(A1h) followed by the requested data.
Note: Application Hint:
It is not allowed to disable the MX- and MR-control in the programming device at
the same time! First, the MX-control must be disabled, then the mC has to wait for
an End of Reception before the MR-control may be disabled. Otherwise, the
SBCX-X does not recognize an End of Reception.
3.7.3.5
MONITOR Time-Out Procedure
To prevent lock-up situations in a MONITOR transmission a time-out procedure can be
enabled by setting the time-out bit (TOUT) in the MONITOR configuration register
(MCONF). An internal timer is always started when the transmitter must wait for the reply
of the addressed device. After 5 ms without reply the timer expires and the transmission
will be aborted with a EOM (End of Message) command by setting the MX bit to ’1’ for
two consecutive IOM-2 frames.
Data Sheet
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SBCX-X
PEB 3081
Description of Functional Blocks
3.7.3.6
MONITOR Interrupt Logic
Figure 58 shows the MONITOR interrupt structure of the SBCX-X. The MONITOR Data
Receive interrupt status MDR has two enable bits, MONITOR Receive interrupt Enable
(MRE) and MR bit Control (MRC). The MONITOR channel End of Reception MER,
MONITOR channel Data Acknowledged MDA and MONITOR channel Data Abort MAB
interrupt status bits have a common enable bit MONITOR Interrupt Enable MIE.
MRE prevents the occurrence of MDR status, including when the first byte of a packet is
received. When MRE is active (1) but MRC is inactive, the MDR interrupt status is
generated only for the first byte of a receive packet. When both MRE and MRC are
active, MDR is always generated and all received MONITOR bytes - marked by a 1-to-0
transition in MX bit - are stored. (Additionally, an active MRC enables the control of the
MR handshake bit according to the MONITOR channel protocol.)
MASK
ISTA
ST
CIC
WOV
TRAN
MOS
ST
CIC
WOV
TRAN
MOS
MRE
MDR
MER
MIE
MDA
MAB
MOSR
MOCR
Interrupt
Figure 58
MONITOR Interrupt Structure
Data Sheet
105
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.7.4
C/I Channel Handling
The Command/Indication channel carries real-time status information between the
SBCX-X and another device connected to the IOM-2 interface.
• One C/I channel (called C/I0) conveys the commands and indications between the
layer-1 and the C/I handler of the SBCX-X. It can be accessed by an external layer-2
device e.g. to control the layer-1 activation/deactivation procedures. C/I0 channel
access may be arbitrated via the TIC bus access protocol. In this case the arbitration
is done in IOM-2 channel 2 (see Figure 41).
The C/I0 channel is accessed via register CIR0 (in receive direction, layer-1 to layer2) and register CIX0 (in transmit direction, layer-2 to layer-1). The C/I0 code is four
bits long. A listing and explanation of the layer-1 C/I codes can be found in
Chapter 3.5.4.
In the receive direction, the code from layer-1 is continuously monitored, with an
interrupt being generated anytime a change occurs (ISTA.CIC). A new code must be
found in two consecutive IOM-2 frames to be considered valid and to trigger a C/I code
change interrupt status (double last look criterion).
In the transmit direction, the code written in CIX0 is continuously transmitted in C/I0.
• A second C/I channel (called C/I1) can be used to convey real time status information
between the SBCX-X and various non-layer-1 peripheral devices e.g. PSB 2161
ARCOFI-BA. The C/I1 channel consists of four or six bits in each direction.The width
can be changed from 4bit to 6bit by setting bit CIX1.CICW.
In 4-bit mode 6-bits are written whereby the higher 2 bits must be set to “1” and 6-bits
are read whereby only the 4 LSBs are used for comparison and interrupt generation
(i.e. the higher two bits are ignored).
The C/I1 channel is accessed via registers CIR1 and CIX1. A change in the received
C/I1 code is indicated by an interrupt status without double last look criterion.
CIC Interrupt Logic
Figure 59 shows the CIC interrupt structure.
A CIC interrupt may originate
– from a change in received C/I channel 0 code (CIC0)
or
– from a change in received C/I channel 1 code (CIC 1).
Data Sheet
106
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SBCX-X
PEB 3081
Description of Functional Blocks
The two corresponding status bits CIC0 and CIC1 are read in CIR0 register. CIC1 can
be individually disabled by clearing the enable bit CI1E in the CIX1 register. In this case
the occurrence of a code change in CIR1 will not be displayed by CIC1 until the
corresponding enable bit has been set to one.
Bits CIC0 and CIC1 are cleared by a read of CIR0.
An interrupt status is indicated every time a valid new code is loaded in CIR0 or CIR1.
The CIR0 is buffered with a FIFO size of two. If a second code change occurs in the
received C/I channel 0 before the first one has been read, immediately after reading of
CIR0 a new interrupt will be generated and the new code will be stored in CIR0. If several
consecutive codes are detected, only the first and the last code is obtained at the first
and second register read, respectively.
For CIR1 no FIFO is available. The actual code of the received C/I channel 1 is always
stored in CIR1.
MASK
ISTA
ST
CIC
ST
CIC
WOV
TRAN
MOS
WOV
TRAN
MOS
CI1E
CIX1
CIC0
CIC1
CIR0
Interrupt
Figure 59
3.7.5
CIC Interrupt Structure
D-Channel Access Control
D-channel access control is defined to guarantee all connected TEs and HDLC
controllers a fair chance to transmit data in the D-channel. Collisions are possible
• on the IOM-2 interface if there is more than one HDLC controller connected or
• on the S-interface when there is more than one terminal connected in a point to
multipoint configuration (NT ® TE1 … TE8).
Both arbitration mechanisms are implemented in the SBCX-X and will be described in
the following two chapters.
Data Sheet
107
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SBCX-X
PEB 3081
Description of Functional Blocks
3.7.5.1
TIC Bus D-Channel Access Control
The TIC bus is imlemented to organize the access to the layer-1 functions provided in
the SBCX-X (C/I-channel) and to the D-channel from up to 7 external communication
controllers (Figure 60).
Note: The TIC Bus can be used in TE/iNT mode only. In other modes it has to be
switched off in order not to disturb the layer-1 control. This is done by
setting bit DIM 1 in register Mode D and bit 4 in register IOM_CR. For more
details please refer to the application note “Reconfigurable PBX”.
To this effect the outputs of the D-channel controllers (e.g. ICC - ISDN Communication
Controller PEB 2070) are wired-or (negative logic, i.e. a “0” wins) and connected to pin
DU. The inputs of the ICCs are connected to pin DD. External pull-up resistors on DU/
DD are required. The arbitration mechanism must be activated by setting
TR_MODE2.DIM2-0=00x.
ICC (7)
.
.
.
TIC-Bus
on IOM-2
ICC (2)
ICC (1)
S-Interface
ICC
SBCX-X
U-Interface
NT
3081_09
Figure 60
Applications of TIC Bus in IOM-2 Bus Configuration
The arbitration mechanism is implemented in the last octet in IOM-2 channel 2 of the
IOM-2 interface (Figure 61). An access request to the TIC bus may either be generated
by software via a µP access to the C/I channel or by one of the D-channel controllers
(ICC). A software access request to the bus is effected by setting the BAC bit (CIX0
register) to ’1’.
Data Sheet
108
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
In the case of an access request to the C/I channel, the SBCX-X checks the Bus
Accessed-bit BAC (bit 5 of last octet of CH2 on DU, see Figure 61) for the status "bus
free“, which is indicated by a logical ’1’. If the bus is free, the SBCX-X transmits its
individual TIC bus address TAD. The SBCX-X sends its TIC bus address TAD and
compares it bit by bit with the value on DU. If a sent bit set to ’1’ is read back as ’0’
because of the access of another source with a lower TAD wishing access to D- or C/
I-channel, the SBCX-X withdraws immediately from the TIC bus, i.e. the remaining TAD
bits are not transmitted. The TIC bus is occupied by the device which sends its address
error-free. If more than one device attempt to seize the bus simultaneously, the one with
the lowest address values wins. This one will set BAC=0 on TIC bus and starts
D-channel transmission in the same frame.
DU
Figure 61
Structure of Last Octet of Ch2 on DU
When the TIC bus is seized by the ICC, the bus is identified to other devices as occupied
via the DU Ch2 Bus Accessed-bit state ’0’ until the access request is withdrawn. After a
successful bus access, the ICC is automatically set into a lower priority class, that is, a
new bus access cannot be performed until the status "bus free" is indicated in two
successive frames.
If none of the devices connected to the IOM-2 interface request access to the D and C/
I channels, the TIC bus address 7 will be present. The device with this address will
therefore have access, by default, to the D and C/I channels.
Data Sheet
109
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.7.5.2
S-Bus Priority Mechanism for D-Channel
The S-bus access procedure specified in ITU I.430 was defined to organize D-channel
access with multiple TEs connected to a single S-bus (Figure 63).
To implement collision detection the D (channel) and E (echo) bits are used. The
D-channel S-bus condition is indicated towards the IOM-2 interface with the S/G bit, i.e.
the availability of the S/T interface D channel is indicated in bit 5 "Stop/Go" (S/G) of the
DD last octet of Ch2 channel (Figure 62).
S/G = 1 : stop
S/G = 0 : go
MR
MX
DD
B1
B2
MON0 D CI0
IC1
MR
MX
IC2
MON1
S/G
A/B
CI1
ITD09693
E E S/G A/B
Stop/Go
Figure 62
Available/Blocked
Structure of Last Octet of Ch2 on DD
The Stop/Go bit is available to other layer-2 devices connected to the IOM-2 interface to
determine if they can access the S/T bus D channel.
The access to the D-channel is controlled by a priority mechanism which ensures that all
competing TEs are given a fair access chance. This priority mechanism discriminates
among the kind of information exchanged and information exchange history: Layer-2
frames are transmitted in such a way that signalling information is given priority (priority
class 1) over all other types of information exchange (priority class 2). Furthermore, once
a TE having successfully completed the transmission of a frame, it is assigned a lower
level of priority of that class. The TE is given back its normal level within a priority class
when all TEs have had an opportunity to transmit information at the normal level of that
priority class.
The priority mechanism is based on a rather simple method: A TE not transmitting
layer-2 frames sends binary 1s on the D-channel. As layer-2 frames are delimited by
flags consisting of the binary pattern “01111110” and zero bit insertion is used to prevent
flag imitation, the D-channel may be considered idle if more than seven consecutive 1s
are detected on the D-channel. Hence by monitoring the D echo channel, the TE may
determine if the D-channel is currently used by another TE or not.
Data Sheet
110
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
A TE may start transmission of a layer-2 frame first when a certain number of
consecutive 1s has been received on the echo channel. This number is fixed to 8 in
priority class 1 and to 10 in priority class 2 for the normal level of priority; for the lower
level of priority the number is increased by 1 in each priority class, i.e. 9 for class 1 and
11 for class 2.
A TE, when in the active condition, is monitoring the D echo channel, counting the
number of consecutive binary 1s. If a 0 bit is detected, the TE restarts counting the
number of consecutive binary 1s. If the required number of 1s according to the actual
level of priority has been detected, the TE may start transmission of an HDLC frame. If
a collision occurs, the TE immediately shall cease transmission, return to the D-channel
monitoring state, and send 1s over the D-channel.
S-Interface
D-channel
control
U-Interface
D-Bits
SBCX-X
PEB 3081
NT
E-Bits
TE 1
D-channel
control
SBCX-X
PEB 3081
TE 2
.
.
.
D-channel
control
SBCX-X
PEB 3081
TE 8
Figure 63
Data Sheet
3081_10
D-Channel Access Control on the S-Interface
111
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
S-Bus D-channel Access Control in the SBCX-X
The above described priority mechanism is fully implemented in the SBCX-X. For this
purpose the D-channel collision detection according to ITU I.430 must be enabled by
setting TR_MODE2.DIM2-0 to ’0x1’. In this case the transceiver continuously compares
the received E-echo bits with its own transmitted D data bits.
Depending on the priority class selected, 8 (priority 8) or 10 (priority 10) consecutive
ONEs (high priority level) need to be detected before the transceiver sends valid
D-channel data on the upstream D-bits on S. In low priority level 9 (priority 8) or 11
(priority 10) consecutive ONEs are required.
The priority class (priority 8 or priority 10) is selected by transferring the appropriate
activation command via the Command/Indication (C/I) channel of the IOM-2 interface to
the transceiver. If the activation is initiated by a TE, the priority class is selected implicitly
by the choice of the activation command. If the S-interface is activated from the NT, an
activation command selecting the desired priority class should be programmed at the TE
on reception of the activation indication (AI8 or AI10). In the activated state the priority
class may be changed whenever required by simply programming the desired activation
request command (AR8 or AR10).
3.7.5.3
S-Bus D-Channel Control in LT-T
If the TE frame structure on the IOM-2 interface is selected, the same D-channel access
procedures as described in Chapter 3.7.5.2 are used in LT-T mode.
For other frame structures used in LT-T mode, D-channel access on S is handled
similarly, with the difference that the S/G bit is not available on IOM-2 but only on the
S/G bit output pin (SGO).
3.7.5.4
D-Channel Control in the Intelligent NT (TIC- and S-Bus)
In intelligent NT applications (selected via register TR_MODE.MODE2-0) one or more
D-channel controllers on the IOM-2 interface share the upstream D-channel with all
connected TEs on the S interface.
The transceiver incorporates an elaborate statemachine for D-channel priority handling
on IOM-2. For the access to the D-channel a similar arbitration mechanism as on the S
interface (writing D-bits, reading back E-bits) is performed for all D-channel sources on
IOM-2. Due to this an equal and fair access is guaranteed for all D-channel sources on
both the S interface and the IOM-2 interface.
This arbitration mechanism is only available in IOM-2 TE mode (12 PCM timeslots) per
frame with enabled TIC bus. The access to the upstream D-channel is handled via the
S/G bit for the HDLC controllers and via E-bit for all connected terminals on S (E-bits are
inverted to block the terminals on S). Furthermore, if more than one HDLC source is
requesting D-channel access on IOM-2 the TIC bus mechanism is used.
Data Sheet
112
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
The arbiter permanently counts the “1s” in the upstream D-channel on IOM-2. If the
necessary number of “1s” is counted and an HDLC controller on IOM-2 requests
upstream D-channel access (BAC bit is set to 0), the arbiter allows this D-channel
controller immediate access and blocks other TEs on S (E-bits are inverted). Similar as
on the S-interface the priority for D-channel access on IOM-2 can be configured to 8 or
10 (TR_CMD.DPRIO).
The upstream device can stop all D-channel sources by setting the A/B-bit to 0. The S/
G bit is not evaluated in this mode.
The configuration settings of the SBCX-X in intelligent NT applications are summarized
in Table 13.
Table 13
SBCX-X Configuration Settings in Intelligent NT Applications
Configuration Description
Configuration Setting
Select intelligent NT mode
Transceiver Mode Register:
TR_MODE.MODE0 = 0 (NT state machine)
or
TR_MODE.MODE0 = 1 (LT-S state machine)
TR_MODE.MODE1 = 1
TR_MODE.MODE2 = 1
Enable S/G bit evaluation
Transceiver Mode Register 2:
TR_MODE2.DIM2-0 = 001
Note: For mode selection in the TR_MODE register the MODE1/2 bits are used to select
intelligent NT mode, MODE0 selects NT or LT-S state machine.
With the configuration settings shown above the SBCX-X in intelligent NT applications
provides for equal access to the D-channel for terminals connected to the S-interface
and for D-channel sources on IOM-2.
For a detailed understanding the following sections provide a complete description on
the procedures used by the D-channel priority handler on IOM-2, although it may not be
necessary to study that in order to use this mode.
Data Sheet
113
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
1. NT D-Channel Controller Transmits Upstream
In the initial state (’Ready’ state) neither the local D-channel sources on IOM-2 nor any
of the terminals connected to the S-bus transmit in the D-channel.
The SBCX-X S-transceiver thus receives BAC = “1” (IOM-2 DU line) and transmits
S/G = “1” (IOM-2 DD line). The access will then be established according to the following
procedure:
• Local D-channel source verifies that BAC bit is set to ONE (currently no bus access).
• Local D-channel source issues TIC bus address and verifies that no controller with
higher priority requests transmission (TIC bus access must always be performed even
if no other D-channel sources are connected to IOM-2).
• Local D-channel source issues BAC = “0” to block other sources on IOM-2 and to
announce D-channel access.
• SBCX-X S-transceiver pulls S/G bit to ZERO (’Idle’ state) as soon as n D-bits = ’1’ are
counted on IOM-2 (see note) to allow for further D-channel access.
• SBCX-X S-transceiver transmits inverted echo channel (E bits) on the S-bus to block
all connected S-bus terminals (E = D).
• Local D-channel source commences with D data transmission on IOM-2 as long as it
receives S/G = “0”.
• After D-channel data transmission is completed the controller sets the BAC bit to
ONE.
• SBCX-X S-transceiver transmits non-inverted echo (E = D).
• SBCX-X S-transceiver pulls S/G bit to ONE (’Ready’ state) to block the D-channel
controller on IOM-2.
Note: “Local D-channel source” means any D-channel source on the IOM-2 interface.
Right after transmission the S/G bit is pulled to ’1’ until n successive D-bits = ’1’
occur on the IOM-2 interface. As soon as n D-bits = ’1’ are seen, the S/G bit is set
to ’0’ and the SBCX-X D-channel controller may start transmission again (if TIC
bus is occupied). This allows an equal access for D-channel sources on IOM-2
and on the S interface.
The number n depends on configuration settings (selected priority 8 or 10) and the
condition of the previous transmission, i.e. if an abort was seen (n = 8 or 10,
respectively) or if the last transmission was successful (n = 9 or 11, respectively).
Figure 64 illustrates the signal flow in an intelligent NT and the algorithm of the
D-channel priority handler on IOM-2 implemented in the SBCX-X.
Data Sheet
114
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
2. Terminal Transmits D-Channel Data Upstream
The initial state is identical to that described in the last paragraph. When one of the
connected S-bus terminals needs to transmit in the D-channel, access is established
according to the following procedure:
• SBCX-X S-transceiver (in intelligent NT) recognizes that the D-channel on the S-bus
is active.
• SBCX-X S-transceiver transfers S-bus D-channel data transparently through to the
upstream IOM-2 bus (IOM-2 channel 0).
For both cases described above the exchange indicates via the A/B bit (controlled by
layer 1) that D-channel transmission on this line is permitted (A/B = “1”). Data
transmission could temporarily be prohibited by the exchange when only a single
D-channel controller handles more lines (A/B = “0”, ELIC-concept).
In case the exchange prohibits D data transmission on this line the A/B bit is set to “0”
(block). For UPN applications with S extension this forces the intelligent NT SBCX-X
S-transceiver to transmit an inverted echo channel on the S-bus, thus disabling all
terminal requests, and switches S/G to A/B, which blocks the D-channel controller in the
intelligent NT.
Note: Although the SBCX-X S-transceiver operates in LT-S mode and is pinstrapped to
IOM-2 channel 0 or 1 it will write into IOM-2 channel 2 at the S/G bit position.
D-channel
controller 2
(e.g. ICC PEB2070)
TE
DS
BAC
D-channel
TE
E-channel
SBCX-X
DU
DD
D
S/G
A/B
TE
D IOM
S/G D
U
transceiver
Exchange
D D BAC TBA
D-channel
controller 1
(TE mode timing)
IOM-2
Masterdevice,
e.g. IEC-Q TE
3081_03
Figure 64
Data Sheet
Data Flow for Collision Resolution Procedure in Intelligent NT
115
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
3.7.6
Activation/Deactivation of IOM-2 Interface
The IOM-2 interface can be switched off in the inactive state, reducing power
consumption to a minimum. In this deactivated state is FSC = ’1’, DCL and BCL = ’0’ and
the data lines are ’1’.
The IOM-2 interface can be kept active while the S interface is deactivated by setting the
CFS bit to "0" (MODE1 register). This is the case after a hardware reset. If the IOM-2
interface should be switched off while the S interface is deactivated, the CFS bit should
be set to ’1’. In this case the internal oscillator is disabled when no signal (INFO 0) is
present on the S bus and the C/I command is ’1111’ = DIU. If the TE wants to activate
the line, it has first to activate the IOM-2 interface either by using the "Software Power
Up" function (IOM_CR.SPU bit) or by setting the CFS bit to "0" again.
The deactivation procedure is shown in Figure 65. After detecting the code DIU
(Deactivate Indication Upstream) the layer 1 of the SBCX-X responds by transmitting
DID (Deactivate Indication Downstream) during subsequent frames and stops the timing
signals synchronously with the end of the last C/I (C/I0) channel bit of the fourth frame.
IOMÒ -2
IOMÒ-2
Deactivated
FSC
DI
DI
DI
DI
DI
DI
DI
DI
DI
DR
DR
DR
DR
DR
DC
DC
DC
DC
DU
DD
B1
B2
D
D CIO
CIO
DCL
ITD09655_s.vsd
Figure 65
Deactivation of the IOM-2 Interface
The clock pulses will be enabled again when the DU line is pulled low (bit SPU in the
IOM_CR register), i.e. the C/I command TIM = "0000" is received by layer 1, or when a
non-zero level on the S-line interface is detected (if TR_CONF0.LDD=0). The clocks are
turned on after approximately 0.2 to 4 ms depending on the oscillator.
Data Sheet
116
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
DCL is activated such that its first rising edge occurs with the beginning of the bit
following the C/I (C/I0) channel.
After the clocks have been enabled this is indicated by the PU code in the C/I channel
and, consequently, by a CIC interrupt. The DU line may be released by resetting the
Software Power Up bit IOM_CR.SPU = ’0’ and the C/I code written to CIX0 before (e.g.
TIM or AR8) is output on DU.
The SBCX-X supplies IOM-2 timing signals as long as there is no DIU command in the
C/I (C/I0) channel. If timing signals are no longer required and activation is not yet
requested, this is indicated by programming DIU in the CIX0 register.
CIC : CIXO = TIM
Int. SPU = 0
~~
SPU = 1
FSC
TIM
TIM
TIM
PU
PU
PU
~~
DU
~~
PU
PU
~~
DD
~~
IOM -CH1
IOM -CH2
IOM -CH2
~~
R
~~
~~
~~ ~~
DU
~~ ~~
FSC
R
B1
DD
MR MX
R
IOM -CH1
~~
~~
0.2 to 4 ms
R
B1
~~
DCL
132 x DCL
ITD09656
Note: The value “132 x DCL” is only valid for
IOM configurations with 3 IOM channels.
Figure 66
Data Sheet
Activation of the IOM-2 interface
117
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
Asynchronous Awake (LT-S, NT, Int. NT mode)
The transceiver is in power down mode (deactivated state) and MODE1.CFS=1
(TR_CONF0.LDD is don’t care in this case). Due to any signal on the line the level detect
circuit will asynchronously pull the DU line on IOM-2 to “0” which is deactivated again
after 2 ms if the oscillator is fully operational. If the oscillator is just starting up in
operational mode, the 2 ms duration is extended correspondingly.
3.8
Auxiliary Interface
The AUX interface provides various functions, which depend on the operation mode (TE,
LT-T, LT-S, NT or intelligent NT mode) selected by pins MODE0 and MODE1/EAW (see
Table 14). After reset the pins are switched as inputs until further configuration is done
by the host.
Table 14
AUX Pin Functions
Pin
TE, Int. NT mode
LT-T, LT-S, NT mode
AUX0
AUX0 (i/o)
CH0 (i)
AUX1
AUX1 (i/o)
CH1 (i)
AUX2
AUX2 (i/o)
CH2 (i)
General Purpose I/O AUX0-2 (TE, Int. NT mode)
These pins can be used as programmable I/O lines.
As inputs (AOE.OEx=1) the state at the pin is latched in when the host performes read
operation to register ARX.
As outputs (AOE.OEx=0) the value in register ATX is driven on the pins with a minimum
delay after the write operation to this register is performed. They can be configured as
open drain (ACFG1.ODx=0) or push/pull outputs (ACFG1.ODx=1). The status (’1’ or ’0’)
at output pins can be read back from register ARX, which may be different from the ATX
value, e.g. if another device drives a different level.
Channel Select CH0-2 (LT-T, LT-S, NT mode)
In linecard mode one FSC frame is a multiplex of up to eight IOM-2 channels, each of
them consisting of B1-, B2-, MONITOR-, D- and C/I-channel and MR- and MX-bits.
One of eight channels on the IOM-2 interface is selected by CH0-2. These pins must be
strapped to VDD or VSS according to Table 15.
Data Sheet
118
2003-02-04
SBCX-X
PEB 3081
Description of Functional Blocks
Table 15
IOM-2 Channel Selection
CH2
CH1
CH0
Channel on IOM-2
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
For DCL = 1.536 MHz one of the IOM-2 channels 0 - 2 can be selected, for DCL =
4.096 MHz any of the eight IOM-2 channels can be selected.
The channel select pins have direct effect on the timeslot selection of the following
registers:
•
•
•
•
•
TR_TSDP_BC1
TR_TSDP_BC2
TR_CR, TRC_CR
DCI_CR, DCIC_CR
MON_CR
Data Sheet
119
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
4
Detailed Register Description
The register mapping of the SBCX-X is shown in Figure 67.
FFh
(Not used)
70h
Interrupt, General Configuration
60h
IOM-2 and MONITOR Handler
40h
Transceiver, C/I Handler
22h
*1)
(Not used)
00h
3081_04
Figure 67
Register Mapping of the SBCX-X
The register set ranging from 22H-3FH pertains to the transceiver and C/I-channel
handler registers.
Data Sheet
120
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
The address range from 40H-5BH is assigned to the IOM handler with the registers for
timeslot and data port selection (TSDP) and the control registers (CR) for the transceiver
data (TR), Monitor data (MON), C/I data (CI) and controller access data (CDA), serial
data strobe signal (SDS), IOM interface (IOM) and synchronous transfer interrupt (STI).
The address range from 5CH-5FH pertains to the MONITOR handler.
General interrupt and configuration registers are contained in the address range
60H-65H.
The register summaries of the SBCX-X are shown in the following tables containing the
abbreviation of the register name and the register bits, the register address, the reset
values and the register type (Read/Write). A detailed register description follows these
register summaries.
The register summaries and the description are sorted in ascending order of the register
address.
Transceiver, C/I-Channel Handler, Auxiliary Interface
NAME
7
6
5
4
3
2
1
0
00H21H
reserved
TR_
MODE2
0
0
0
0
0
ADDR R/WRES
DIM2 DIM1 DIM0
reserved
22H
R/W 00H
23-2DH
CIR0
CODR0
CIC0
CIC1
S/G
CIX0
CODX0
TBA2 TBA1 TBA0
BAS
2EH
R F3H
BAC
2EH W
FEH
CIR1
CODR1
CICW CI1E
2FH R
FEH
CIX1
CODX1
CICW CI1E
2FH W
FEH
TR_
CONF0
DIS_
TR
TR_
CONF1
0
TR_
CONF2
DIS_
TX
Data Sheet
BUS
EN_
ICV
RPLL_ EN_
ADJ SFSC
PDS
0
0
L1SW
0
EXLP
LDD
30H
R/W 01H
0
0
x
x
x
31H
R/W
RLP
0
0
SGP
SGD
32H
R/W 80H
121
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
Transceiver, C/I-Channel Handler, Auxiliary Interface
NAME
7
TR_STA
RINF
TR_CMD
SQRR1
6
5
4
3
2
1
0
SLIP
ICV
0
FSYN
0
LD
33H
R 00H
PD
LP_A
0
34H
R/W 08H
XINF
MSYN MFEN
DPRIO TDDIS
ADDR R/WRES
0
0
SQR11SQR12SQR13SQR14
35H
R 40H
0
0
SQX11 SQX12SQX13 SQX14
35H
W 4FH
SQRR2 SQR21SQR22SQR23SQR24SQR31SQR32SQR33SQR34
36H
R 00H
SQXR2 SQX21SQX22SQX23SQX24SQX31 SQX32SQX33 SQX34
36H
W 00H
SQRR3 SQR41SQR42SQR43SQR44SQR51SQR52SQR53SQR54
37H
R 00H
SQXR3 SQX41SQX42SQX43SQX44SQX51 SQX52SQX53 SQX54
37H
W 00H
ISTATR
0
x
x
x
LD
RIC
SQC
SQW
38H
R 00H
MASKTR
1
1
1
1
LD
RIC
SQC
SQW
39H
R/W FFH
TR_
MODE
0
0
0
0
SQXR1
0
MFEN
DCH_ MODE MODE MODE
INH
2
1
0
reserved
3AH R/W 00H
3BH
ACFG1
0
0
0
0
0
OD2
OD1
OD0
3CH R/W 00H
ACFG2
0
0
0
0
ACL
LED
0
0
3DH R/W 00H
AOE
1
1
1
1
1
OE2
OE1
OE0
3EH R/W FFH
ARX
-
-
-
-
-
AR2
AR1
AR0
3FH
R
ATX
0
0
0
0
0
AT2
AT1
AT0
3FH
W 00H
Data Sheet
122
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
IOM Handler (Timeslot , Data Port Selection,
CDA Data and CDA Control Register)
Name
7
6
5
4
3
2
1
0
ADDR R/WRES
CDA10
Controller Data Access Register (CH10)
40H
R/W FFH
CDA11
Controller Data Access Register (CH11)
41H
R/W FFH
CDA20
Controller Data Access Register (CH20)
42H
R/W FFH
CDA21
Controller Data Access Register (CH21)
43H
R/W FFH
CDA_ DPS
TSDP10
0
0
TSS
44H
R/W 00H
CDA_ DPS
TSDP11
0
0
TSS
45H
R/W 01H
CDA_ DPS
TSDP20
0
0
TSS
46H
R/W 80H
CDA_ DPS
TSDP21
0
0
TSS
47H
R/W 81H
reserved
48-4BH
TR_
TSDP_
BC1
DPS
0
0
TSS
4CH R/W 00H
TR_
TSDP_
BC2
DPS
0
0
TSS
4DH R/W 01H
CDA1_
CR
0
0
EN_ EN_I1 EN_I0 EN_O1EN_O0 SWAP
TBM
4EH R/W 00H
CDA2_
CR
0
0
EN_ EN_I1 EN_I0 EN_O1EN_O0 SWAP
TBM
4FH R/W 00H
Data Sheet
123
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
IOM Handler (Control Registers, Synchronous Transfer
Interrupt Control), MONITOR Handler
Name
7
6
5
4
3
EN_
D
EN_
B2R
EN_
B1R
EN_
B2X
EN_
B1X
CS2-0
50H R/W F8H
(CI_CS=0)
TRC_CR
0
0
0
0
0
CS2-0
50H R/W 00H
TR_CR
2
1
0
ADDR R/WRES
(CI_CS=1)
reserved
DCI_CR
51-52H
DPS_ EN_
(CI_CS=0) CI1
CI1
0
0
0
DCIC_CR
0
0
0
0
CS2-0
53H R/W 00H
EN_
MON
0
0
0
CS2-0
54H R/W 40H
0
0
0
0
53H R/W 80H
(CI_CS=1)
MON_CR DPS
SDS1_CR ENS_ ENS_ ENS_
TSS TSS+1 TSS+3
TSS
55H R/W 00H
SDS2_CR ENS_ ENS_ ENS_
TSS TSS+1 TSS+3
TSS
56H R/W 00H
IOM_CR
STI
ASTI
MSTI
SPU
DIS_ CI_CS TIC_
AW
DIS
STOV STOV STOV STOV
21
20
11
10
0
0
0
STOV STOV STOV STOV
21
20
11
10
SDS_
CONF
0
MCDA
MCDA21
Data Sheet
0
0
0
0
MCDA20
EN_ CLKM DIS_
BCL
OD
DIS_
IOM
57H R/W 08H
STI
21
STI
20
STI
11
STI
10
58H
R 00H
ACK
21
ACK
20
ACK
11
ACK
10
58H
W 00H
STI
21
STI
20
STI
11
STI
10
59H R/W FFH
DIOM_ DIOM_ SDS2_ SDS1_ 5AH R/W 00H
INV SDS BCL BCL
MCDA11
124
MCDA10
5BH
R FFH
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
MOR
MONITOR Receive Data
5CH
R FFH
MOX
MONITOR Transmit Data
5CH
W FFH
R 00H
MOSR
MDR
MER
MDA
MAB
0
0
0
0
5DH
MOCR
MRE
MRC
MIE
MXC
0
0
0
0
5EH R/W 00H
MSTA
0
0
0
0
0
MAC
0
TOUT
5FH
R 00H
MCONF
0
0
0
0
0
0
0
TOUT
5FH
W 00H
1
0
Interrupt, General Configuration Registers
NAME
7
6
5
4
ISTA
0
0
ST
CIC
AUX TRAN MOS
0
60H
R 00H
MASK
1
1
ST
CIC
AUX TRAN MOS
1
60H
W FFH
AUXI
0
0
EAW WOV
TIN
0
0
0
61H
R 00H
AUXM
1
1
EAW WOV
TIN
1
1
1
61H
W FFH
MODE1
0
0
0
62H
R/W 00H
MODE2
0
0
0
63H
R/W 00H
ID
0
0
DESIGN
64H
R 01H
SRES
RES_
CI
0
0
64H
W 00H
TIMR
TMD
0
65H
R/W 00H
0
3
2
WTC1 WTC2 CFS RSS2 RSS1
0
RES_
MON
INT_
POL
0
PPSDX
RES_ RES_ RES_
IOM
TR RSTO
CNT
reserved
Data Sheet
0
125
ADDR R/WRES
66H6FH
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
4.1
Transceiver and C/I Registers
4.1.1
TR_MODE2 - Transceiver Mode Register 2
Value after reset: 00H
7
TR_
MODE2
0
0
0
0
0
0
DIM2
DIM1
DIM0
RD/WR (22)
DIM2-0 ... Digital Interface Modes
These bits define the characteristics of the IOM Data Ports (DU, DD). The DIM0 bit
enables/disables the collission detection. The DIM1 bit enables/disables the TIC bus
access. The effect of the individual DIM bits is summarized in the table below.
DIM2
DIM1 DIM0 Characteristics
0
0
Transparent D-channel, the collission detection is disabled
0
1
Stop/go bit evaluated for D-channel access handling
0
0
Last octet of IOM channel 2 used for TIC bus access
0
1
TIC bus access is disabled
1
x
x
Reserved
Example: ’010’ selects transparent D-channel, collision detection disabled and TIC bus
disabled.
Data Sheet
126
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
4.1.2
CIR0 - Command/Indication Receive 0
Value after reset: F3H
7
CIR0
0
CODR0
CIC0
CIC1
S/G
BAS
RD (2E)
CODR0 ... C/I Code 0 Receive
Value of the received Command/Indication code. A C/I-code is loaded in CODR0 only
after being the same in two consecutive IOM-frames and the previous code has been
read from CIR0.
CIC0 ... C/I Code 0 Change
A change in the received Command/Indication code has been recognized. This bit is set
only when a new code is detected in two consecutive IOM-frames. It is reset by a read
of CIR0.
CIC1 ... C/I Code 1 Change
A change in the received Command/Indication code in IOM-channel 1 has been
recognized. This bit is set when a new code is detected in one IOM-frame. It is reset by
a read of CIR0.
S/G ... Stop/Go Bit Monitoring
Indicates the availability of the upstream D-channel on the S/T interface.
1: Stop
0: Go
BAS ... Bus Access Status
Indicates the state of the TIC-bus:
0: the SBCX-X itself occupies the D- and C/I-channel
1: another device occupies the D- and C/I-channel
Note: The CODR0 bits are updated every time a new C/I-code is detected in two
consecutive IOM-frames. If several consecutive valid new codes are detected and
CIR0 is not read, only the first and the last C/I code is made available in CIR0 at
the first and second read of that register, respectively.
Data Sheet
127
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
4.1.3
CIX0 - Command/Indication Transmit 0
Value after reset: FEH
7
CIX0
0
CODX0
TBA2 TBA1 TBA0
BAC
WR (2E)
CODX0 ... C/I-Code 0 Transmit
Code to be transmitted in the C/I-channel 0.
The code is only transmitted if the TIC bus is occupied. If TIC bus is enabled but
occupied by another device, only “1s” are transmitted.
TBA2-0 ... TIC Bus Address
Defines the individual address for the SBCX-X on the IOM bus.
This address is used to access the C/I- and D-channel on the IOM interface.
Note: If only one device is liable to transmit in the C/I- and D-channels of the IOM it
should always be given the address value ’7’.
BAC ... Bus Access Control
Only valid if the TIC-bus feature is enabled (MODED.DIM2-0).
If this bit is set, the SBCX-X will try to access the TIC-bus to occupy the C/I-channel even
if no D-channel frame has to be transmitted. It should be reset when the access has been
completed to grant a similar access to other devices transmitting in that IOM-channel.
Note: Access is always granted by default to the SBCX-X with TIC-Bus Address
(TBA2-0, STCR register) ’7’, which has the lowest priority in a bus configuration.
4.1.4
CIR1 - Command/Indication Receive 1
Value after reset: FEH
7
CIR1
0
CODR1
CICW
CI1E
RD (2F)
CODR1 ... C/I-Code 1 Receive
CICW, CI1E ... C/I-Channel Width, C/I-Channel 1 Interrupt Enable
These two bits contain the read back values from CIX1 register (see below).
Data Sheet
128
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
4.1.5
CIX1 - Command/Indication Transmit 1
Value after reset: FEH
7
0
CIX1
CODX1
CICW
CI1E
WR (2F)
CODX1 ... C/I-Code 1 Transmit
Bits 7-2 of C/I-channel 1 timeslot.
CICW... C/I-Channel Width
CICW selects between a 4 bit (’0’) and 6 bit (’1’) C/I1 channel width.
The C/I1 handler always reads and writes 6-bit values but if 4-bit is selected, the higher
two bits are ignored for interrupt generation. However in write direction the full CODX1
code is transmitted, i.e. the host must write the higher two bits to “1”.
CI1E ... C/I-Channel 1 Interrupt Enable
Interrupt generation ISTA.CIC of CIR0.CIC1 is enabled (1) or masked (0).
4.1.6
TR_CONF0 - Transceiver Configuration Register 0
Value after reset: 01H
7
TR_
CONF0
0
DIS_
TR
BUS
EN_
ICV
0
L1SW
0
EXLP
LDD
RD/WR (30)
DIS_TR ... Disable Transceiver
Setting DIS_TR to “1” disables the transceiver. In order to reenable the transceiver
again, a transceiver reset must be issued (SRES.RES_TR = 1). The transceiver must
not be reenabled by setting DIS_TR from “1” to “0”.
For general information please refer to Chapter 3.3.9.
BUS ... Point-to-Point / Bus Selection (NT/LT-S/Int. NT mode only)
0: Adaptive Timing (Point-to-Point, extended passive bus).
1: Fixed Timing (Short passive bus).
Data Sheet
129
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
EN_ICV ... Enable Illegal Code Violation
0: normal operation
1: ICV enabled. The receipt of at least one illegal code violation within one multiframe is
indicated by the C/I indication ’1011’ (CVR) in two consecutive IOM frames.
L1SW ... Enable Layer 1 State Machine in Software
0: Layer 1 state machine of the SBCX-X is used
1: Layer 1 state machine is disabled. The functionality can be realized in software.
The commands can be written to register TR_CMD and the status can be read from
TR_STA.
For general information please refer to Chapter 3.5.
EXLP ... External loop
In case the analog loopback is activated with C/I = ARL or with the LP_A bit in the
TR_CMD register the loop is a
0: internal loop next to the line pins
1: external loop which has to be closed between SR1/2 and SX1/SX2
Note:The external loop is only useful if bit DIS_TX of register TR_CONF2 is set to ’0’.
For general information please refer to Chapter 3.3.10.
LDD ... Level Detection Discard
0: Automatic clock generation after detection of any signal on the line in
power down state
1: No clock generation after detection of any signal on the line in power down state
Note: If an interrupt by the level detect circuitry is generated, the microcontroller has to
set this bit to ’0’ for an activation of the S/T interface.
For general information please refer to Chapter 3.3.8 and Chapter 3.7.6.
Data Sheet
130
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
4.1.7
TR_CONF1 - Transceiver Configuration Register 1
Value after reset: 0xH
7
TR_
CONF1
0
0
RPLL_ EN_
ADJ SFSC
0
0
x
x
x
RD/WR (31)
RPLL_ADJ ... Receive PLL Adjustment
0: DPLL tracking step is 0.5 XTAL period per S-frame
1: DPLL tracking step is 1 XTAL period per S-frame
EN_SFSC ... Enable Short FSC
0: No short FSC is generated
1: A short FSC is generated once per multiframe (every 40th IOM frame)
x ... Undefined
The value of these bits depends on the selected mode. It is important to note that these
bits must not be overwritten to a different value when accessing this register.
4.1.8
TR_CONF2 - Transmitter Configuration Register 2
Value after reset: 80H
7
TR_
CONF2
0
DIS_
TX
PDS
0
RLP
0
0
SGP
SGD
RD/WR (32)
DIS_TX ... Disable Line Driver
0: Transmitter is enabled
1: Transmitter is disabled
For general information please refer to Chapter 3.3.9.
Data Sheet
131
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
PDS ... Phase Deviation Select
Defines the phase deviation of the S-transmitter.
0: The phase deviation is 2 S-bits minus 7 oscillator periods plus analog delay plus
delay of the external circuitry.
1: The phase deviation is 2 S-bits minus 9 oscillator periods plus analog delay plus
delay of the external circuitry.
For general information please refer to Chapter 3.3.7.
RLP ... Remote Line Loop
0: Remote Line Loop open
1: Remote Line Loop closed
For general information please refer to Chapter 3.3.10.
SGP ... Stop/Go Bit Polarity
Defines the polarity of the S/G bit output on pin SGO.
0: low active (SGO=0 means “go”; SGO=1 means “stop”)
1: high active (SGO=1 means “go”; SGO=0 means “stop”)
SGD ... Stop/Go Bit Duration
Defines the duration of the S/G bit output on pin SGO.
0: active during the D-channel timeslot
1: active during the whole corresponding IOM frame (starts and ends with the beginning
of the D-channel timeslot)
Note: Outside the active window of SGO (defined in SGD) the level on pin SGO remains
in the “stop”-state depending on the selected polarity (SGP), i.e. SGO=1 (if
SGP=0) or SGO=0 (if SGP=1) outside the active window.
Data Sheet
132
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
4.1.9
TR_STA - Transceiver Status Register
Value after reset: 00H
7
TR_
STA
0
RINF
SLIP
ICV
0
FSYN
0
LD
RD (33)
Important: This register is used only if the Layer 1 state machine of the SBCX-X is
disabled (TR_CONF0.L1SW = 1) and implemented in software! With the SBCX-X layer
1 state machine enabled, the signals from this register are automatically evaluated.
For general information please refer to Chapter 3.5.
RINF ... Receiver INFO
00: Received INFO 0
01: Received any signal except INFO 0,2,3,4
10: Reserved (NT mode) or INFO 2 (TE mode)
11: Received INFO 3 (NT mode) or INFO 4 (TE mode)
SLIP ... SLIP Detected
A ’1’ in this bit position indicates that a SLIP is detected in the receive or transmit path.
ICV ... Illegal Code Violation
0: No illegal code violation is detected
1: Illegal code violation (ANSI T1.605) in data stream is detected
FSYN ... Frame Synchronization State
0: The S/T receiver is not synchronized
1: The S/T receiver has synchronized to the framing bit F
LD ... Level Detection
0: No receive signal has been detected on the line.
1: Any receive signal has been detected on the line.
Data Sheet
133
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
4.1.10
TR_CMD - Transceiver Command Register
Value after reset: 08H
7
TR_
CMD
0
XINF
DPRIO TDDIS
PD
LP_A
0
RD/WR (34)
Important: This register is only writable if the Layer 1 state machine of the SBCX-X is
disabled (TR_CONF0.L1SW = 1)! With the SBCX-X layer 1 state machine enabled, the
signals from this register are automatically generated, but nevertheless this register can
always be read.
DPRIO can also be written in intelligent NT mode.
XINF ... Transmit INFO
000: Transmit INFO 0
001: reserved
010: Transmit INFO 1 (TE mode) or INFO 2 (NT mode)
011: Transmit INFO 3 (TE mode) or INFO 4 (NT mode)
100: Send continous pulses at 192 kbit/s alternating or 96 kHz rectangular, respectively
(SCP)
101: Send single pulses at 4 kbit/s with alternating polarity corresponding to 2 kHz
fundamental mode (SSP)
11x: reserved
DPRIO ... D-Channel Priority (always writable in Int. NT mode)
0: Priority Class 1 for D channel access on IOM (Int. NT) or on S interface (TE/LT-T)
1: Priority Class 2 for D channel access on IOM (Int. NT) or on S interface (TE/LT-T)
TDDIS ... Transmit Data Disabled (TE mode)
0: The B and D channel data are transparently transmitted on the S/T interface if INFO 3
is being transmitted
1: The B and D channel data are set to logical ’1’ on the S/T interface if INFO 3 is being
transmitted
PD ... Power Down
0: The transceiver is set to operational mode
1: The transceiver is set to power down mode
For general information please refer to Chapter 3.5.1.2.
Data Sheet
134
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
LP_A ... Loop Analog
The setting of this bit corresponds to the C/I command ARL.
0: Analog loop is open
1: Analog loop is closed internally or externally according to the EXLP bit in the
TR_CONF0 register
For general information please refer to Chapter 3.3.10.
4.1.11
SQRR1 - S/Q-Channel Receive Register 1
Value after reset: 40H
7
SQRR
MSYN MFEN
0
0
0
SQR11 SQR12 SQR13 SQR14
RD (35)
For general information please refer to Chapter 3.3.2.
MSYN ... Multiframe Synchronization State
0: The S/T receiver has not synchronized to the received FA and M bits
1: The S/T receiver has synchronized to the received FA and M bits
MFEN ... Multiframe Enable
Read-back of the MFEN bit of the SQXR register
SQR11-14 ... Received S Bits
Received S bits in frames 1, 6, 11 and 16 (TE mode)
received Q bits in frames 1, 6, 11 and 16 (NT mode).
Data Sheet
135
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
4.1.12
SQXR1- S/Q-Channel TX Register 1
Value after reset: 4FH
7
SQXR1
0
0
MFEN
0
0
SQX11 SQX12 SQX13 SQX14
WR (35)
MFEN ... Multiframe Enable
Used to enable or disable the multiframe structure (see Chapter 3.3.2)
0: S/T multiframe is disabled
1: S/T multiframe is enabled
Readback value in SQRR1.
SQX11-14 ... Transmitted S/Q Bits
Transmitted Q bits (FA bit position) in frames 1, 6, 11 and 16 (TE mode),
transmitted S bits (FA bit position) in frames 1, 6, 11 and 16 (NT mode).
4.1.13
SQRR2 - S/Q-Channel Receive Register 2
Value after reset: 00H
7
SQRR2
0
SQR21 SQR22 SQR23 SQR24 SQR31 SQR32 SQR33 SQR34
RD (36)
SQR21-24, SQR31-34... Received S Bits (TE mode only)
Received S bits in frames 2, 7, 12 and 17 (SQR21-24, subchannel 2),
and in frames 3, 8, 13 and 18 (SQR31-34, subchannel 3).
Data Sheet
136
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
4.1.14
SQXR2 - S/Q-Channel TX Register 2
Value after reset: 00H
7
SQXR2
0
SQX21 SQX22 SQX23 SQX24 SQX31 SQX32 SQX33 SQX34
WR (36)
SQX21-24, SQX31-34... Transmitted S Bits (NT mode only)
Transmitted S bits in frames 2, 7, 12 and 17 (SQX21-24, subchannel 2),
and in frames 3, 8, 13 and 18 (SQX31-34, subchannel 3).
4.1.15
SQRR3 - S/Q-Channel Receive Register 3
Value after reset: 00H
7
SQRR3
0
SQR41 SQR42 SQR43 SQR44 SQR51 SQR52 SQR53 SQR54
RD (37)
SQR41-44, SQR51-54... Received S Bits (TE mode only)
Received S bits in frames 4, 9, 14 and 19 (SQR41-44, subchannel 4),
and in frames 5, 10, 15 and 20 (SQR51-54, subchannel 5).
4.1.16
SQXR3 - S/Q-Channel TX Register 3
Value after reset: 00H
7
SQXR3
0
SQX41 SQX42 SQX43 SQX44 SQX51 SQX52 SQX53 SQX54
WR (37)
SQX41-44, SQX51-54... Transmitted S Bits (NT mode only)
Transmitted S bits in frames 4, 9, 14 and 19 (SQX41-44, subchannel 4),
and in frames 5, 10, 15 and 20 (SQX51-54, subchannel 5).
4.1.17
ISTATR - Interrupt Status Register Transceiver
Value after reset: 00H
Data Sheet
137
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
7
ISTATR
0
0
x
x
x
LD
RIC
SQC
SQW
RD (38)
For all interrupts in the ISTATR register the following logical states are defined:
0: Interrupt is not acitvated
1: Interrupt is acitvated
x ... Reserved
Bits set to “1” in this bit position must be ignored.
LD ... Level Detection
Any receive signal has been detected on the line. This bit is set to “1” (i.e. an interrupt is
generated if not masked) as long as any receiver signal is detected on the line.
RIC ... Receiver INFO Change
RIC is activated if one of the TR_STA bits RINF or ICV has changed. This bit is reset by
reading the TR_STA register.
SQC ... S/Q-Channel Change
A change in the received S-channel (TE) or Q-channel (NT) has been detected. The new
code can be read from the SQRxx bits of registers SQRR1-3 within the duration of the
next multiframe (5 ms). This bit is reset by a read access to the corresponding SQRRx
register.
SQW ... S/Q-Channel Writable
The S/Q channel data for the next multiframe is writable.
The register for the Q (S) bits to be transmitted (received) has to be written (read) within
the duration of the next multiframe (5 ms). This bit is reset by writing register SQXRx.
4.1.18
MASKTR - Mask Transceiver Interrupt
Value after reset: FFH
7
MASKTR
Data Sheet
0
1
1
1
1
LD
138
RIC
SQC
SQW
RD/WR (39)
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
The transceiver interrupts LD, RIC, SQC and SQW are enabled (0) or disabled (1).
4.1.19
TR_MODE - Transceiver Mode Register 1
Value after reset: 000000xxB
7
TR_
MODE
0
0
0
0
0
DCH_ MODE MODE MODE RD/WR (3A)
INH
2
1
0
For general information please refer also to Chapter 3.7.5.4.
DCH_INH ... D-Channel Inhibit (NT, LT-S, Int. NT mode only)
Setting this bit to ’1’ has the effect that the S-transceiver blocks the access to the
D-channel on S by inverting the E-bits.
The pin DCI, which performs the same funtion, is internally combined (EXOR-logic) with
DCH_INH, i.e. either setting the bit to ’1’ or pulling the pin high will block the D-channel
access, however activating pin and bit simultaneously must not be done.
If this bit was not set before, reading DCH_INH reflects the status on pin DCI, i.e. the
D-channel inhibit function is controlled by the pin. If the function should be controlled by
programming DCH_INH, the pin DCI must be strapped to “0” or “1”.
MODE2-0 ... Transceiver Mode
000:
001:
010:
011:
110:
111:
100:
101:
TE mode
LT-T mode
NT mode
LT-S mode
Intelligent NT mode (with NT state machine)
Intelligent NT mode (with LT-S state machine)
reserved
reserved
Note: The three modes TE, LT-T and LT-S can be selected by pin strapping (reset
values for bits TR_MODE.MODE0,1 loaded from pins MODE0,1), all other modes
are programmable only.
Data Sheet
139
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
4.2
Auxiliary Interface Registers
4.2.1
ACFG1 - Auxiliary Configuration Register 1
Value after reset: 00H
7
ACFG1
0
0
0
0
0
0
OD2
OD1
OD0
RD/WR (3C)
For general information please refer to Chapter 3.8.
OD2-0 ... Output Driver Select for AUX2 - AUX0
0: output is open drain
1: output is push/pull
Note: The ODx configuration is only valid if the corresponding output is enabled in the
AOE register.
AUX0-2 are only available in TE and Int. NT mode and not in all other modes (used
as channel select).
4.2.2
ACFG2 - Auxiliary Configuration Register 2
Value after reset: 00H
7
ACFG2
0
0
0
0
0
ACL
LED
0
0
RD/WR (3D)
ACL ... ACL Function Select
0: Pin ACL automatically indicates the S-bus activation status by a LOW level.
1: The output state of ACL is programmable by the host in bit LED.
Note: An LED with preresistance may directly be connected to ACL.
LED ... LED Control
If enabled (ACL=1) the LED with preresistance connected between VDD and ACL is
switched ...
0: Off (high level on pin ACL)
1: On (low level on pin ACL)
Data Sheet
140
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
4.2.3
AOE - Auxiliary Output Enable Register
Value after reset: FFH
7
AOE
0
1
1
1
1
1
OE2
OE1
OE0
RD/WR (3E)
For general information please refer to Chapter 3.8.
OE2-0 ... Output Enable for AUX2 - AUX0
0: Pin AUX2-0 is configured as output. The value of the corresponding bit in the ATX
register is driven on AUX2-0.
1: Pin AUX2-0 is configured as input. The value of the corresponding bit can be read from
the ARX register.
Note: In NT and LT modes the pins AUX0-2 are not available as I/O pins.
4.2.4
ARX - Auxiliary Interface Receive Register
Value after reset: (not defined)
7
ARX
0
-
-
-
-
-
AR2
AR1
AR0
RD (3F)
AR2-0 ... Auxiliary Receive
The value of AR2-0 always reflects the level at pin AUX2-0 at the time when ARX is read
by the host even if a pin is configured as output.
Note: In NT and LT modes the pins AUX0-2 are not available as I/O pins.
Data Sheet
141
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SBCX-X
PEB 3081
Detailed Register Description
4.2.5
ATX - Auxiliary Interface Transmit Register
Value after reset: 00H
7
ATX
0
0
0
0
0
0
AT2
AT1
AT0
WR (3F)
AT2-0 ... Auxiliary Transmit
A ’0’ or ’1’ in AT2-0 will drive a low or a high level at pin AUX2-0 if the corresponding
output is enabled in the AOE register.
Note: In NT and LT modes the pins AUX0-2 are not available as I/O pins.
4.3
IOM-2 and MONITOR Handler
4.3.1
CDAxy - Controller Data Access Register xy
7
CDAxy
0
Controller Data Access Register
RD/WR
(40-43)
Data registers CDAxy which can be accessed from the controller.
Register
Register Address
Value after Reset
CDA10
40H
FFH
CDA11
41H
FFH
CDA20
42H
FFH
CDA21
43H
FFH
Data Sheet
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SBCX-X
PEB 3081
Detailed Register Description
4.3.2
XXX_TSDPxy - Time Slot and Data Port Selection for CHxy
7
XXX_
TSDPxy
0
DPS
0
0
TSS
RD/WR
(44-4D)
Register
Register
Address
Value after Reset
CDA_TSDP10
44H
00H ( = output on B1-DD)
CDA_TSDP11
45H
01H ( = output on B2-DD)
CDA_TSDP20
46H
80H ( = output on B1-DU)
CDA_TSDP21
47H
81H ( = output on B2-DU)
TR_TSDP_BC1
4CH
00H ( = transceiver output on B1-DD), see note
TR_TSDP_BC2
4DH
01H ( = transceiver output on B2-DD), see note
This register determines the time slots and the data ports on the IOM-2 interface for the
data channels ’xy’ of the functional units ’XXX’ which are Controller Data Access (CDA)
and Transceiver (TR). The position of B-channel data from the S-interface is
programmed in TR_TSDP_BC1 and TR_TSDP_BC2.
DPS ... Data Port Selection
0:The data channel xy of the functional unit XXX is output on DD.
The data channel xy of the functional unit XXX is input from DU.
1:The data channel xy of the functional unit XXX is output on DU.
The data channel xy of the functional unit XXX is input from DD.
Note: For the CDA (controller data access) data the input is determined by the
CDA_CRx.SWAP bit. If SWAP = ’0’ the input for the CDAxy data is vice versa to
the output setting for CDAxy. If the SWAP = ’1’ the input from CDAx0 is vice versa
to the output setting of CDAx1 and the input from CDAx1 is vice versa to the output
setting of CDAx0. See controller data access description in Chapter 3.7.1.1.
TSS ... Timeslot Selection
Selects one of 32 timeslots (0...31) on the IOM-2 interface for the data channels.
Note: The reset values for TR_TSDP_BC1/2 are depending on the mode selection
(MODE0/1) and channel selection (CH0-2).
Data Sheet
143
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
4.3.3
CDAx_CR - Control Register Controller Data Access CH1x
7
CDAx_
CR
0
0
0
EN_
TBM
EN_I1 EN_I0 EN_O EN_O SWA
1
0
P
RD/WR
(4E-4F)
Register
Register Address
Value after Reset
CDA1_CR
4EH
00H
CDA2_CR
4FH
00H
For general information please refer to Chapter 3.7.1.1.
EN_TBM ... Enable TIC Bus Monitoring
0: The TIC bus monitoring is disabled
1: The TIC bus monitoring with the CDAx0 register is enabled. The TSDPx0 register
must be set to 08H for monitoring from DU or 88H for monitoring from DD, respectively.
(This selection is only valid if IOM_CR.TIC_DIS = 0).
EN_I1, EN_I0 ... Enable Input CDAx0, CDAx1
0: The input of the CDAx0, CDAx1 register is disabled
1: The input of the CDAx0, CDAx1 register is enabled
EN_O1, EN_O0 ... Enable Output CDAx0, CDAx1
0: The output of the CDAx0, CDAx1 register is disabled
1: The output of the CDAx0, CDAx1 register is enabled
SWAP ... Swap Inputs
0: The time slot and data port for the input of the CDAxy register is defined by its own
TSDPxy register. The data port for the CDAxy input is vice versa to the output setting
for CDAxy.
1: The input (time slot and data port) of the CDAx0 is defined by the TSDP register of
CDAx1 and the input of CDAx1 is defined by the TSDP register of CDAx0. The data
port for the CDAx0 input is vice versa to the output setting for CDAx1. The data port
for the CDAx1 input is vice versa to the output setting for CDAx0. The input definition
for time slot and data port CDAx0 are thus swapped to CDAx1 and for CDAx1 to
CDAx0. The outputs are not affected by the SWAP bit.
Data Sheet
144
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
4.3.4
TR_CR - Control Register Transceiver Data (IOM_CR.CI_CS=0)
Value after reset: F8H
7
TR_CR
0
EN_
D
EN_
B2R
EN_
B1R
EN_
B2X
EN_
B1X
CS2-0
RD/WR (50)
Read and write access to this register is only possible if IOM_CR.CI_CS = 0.
EN_D ... Enable Transceiver D-Channel Data
EN_B2R ... Enable Transceiver B2 Receive Data
EN_B1R ... Enable Transceiver B1 Receive Data
EN_B2X ... Enable Transceiver B2 Transmit Data
EN_B1X ... Enable Transceiver B1 Transmit Data
This register is used to individually enable/disable the D-channel (both RX and TX
direction) and the receive/transmit paths for the B-channels of the S-transceiver.
0: The corresponding data path to the transceiver is disabled.
1: The corresponding data path to the transceiver is enabled.
Note: “Receive Data” refers to the data which is received on the S interface and
forwarded to IOM-2. “Transmit data” refers to the data which is coming from
IOM-2 and transmitted on the S interface.
CS2-0 ... Channel Select for Transceiver D-channel
This register is used to select one of eight IOM channels to which the transceiver
D-channel data is related to.
Note: The reset value is determined by the channel select pins CH2-0 which are directly
mapped to CS2-0. It should be noted that writing TR_CR.CS2-0 will also write to
TRC_CR.CS2-0 and therefore modify the channel selection for the transceiver
C/I0 data.
Data Sheet
145
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
4.3.5
TRC_CR - Control Register Transceiver C/I0 (IOM_CR.CI_CS=1)
Value after reset: 00H
7
TRC_CR
0
0
0
0
0
0
CS2-0
RD/WR (50)
Write access to this register is possible if IOM_CR.CI_CS = 0 or IOM_CR.CI_CS = 1.
Read access to this register is possible only if IOM_CR.CI_CS = 1.
CS2-0 ... Channel Select for the Transceiver C/I0 Channel
This register is used to select one of eight IOM channels to which the transceiver C/I0
channel data is related to. The reset value is determined by the channel select pins CH20 and the MODE2-bit.
4.3.6
DCI_CR - Control Register for CI1 Handler (IOM_CR.CI_CS=0)
Value after reset: 80H
7
DCI_CR
DPS_
CI1
0
EN_
CI1
0
0
0
0
0
0
RD/WR (53)
Read and write access to this register is only possible if IOM_CR.CI_CS = 0. It should
be noted that a writing the DCI_CR register will also perform a write access to DCIC_CR,
i.e. the lower 3 bits of DCI_CR will be written to DCIC_CR.CS2-0.
DPS_CI1 ... Data Port Selection CI1 Handler Data
0: The CI1 handler data is output on DD and input from DU
1: The CI1 handler data is output on DU and input from DD
EN_CI1 ... Enable CI1 Handler Data
0: CI1 handler data access is disabled
1: CI1 handler data access is enabled
Note: The timeslot for the C/I1 handler cannot be programmed but is fixed to IOM
channel 1.
Data Sheet
146
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
4.3.7
DCIC_CR - Control Register for CI0 Handler (IOM_CR.CI_CS=1)
Value after reset: 00H
7
DCIC_CR
0
0
0
0
0
0
CS2-0
RD/WR (53)
Write access to this register is possible if IOM_CR.CI_CS = 0 or IOM_CR.CI_CS = 1.
Read access to this register is possible only if IOM_CR.CI_CS = 1.
CS2-0 ... Channel Select for C/I0 Handler
This register is used to select one of eight IOM channels. If enabled, the data of the
C/I0 handler is connected to the corresponding C/I0 timeslot of that IOM channel.
The reset value is determined by the channel select pins CH2-0 which are mapped to
CS2-0.
Data Sheet
147
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
4.3.8
MON_CR - Control Register Monitor Data
Value after reset: 40H
7
MON_CR
0
DPS
EN_
MON
0
0
0
CS2-0
RD/WR (54)
For general information please refer to Chapter 3.7.3.
DPS ... Data Port Selection
0: The Monitor data is output on DD and input from DU
1: The Monitor data is output on DU and input from DD
EN_MON ... Enable Output
0: The Monitor data input and output is disabled
1: The Monitor data input and output is enabled
CS2-0 ... MONITOR Channel Selection
000: The MONITOR data is input/output on MON0 (3rd timeslot on IOM-2)
001: The MONITOR data is input/output on MON1 (7th timeslot on IOM-2)
010: The MONITOR data is input/output on MON2 (11th timeslot on IOM-2)
:
111: The MONITOR data is input/output on MON7 (31st timeslot on IOM-2)
Note: The reset value is determined by the channel select pins CH2-0 which are directly
mapped to CS2-0.
Data Sheet
148
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
4.3.9
SDSx_CR - Control Register Serial Data Strobe x
Value after reset: 00H
7
0
SDSx_CR ENS_ ENS_ ENS_
TSS TSS+1 TSS+3
TSS
RD/WR
(55-56)
Register
Register Address
Value after Reset
SDS1_CR
55H
00H
SDS2_CR
56H
00H
This register is used to select position and length of the strobe signals. The length can
be any combination of two 8-bit timeslot (ENS_TSS, ENS_TSS+1) and one 2-bit timeslot
(ENS_TSS+3).
For general information please refer to Chapter 3.7.2 and Chapter 3.7.2.2.
ENS_TSS ... Enable Serial Data Strobe of timeslot TSS
ENS_TSS+1 ... Enable Serial Data Strobe of timeslot TSS+1
0: The serial data strobe signal SDSx is inactive during TSS, TSS+1
1: The serial data strobe signal SDSx is active during TSS, TSS+1
ENS_TSS+3 ... Enable Serial Data Strobe of timeslot TSS+3 (D-Channel)
0: The serial data strobe signal SDSx is inactive during the D-channel (bit7, 6) of TSS+3
1: The serial data strobe signal SDSx is active during the D-channel (bit7, 6) of TSS+3
TSS ... Timeslot Selection
Selects one of 32 timeslots on the IOM-2 interface (with respect to FSC) during which
SDSx is active high or provides a strobed BCL clock output (see SDS_CONF.SDS1/
2_BCL). The data strobe signal allows standard data devices to access a programmable
channel.
Data Sheet
149
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
4.3.10
IOM_CR - Control Register IOM Data
Value after reset: 08H
7
IOM_CR
0
SPU
DIS_ CI_CS TIC_
AW
DIS
EN_
BCL
CLKM DIS_
OD
DIS_
IOM
RD/WR (57)
SPU ... Software Power Up
0: The DU line is normally used for transmitting data
1: Setting this bit to ’1’ will pull the DU line to low. This will enforce connected layer 1
devices to deliver IOM-clocking.
After a subsequent ISTA.CIC-interrupt (C/I-code change) and reception of the C/I-code
”PU” (Power Up indication in TE-mode) the microcontroller writes an AR or TIM
command as C/I-code in the CIX0-register, resets the SPU bit and waits for the following
CIC-interrupt.
For general information please refer to Chapter 3.7.6.
DIS_AW ... Disable Asynchronous Awake (for NT, LT-S and Int. NT mode)
Setting this bit to “1” disables the Asynchronous Awake function of the transceiver.
CI_CS ... C/I Channel Selection
The channel selection for D-channel and C/I-channel is done in the channel select bits
CH2-0 of register TR_CR (for the transceiver) and DCI_CR (for the C/I-channel
controller).
0: A write access to CS2-0 has effect on the configuration of D- and C/I-channel,
whereas a read access delivers the D-channel configuration only.
1: A write access to CS2-0 has effect on the configuration of the C/I-channel only,
whereas a read access delivers the C/I-channel configuration only.
TIC_DIS ... TIC Bus Disable
0: The last octet of IOM channel 2 (12th timeslot) is used as TIC bus (in a frame timing
mode with 12 timeslots only).
1: The TIC bus is disabled. The last octet of the last IOM time slot (TS 11) can be used
as every time slot.
Data Sheet
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2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
EN_BCL ... Enable Bit Clock BCL/SCLK
0: The BCL/SCLK clock is disabled
1: The BCL/SCLK clock is enabled.
CLKM ... Clock Mode
If the transceiver is disabled (DIS_TR = ’1’) or in NT, LT-S and Int. NT mode the DCL
from the IOM-2 interface is an input.
0: A double bit clock is connected to DCL
1: A single bit clock is connected to DCL
For general information please refer to Chapter 3.7.
DIS_OD ... Disable Open Drain Drivers
0: DU/DD are open drain drivers
1: DU/DD are push pull drivers
DIS_IOM ... Disable IOM
DIS_IOM should be set to ’1’ if external devices connected to the IOM interface should
be “disconnected“ e.g. for power saving purposes or for not disturbing the internal IOM
connection. However, the SBCX-X internal operation is independent of the DIS_IOM bit.
0: The IOM interface is enabled
1: The IOM interface is disabled. The FSC, DCL clock outputs have high impedance;
clock inputs are active; DU, DD data line inputs are switched off and outputs have high
impedance; except in TE/LT-T mode the DU line is input (“0”-level causes activation), so
the DU pin must be terminated (pull up resistor).
Data Sheet
151
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
4.3.11
STI - Synchronous Transfer Interrupt
Value after reset: 00H
7
STI
0
STOV STOV STOV STOV
21
20
11
10
STI
21
STI
20
STI
11
STI
10
RD (58)
For all interrupts in the STI register the following logical states are applied:
0: Interrupt is not activated
1: Interrupt is activated
The interrupts are automatically reset by reading the STI register. For general
information please refer to Chapter 3.7.1.1.
STOVxy ... Synchronous Transfer Overflow Interrupt
Enabled STOV interrupts for a certain STIxy interrupt are generated when the STIxy has
not been acknowledged in time via the ACKxy bit in the ASTI register. This must be one
(for DPS=’0’) or zero (for DPS=’1’) BCL clocks before the time slot which is selected for
the STOV.
STIxy ... Synchronous Transfer Interrupt
Depending on the DPS bit in the corresponding TSDPxy register the Synchronous
Transfer Interrupt STIxy is generated two (for DPS=’0’) or one (for DPS=’1’) BCL clock
after the selected time slot (TSDPxy.TSS).
Note: STOVxy and ACKxy are useful for synchronizing microcontroller accesses and
receive/transmit operations. One BCL clock is equivalent to two DCL clock cycles.
Data Sheet
152
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
4.3.12
ASTI - Acknowledge Synchronous Transfer Interrupt
Value after reset: 00H
7
ASTI
0
0
0
0
0
ACK
21
ACK
20
ACK
11
ACK
10
WR (58)
For general information please refer to Chapter 3.7.1.1.
ACKxy ... Acknowledge Synchronous Transfer Interrupt
After an STIxy interrupt the microcontroller has to acknowledge the interrupt by setting
the corresponding ACKxy bit to “1”.
4.3.13
MSTI - Mask Synchronous Transfer Interrupt
Value after reset: FFH
7
MSTI
STOV STOV STOV STOV
21
20
11
10
0
STI
21
STI
20
STI
11
STI
10
RD/WR (59)
For the MSTI register the following logical states are applied:
0: Interrupt is not masked
1: Interrupt is masked
For general information please refer to Chapter 3.7.1.1.
STOVxy ... Synchronous Transfer Overflow for STIxy
Mask bits for the corresponding STOVxy interrupt bits.
STIxy ... Synchronous Transfer Interrupt xy
Mask bits for the corresponding STIxy interrupt bits.
Data Sheet
153
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
4.3.14
SDS_CONF - Configuration Register for Serial Data Strobes
Value after reset: 00H
7
SDS_
CONF
0
0
0
0
0
DIOM_ DIOM_ SDS2_ SDS1_ RD/WR (5A)
INV
SDS BCL
BCL
For general information on SDS1/2_BCL please refer to Chapter 3.7.2.
DIOM_INV ... DU/DD on IOM Timeslot Inverted
0: DU/DD are active during SDS1 HIGH phase and inactive during the LOW phase.
1: DU/DD are active during SDS1 LOW phase and inactive during the HIGH phase.
This bit has only effect if DIOM_SDS is set to ’1’ otherwise DIOM_INV is don’t care.
DIOM_SDS ... DU/DD on IOM Controlled via SDS1
0: The pin SDS1 and its configuration settings are used for serial data strobe only. The
IOM-2 data lines are not affected.
1: The DU/DD lines are deactivated during the High/Low phase (selected via
DIOM_INV) of the SDS1 signal. The SDS1 timeslot is selected in SDS1_CR.
SDSx_BCL ... Enable IOM Bit Clock for SDSx
0: The serial data strobe is generated in the programmed timeslot.
1: The IOM bit clock is generated in the programmed timeslot.
Data Sheet
154
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
4.3.15
MCDA - Monitoring CDA Bits
Value after reset: FFH
7
MCDA
0
MCDA21
Bit7
Bit6
MCDA20
Bit7
Bit6
MCDA11
Bit7
Bit6
MCDA10
Bit7
RD (5B)
Bit6
MCDAxy ... Monitoring CDAxy Bits
Bit 7 and Bit 6 of the CDAxy registers are mapped into the MCDA register.
This can be used for monitoring the D-channel bits on DU and DD and the ’Echo bits’ on
the TIC bus with the same register
4.3.16
MOR - MONITOR Receive Channel
Value after reset: FFH
7
MOR
0
Monitor Receiver Data
RD (5C)
Contains the MONITOR data received in the IOM-2 MONITOR channel according to the
MONITOR channel protocol. The MONITOR channel (0-7) can be selected by setting the
monitor channel select bit MON_CR.MCS.
4.3.17
MOX - MONITOR Transmit Channel
Value after reset: FFH
7
MOX
0
Monitor Transmit Data
WR (5C)
Contains the MONITOR data to be transmitted in IOM-2 MONITOR channel according
to the MONITOR channel protocol.The MONITOR channel (0-7) can be selected by
setting the monitor channel select bit MON_CR.MCS
Data Sheet
155
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
4.3.18
MOSR - MONITOR Interrupt Status Register
Value after reset: 00H
7
MOSR
0
MDR
MER
MDA
MAB
0
0
0
0
RD (5D)
MDR ... MONITOR channel Data Received
MER ... MONITOR channel End of Reception
MDA ... MONITOR channel Data Acknowledged
The remote end has acknowledged the MONITOR byte being transmitted.
MAB ... MONITOR channel Data Abort
4.3.19
MOCR - MONITOR Control Register
Value after reset: 00H
7
MOCR
0
MRE
MRC
MIE
MXC
0
0
0
0
RD/WR (5E)
MRE ... MONITOR Receive Interrupt Enable
0: MONITOR interrupt status MDR generation is masked
1: MONITOR interrupt status MDR generation is enabled
MRC ... MR Bit Control
Determines the value of the MR bit:
0: MR is always ’1’. In addition, the MDR interrupt is blocked, except for the first byte of
a packet (if MRE = 1).
1: MR is internally controlled by the SBCX-X according to MONITOR channel protocol.
In addition, the MDR interrupt is enabled for all received bytes according to the
MONITOR channel protocol (if MRE = 1).
Data Sheet
156
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
MIE ... MONITOR Interrupt Enable
MONITOR interrupt status MER, MDA, MAB generation is enabled (1) or masked (0).
MXC ... MX Bit Control
Determines the value of the MX bit:
0: The MX bit is always ’1’.
1: The MX bit is internally controlled by the SBCX-X according to MONITOR channel
protocol.
4.3.20
MSTA - MONITOR Status Register
Value after reset: 00H
MSTA
0
0
0
0
0
MAC
0
TOUT
RD (5F)
TOUT
WR (5F)
MAC ... MONITOR Transmit Channel Active
The data transmisson in the MONITOR channel is in progress.
TOUT ... Time-Out
Read-back value of the TOUT bit.
4.3.21
MCONF - MONITOR Configuration Register
Value after reset: 00H
MCONF
0
0
0
0
0
0
0
TOUT... Time-Out
0: The monitor time-out function is disabled
1: The monitor time-out function is enabled
Data Sheet
157
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
4.4
Interrupt and General Configuration
4.4.1
ISTA - Interrupt Status Register
Value after reset: 00H
7
ISTA
0
0
0
ST
CIC
AUX
TRAN MOS
0
RD (60)
For all interrupts in the ISTA register following logical states are applied:
0: Interrupt is not acitvated
1: Interrupt is acitvated
ST ... Synchronous Transfer
This interrupt is generated to enable the microcontroller to lock on to the IOM timing for
synchronous transfers. The source can be read from the STI register.
CIC ... C/I Channel Change
A change in C/I channel 0 or C/I channel 1 has been recognized. The actual value can
be read from CIR0 or CIR1.
AUX ... Auxiliary Interrupts
Signals an interrupt generated from external awake (pin EAW), watchdog timer overflow
(WOV) or from the timer (TIN). The source can be read from the auxiliary interrupt
register AUXI.
TRAN ... Transceiver Interrupt
An interrupt originated in the transceiver interrupt status register (ISTATR) has been
recognized.
MOS ... MONITOR Status
A change in the MONITOR Status Register (MOSR) has occured.
Note: A read of the ISTA register clears none of the interrupts. They are only cleared by
reading the corresponding status register.
Data Sheet
158
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
4.4.2
MASK - Mask Register
Value after reset: FFH
7
MASK
0
1
1
ST
CIC
AUX
TRAN MOS
1
WR (60)
For the MASK register following logical states are applied:
0: Interrupt is enabled
1: Interrupt is disabled
Each interrupt source in the ISTA register can selectively be masked/disabled by setting
the corresponding bit in MASK to ’1’. Masked interrupt status bits are not indicated when
ISTA is read. Instead, they remain internally stored and pending, until the mask bit is
reset to ’0’.
Note: In the event of a C/I channel change, CIC is set in ISTA even if the corresponding
mask bit in MASK is set, but no interrupt is generated.
4.4.3
AUXI - Auxiliary Interrupt Status Register
Value after reset: 00H
7
AUXI
0
0
0
EAW
WOV
TIN
0
0
0
RD (61)
For all interrupts in the ISTA register following logical states are applied:
0: Interrupt is not acitvated
1: Interrupt is acitvated
EAW ... External Awake Interrupt
An interrupt from the EAW pin has been detected.
WOV ... Watchdog Timer Overflow
Signals the expiration of the watchdog timer, which means that the microcontroller has
failed to set the watchdog timer control bits WTC1 and WTC2 (MODE1 register) in the
correct manner. A reset pulse has been generated by the SBCX-X.
TIN ... Timer Interrupt
An interrupt originated from the timer is recognized, i.e the timer has expired.
Data Sheet
159
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
4.4.4
AUXM - Auxiliary Mask Register
Value after reset: FFH
7
AUXM
0
1
1
EAW
WOV
TIN
1
1
1
WR (61)
For the MASK register following logical states are applied:
0: Interrupt is enabled
1: Interrupt is disabled
Each interrupt source in the AUXI register can selectively be masked/disabled by setting
the corresponding bit in AUXM to ’1’. Masked interrupt status bits are not indicated when
AUXI is read. Instead, they remain internally stored and pending, until the mask bit is
reset to ’0’.
4.4.5
MODE1 - Mode1 Register
Value after reset: 00H
7
MODE1
0
0
0
0
WTC1 WTC2
CFS
RSS2 RSS1
RD/WR (62)
WTC1, 2 ... Watchdog Timer Control 1, 2
After the watchdog timer mode has been selected (RSS = ’11’) the watchdog timer is
started. During every time period of 128 ms the microcontroller has to program the
WTC1 and WTC2 bit in the following sequence
1.
2.
WTC1
WTC2
1
0
0
1
to reset and restart the watchdog timer.
If WTC1/2 is not written fast enough in this way, the timer expires and a WOV-interrupt
(AUXI register) together with a reset pulse is generated.
Data Sheet
160
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
CFS ... Configuration Select
This bit determines clock relations and recovery on S/T and IOM interfaces.
0: The IOM interface clock and frame signals are always active, "Power Down" state
included.
The states "Power Down" and "Power Up" are thus functionally identical except for the
indication: PD = 1111 and PU = 0111.
With the C/I command Timing (TIM) the microcontroller can enforce the "Power Up" state
and with C/I command Deactivation Indication (DI) the "Power Down" state is reached
again.
However, it is also possible to activate the S-interface directly with the C/I command
Activate Request (AR 8/10/L) without the TIM command.
1: The IOM interface clock and frame signals are normally inactive ("Power Down").
For activating the IOM-2 clocks the "Power Up" state can be induced by software
(IOM_CR.SPU) or by resetting CFS again.
After that the S-interface can be activated with the C/I command Activate Request (AR
8/10/L). The "Power Down" state can be reached again with the C/I command
Deactivation Indication (DI).
Note: After reset the IOM interface is always active. To reach the "Power Down" state
the CFS-bit has to be set.
For general information please refer to Chapter 3.3.8.
RSS2, RSS1... Reset Source Selection 2,1
The SBCX-X reset sources for the RSTO output pin can be selected according to the
table below.
RSS
C/I Code
Change
EAW
Watchdog
Timer
Bit 1
Bit 0
0
0
0
1
1
0
x
x
--
1
1
--
--
x
Data Sheet
--
--
-(reserved)
161
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
• If RSS = ’00’ no above listed reset source is selected and therefore no reset is
generated at RSTO.
• Watchdog Timer
After the selection of the watchdog timer (RSS = ’11’) the timer is reset and started.
During every time period of 128 ms the microcontroller has to program the WTC1 and
WTC2 bits in two consecutive bit pattern (see description of the WTC1, 2 bits)
otherwise the watchdog timer expires and a reset pulse of 125 µs £ t£ 250 µs is
generated. Deactivation of the watchdog timer is only possible with a hardware reset.
• If RSS = ’10’ is selected the following two reset sources generate a reset pulse of
125 µs £ t £ 250 µs at the RSTO pin:
- External (Subscriber) Awake (EAW)
The EAW input pin serves as a request signal from the subscriber to initiate the awake
function in a terminal and generates a reset pulse (in TE mode only).
- Exchange Awake (C/I Code)
A C/I Code change generates a reset pulse.
After a reset pulse generated by the SBCX-X and the corresponding interrupt (WOV or
CIC) the actual reset source can be read from the ISTA.
4.4.6
MODE2 - Mode2 Register
Value after reset: 00H
7
MODE2
0
0
0
0
0
INT_
POL
0
0
PPSDX RD/WR (63)
INT_POL ... Interrupt Polarity
Selects the polarity of the interrupt pin INT.
0: low active with open drain characteristic (default)
1: high active with push pull characteristic
PPSDX ... Push/Pull Output for SDX (SCI Interface)
0: The SDX pin has open drain characteristic
1: The SDX pin has push/pull characteristic
Data Sheet
162
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
4.4.7
ID - Identification Register
Value after reset: 01H
7
ID
0
0
0
DESIGN
RD (64)
DESIGN ... Design Number
The design number allows to identify different hardware designs of the SBCX-X by
software.
01H: Version 1.4
(all other codes reserved)
4.4.8
SRES - Software Reset Register
Value after reset: 00H
7
SRES
RES_
CI
0
0
0
RES_
MON
0
RES_ RES_ RES_
IOM
TR RSTO
WR (64)
RES_xx ... Reset Functional Block xx
A reset can be activated on the functional block C/I-handler, Monitor channel, IOM
handler, S-transceiver and to pin RSTO.
Setting one of these bits to “1” causes the corresponding block to be reset for a duration
of 4 BCL clock cycles, except RES_RSTO which is activated for a duration of
125 ... 250µs. The bits are automatically reset to “0” again.
Data Sheet
163
2003-02-04
SBCX-X
PEB 3081
Detailed Register Description
4.4.9
TIMR - Timer Register
Value after reset: 00H
7
TIMR
0
TMD
0
CNT
RD/WR (65)
TMD ... Timer Mode
The timer can be used in two different modes of operation.
0: Count Down Timer.
An interrupt is generated only once after a time period of 1 ... 63 ms.
1: Periodic Timer.
An interrupt is periodically generated every 1 ... 63 ms (see CNT).
CNT ... Timer Counter
0: Timer off.
1 ... 63: Timer period = 1 ... 63 ms
By writing ’0’ to CNT the timer is immediately stopped. A value different from that
determines the time period after which an interrupt will be generated.
If the timer is already started with a certain CNT value and is written again before an
interrupt has been released, the timer will be reset to the new value and restarted again.
An interrupt is indicated to the host in AUXI.TIN.
Note: Reading back this value delivers back the current counter value which may differ
from the programmed value if the counter is running.
Data Sheet
164
2003-02-04
SBCX-X
PEB 3081
Electrical Characteristics
5
Electrical Characteristics
5.1
Absolute Maximum Ratings
Parameter
Symbol
TA
TSTG
VS
Ambient temperature under bias
Storage temperature
Input/output voltage on any pin
with respect to ground
Maximum voltage on any pin
with respect to ground
Vmax
Limit Values
Unit
min.
max.
0
+70
°C
– 55
150
°C
– 0.3
5.25
V
5.5
V
Note: Stresses above those listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the integrated circuit.
The supply voltage must show a monotonic rise.
Data Sheet
165
2003-02-04
SBCX-X
PEB 3081
Electrical Characteristics
5.2
DC Characteristics
VDD/VSS = 3.3 V ± 5%; TA = 0 to 70 °C
Parameter
Symbol
Limit Values
min.
typ.
Unit Test Condition
max.
H-input level
(except pins SR1/2)
VIH
2.0
5.25
V
L-input level
(except pins SR1/2)
VIL
– 0.3
0.8
V
H-output level
(except pin XTAL2,
SX1/2)
VOH
2.4
L-output level
(except pin XTAL2,
SX1/2)
VOL
Input leakage current
Output leakage current
(all pins except
SX1/2,SR1/2,XTAL1/2)
ILI
ILO
0.45
V
IOH = - 400 mA
V
IOL = 6 mA (DU, DD,
C768)
IOL = 4.5 mA (ACL)
IOL = 2 mA (all others)
±1
±1
mA
mA
0V< VIN<VDD
0V< VOUT<VDD
Inputs at VSS / VDD
No output loads
except SX1,2 (50 W)
Power supply currentPower Down
- Clocks Off
IPD1
300
mA
- Clocks On
IPD2
3
mA
Power supply current
- S operational (96 kHz) IOP1
30
mA
DCL=1536 kHz
IOP2
30
mA
DCL=4096 kHz
- B1=00H,B2=FFH, D=0 IOP3
25
mA
DCL=1536 kHz
Data Sheet
166
2003-02-04
SBCX-X
PEB 3081
Electrical Characteristics
5.3
Capacitances
TA = 25 °C, VDD = 3.3 V ± 5 % VSSA = 0 V, VSS = 0 V, fc = 1 MHz, unmeasured pins
grounded.
Parameter
Symbol
Limit Values Unit
min.
Remarks
max.
Input Capacitance
I/O Capacitance
CIN
CI/O
7
7
pF
pF
All pins except SX1,2 and
XTAL1,2
Output Capacitance
against VSS
COUT
10
pF
pins SX1,2
Data Sheet
167
2003-02-04
SBCX-X
PEB 3081
Electrical Characteristics
5.4
Oscillator Specification
Recommended Oscillator Circuits
33 pF
41
External
Oscillator
Signal
XTAL1
CL
41
XTAL1
7.68 MHz
33 pF
42
N.C.
XTAL2
42
XTAL2
CL
Crystal Oscillator Mode
Driving from External Source
ITS09659
Figure 68
Oscillator Circuits
Parameter
Symbol
Limit Values
Unit
Frequency
f
7.680
MHz
max. 100
ppm
max. 40
pF
Frequency calibration tolerance
Load capacitance
CL
Oscillator mode
fundamental
Note: It is important to note that the load capacitance depends on the recommendation
of the crystal specification. Typical values are 22 ... 33 pF.
XTAL1 Clock Characteristics (external oscillator input)
Parameter
Limit Values
Duty cycle
Data Sheet
168
min.
max.
1:2
2:1
2003-02-04
SBCX-X
PEB 3081
Electrical Characteristics
5.5
AC Characteristics
TA = 0 to 70 °C, VDD = 3.3 V ± 5 %
Inputs are driven to 2.4 V for a logical "1" and to 0.45 V for a logical "0". Timing
measurements are made at 2.0 V for a logical "1" and 0.8 V for a logical "0". The AC
testing input/output waveforms are shown in Figure 69.
2.4
2.0
2.0
Device
Under
Test
Test Points
0.8
0.8
C Load = 100 pF
0.45
ITS09660
Figure 69
Data Sheet
Input/Output Waveform for AC Tests
169
2003-02-04
SBCX-X
PEB 3081
Electrical Characteristics
5.6
IOM-2 Interface Timing
Data is transmitted with the rising edge of DCL and sampled with its falling edge. Below
figure shows double clock mode timing (the length of a timeslot is 2 DCL cycles),
however, the timing parameters are valid both in single and double clock mode. For the
direction of DU,DD (input or output) please refer to Chapter 3.4.
Figure 70
Data Sheet
IOM-2 Timing (TE mode)
170
2003-02-04
SBCX-X
PEB 3081
Electrical Characteristics
DCL (I)
t FSW
t FSS
FSC (I)
t FSH
t FSS
t FSH
t IIH
t IIS
Bit 0
DU/DD (I)
t IOD
DU/DD (O)
Bit 0
t SDD
SDS (O)
ITT09680
Figure 71
IOM-2 Timing (LT-S, LT-T, NT mode)
Parameter
Symbol
Limit Values
min.
Unit
max.
60
ns
IOM output data delay
tIOD
IOM input data setup
tIIS
4
ns
IOM input data hold
tIIH
3
ns
FSC strobe delay (see note)
tFSD
-135
Strobe signal delay
15
ns
tSDD
50
ns
BCL delay
tBCD
30
ns
Frame sync setup
tFSS
20
ns
Frame sync hold
tFSH
30
ns
Frame sync width
tFSW
40
ns
Data Sheet
171
2003-02-04
SBCX-X
PEB 3081
Electrical Characteristics
Note: Min. value in synchronous state, max. value in non-synchronous state. This
results in a phase shift of FSC when the S-Bus gets activated, this is the FSC
signal is shifted by 135 ns. This applies only to TE mode.
DCL Clock Output Characteristics
2.3 V
Figure 72
Definition of Clock Period and Width
Symbol
Limit Values
Unit
Test Condition
osc ± 100 ppm
min.
typ.
max.
tP
585
651
717
ns
tWH
260
325
391
ns
tWL
260
325
391
ns
osc ± 100 ppm
osc ± 100 ppm
DCL Clock Input Characteristics
Parameter
Limit Values
Duty cycle
Data Sheet
172
min.
max.
40
60
Unit
%
2003-02-04
SBCX-X
PEB 3081
Electrical Characteristics
5.7
Serial Control Interface (SCI) Timing
t1
t4
t2
t3
t5
CS
SCL
t6
t7
t9
SDR
t8
SDX
Figure 73
SCI Interface
Parameter
SCI Interface
Symbol
SCL cycle time
t1
200
ns
SCL high time
t2
100
ns
SCL low time
t3
100
ns
CS setup time
t4
2
ns
CS hold time
t5
10
ns
SDR setup time
t6
10
ns
SDR hold time
t7
6
ns
SDX data out delay
t8
30
ns
CS high to SDX tristate
t9
40
ns
Data Sheet
Limit Values
min.
173
Unit
max.
2003-02-04
SBCX-X
PEB 3081
Electrical Characteristics
5.8
Reset
Parameter
Symbol
Limit Values
Unit
Test Conditions
ms
Power On/Power Down
to Power Up (Standby)
min.
Length of active
low state
tRES
4
2 x DCL
clock cycles
During Power Up (Standby)
t RES
RES
21150_26
Figure 74
Data Sheet
Reset Signal RES
174
2003-02-04
SBCX-X
PEB 3081
Electrical Characteristics
5.9
S-Transceiver
Parameter
Symbol
Limit Values
min.
typ.
Unit Test Condition
max.
VDD= 3.3 V ± 5 %; VSS= 0 V; TA = 0 to 70 °C
Absolute value of output VX
pulse amplitude
| VSX2 – VSX1 |
1.17
V
RL = ¥
Transmitter output
current
IX
26
mA
RL = 5.6 W
Transmitter output
impedance (SX1,2)
ZX
10
kW
0
W
Inactive or during
binary one;
during binary zero
RL = 50 W
30
kW
VDD = 3.3 V
Receiver Input
impedance (SR1,2)
Data Sheet
ZR
175
2003-02-04
SBCX-X
PEB 3081
Electrical Characteristics
5.10
Recommended Transformer Specification
Parameter
Symbol
Limit Values
min.
Transformer ratio
Main inductance
Leakage inductance
typ.
max.
1:1
L
25
mH
20
mH
LL
Capacitance between C
primary and secondary
side
Copper resistance
Unit Test Condition
R
1.7
2.0
no DC current,
10 kHz
2.5 mA DC current,
10 kHz
8
6
µH
µH
NT/LT-S mode, 10 kHz
TE/LT-T mode, 10 kHz
80
pF
1 kHz
2.3
W
Note: In TE/LT-T mode, at the pulse shape measurement with a load of 400 W (e.g.
K 1403 approval test “Pulse shape”) overshots might occur with a leakage
inductance greater than 6 mH.
Data Sheet
176
2003-02-04
SBCX-X
PEB 3081
Electrical Characteristics
5.11
Line Overload Protection
The maximum input current for the S-transceiver lines (under overvoltage conditions) is
given as a function of the width of a rectangular input current pulse. The desctruction
limits are shown in Figure 75.
i
[A]
3
2
1.5
1
0.80
0.65
0.52
0.40
t
-8
10
-7
10
-6
10
-5
10
-4
10
-3
10
-2
10
[s]
21150_35
Figure 75
Maximum Line Input Current
Data Sheet
177
2003-02-04
SBCX-X
PEB 3081
Electrical Characteristics
5.12
EMC / ESD Aspects
To improve performance with respect to EMC and ESD requirements it is recommended
to provide additional capacitors in the middle tap of the transformers (see Figure 76
below). The values for C1 and C2 should be in the range 1 ... 10 nF. They can be located
either on the chip side of the transformer (option 1) or on the S bus side (option 2), but
not on both sides.
This improves EMC immunity acording to EN55024 which is mandatory since 2001-0701.
Note: The figure does not show any other components required for protection circuit in
receive and transmit direction as this is not affected by including C1 and C2.
Test Setup
Transmitter (NT)
Ck1
Cp1
Cp2
SR1
AC
C1
C1
SR2
Ck2
C1 and C2 are also possible
at this position (option 2)
Ck3
C2
C1, C2 required to supress
common mode signals (option 1)
AC
C2
SX1
SX2
Ck4
AC
Cp3
Cp4
Test Generator
0.15MHz - 80MHz carrier
with 1 kHz, 80% amplitude
modulated signal
Figure 76
Data Sheet
21150_34
Couple Capacity: Ck1 ¹ Ck2 ¹ Ck3 ¹ Ck4
Parasitic Capacity: Cp1 ¹ Cp2 ¹ Cp3 ¹ Cp4
Transmitter (TE)
Transformer Circuitry
178
2003-02-04
SBCX-X
PEB 3081
Package Outlines
6
Package Outlines
H
7˚ MAX.
0.15 +0.08
-0.02
2.45 MAX.
2 +0.1
-0.05
0.25 MIN.
P-MQFP-44
(Plastic Metric Quad Flat Package)
0.88 ±0.15
0.8
8
0.3 +0.15
C
0.1
0.2 M A-B D C 44x
13.2
0.2 A-B D 44x
10 1)
0.2 A-B D H 4x
D
A
44
Index Marking
1)
13.2
10 1)
B
1
0.6 x 45˚
Does not include plastic or metal protrusion of 0.25 max. per side
GPM05622
You can find all of the current packages, types of packing, and others on the Infineon Internet Page
“Products”: http://www.infineon.com/products.
Dimensions in mm
SMD = Surface Mounted Device
Data Sheet
178
2003-02-04
SBCX-X
PEB 3081
Package Outlines
P-TQFP-48
(Plastic Thin Quad Flat Package)
GPP05612
You can find all of the current packages, types of packing, and others on the Infineon Internet Page
“Products”: http://www.infineon.com/products.
Dimensions in mm
SMD = Surface Mounted Device
Data Sheet
179
2003-02-04
SBCX-X
PEB 3081
Appendix
7
Appendix
Transceiver, C/I-Channel Handler, Auxiliary Interface
NAME
7
6
5
4
3
2
1
0
reserved
TR_
MODE2
0
0
0
0
0
ADDR R/WRES
00H21H
DIM2 DIM1 DIM0
reserved
22H
R/W 00H
23-2DH
CIR0
CODR0
CIC0
CIC1
S/G
CIX0
CODX0
TBA2 TBA1 TBA0
BAS
2EH
R F3H
BAC
2EH W
FEH
CIR1
CODR1
CICW CI1E
2FH R
FEH
CIX1
CODX1
CICW CI1E
2FH W
FEH
TR_
CONF0
DIS_
TR
TR_
CONF1
0
TR_
CONF2
DIS_
TX
TR_STA
EN_
ICV
0
L1SW
0
EXLP
LDD
30H
R/W 01H
0
0
x
x
x
31H
R/W
0
RLP
0
0
SGP
SGD
32H
R/W 80H
SLIP
ICV
0
FSYN
0
LD
33H
R 00H
PD
LP_A
0
34H
R/W 08H
RPLL_ EN_
ADJ SFSC
PDS
RINF
TR_CMD
SQRR1
BUS
XINF
MSYN MFEN
DPRIO TDDIS
0
0
SQR11SQR12SQR13SQR14
35H
R 40H
0
0
SQX11 SQX12SQX13 SQX14
35H
W 4FH
SQRR2 SQR21SQR22SQR23SQR24SQR31SQR32SQR33SQR34
36H
R 00H
SQXR2 SQX21SQX22SQX23SQX24SQX31 SQX32SQX33 SQX34
36H
W 00H
SQRR3 SQR41SQR42SQR43SQR44SQR51SQR52SQR53SQR54
37H
R 00H
SQXR3 SQX41SQX42SQX43SQX44SQX51 SQX52SQX53 SQX54
37H
W 00H
SQXR1
Data Sheet
0
MFEN
180
2003-02-04
SBCX-X
PEB 3081
Appendix
Transceiver, C/I-Channel Handler, Auxiliary Interface
NAME
7
6
5
4
3
2
1
0
ISTATR
0
x
x
x
LD
RIC
SQC
SQW
38H
R 00H
MASKTR
1
1
1
1
LD
RIC
SQC
SQW
39H
R/W FFH
TR_
MODE
0
0
0
0
DCH_ MODE MODE MODE
INH
2
1
0
reserved
ADDR R/WRES
3AH R/W 00H
3BH
ACFG1
0
0
0
0
0
OD2
OD1
OD0
3CH R/W 00H
ACFG2
0
0
0
0
ACL
LED
0
0
3DH R/W 00H
AOE
1
1
1
1
1
OE2
OE1
OE0
3EH R/W FFH
ARX
-
-
-
-
-
AR2
AR1
AR0
3FH
R
ATX
0
0
0
0
0
AT2
AT1
AT0
3FH
W 00H
IOM Handler (Timeslot , Data Port Selection,
CDA Data and CDA Control Register)
Name
7
6
5
4
3
2
1
0
ADDR R/WRES
CDA10
Controller Data Access Register (CH10)
40H
R/W FFH
CDA11
Controller Data Access Register (CH11)
41H
R/W FFH
CDA20
Controller Data Access Register (CH20)
42H
R/W FFH
CDA21
Controller Data Access Register (CH21)
43H
R/W FFH
CDA_ DPS
TSDP10
0
0
TSS
44H
R/W 00H
CDA_ DPS
TSDP11
0
0
TSS
45H
R/W 01H
CDA_ DPS
TSDP20
0
0
TSS
46H
R/W 80H
Data Sheet
181
2003-02-04
SBCX-X
PEB 3081
Appendix
CDA_ DPS
TSDP21
0
0
TSS
47H
reserved
R/W 81H
48-4BH
TR_
TSDP_
BC1
DPS
0
0
TSS
4CH R/W 00H
TR_
TSDP_
BC2
DPS
0
0
TSS
4DH R/W 01H
CDA1_
CR
0
0
EN_ EN_I1 EN_I0 EN_O1EN_O0 SWAP
TBM
4EH R/W 00H
CDA2_
CR
0
0
EN_ EN_I1 EN_I0 EN_O1EN_O0 SWAP
TBM
4FH R/W 00H
IOM Handler (Control Registers, Synchronous Transfer
Interrupt Control), MONITOR Handler
Name
7
6
5
4
3
EN_
B2R
EN_
B1R
EN_
B2X
EN_
B1X
CS2-0
50H R/W F8H
(CI_CS=0)
EN_
D
TRC_CR
0
0
0
0
0
CS2-0
50H R/W 00H
TR_CR
2
1
0
ADDR R/WRES
(CI_CS=1)
reserved
DCI_CR
51-52H
DPS_ EN_
(CI_CS=0) CI1
CI1
0
0
0
DCIC_CR
0
0
0
0
CS2-0
53H R/W 00H
EN_
MON
0
0
0
CS2-0
54H R/W 40H
0
0
0
0
53H R/W 80H
(CI_CS=1)
MON_CR DPS
SDS1_CR ENS_ ENS_ ENS_
TSS TSS+1 TSS+3
Data Sheet
TSS
182
55H R/W 00H
2003-02-04
SBCX-X
PEB 3081
Appendix
SDS2_CR ENS_ ENS_ ENS_
TSS TSS+1 TSS+3
IOM_CR
SPU
STI
TSS
DIS_ CI_CS TIC_
AW
DIS
STOV STOV STOV STOV
21
20
11
10
ASTI
0
MSTI
0
0
0
STOV STOV STOV STOV
21
20
11
10
SDS_
CONF
0
0
MCDA
MCDA21
0
0
MCDA20
56H R/W 00H
EN_ CLKM DIS_
BCL
OD
DIS_
IOM
57H R/W 08H
STI
21
STI
20
STI
11
STI
10
58H
R 00H
ACK
21
ACK
20
ACK
11
ACK
10
58H
W 00H
STI
21
STI
20
STI
11
STI
10
59H R/W FFH
DIOM_ DIOM_ SDS2_ SDS1_ 5AH R/W 00H
INV SDS BCL BCL
MCDA11
MCDA10
5BH
R FFH
MOR
MONITOR Receive Data
5CH
R FFH
MOX
MONITOR Transmit Data
5CH
W FFH
R 00H
MOSR
MDR
MER
MDA
MAB
0
0
0
0
5DH
MOCR
MRE
MRC
MIE
MXC
0
0
0
0
5EH R/W 00H
MSTA
0
0
0
0
0
MAC
0
TOUT
5FH
R 00H
MCONF
0
0
0
0
0
0
0
TOUT
5FH
W 00H
1
0
Interrupt, General Configuration Registers
NAME
7
6
5
4
ISTA
0
0
ST
CIC
AUX TRAN MOS
0
60H
R 00H
MASK
1
1
ST
CIC
AUX TRAN MOS
1
60H
W FFH
AUXI
0
0
EAW WOV
TIN
0
0
0
61H
R 00H
AUXM
1
1
EAW WOV
TIN
1
1
1
61H
W FFH
MODE1
0
0
62H
R/W 00H
Data Sheet
0
3
2
WTC1 WTC2 CFS RSS2 RSS1
183
ADDR R/WRES
2003-02-04
SBCX-X
PEB 3081
Appendix
Interrupt, General Configuration Registers
NAME
7
6
5
4
3
2
1
0
MODE2
0
0
0
0
INT_
POL
0
0
PPSDX
ID
0
0
SRES
RES_
CI
0
TIMR
TMD
0
0
RES_
MON
63H
R/W 00H
DESIGN
64H
R 01H
0
64H
W 00H
65H
R/W 00H
RES_ RES_ RES_
IOM
TR RSTO
CNT
reserved
Data Sheet
ADDR R/WRES
184
66H6FH
2003-02-04
SBCX-X
PEB 3081
Index
A
Absolute maximum ratings 165
AC characteristics 169
ACFG1 register 140
ACFG2 register 140
ACKxy bits 153
ACL bit 140
Activation 76
Activation indication - pin ACL 35
Activation LED 35
Activation/deactivation of IOM-2 interface
116
AOE register 141
Appendix 180
Applications 16
AR2-0 bits 141
Architecture 23
ARX register 141
ASTI register 153
Asynchronous awake 118
AT2-0 bits 142
ATX register 142
AUX bit 158
AUXI register 159
Auxiliary interface 118
AUXM register 160
B
BAC bit 128
BAS bit 127
BUS bit 129
C
C/I channel 106
Capacitances 167
CDA_TSDPxy registers 143
CDAx_CR register 144
CDAxy registers 142
CFS bit 160
CI_CS bit 150
CI1E bit 128
CIC bit 158
Data Sheet
CIC1/0 bits 127
CICW bit 128
CIR0 register 127
CIR1 register 128
CIX0 register 128
CIX1 register 129
CLKM bit 150
Clock generation 53
CNT bits 164
CODR0 bits 127
CODR1 bits 128
CODX0 bits 128
CODX1 bits 129
Control of layer-1 58
Controller data access 84
D
DC characteristics 166
DCH_INH bit 139
D-channel access control
Intelligent NT 112
S-bus D-channel control in LT-T 112
S-bus priority mechanism 110
TIC bus 108
DCI_CR register 146
Deactivation 76
Delay between IOM-2 and S 42
DESIGN bits 163
Device architecture 23
DIM2-0 bits 126
DIS_AW bit 150
DIS_IOM bit 150
DIS_OD bit 150
DIS_TR bit 129
DIS_TX bit 131
DPRIO bit 134
DPS bit 143, 148
DPS_CI1 bit 146
E
EAW bit 159
Electrical characteristics 165
EN_B2/1R bits 145
185
2003-02-04
SBCX-X
PEB 3081
Index
EN_B2/1X bits 145
EN_BCL bit 150
EN_CI1 bit 146
EN_D bit 145
EN_I0 bit 144
EN_I1 bit 144
EN_ICV bit 129
EN_MON bit 148
EN_O0 bit 144
EN_O1 bit 144
EN_SFSC bit 131
EN_TBM bit 144
ENS_TSSx bits 149
Exchange awake 32
EXLP bit 129
External reset input 32
F
Features 14
FSYN bit 133
Functional blocks 23
I
I/O lines 118
ICV bit 133
ID register 163
INT_POL bit 162
Intelligent NT 112
Interrupt structure 29
IOM_CR register 150
IOM-2 79
Frame structure (LT) 81
Frame structure (NT) 81
Frame structure (TE) 80
Handler 82
Interface Timing 169
LT-S, LT-T, NT modes 79
Monitor channel 97
TE mode 79
ISTA register 158
ISTATR register 137
Data Sheet
J
Jitter 56
L
L1SW bit 129
LD bit 133, 137
LDD bit 129
LED bit 140
LED output 35
Level detection 50
Logic symbol 15
Looping data 85
LP_A bit 134
LT-T mode 112
M
MAB bit 156
MAC bit 157
MASK register 159
MASKTR register 138
MCDA register 155
MCDAxy bits 155
MCONF register 157
MDA bit 156
MDR bit 156
MER bit 156
MFEN bit 135, 136
Microcontroller interfaces 25
MIE bit 156
MOCR register 156
MODE1 register 160
MODE2 register 162
MODE2-0 bits 139
MON_CR register 148
Monitor channel
Error treatment 101
Handshake procedure 98
Interrupt logic 105
Master device 103
Slave device 103
Time-out procedure 104
Monitoring data 89
186
2003-02-04
SBCX-X
PEB 3081
Index
Monitoring TIC bus 89
MOR register 155
MOS bit 158
MOSR register 156
MOX register 155
MRC bit 156
MRE bit 156
MSTA register 157
MSTI register 153
MSYN bit 135
Multiframing 40
MXC bit 156
O
OD2-0 bits 140
OE2-0 bits 141
Oscillator 168
Oscillator clock output 57
Overview 11
P
Package Outlines 178
PD bit 134
PDS bit 131
Pin configuration 17
PPSDX bit 162
R
Receive PLL 56
Register description 120
RES_xxx bits 163
Reset generation 31
Reset source selection 31
Reset timing 173
RIC bit 137
RINF bits 133
RLP bit 131
RPLL_ADJ bit 131
RSS2/1 bits 160
S
S/G bit 114, 127
S/T-Interface 36
Data Sheet
Circuitry 47
Coding 38
Delay compensation 50
External protection circuitry 47
Multiframing 40
Receiver characteristics 46
Transceiver enable/disable 50
Transmitter characteristics 45
S-bus priority mechanism 110
SCI - serial control interface 26
SCI interface timing 172
SDS 94
SDS_CONF register 154
SDS2/1_BCL bits 154
SDSx_CR registers 149
Serial data strobe 94
SGD bit 131
SGP bit 131
Shifting data 85
SLIP bit 133
Software reset 32
SPU bit 150
SQC bit 137
SQR11-14 bits 135
SQR21-24 bits 136
SQR31-34 bits 136
SQR41-44 bits 137
SQR51-54 bits 137
SQRR1 register 135
SQRR2 register 136
SQRR3 register 137
SQW bit 137
SQX11-14 bits 136
SQX21-24 137
SQX31-34 bits 137
SQX41-44 bits 137
SQX51-54 bits 137
SQXR1 register 136
SQXR2 register 137
SQXR3 register 137
SRES register 163
ST bit 158
State machine
187
2003-02-04
SBCX-X
PEB 3081
Index
LT-S mode 67
NT mode 71
TE and LT-T mode 60
STI register 152
STIxy bits 152, 153
Stop/Go bit 114, 127
STOVxy bits 152, 153
Strobed data clock 94
Subscriber awake 32
SWAP bit 144
Synchronous transfer 90
X
XINF bits 134
T
TBA2-0 bits 128
TDDIS bit 134
Test functions 51
TIC bus 108
TIC_DIS bit 150
Timer 33
TIMR register 164
TIN bit 159
TMD bit 164
TOUT bit 157
TR_CMD register 134
TR_CONF0 register 129
TR_CONF1 register 131
TR_CONF2 register 131
TR_CR register 145
TR_MODE register 139
TR_MODE2 register 126
TR_STA register 133
TR_TSDP_BC1/2 registers 143
TRAN bit 158
Transceiver enable/disable 50
Transformer specification 175
TSS bits 143, 149
Typical applications 16
W
Watchdog timer 32
WOV bit 159
WTC1/2 bits 160
Data Sheet
188
2003-02-04
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