ETC PLL2027XA

20MHz ~ 200MHz PIXEL CLOCK GENERATOR
General Description
PLL2027XA
Features
The PLL2027XA is a Phase-Locked Loop (PLL) frequency
synthesizer constructed in CMOS on single monolithic
structure. The PLL macrofunctions provide frequency
multiplication capabilities.
The output clock frequency Fout is related to the reference
input clock frequency Fin by the following equation:
Fout=((M+2)*Fin)/(2P*2S)
Where, Fout is the output clock frequency.
Fin is the reference input clock frequency.
m,p and s are the values for programmable dividers.
PLL2027XA consists of a phase/Frequency Detector(PFD),
a Charge Pump an External Loop Filter, a Voltage
Controlled Oscillator(VCO), a 2bit Pre-divider, an 14bit
Main divider and 2bit Post Scaler as shown in Figure1.
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•
•
•
•
•
•
0.35um CMOS device technology
3.3 Volt single power supply
Input Frequency Range: 15K ~ 250KHz
Output frequency range: 20M ~ 200MHz
Clock-to-Clock Jitter ±150ps at 200MHz
Duty ratio 45% to 55%(All tuned range)
Frequency changed by programmable
divider
• Power down mode
FUNCTIONAL BLOCK DIAGRAM
FIN
Pre Divider
P
PFD
Charge
Pump
VCO
Loop
Filter
Main Divider
M
Figure 1. Phase Locked Loop Block Diagram
Ver 2.1 (AUG. 2000 )
No responsibility is assumed by SEC for its use nor for
any infringements of patents or other rights of third parties
that may result from its use. The contents of the datasheet
is subject to change without any notice.
SAMSUNG ELECTRONICS Co. LTD
Post Scaler
S
FOUT
PLL2027XA
20MHZ~200MHZ PIXEL CLOCK GENERATOR
CORE PIN DESCRIPTION
NAME
I/O
TYPE
I/O PAD
PIN DESCRIPTION
VDD2
DP
vddd
Digital power supply
VSS2
DG
vssd
Digital ground
VDD1
AP
vdda
Analog power supply
VSS1
AG
vssa
Analog ground
VBB1
AB/DB
vbba
Analog / Digital sub bias
FIN
DI
picc_bb
Reference Frequency Input
CZ
AO
poar50_bb
CP
AI
piar50_bb
. External Loop Filter.
Refer to Figure(Core Configuration)
FOUT
DO
pot12_bb
20MHz~200MHz clock output
FSPLL clock power down.
-When PWRDN is High, PLL do not
operate.
-If isn't used this pin, tied to VSS.
PWRDN
DI
picc_bb
P[1:0]
DI
picc_bb
The values for 2bit
programmable pre-divider.
M[13:0]
DI
picc_bb
The values for 14bit
programmable main divider.
S[1:0]
DI
picc_bb
The values for 2bit
programmable post scaler.
I/O TYPE ABBR.
•
•
•
•
AI : Analog Input
DI : Digital Input
AO : Analog Output
DO : Analog Output
•
•
•
•
•
•
AP
AG
AB
DP
DG
DB
:
:
:
:
:
:
Analog Power
Analog Ground
Analog Sub Bias
Digital Power
Digital Ground
Digital Sub Vias
• BD : Bidirectional Port
CORE CONFIGURATION
FIN
PWRDN
M[7:0]
M[0]
M[1]
M[2]
M[3]
M[4]
M[5]
M[6]
M[7]
M[8]
M[9]
M[10]
M[11]
M[12]
M[13]
P[1:0]
P[0]
P[1]
S[1:0]
S[0]
S[1]
SEC ASIC
FOUT
pll2027xa
CP
CZ
ANALOG
PLL2027XA
20MHZ~200MHZ PIXEL CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS (Ta=25 ºC)
Characteristics
Supply Voltage
Symbol
Value
Unit
5
V
VDD2
VDD1
Voltage on Any Digital Pin
Vin
vss-0.25 to vdd+0.25
V
Storage Temperature
Tstg
-45 to 125
ºC
Applicable pin
VDD2,VDD1,VSS2,
VSS1,VBB1
P[1:0],M[13:0],S[1:0]
PWRDN
-
NOTES
1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently.
Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each
condition value is applied with the other values kept within the following operating conditions and function
operation under any of these conditions is not implied.
2. All voltages are measured with respect to VSS2 unless otherwise specified.
3. 100pF capacitor is discharged through a 1.5Kohm resistor (Human body model)
Recommended Operating Conditions
Characteristics
Symbol
Min
Supply Voltage Differential
VDD2-VDD1
Input Frequency
Operating Temperature
External Loop Filter
Typ
Max
Unit
-0.1
+0.1
V
Fin
15
250
Khz
Topr
0
70
ºC
236
nF
NOTES
1. It is strongly recommended that all the supply pins (VDD2, VDD1) be powered to the same supply
voltage to avoid power latch-up.
SEC ASIC
ANALOG
PLL2027XA
20MHZ~200MHZ PIXEL CLOCK GENERATOR
DC ELECTRICAL CHARACTERISTICS
Characteristics
Symbol
Min
Typ
Max
Unit
Operating Voltage
VDD2/VDD1
3.135
3.3
3.465
V
Digital Input Voltage High
VIH
2.5
Digital Input Voltage Low
VIL
0.8
V
Idd
5
mA
Ipd
50
uA
Dynamic Current
Power Down Current
V
AC ELECTRICAL CHARACTERISTICS
Characteristics
Symbol
Min
Input Frequency
FIN
Output Clock Frequency
Max
Unit
15
250
KHz
FOUT
20
200
Mhz
Input Clock Duty Cycle
TID
40
60
%
Output Clock Duty Cycle
TOD
45
55
%
Input Glitch Pulse Width
TIGP
1
Locking Time
TLT
Jitter,Clock to Clock
TJCC
-150
Typ
ns
10
ms
+150
ps
NOTES
1. It is strongly recommended that input signal is not generated glitch, but if consumer cannot help generating
glitch, Consumer must carefully considerate the specification.
SEC ASIC
ANALOG
PLL2027XA
20MHZ~200MHZ PIXEL CLOCK GENERATOR
Functional Description
A PLL is the circuit synchronizing an output signal (generated by an VCO) with a reference
or input signal in frequency as well as in phase.
In this application, it includes the following basic blocks.
. The voltage-controlled oscillator to generate the output frequency
. The divider P devides the reference frequency by p
. The divider M devides the VCO output frequency by m
. The divider S divides the VCO output frequency by s
. The phase frequency detector
detects the phase difference between the reference frequency
and the output frequency (after division) and controls the charge pump voltage.
. The loop filter
removes high frequency components in charge pump voltage and does
smooth and clean control of VCO
The m, p, s values can be programmed by 18bit digital data from the external source. So the PLL
can be locked in the desired frequency.
Fout = m * Fin / p*s
Fin = 15K ~ 250KHz, m=M+2 , p=2^P, s=2^S
Digital data format:
Main Divider
Pre Divider
Post Scaler
M13,M12,M11,M10,M9,M8,M7,M6,M5,M4,M3,M2,M1,M0
P1,P0
S1,S0
NOTES
. S[1] - S[0] : Output Frequency Scaler
. M[13] - M[0] : VCO Frequency Divider
. P[1] - P[0] : Reference Frequency Input Divider
SEC ASIC
ANALOG
PLL2027XA
20MHZ~200MHZ PIXEL CLOCK GENERATOR
CORE EVALUATION GUIDE
For the embedded PLL, we must consider the test circuits for the embedded PLL core in multiple applications.
Hence the following requirements should be satisfied.
- The FILTER(CP,CZ) and FOUT pins must be bypassed for external test.
- For PLL test (Below 2 examples),
it is needed to control the dividers - M[13:0],P[1:0] and S[1:0] -that generate multiple clocks.
#1. Registers can be used for easy control of divider values.
#2. N sample bits of 18-bit divider pins can be bypassed for test using MUX.
3.3V Digital Power
3.3V Analog Power
GND
External Clock Source
GND
FIN
VDD2 VSS2
VDD1 VSS1 VBB1
FOUT
PWRDN
pll2027xa
M[13:0]
#1.18bit Register Block
CP
CZ
P[1:0]
S[1:0]
Select Pin
NOTES
Test Pins of N Sample bits
#2
M
U
X
: 10uF ELECTROLYTIC CAPACITOR
UNLESS OTHERWISE SPECIFIED
: 104 CERAMIC CAPACITOR
UNLESS OTHERWISE SPECIFIED
Internal Divider Signal Line
SEC ASIC
ANALOG
PLL2027XA
20MHZ~200MHZ PIXEL CLOCK GENERATOR
PACKAGE CONFIGURATION
C
INDEX1
1
48
INDEX2
NC
2
47
FOUT
VSSO
3
46
EN
L
H
VDDO
4
45
TN
L
H
NC
5
44
NC
6
43
VBB1
VBB1
H
L
S1
7
42
PWRDN
H
L
S0
8
41
CP
VSS2
9
40
CZ
10
39
PWDVCO
11
38
VDD1
12
pll2027xa 37
M0
13
36
C
VSS2
VDD2
VDD2
H
L
PLL ouput Clock
L
H
External
Loop Filter
L
H
C
VDD1
VSS1
H
L
M1
14
35
VSS1
H
L
M2
15
34
NC
H
L
M3
16
33
FIN
H
L
M4
17
32
NC
H
L
M5
18
31
NC
H
L
M6
19
30
NC
H
L
M7
20
29
NC
H
L
M8
21
28
P1
L
H
H
L
M9
22
27
P0
L
H
H
L
M10
23
26
M13
L
H
H
L
M11
24
25
M12
L
H
Exteral Input Clock
(15KHz ~ 250KHz)
Note
C
10uF
103
SEC ASIC
ANALOG
PLL2027XA
20MHZ~200MHZ PIXEL CLOCK GENERATOR
PACKAGE PIN DESCRIPTION
NAME
PIN NO
I/O TYPE
PIN DESCRIPTION
VDD2
11,12
DP
Digital power supply
VSS2
9,10
DG
Digital ground
VBB1
43,44
AB/DB
PWRDN
42
DI
P[0]~P[1]
27,28
DI
Pre-Divider Input
VDD1
37,38
AP
Analog power supply
VSS1
35,36
AG
Analog ground
FIN
33
DI
Pll Input pin (15KHz ~ 250KHz)
PWDVCO
39
AI
- Only VCO Power Down.(Test Block pin)
- PWDVCO is high, VCO do not operate.
- If isn't used this pin, tied to VSS1
CZ
40
AO
- Loop filter( Pump output ) - refer to loop filter.
CP
41
AI
- Loop Filter( VCO Input ) - refer to loop filter.
FOUT
47
DO
20MHZ~200MHz clock output
Analog / Digital Sub Bias
FSPLL clock power down
-PWRDN is High, PLL do not operating under
this condition.
- If isn't used this pin, tied to VSS2.
S[0]~S[1]
7,8
DI
Post scaler input
M[0]~M[13]
13 ~ 26
DI
14bit main divider input
VDDO
4
PP
I/O PAD Power
VSSO
3
PG
I/O PAD Power
TN
46
PI
Test pin (VDDO, Logic State High)
EN
45
PI
Test pin (VSSO, Logic State Low)
NOTES
1. I/O TYPE PP and PG denote PAD power and PAD ground respectively.
SEC ASIC
ANALOG
PLL2027XA
20MHZ~200MHZ PIXEL CLOCK GENERATOR
* EXTERNAL LOOP FILTER
CZ
CP
R2
R1
C2
R1
R2
C1
C2
:2.02K
:0.1K
:236nF
:18nF
C1
CORE LAYOUT GUIDE
- The digital power(VDD2,VSS2) and the analog power(VDD1,VSS1) must be dedicated to PLL only and
seperated. If the dedicated VDD2 and VSS2 is not allowed that of the least power consuming block is
shared with the PLL.
- The POAR50_BB, PIAR50_BB pad is used as a CZ, CP pad that contains only ESD production diodes without
any resistors and buffers.
- The FOUT and CZ, CP pins must be placed far from the internal signals in order to avoid overlapping
signal lines.
- The blocks having a large digital switching current must be located away from the PLL core.
- The PLL core must be shielded by guardring.
- For the FOUT pad, you can use a custom drive buffer or POT12_BB buffer considering the drive current.
SEC ASIC
ANALOG
20MHZ~200MHZ PIXEL CLOCK GENERATOR
PLL2027XA
Design Considerations
The following design consideratios apply:
* Phase tolerance and jitter are independent of the PLL frequency.
* Jitter is affected by the noise frequency in the power(VDD2/VSS2,VDD1/VSS1) .
It increases when the noise level increases.
* A CMOS-level input reference clock is recommend for signal compatibility with
the PLL circuit. Other levels such as TTL may degrade the tolerances.
* The use of two, or more PLLs requires special design considerations. Please
consult your application engineer for more information.
* The following apply to the noise level, which can be minimized by using good
analog power and ground isolation techniques in the system:
- Use wide PCB traces for POWER(VDD2/VSS2 VDD1/VSS1) connections to the PLL core.
Seperate the traces from the chip's VDD2/VSS2,VDD1/VSS1 supplies.
- Use proper VDD2/VSS2,VDD1/VSS1 de-coupling.
- Use good power and ground sources on the board.
- Use Power VBB1 for minimize substrate noise
* The PLL core should be placed as close as possible to the dedicated loop filter and analog
Power and ground pins.
* It is inadvisable to locate noise-generating signals, such as data buses and high-current
outputs, near the PLL I/O cells.
* Other related I/O signals should be placed near the PLL I/O but do not have any predefined placement restriction
SEC ASIC
ANALOG
PLL2027XA
20MHZ~200MHZ PIXEL CLOCK GENERATOR
PLL Specification
We appreciate your interest in our products. If you have further questions, please specify in
the attached form. Thank you very much.
Parameter
Min
Typ
Max
Unit
Remarks
Supply Voltage
Output frequency range
Input frequency range
Cycle to Cycle Jitter
Lock up time
Dynamic current
Stand by current
Output clock duty ratio
Long term jitter
Output slew rate
- Do you need XTAL driver buffer in PLL Core?
If you need it, what's the crystal frequency range? If not, What's the input frequency range?
-
Do you need the lock detector?
Do you need the I/O cell of SEC?
Do you need the external pin for PLL test?
What's the main frequency & frequency range?
How many FSPLLs do you use in your system?
What's output loading?
Could you external/internal pin configurations as required?
Specially requested function list :
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