a CMOS, Low-Voltage, 3-Wire Serially-Controlled, Matrix Switches ADG738/ADG739 FEATURES 3-Wire Serial Interface 2.7 V to 5.5 V Single Supply 2.5 ⍀ On Resistance 0.75 ⍀ On-Resistance Flatness 100 pA Leakage Currents Single 8-to-1 Multiplexer ADG738 Dual 4-to-1 Multiplexer ADG739 Power-On Reset TTL/CMOS-Compatible APPLICATIONS Data Acquisition Systems Communication Systems Relay Replacement Audio and Video Switching FUNCTIONAL BLOCK DIAGRAMS ADG738 ADG739 S1 S1A DA S4A D S1B DB S8 S4B INPUT SHIFT REGISTER INPUT SHIFT REGISTER DOUT SCLK DIN SYNC RESET DOUT SCLK DIN SYNC GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADG738 and ADG739 are CMOS analog matrix switches with a serially-controlled 3-wire interface. The ADG738 is an 8-channel matrix switch, while the ADG739 is a dual 4-channel matrix switch. On resistance is closely matched between switches and very flat over the full signal range. 1. 3-Wire Serial Interface. The ADG738 and ADG739 utilize a 3-wire serial interface that is compatible with SPI™, QSPI™, MICROWIRE™, and some DSP interface standards. The output of the shift register DOUT enables a number of these parts to be daisy-chained. On power-up, the internal shift register contains all zeros and all switches are in the OFF state. 4. Any configuration of switches may be on or off at any one time. 2. Single Supply Operation. The ADG738 and ADG739 are fully specified and guaranteed with 3 V and 5 V supply rails. 3. Low On Resistance, 2.5 Ω typical. 5. Guaranteed Break-Before-Make Switching Action. 6. Small 16-lead TSSOP Package. Each switch conducts equally well in both directions when on, making these parts suitable for both multiplexing and demultiplexing applications. As each switch is turned on or off by a separate bit, these parts can also be configured as a type of switch array, where any, all, or none of the eight switches may be closed at any time. The input signal range extends to the supply rails. All channels exhibit break-before-make switching action, preventing momentary shorting when switching channels. The ADG738 and ADG739 are available in 16-lead TSSOP packages. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 ADG738/ADG739–SPECIFICATIONS1 (V Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On-Resistance Match Between Channels (∆RON) On-Resistance Flatness (RFLAT(ON)) B Version –40ⴗC 25ⴗC to +85ⴗC 0 V to VDD 2.5 4.5 5 0.4 0.8 0.75 1.2 LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH ± 0.01 ± 0.1 ± 0.01 ± 0.1 ± 0.01 ± 0.1 ± 0.3 ±1 ±1 2.4 0.8 0.005 ± 0.1 CIN, Digital Input Capacitance 3 DIGITAL OUTPUT Output Low Voltage COUT, Digital Output Capacitance 4 DYNAMIC CHARACTERISTICS2 tON 20 0.4 DD = 5 V ⴞ 10%, GND = 0 V, unless otherwise noted.) Unit V Ω typ Ω max Ω typ Ω max Ω typ Ω max nA typ nA max nA typ nA max nA typ nA max V min V max µA typ µA max pF typ Break-Before-Make Time Delay, tD 9 Charge Injection ±3 Off Isolation –55 –75 dB typ dB typ Channel-to-Channel Crosstalk –55 –75 dB typ dB typ 65 100 13 MHz typ MHz typ pF typ 85 42 pF typ pF typ 96 48 pF typ pF typ 10 µA typ µA max –3 dB Bandwidth ADG738 ADG739 CS (OFF) CD (OFF) ADG738 ADG739 CD, CS (ON) ADG738 ADG739 POWER REQUIREMENTS IDD 20 VDD = 5.5 V VD = 4.5 V/1 V, VS = 1 V/4.5 V; Test Circuit 2 VD = 4.5 V/1 V, VS = 1 V/4.5 V; Test Circuit 3 VD = VS = 1 V/4.5 V, Test Circuit 4 VIN = VINL or VINH RL = 300 Ω, CL = 35 pF, Test Circuit 5; VS1 = 3 V RL = 300 Ω, CL = 35 pF, Test Circuit 5; VS1 = 3 V RL = 300 Ω, CL = 35 pF; VS1 = VS8 = 3 V, Test Circuit 5 VS = 2.5 V, RS = 0 Ω, CL = 1 nF; Test Circuit 6 RL = 50 Ω, CL = 5 pF, f = 10 MHz; RL = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 8 RL = 50 Ω, CL = 5 pF, f = 10 MHz; RL = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 7 10 1 VS = 0 V to VDD, IS = 10 mA ISINK = 6 mA tOFF 17 VS = 0 V to VDD, IS = 10 mA; Test Circuit 1 VS = 0 V to VDD, IS = 10 mA max pF typ ns typ ns max ns typ ns max ns typ ns min pC typ 32 Test Conditions/Comments RL = 50 Ω, CL = 5 pF, Test Circuit 8 VDD = 5.5 V Digital Inputs = 0 V or 5.5 V NOTES 1 Temperature range is as follows: B Version: –40°C to +85°C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice. –2– REV. 0 ADG738/ADG739 SPECIFICATIONS1 (V DD Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) = 3 V ⴞ 10%, GND = 0 V, unless otherwise noted.) B Version –40ⴗC 25ⴗC to +85ⴗC 0 V to VDD 6 11 On-Resistance Match Between Channels (∆RON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH ± 0.01 ± 0.1 ± 0.01 ± 0.1 ± 0.01 ± 0.1 12 0.4 1.2 3.5 ±1 ±1 V min V max µA typ µA max pF typ 0.005 ± 0.1 3 DIGITAL OUTPUT Output Low Voltage COUT, Digital Output Capacitance 4 DYNAMIC CHARACTERISTICS2 tON 40 V Ω typ Ω max Ω typ Ω max Ω typ nA typ nA max nA typ nA max nA typ nA max ± 0.3 2.0 0.4 CIN, Digital Input Capacitance Unit 0.4 Break-Before-Make Time Delay, tD 12 Charge Injection ±3 Off Isolation –55 –75 dB typ dB typ Channel-to-Channel Crosstalk –55 –75 dB typ dB typ 65 100 13 MHz typ MHz typ pF typ 85 42 pF typ pF typ 96 48 pF typ pF typ 10 µA typ µA max –3 dB Bandwidth ADG738 ADG739 CS (OFF) CD (OFF) ADG738 ADG739 CD, CS (ON) ADG738 ADG739 POWER REQUIREMENTS IDD 20 NOTES 1 Temperature ranges are as follows: B Versions: –40°C to +85°C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice. REV. 0 –3– VIN = VINL or VINH RL = 300 Ω, CL = 35 pF, Test Circuit 5; VS1 = 2 V RL = 300 Ω, CL = 35 pF, Test Circuit 5; VS1 = 2 V RL = 300 Ω, CL = 35 pF; VS = 2 V, Test Circuit 5 VS = 1.5 V, RS = 0 Ω, CL = 1 nF; Test Circuit 6 RL = 50 Ω, CL = 5 pF, f = 10 MHz; RL = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 8 RL = 50 Ω, CL = 5 pF, f = 10 MHz; RL = 50 Ω, CL = 5 pF, f = 1 MHz; Test Circuit 7 14 1 VS = 0 V to VDD, IS = 10 mA VDD = 3.3 V VS = 3 V/1 V, VD = 1 V/3 V; Test Circuit 2 VD = 3 V/1 V, VD = 1 V/3 V; Test Circuit 3 VD = VS = 3 V/1 V, Test Circuit 4 ISINK = 6 mA tOFF 25 VS = 0 V to VDD, IS = 10 mA; Test Circuit 1 VS = 0 V to VDD, IS = 10 mA max pF typ ns typ ns max ns typ ns max ns typ ns min pC typ 70 Test Conditions/Comments RL = 50 Ω, CL = 5 pF, Test Circuit 8 VDD = 3.3 V Digital Inputs = 0 V or 3.3 V ADG738/ADG739 TIMING CHARACTERISTICS1, 2 (V DD = 2.7 V to 5.5 V. All specifications –40ⴗC to +85ⴗC, unless otherwise noted.) Parameter Limit at TMIN, TMAX Unit Conditions/Comments fSCLK t1 t2 t3 t4 t5 t6 t7 t8 t9 3 30 33 13 13 0 5 4.5 0 33 20 MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min SCLK Cycle Frequency SCLK Cycle Time SCLK High Time SCLK Low Time SYNC to SCLK Active Edge Setup Time Data Setup Time Data Hold Time SCLK Falling Edge to SYNC Rising Edge Minimum SYNC High Time SCLK Rising Edge to DOUT Valid NOTES 1 See Figure 1. 2 All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (V IL + VIH)/2. 3 CL = 20 pF, RL = 1 kΩ. Specifications subject to change without notice. t1 SCLK t2 t8 t3 t7 t4 SYNC t6 t5 DIN DB7 DB0 t9 DOUT DB71 DB01 NOTE DATA FROM LAST WRITE CYCLE 1 Figure 1. 3-Wire Serial Interface Timing Diagram –4– REV. 0 ADG738/ADG739 PIN FUNCTION DESCRIPTIONS ADG738 ADG739 Mnemonic Function 1 1 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. These devices can accommodate serial input rates of up to 30 MHz. Active low control input that clears the input register and turns all switches to the OFF condition. Serial Data Input. Data is clocked into the 8-bit input register on the falling edge of the serial clock input. Source. May be an input or output. Drain. May be an input or output. Source. May be an input or output. Power Supply Input. These parts can be operated from a supply of 2.7 V to 5.5 V. Ground Reference. Data Output. This allows a number a parts to be daisy-chained. Data is clocked out of the input shift register on the rising edge of SCLK. This is an open drain output which should be pulled to the supply with an external resistor. Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and the input shift register is enabled. Data is transferred on the falling edges of the following clocks. Taking SYNC high updates the switch conditions. RESET 2 3 3 DIN 4, 5, 6, 7 8 9, 10, 11, 12 13 14 15 4, 5, 6, 7 8, 9 10, 11, 12, 13 14 15 16 Sxx Dx Sxx VDD GND DOUT 16 2 SYNC PIN CONFIGURATIONS SCLK 1 16 SYNC SCLK 1 16 DOUT RESET 2 15 DOUT SYNC 2 15 GND 14 GND DIN 3 13 VDD S1A 4 12 S5 S2A 5 S3 6 11 S6 S3A 6 11 S3B S4 7 10 S7 S4A 7 10 S4B D 8 9 S8 DA 8 9 DB DIN 3 ADG738 S1 4 S2 5 TOP VIEW (Not to Scale) ADG739 14 VDD 13 S1B TOP VIEW (Not to Scale) 12 S2B ORDERING GUIDE Model Temperature Range Package Description Package Option ADG738BRU ADG739BRU –40°C to +85°C –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) RU-16 RU-16 REV. 0 –5– ADG738/ADG739 ABSOLUTE MAXIMUM RATINGS 1 TSSOP Package θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . 150.4°C/W θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . 27.6°C/W Lead Temperature, Soldering (10 seconds) . . . . . . . . . . 300°C IR Reflow, Peak Temperature . . . . . . . . . . . . . . . . . . . . 220°C (TA = 25°C unless otherwise noted.) VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Analog, Digital Inputs2 . . . . . . . . . . –0.3 V to VDD + 0.3 V or 30 mA, Whichever Occurs First Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA (Pulsed at 1 ms, 10% Duty Cycle max) Continuous Current, Each S . . . . . . . . . . . . . . . . . . . . . 30 mA Continuous Current D, ADG739 . . . . . . . . . . . . . . . . . 80 mA Continuous Current D, ADG738 . . . . . . . . . . . . . . . . 120 mA Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Overvoltages at IN, S or D will be clamped by internal diodes. Current should be limited to the maximum ratings given. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG738/ADG739 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE TERMINOLOGY VDD Most Positive Power Supply Potential. CD, CS (ON) “ON” Switch Capacitance. Measured with reference to ground. IDD Positive Supply Current. GND Ground (0 V) Reference. CIN Digital Input Capacitance. S Source Terminal. May be an input or output. tON D Drain Terminal. May be an input or output. Delay time between the 50% and 90% points of the SYNC rising edge and the switch “ON” condition. VD (VS) Analog Voltage on Terminals D, S. tOFF RON Ohmic Resistance between D and S. ∆RON On Resistance Match Between any Two Channels, i.e., RONmax – RONmin. Delay time between the 50% and 90% points of the SYNC rising edge and the switch “OFF” condition. tD “OFF” time measured between the 80% points of both switches when switching from one switch to another. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Off Isolation A measure of unwanted signal coupling through an “OFF” switch. Crosstalk A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth The frequency at which the output is attenuated by 3 dBs. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. IS (OFF) Source Leakage Current with the Switch “OFF.” ID (OFF) Drain Leakage Current with the Switch “OFF.” ID, IS (ON) Channel Leakage Current with the Switch “ON.” VINL Maximum Input Voltage for Logic “0.” VINH Minimum Input Voltage for Logic “1.” IINL(IINH) Input Current of the Digital Input. CS (OFF) “OFF” Switch Source Capacitance. Measured with reference to ground. CD (OFF) “OFF” Switch Drain Capacitance. Measured with reference to ground. On Response The frequency response of the “ON” switch. Insertion Loss –6– The loss due to the ON resistance of the switch. REV. 0 Typical Performance Characteristics–ADG738/ADG739 8 TA = 25ⴗC VSS = 0V VDD = 2.7V 6 VDD = 3.3V 5 4 VDD = 4.5V VDD = 5.5V 3 8 VDD = 5V VSS = 0V 7 ON RESISTANCE – ⍀ ON RESISTANCE – ⍀ 7 2 6 5 4 +25ⴗC 3 +85ⴗC 2 –40ⴗC 1 0 2 3 5 4 0 VD, VS, DRAIN OR SOURCE VOLTAGE – V 2 3 4 Figure 3. On Resistance as a Function of VD (VS) for Different Temperatures 0.12 0.12 VDD = 5V VSS = 0V TA = 25ⴗC 0.08 CURRENT – nA ID (OFF) 0 1 2 3 VD (VS) – Volts 4 0.00 IS (OFF) –0.04 ID (OFF) VDD = 5V VSS = 0V 0.30 0.20 0.15 –0.12 5 ID (OFF) 0.10 ID (ON) 0.05 0.00 0 0.5 1.0 1.5 2.0 VD (VS) – Volts 2.5 3.0 Figure 6. Leakage Currents as a Function of VD (VS) IS (OFF) –0.05 15 25 35 45 55 65 TEMPERATURE – ⴗC TA = 25ⴗC 10 VDD = 5V VSS = 0V 1m CURRENT – A 0.20 0.15 0.10 0 VDD = 5V 100 VDD = 3V VDD = 3V VSS = 0V –10 –20 ID (OFF) 0.05 85 20 TA = 25ⴗC 0.25 75 Figure 7. Leakage Currents as a Function of Temperature 10m VDD = 3V VSS = 0V 0.30 10 –30 0.00 IS (OFF) 25 35 45 55 65 TEMPERATURE – ⴗC ID (ON) 75 85 Figure 8. Leakage Currents as a Function of Temperature REV. 0 0.35 –0.08 0.35 –0.05 15 +25ⴗC 2 Figure 4. On Resistance as a Function of VD (VS) for Different Temperatures QINJ – pC CURRENT – nA IS (OFF) Figure 5. Leakage Currents as a Function of VD (VS) CURRENT – nA ID (ON) 0.04 0.00 –0.12 –40ⴗC 3 0.25 0.04 –0.08 4 1.0 1.5 2.0 2.5 3.0 0 0.5 VD OR VS – DRAIN OR SOURCE VOLTAGE – V VDD = 3V VSS = 0V TA = 25ⴗC ID (ON) –0.04 +85ⴗC 5 0 5 VD OR VS – DRAIN OR SOURCE VOLTAGE – V Figure 2. On Resistance as a Function of VD (VS) 0.08 1 CURRENT – nA 1 6 1 1 0 0 VDD = 3V VSS = 0V 7 ON RESISTANCE – ⍀ 8 1 10k 100k 1M 10M FREQUENCY – Hz 100M Figure 9. Input Currents vs. Switching Frequency –7– –40 0 1 2 3 VOLTAGE – Volts 4 5 Figure 10. Charge Injection vs. Source Voltage ADG738/ADG739 VDD = 5V TA = 25ⴗC TON, VDD = 3V 45 ATTENUATION – dB 35 TON, VDD = 5V 30 25 TOFF, VDD = 3V 20 15 10 –40 –60 –80 –40 –60 –80 –100 –100 5 VDD = 5V TA = 25ⴗC –20 ATTENUATION – dB –20 40 TIME – ns 0 0 50 TOFF, VDD = 5V 0 –40 –20 0 20 40 TEMPERATURE – ⴗC 60 80 Figure 11. TON /TOFF Times vs. Temperature –120 30k 100k 1M 10M FREQUENCY – Hz 100M Figure 12. Off Isolation vs. Frequency –120 30k 100k 1M 10M FREQUENCY – Hz 100M Figure 13. Crosstalk vs. Frequency 0 ATTENUATION – dB VDD = 5V TA = 25ⴗC –5 ADG738 ADG739 –10 –15 –20 30k 100k 1M 10M FREQUENCY – Hz 100M Figure 14. On Response vs. Frequency –8– REV. 0 ADG738/ADG739 GENERAL DESCRIPTION MICROPROCESSOR INTERFACING The ADG738 and ADG739 are serially controlled, 8-channel and dual 4-channel Matrix Switches respectively. While providing the normal multiplexing and demultiplexing functions, these parts also provide the user with more flexibility as to where their signal may be routed. Each bit of the 8-bit serial word corresponds to one switch of the part. A Logic 1 in the particular bit position turns on the switch, while a Logic 0 turns the switch off. Because each switch is independently controlled by an individual bit, this provides the option of having any, all, or none of the switches ON. This feature may be particularly useful in the demultiplexing application where the user may wish to direct one signal from the drain to a number of outputs (sources). Care must be taken, however, in the multiplexing situation where a number of inputs may be shorted together (separated only by the small on resistance of the switch). Microprocessor interfacing to the ADG738/ADG739 is via a serial bus that uses standard protocol compatible with microcontrollers and DSP processors. The communications channel is a 3-wire (minimum) interface consisting of a clock signal, a data signal, and a synchronization signal. The ADG738/ADG739 requires an 8-bit data word with data valid on the falling edge of SCLK. Data from the previous write cycle is available on the DOUT pin. The following figures illustrate simple 3-wire interfaces with popular microcontrollers and DSPs. ADSP-21xx to ADG738/ADG739 An interface between the ADG738/ADG739 and the ADSP21xx is shown in Figure 16. In the interface example shown, SPORT0 is used to transfer data to the Matrix Switch. The SPORT control register should be configured as follows: internal Clock operation, alternate framing mode; active low framing signal. When changing the switch conditions, a new 8-bit word is written to the input shift register. Some of the bits may be the same as the previous write cycle, as the user may not wish to change the state of some switches. In order to minimize glitches on the output of these switches, the part cleverly compares the state of switches from the previous write cycle. If the switch is already in the ON condition, and is required to stay ON, there will be minimal glitches on the output of the switch. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. As the data is clocked out of the DSP on the rising edge of SCLK, no glue logic is required to interface the DSP to the Matrix Switch. The update of each switch condition takes place automatically when TFS is taken high. TFS POWER-ON RESET ADSP-21xx* On power-up of the device, all switches will be in the OFF condition and the internal shift register is filled with zeros and will remain so until a valid write takes place. DT SCLK SYNC DIN ADG738/ ADG739 SCLK *ADDITIONAL PINS OMITTED FOR CLARITY. SERIAL INTERFACE Figure 16. ADSP-21xx to ADG738/ADG739 Interface The ADG738 and ADG739 have a 3-wire serial interface (SYNC, SCLK, and DIN), which is compatible with SPI, QSPI, MICROWIRE interface standards and most DSPs. Figure 1 shows the timing diagram of a typical write sequence. 8051 Interface to ADG738/ADG739 A serial interface between the ADG738/ADG739 and the 8051 is shown in Figure 17. TXD of the 8051 drives SCLK of the ADG738/ADG739, while RXD drives the serial data line, DIN. P3.3 is a bit-programmable pin on the serial port and is used to drive SYNC. Data is written to the 8-bit shift register via DIN under the control of the SYNC and SCLK signals. Data may be written to the shift register in more or less than eight bits. In each case the shift register retains the last eight bits that were written. The 8051 provides the LSB of its SBUF register as the first bit in the data stream. The user will have to ensure that the data in the SBUF register is arranged correctly as the switch expects MSB first. When SYNC goes low, the input shift register is enabled. Data from DIN is clocked into the shift register on each falling edge of SCLK. Each bit of the 8-bit word corresponds to one of the eight switches. Figure 15 shows the contents of the input shift register. Data appears on the DOUT pin on the rising edge of SCLK suitable for daisy-chaining, delayed, of course, by eight bits. When all eight bits have been written into the shift register, the SYNC line is brought high again. The switches are updated with the new configuration and the input shift register is disabled. With SYNC held high, any further data or noise on the DIN line will have no effect on the shift register. S7 80C51/80L51* DB0 (LSB) DB7 (MSB) S8 When data is to be transmitted to the Matrix Switch, P3.3 is taken low. Data on RXD is clocked out of the microcontroller on the rising edge of TXD and is valid on the falling edge. As a result no glue logic is required between the ADG738/ADG739 and microcontroller interface. S6 S5 S4 S3 S2 S1 DATA BITS SYNC RXD DIN TXD SCLK ADG738/ ADG739 *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 15. Input Shift Register Contents REV. 0 P3.3 Figure 17. 8051 Interface to ADG738/ADG739 –9– ADG738/ADG739 MC68HC11 Interface to ADG738/ADG739 Figure 18 shows an example of a serial interface between the ADG738/ADG739 and the MC68HC11 microcontroller. SCK of the 68HC11 drives the SCLK of the Matrix Switch, while the MOSI output drives the serial data line, DIN. SYNC is driven from one of the port lines, in this case PC7. allows for different combinations of the four serial devices to be addressed at any one time. If more devices need to be addressed via one chip select line, the ADG738 is an 8-channel device and would allow further expansion of the chip select scheme. There may be some digital feedthrough from the digital input lines because SCLK and DIN are permanently connected to each device. Using a burst clock will minimize the effects of digital feedthrough on the analog channels. SYNC PC7 ADG739 MC68HC11* DIN MOSI ADG738/ ADG739 SYNC DIN SCLK SCK SCLK *ADDITIONAL PINS OMITTED FOR CLARITY. VDD Figure 18. MC68HC11 Interface to ADG738/ADG739 ADG738 SYNC 1/2 OF ADG739 The 68HC11 is configured for master mode; MSTR = 1, CPOL = 0 and CPHA = 1. When data is transferred to the part, PC7 is taken low, data is transmitted MSB first. Data appearing on the MOSI output is valid on the falling edge of SCK. If the user wishes to verify the data previously written to the input shift register, the DOUT line could be connected to MISO of the MC68HC11, and with SYNC low, the shift register would clock data out on the rising edges of SCLK. S2A DA SYNC1 S3A S4A FROM CONTROLLER OR DSP SCLK OTHER SPI DEVICE SYNC DIN SCLK SCLK DIN SYNC OTHER SPI DEVICE SYNC2 APPLICATIONS Expand the Number of Selectable Serial Devices Using an ADG739 The dual 4-channel ADG739 multiplexer can be used to multiplex a single chip select line in order to provide chip selects for up to four devices on the SPI bus. Figure 19 illustrates the ADG739 in such a typical configuration. All devices receive the same serial clock and serial data, but only one device will receive the SYNC signal at any one time. The ADG739 is a serially controlled device also. One bit programmable pin of the microcontroller is used to enable the ADG739 via SYNC2, while another bit programmable pin is used as the chip select for the other serial devices, SYNC1. Driving SYNC2 low enables changes to be made to the addressed serial devices. By bringing SYNC1 low, the selected serial device hanging from the SPI bus will be enabled and data will be clocked into its shift register on the falling edges of SCLK. The convenient design of the matrix switch DIN S1A SYNC SCLK DIN SCLK DIN Figure 19. Addressing Multiple Serial Devices Using an ADG739 Daisy-Chaining Multiple ADG738s A number of ADG738 matrix switches may be daisy-chained simply by using the DOUT pin. DOUT is an open drain output that should be pulled to the supply with an external resistor. Figure 20 shows a typical implementation. The SYNC pin of all three parts in the example are tied together. When SYNC is brought low, the input shift registers of all parts are enabled, data is written to the parts via DIN, and clocked through the shift registers. When the transfer is complete, SYNC is brought high and all switches are updated simultaneously. Further shift registers may be added in series. VDD R SCLK R SCLK SCLK ADG739 DIN SYNC DIN SYNC DOUT R SCLK ADG739 DIN DOUT SYNC ADG739 DIN SYNC DOUT TO OTHER SERIAL DEVICES Figure 20. Multiple ADG739 Devices in a Daisy-Chained Configuration –10– REV. 0 ADG738/ADG739 TEST CIRCUITS IDS VDD V1 VDD IS (OFF) S1 A S2 S VS D D S8 VD VS GND RON = V1/IDS Test Circuit 3. IS (OFF) Test Circuit 1. On Resistance VDD VDD VDD VDD S1 S1 S2 D ID (OFF) S8 ID (ON) S8 A D A VD VD GND VS GND VS Test Circuit 2. ID (OFF) Test Circuit 4. ID (ON) VDD VDD SYNC SYNC 50% 50% ADG738* S1 VS1 S2 THRU S7 S8 VS1 VS8 90% VOUT D GND CL 35pF RL 300⍀ VOUT VS1 = VS8 tOFF * SIMILAR CONNECTION FOR ADG739 tOPEN tON Test Circuit 5. Switching Times and Break-Before-Make Times SYNC VDD ADG738* SWITCH ON RS VS S D SWITCH OFF VOUT QINJ = CL x ⌬VOUT CL 1nF INPUT LOGIC GND * SIMILAR CONNECTION FOR ADG739 Test Circuit 6. Charge Injection REV. 0 80% 80% VOUT 90% –11– ⌬VOUT ADG738/ADG739 VDD VDD VDD VDD ADG738* S1 D RL 50⍀ S2 VS VS ADG738* VOUT D S8 GND GND RL 50⍀ C3834–8–4/00 (rev. 0) 01003 50⍀ S1 S8 VOUT * SIMILAR CONNECTION FOR ADG739 *SIMILAR CONNECTION FOR ADG739 CHANNEL-TO-CHANNEL CROSSTALK = 20LOG10(VOUT/VS) S1 IS SWITCHED OFF FOR OFF ISOLATION MEASUREMENTS AND ON FOR BANDWIDTH MEASUREMENTS OFF ISOLATION = 20LOG10(VOUT/VS) INSERTION LOSS = 20LOG10 Test Circuit 7. Channel-to-Channel Crosstalk VOUT WITH SWITCH VOUT WITHOUT SWITCH Test Circuit 8. Off Isolation and Bandwidth OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead TSSOP (RU-16) 0.201 (5.10) 0.193 (4.90) 16 9 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 8 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0256 (0.65) 0.0118 (0.30) BSC 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) 8ⴗ 0ⴗ 0.028 (0.70) 0.020 (0.50) PRINTED IN U.S.A. SEATING PLANE 0.0433 (1.10) MAX –12– REV .0