ETC RD-19230FX-203

RD-19230
16-BIT MONOLITHIC TRACKING
RESOLVER-TO-DIGITAL CONVERTER
DESCRIPTION
FEATURES
The RD-19230 is a versatile, low cost,
state-of-the-art 16-bit monolithic Resolverto-Digital Converter. This single chip converter offers programmable features such
as resolution, bandwidth, velocity output
scaling and encoder emulation.
Resolution programming allows selection of 10, 12, 14, or 16-bit, with accuracies to 2.3 min. The parallel digital data
and the internal encoder emulation signals (A QUAD B) have independent resolution control. Internal encoder emulation will permit inhibiting (freezing) the
parallel digital data without interrupting
the A and B outputs.
The internal Synthesized Reference section eliminates errors due to quadrature
voltage and ensures operation with a
rotor-to-stator phase shift of up to 45
degrees. The velocity output (VEL) can
be used in place of a tachometer. It has a
range of ±4 V relative to analog ground.
The velocity scale factor/tracking rate is
programmed with a single resistor. This
converter provides the option of using a
second set of filter components which can
be used in dual bandwidth or switch on the
fly applications.
•
•
•
•
Accuracy up to 2.3 arc minutes
The RD-19230 is available with operating
temperature ranges of 0° to +70°C and
-40° to +85°C.
•
Internal Encoder Emulation
with Independent Resolution
Control
•
Differential Resolver Input
Mode
•
Velocity Output Eliminates
Tachometer
•
Built-In-Test (BIT) Output,
No 180° Hangup
•
-40° to +85°C Operating
Temperature
APPLICATIONS
With its low cost, small size, high accuracy, and versatile performance, the RD19230 converter is ideal for use in modern
high performance industrial control systems. It is ideal for users who wish to use
a resolver input in their encoder based
system. Typical applications include motor
control, machine tool control, robotics, and
process control.
Cbw
RH
V
E
L
S
J
1
S
J
2
+5 Volt Only Option
Programmable Resolution,
Bandwidth and Tracking Rate
Rb
Cbw/10
Rb
Cbw
Cbw/10
VEL2 VEL1
SYNTHESIZED
REFERENCE
SIN
-S
-
+S
+
CONTROL
TRANSFORMER
COS
-C
-
+C
+
VDDP
PCAP
NCAP
VSSP
RL BIT
V
E
L
Internal Synthesized Reference
GAIN
SHIFT
-
DEMODULATOR
VEL
+
D1 D0
D1
-5 V
INVERTER
D0
A GND
VDD
GND
VSS
EM
RV
HYSTERESIS
VCO
&
TIMING
-VCO
R CLK
INTERNAL
ENCODER
EMULATION
DATA
LATCH
INH
16 BIT
UP/DOWN
COUNTER
EL
BIT 1 - BIT 16
D1 D0
A QUAD B A U/B
ZIP_EN
R SET
CB/ZIP
UP/DN
FIGURE 1. RD-19230 SERIES BLOCK DIAGRAM
© 1999 Data Device Corporation
TABLE 1. RD-19230 SPECIFICATIONS (CONTINUED)
TABLE 1. RD-19230 SPECIFICATIONS
These specs apply over the rated power supply, temperature, and reference frequency ranges; 10% signal amplitude variation, and 10% harmonic distortion.
PARAMETER
UNIT
RESOLUTION
Bits
FREQUENCY RANGE
Hz
10, 12, 14, or 16 (note 1 & 2)
47-1k(4)
1k - 4k
REFERENCE
Type
Voltage: differential
single ended
overload
Frequency
Input Impedance
(+REF, -REF)
Differential
Vp-p ±10 max.
Vp ±5 max.
Vrms ±25 continuous; ±100 transient
Hz DC to 10k
Ω
10M min. || 20 pf
SIGNAL INPUT
Type
Voltage: operating
overload
Input impedance
DIGITAL INPUTS
TTL / CMOS Compatible
Inputs
Logic 0 enables; Data stable
within 150 ns
Logic 1 = High Impedance; Data
High Z within 100 ns
CMOS Compatable Inputs
SHIFT
UP/DN
A QUAD B
A, B
Drive Capability
DYNAMIC
CHARACTERISTICS
Resolution
Tracking Rate (min)(note 6)
Bandwidth (Closed Loop)
Ka
A1
A2
A
B
Acceleration (1 LSB lag)
Settling Time (179° step)
VELOCITY
CHARACTERISTICS
Polarity
Voltage Range (Full Scale)
Scale Factor Error
Scale Factor TC
Reversal Error
Linearity
Zero Offset
Zero Offset TC
Load
POWER SUPPLIES
Nominal Voltage
Voltage Range
Max Volt. w/o Damage
Current
Logic 0 = 0.8 V max.
Logic 1 = 2.0 V min.
Loading = 10 µA max P.U. current source to +5 V || 5 pF max.
CMOS transient protected
Enable Bits 1 to 8 (EM)
ZIP_EN
Built-In-Test (BIT)
(+S, -S, SIN, +C, -C, COS)
Resolver, differential,
groundbased
Vrms 2 ±15%
Vrms ±25 continuous
Ω
10M min || 10 pF.
Logic 0 inhibits; Data stable within 150 ns
Resolution and Mode
Control (D1 & D0)
(See notes 1 & 2)
Zero Index Pulse (ZIP)
(note 5)
45 max. from 400 Hz to 10kHz
Inhibit (INH)
Enable Bits 9 to 16 (EL)
Converter Busy (CB)
4 +1 LSB 4 +1 LSB 5 +1 LSB
2 +1 LSB 2 +1 LSB 3 +1 LSB
±1
±1
±2
±1
±1
±2
Mode D1 D0 Resolution
resolver 0
0
10 bits
0
1
12 bits
1
0
14 bits
1
1
16 bits
LVDT -5V
0
8 bits
0
-5V
10 bits
1
-5V
12 bits
-5V -5V
14 bits
Logic 0 enables ZIP
Logic 1 enables CB
Logic 0 = 1.5 V max.
Logic 1 = 3.5 V min.
negative voltage = -3.5 V min.
Logic 1 select VEL1 components
Logic 0 select VEL2 components
TEMPERATURE RANGE
Operating
-30X
-20X
Storage
Logic 1 will increase gain by 4
Logic 0 will decrease gain by 4
-5 V gain remains constant
PHYSICAL
CHARACTERISTICS
Size: 64-pin Quad Flat Pack
WEIGHT
Logic 0 enables encoder emulation
Falling edge latches encoder
resolution
2
VALUE
10, 12, 14, or 16 parallel lines;
natural binary angle positive
logic (see note 2)
0.25 to 0.75 µs positive pulse
leading edge initiates counter
update. (CB functions with
ZIP_EN pin tied to +5 V or NC)
Logic 1 at all 0’s
(ZIP_EN pin tied to GND)
Logic 0 for BIT condition.
~ ±100 LSB’s of error with a filter of 500 µs, Loss of Signal
(LOS) less than 500 mV, or
Loss of Reference (LOR) less
than 500 mV
Incremental Encoder Output
50 pF+
Logic 0: 1 TTL load, 1.6 mA at
0.4 V max.
Logic 1; 10 TTL loads, -0.4 mA
at 2.8 V min.
Logic 0; 100 mV max. driving
CMOS
Logic 1; +5 V supply minus
100 mV min. driving CMOS
High Z; 10 µA || 5 pF max.
4k - 10k
Min
Min
LSB
LSB
deg
UNIT
DIGITAL OUTPUTS
Parallel Data (1-16)
VALUE
ACCURACY -XX2
-XX3 (note 3)
REPEATABILITY
DIFFERENTIAL LINEARITY
SYNTHESIZED REFERENCE
±Sig/Ref Phase Shift Correction
PARAMETER
(at maximum bandwidth)
bits
rps
Hz
1/sec2
1/sec
1/sec
1/sec
1/sec
deg/s2
msec
10
1152
1200
5.7M
19.5
295k
2400
1200
2M
2
12
14
288
72
1200 600
5.7M 1.4M
19.5 4.9
295k 295k
2400 1200
1200 600
500k 30k
8
20
16
18
300
360k
1.2
295k
600
300
2k
50
Positive for increasing angle
±4 (at nominal power supply)
V
10 typ
20 max
%
100 typ
200 max
PPM/°C
0.75 typ
1.3 max
%
0.25 typ
0.50 max
%
5 typ
10 max
mV
15 typ
30 max
µV/°C
8 max
kΩ
(note 6)
V
+5 (VDD)
-5 (VSS)
%
±5
±5
V
+7
-7
mA
25 max. (each)
°C
°C
°C
0 to +70
-40 to +85
-40 to +85
in(mm)
0.52 x 0.52 (13.2 x 13.2)
oz(g)
0.018 ( 0.5 )
TABLE 1 notes:
1. Unused data bits are set to logic “0.”
2. In LVDT mode, Bit 3 is the MSB and resolution is
programmable to 8,10, 12, and 14 bits.
3. Accuracy in LVDT mode is 0.15% + 1 LSB of full scale.
4. In the frequency range of 47Hz to 1kHz, there will be
1 LSB of jitter at quadrant boundaries.
5. The maximum phase shift tolerance will degrade linearly
from 45 degrees at 400 Hz to 30 degrees at 60 Hz.
6. When using the -5V inverter, the VDD supply current will
double and VSSP can be up to 20% low, or -4V.
7. || = in parallel with.
clamps to the ±5 VDC supplies. By performing the following
trigonometric identity, SINθ(COSφ) - COSθ(SINφ) = SIN(θ-φ),
the Control Transformer (CT) compares the analog input signals
( θ ) with the digital output ( φ ), resulting in an error signal proportional to the sin of the angular difference. The CT uses a
combination of amplifiers, switches, logic and capacitors in precision ratios to perform the calculation.
Note: The error output of the CT is normally sinusoidal, but
in LVDT mode, it is triangular (linear) and can be used to
convert any linear transducer output.
The converter accuracy is limited by the precision of
puting elements in the CT. Instead of a traditional
resistor network, this converter uses capacitors with
controlled ratios. Sampling techniques are used to
errors due to voltage drift and op-amp offsets.
THEORY OF OPERATION
The RD-19230 is a mixed signal CMOS IC containing analog
input and digital output sections. Precision analog circuitry is
merged with digital logic to form a complete high-performance
tracking resolver-to-digital converter. For user flexibility and convenience, the converter bandwidth, dynamics, and velocity scaling are externally set with passive components.
the comprecision
precisely
eliminate
The error processing is performed using the industry standard
technique for Type II tracking converters. The DC error is integrated yielding a velocity voltage which in turn drives a voltage
controlled oscillator (VCO). This VCO is an incremental integrator (constant voltage input to position rate output) which, together with the velocity integrator, forms a Type II servo feedback
loop. A lead in the frequency response is introduced to stabilize
the loop and another lag at higher frequency is introduced to
reduce the gain and ripple at the carrier frequency and above.
The settings of the various error processor gains and break frequencies are done with external resistors and capacitors so that
the converter loop dynamics can be easily controlled by the user.
FIGURE 1 is the Functional Block Diagram of RD-19230. The
analog conversion electronics require ±5 VDC power supplies,
and the converter contains a charge pump to provide the user
with the option of a single-ended +5 VDC supply. The converter
front-end consists of differential sine and cosine input amplifiers
which are protected up to ±25 V with 2 kΩ resistors and diode
RB CBW
VEL
C BW /10
VEL SJ1
RV
VEL
-VCO
50 pf
C VCO
CT
RESOLVER
INPUT
(θ)
+
R1
GAIN
-
VCO
DEMOD
1
CS FS
11 mV/LSB
±1.25 V
THRESHOLD
16 BIT
UP/DOWN
COUNTER
DIGITAL
OUTPUT
(φ)
H=1
FIGURE 2. TRANSFER FUNCTION BLOCK DIAGRAM #1
3
TRANSFER FUNCTION AND BODE PLOT
GENERAL SETUP CONDITIONS
The dynamic performance of the converter can be determined
from its Transfer Function Block Diagrams and Bode Plots (open
and closed loop). These are shown in FIGURES 2, 3, and 4.
DDC has external component selection software which considers all the criteria below. In a simple fashion, it asks the key system parameters (carrier frequency, resolution, bandwidth, and
tracking rate) needed to derive the external component values.
The open loop transfer function is as follows:
The following recommendations should be considered when
installing the RD-19230 R/D converter:
A2 S +1
B
Open Loop Transfer Function =
2
S
S
+1
10B
(
(
)
)
The components of gain coefficient are error gradient, integrator
gain, and VCO gain. These can be broken down as follows:
1) In setting the bandwidth (BW) and Tracking Rate (TR) (selecting five external components), the system requirements need to
be considered. For the greatest noise immunity, select the minimum BW and TR the system will allow. Selecting a fBW that is
too low relative to the maximum application tracking rate can create a spin-around condition in which the converter never settles.
The relationship to insure against this condition is detailed in
TABLE 2.
- Error Gradient = 0.011 volts per LSB (CT + Error Amp + Demod
with 2 Vrms input)
2) Power supplies are ±5 VDC. For lowest noise performance it
is recommended that a 0.1 µF or larger cap be connected from
each supply to ground near the converter package.
where A is the gain coefficient and A2=A1A2
and B is the frequency of lead compensation.
- Integrator Gain = Cs Fs volts per second per volt
1.1 CBW
- VCO Gain =
3) Resolver inputs and velocity output are referenced to AGND.
This pin should be connected to GND near the converter package. Digital currents flowing through ground will not disturb the
analog signals.
1
LSBs per second per volt
1.25 RV CVCO
where: Cs = 10 pF
Fs = 67 kHz when R CLK = 30 kΩ
CVCO = 50 pF
4) This device has several high impedance amplifier inputs
(+C, -C, +S, -S, -VCO, VEL SJ1, and VEL SJ2) that are sensitive
to noise coupling. External components should be connected as
close to the converter as possible.
RV, RB, and CBW are selected by the user to set velocity scaling
and bandwidth.
2d
-1
b/o
ct
(CRITICALLY DAMPED)
GAIN = 4
2A
VELOCITY
OUT
ERROR PROCESSOR
RESOLVER
INPUT
(θ)
CT
+
e
-
VCO
A2
S
A1 S + 1
B
S S +1
10B
OPEN LOOP
B
A
-6
db
ω (rad/sec)
10B
/oc
(B = A/2)
DIGITAL
POSITION
OUT (φ)
t
GAIN = 0.4
f BW = BW (Hz) =
H=1
CLOSED LOOP
FIGURE 3. TRANSFER FUNCTION
BLOCK DIAGRAM #2
2A
2 2A
FIGURE 4. BODE PLOTS
4
2A
π
ω (rad/sec)
5) Setup of bandwidth and velocity scaling for the optimized critically damped case should proceed as follows:
Note: Use of the -5 V inverter is not recommended for applications that require the highest BW and Tracking Rates.
- Select the desired f BW (closed loop) based on overall
system dynamics.
HIGHER TRACKING RATES AND CARRIER
FREQUENCIES.
- Select f carrier ≥ 3.5f BW
Maximum tracking rate is limited by the velocity voltage saturation (nominally 4 V) and the maximum internal clock rate (nominally 1,333,333 Hz for R CLK = 30k). To achieve higher tracking
- Select the applications tracking rate (in accordance with TABLE 3),
and use appropriate values for R SET and R CLK
Full Scale Velocity Voltage
Tracking Rate (rps) x 2 resolution x 50 pF x 1.25 V
- Compute Rv =
TABLE 3. MAX TRACKING RATE (MIN) IN RPS
3.2 x Fs (Hz) x 108
- Compute CBW (pF) =
Rv x (f BW)2
- Where Fs = 67 kHz for R CLK = 30 KΩ
100 kHz for R CLK = 20 KΩ
125 kHz for R CLK = 15 KΩ
RESOLUTION
R SET
Ω)
(Ω
R CLK
Ω)
(Ω
12
14
16
30k** or open
30k
1152 288
72
18
23k
20k
1728 432 108 27
23k
15k
2304 576
10
*
*
0.9
CBW x f BW
- Compute RB =
TABLE 4. CARRIER FREQUENCY (MAX)
IN KHZ
- Compute
CBW
10
R CLK
Ω)
(Ω
10
12
14
16
30k** or open
30k
10
10
7
5
23k
30k
10
10
10
7
23k
20k
10
10
10
10
23k
15k
10
10
*
*
As an example:
Calculate component values for a 16 bit converter with 100Hz
bandwidth, a tracking rate of 10 RPS and a full scale velocity
of 4 Volts.
- Rv =
RESOLUTION
R SET
Ω)
(Ω
* Not recommended.
** The use of a high quality thin-film resistor will provide better temperature
stability than leaving open.
4V
= 97655 Ω
10 rps x 216 x 50 pF x 1.25 V
- Compute CBW (pF) =
- Compute RB =
3.2 x 67 kHz x 108
= 21955 pF
97655 x 100 Hz2
+5V
0.9
= 410 kΩ
21955 x 10 -12 x 100 Hz
6) Using the -5V Inverter will eliminate the need for a -5 V supply. Refer to FIGURE 5. for the necessary connections.
+
10 F/10V
When using the built-in -5 V inverter, the maximum tracking rate
should be scaled for a full-scale velocity output of 3.5 V max.
TABLE 2. TRACKING/BW RELATIONSHIP
RPS (MAX)/BW
RESOLUTION
1
10
0.50
12
0.25
14
0.125
16
33
58
27
VDD
VDD
VDDP
26
PCAP
24
NCAP
23
16
17
VSSP
VSS
VSS
25
22
GND
AGND
RD-19230
47 F/10V
+
FIGURE 5. -5V INVERTER CONNECTIONS
5
rates, a higher internal counting rate must be programmed by
setting RCLK to a value less than 30k. See TABLE 4. for the
appropriate values.
internal clock rate. Choose the tracking rate in accordance with
TABLE 3 to insure this relationship. The rates shown in TABLE
3 are based on ~90% of the nominal internal clock rate.
The Rv resistor and an internal 50pF cap are configured as an
integrating circuit that resets to zero after a count occurs in either
direction. This circuit acts as a VCO with velocity as its input and
CB as its output. The Rv resistor and an internal 50pF cap determine the maximum rate of the VCO. Rv must be chosen such
that the maximum rate of the VCO is less than the maximum
The relationship between the velocity voltage and the VCO rate
is given by:
Velocity Voltage
VCO Frequency
=
1
(Rv x 50 pF x 1.25)
TABLE 5. TRANSFORMERS
INPUT SIGNAL INPUT VOLTAGE INPUT FREQUENCY
TYPE
(Vrms)
(HZ)
PART
NUMBER
FIGURE
NUMBER
Synchro
11.8
400
52034
6
Synchro
90
400
52035
6
Resolver
11.8
400
52036
7
Resolver
26
400
52037
7
Resolver
90
400
52038
7
Reference
Reference
400
B-426*
8
Synchro
Synchro
60
52039**
9
Reference
Reference
60
24133**
9
* Beta Transformer
** 60 Hz synchro transformers are active (require ±15V DC power supplies) and are available in two
temperature ranges; -1: -55° to +125° and -3: 0° to + 70°.
6
0.61 MAX
(15.49)
0.61 MAX
(15.49)
0.30 MAX
(7.62)
0.15 MAX
(3.81)
0.09 MAX
(2.29)
0.09 MAX
(2.29)
0.15 MAX
(3.81)
1
3 4 5
11 12
14 15
T1A
T1B
10 9 8 7 6
20 19 18 17 16
0.81 MAX
(20.57)
0.600
(15.24)
0.115 MAX
(2.92)
SIDE VIEW
0.100 (2.54) TYP
TOL NON CUM
TERMINALS
0.025 –0.001 (6.35 –0.03) DIAM
0.125 (3.18) MIN LENGTH
SOLDER PLATED BRASS
BOTTOM VIEW
BOTTOM VIEW
PIN NUMBERS FOR REF. ONLY
Dimensions are shown in inches (mm).
T1A
1
S1
6
-SIN
10
+SIN
5
3
S3
SYNCHRO
INPUT
RESOLVER
OUTPUT
T1B
S2
11
16
-COS
15
20
+COS
FIGURE 6. TRANSFORMER LAYOUT AND SCHEMATIC (SYNCHRO INPUT - 52034/52035)
0.61 MAX
(15.49)
0.61 MAX
(15.49)
0.30 MAX
(7.62)
0.15 MAX
(3.81)
0.09 MAX
(2.29)
0.09 MAX
(2.29)
0.15 MAX
(3.81)
1
3 4 5
11 12
14 15
T1A
T1B
10 9 8 7 6
20 19 18 17 16
0.81 MAX
(20.57)
0.600
(15.24)
0.115 MAX
(2.92)
SIDE VIEW
0.100 (2.54) TYP
TOL NON CUM
TERMINALS
0.025 –0.001 (6.35 –0.03) DIAM
0.125 (3.18) MIN LENGTH
SOLDER PLATED BRASS
BOTTOM VIEW
BOTTOM VIEW
PIN NUMBERS FOR REF. ONLY
Dimensions are shown in inches (mm).
T1A
S1
S3
1
6
-SIN
3
10
+SIN
RESOLVER
INPUT
RESOLVER
OUTPUT
T1B
S4
S2
11
16
-COS
15
20
+COS
FIGURE 7. TRANSFORMER LAYOUT AND SCHEMATIC (RESOLVER INPUT - 52036/52037/52038)
7
CASE IS BLACK AND
NON-CONDUCTIVE
0.32 MAX
(8.13)
0.61 MAX
(15.49)
0.125 MIN
(3.17)
0.25
(6.35)
MIN.
1.14 MAX
(28.96)
0.09 MAX
(2.29)
0.15 MAX
(3.81)
1 2 3
•
•
•
•
+
S3
S1
*
*
+15 V
(+15 V)
+S
(-R)
*
*
5
0.600 0.81 MAX
(15.24) (20.57)
T1A
1.14 MAX
(28.96)
0.85 ±0.010
(21.59 ±0.25)
52039
or
24133
10 9 8 7 6
0.105 (2.66)
SIDE VIEW
0.100 (2.54) TYP
TOL NON CUM
TERMINALS
0.025 ±0.001 (6.35 ±0.03) DIAM
0.125 (3.18) MIN LENGTH
SOLDER-PLATED BRASS
BOTTOM VIEW
(RH)
S2
(RL)
•
+
*
(V)
V
(+R)
+C
(-Vs)
-Vs
•
•
•
(BOTTOM VIEW)
0.13 ±0.03
(3.30 ±0.76)
Dimensions are shown in inches (mm).
0.21 ±0.3
(5.33 ±0.76)
0.175 ±0.010 (4.45 ±0.25)
NONCUMULATIVE
TOLERANCE
1
6
5
10
INPUT
0.42
(10.67)
MAX.
0.040 ±0.002 DIA. PIN.
SOLDER PLATED BRASS
OUTPUT
The mechanical outline is the same for the synchro input transformer (52039) and the reference input transformer (24133),
except for the pins. Pins for the reference transformer are shown
in parenthesis ( ) below. An asterisk * indicates that the pin is
omitted.
FIGURE 9. 60 HZ SYNCHRO AND REFERENCE
TRANSFORMER DIAGRAMS
(SYNCHRO INPUT - 52039 / REFERENCE INPUT - 24133)
FIGURE 8. TRANSFORMER LAYOUT AND SCHEMATIC
(REFERENCE INPUT - B-426)
TYPICAL INPUTS
FIGURES 10 through 14 illustrate typical input configurations.
EXTERNAL
REFERENCE
LO
HI
6
1
B-426
10
5
RL
RH
RESOLVER INPUT OPTION
S1
S3
S4
S2
10
1
-S
SIN
-R
+R
+S
TIA
3
6
11
20
+C
-C
TIB
RD-19230
COS
AGND
15
16
52036(11.8V)
OR
52037(26V)
OR
52038(90V)
GND
OR
RL
RH
SYNCHRO INPUT OPTION
S1
S3
S2
1
3
10
TIA
5
6
11
20
15
+S
+C
TIB
16
52034(11.8V)
OR
52037(90V)
FIGURE 10. TYPICAL TRANSFORMER CONNECTIONS
8
EXTERNAL
REF
LO HI
R1
R2
R3
See Note 3.
+S
S1
S2
RL
RH
-S
SIN
COS
-C
S3
S4
R4
+C
See Note 3.
A GND
GND
RESOLVER
Notes:
1) Resistors selected to limit Vref peak to between 1.5 V and 4 V.
2) External reference LO is grounded, then R3 and R4 are not
needed, and -R is connected to GND.
3) 10k ohms, 1% series current limit resistors are recommended.
FIGURE 11. TYPICAL CONNECTIONS, 2 V RESOLVER, DIRECT INPUT
S3
R1
+S
-S
SIN
-C
COS
R2
S1
S2
R1
+C
R2
S4
A GND
GND
2
R2
=
X Volt
R1 + R2
R1 + R2 should not load the Resolver; it is recommended to use a R2 = 10 kΩ
R1 + R2 Ratio erros will result in Angular errors,
2 cycle, 0.1% Ratio error = 0.029 Peak Error.
FIGURE 12. TYPICAL CONNECTIONS, X- VOLT RESOLVER, DIRECT INPUT
9
SIN
3
S1
S3
1
Rf
Ri
-S
-
2
6
Ri
+S
+
5
Rf
4
A GND
RESOLVER
INPUT
S4
S2
16
COS
13
Rf
Ri
-C
-
15
7
Ri
+C
+
8 10
Rf
12
CONVERTER
S1 and S3, S2 and S4, and RH and RL should be ideally twisted shielded, with the shield tied to GND at the converter.
For DDC-49530: Ri = 70.8 KΩ, 11.8 V input, synchro or resolver.
For DDC-49590: Ri = 270 KΩ, 90 Volt input, synchro or resolver.
Maximum additional error is 1 minute.
When using discrete resistors: Resolver L-L voltage = Ri x 2 Vrms, where Rf ≥ 6 kΩ
Rf
FIGURE 13. DIFFERENTIAL RESOLVER INPUT, USING DDC-49530 (11.8 V) OR DDC-49590 (90 V)
SIN
3
S1
S3
1
Rf
Ri
-S
-
2
6
Ri
+S
+
5
Rf
A GND
SYNCHRO
INPUT
S2
16
Ri
7
Ri
9
4
COS
14
Rf / 3
-C
8
15
-
15
Ri /2
+C
10
Rf / 3
11
+
CONVERTER
S1, S2, S3 should be triple twisted shielded; RH and RL should be twisted shielded;
In both cases the shield should be tied to GND at the converter.
11.8 Volt input = DDC-49530: Ri = 70.8 KΩ, 11.8 V input, synchro or resolver.
90 Volt input = DDC-49590: Ri = 270 KΩ, 90 Volt input, synchro or resolver.
Maximum additional error is 1 minute.
R
When using discrete resistors: Resolver L-L voltage = i x 2 Vrms, where Rf ≥ 6 kΩ
Rf
FIGURE 14. SYNCHRO INPUT, USING DDC-49530 (11.8 V) OR DDC-49590 (90 V)
10
DC INPUTS
TABLE 6. PRECHARGE AMPLIFIER
GAIN PROGRAMMING
As noted in TABLE 1 the RD-19230 will accept DC inputs. It is
necessary to set the REF input to DC by tying RH to +5 V and
RL to GND or -5 \/.
UP/DN
VELOCITY TRIMMING
RD-19230 specifications for velocity scaling, reversal error, and
offset are contained in TABLE 1. Velocity scaling and offset are
externally trimmable for applications requiring tighter specifications than those available from the standard unit. FIGURE 15
shows the setup for trimming these parameters with external
pots. It should also be noted that when the resolution is changed,
VEL Scaling is also changed.
GAIN
Logic 0
4
Logic 1
1/4
-5 V
1
UP/DN
The UP/DN input selects the gain of the amplifier driving the deselected set of bandwidth components. UP/DN has three input
states. See TABLE 6 to relate input to gain.
BENEFIT OF SWITCHING RESOLUTION ON THE FLY
OPTIONAL BANDWIDTH COMPONENTS
Switching resolution on the fly can be used in applications that
require high resolution for accurate position control, and tracking
rates or settling times that are faster than the high resolution
mode will allow.
The RD-19230 provides the option of using a second set of
bandwidth components. The second set of components can be
used for switch-on-the-fly or dual-bandwidth applications. The
SHIFT and UP/DN inputs are used when when switching bandwidth components, and their operation is described below. Refer
to the block diagram on page 1.
The RD-19230 can track four times faster for each step down in
resolution (i.e., a step from 16 bits to 14 bits). The velocity output will be scaled down by a factor of four with each step down
in resolution. For example, if the velocity output is scaled such
that 4 Volts = 10 RPS in 16 bit resolution, then the same converter will output 1 Volt for 10 RPS in 14 bit resolution. To avoid
glitches in the velocity output, the second set of bandwidth components can be pre-charged to the expected voltage, and
switched in using the SHIFT input at the same time the resolution is changed. This will allow for a smooth velocity transition,
resulting in reduced errors and minimal settling time after the
change.
SHIFT
The SHIFT pin is an input that chooses between the VEL1 and
VEL2 bandwidth components. This pin has an internal pull-up to
+5V. When the SHIFT pin is left open, or a logic 1 is applied, the
VEL1 components are selected. When a Logic 0 is applied, the
VEL2 components are selected. The deselected set of bandwidth components are driven by an amplifier, with programmable
gain, that follows the velocity amplifier. This amplifier can be
used to pre-charge the deselected set of components to the voltage level that is expected after a change in resolution. (See
description on BENEFIT OF SWITCHING RESOLUTION ON
THE FLY.)
FIGURE 17 shows the way the converter behaves during a
change in resolution while tracking at a constant velocity. The
first illustration shows the benefits of switching in pre-charged
components while changing resolution. The second illustration
shows the result without the benefits of switching on the fly.
The signals that have been recorded are:
+5 V
-VCO
2
100 RV
0.8 R V
100 kΩ
(OFFSET)
1) VEL: velocity output pin on the RD-19230
-5 V
2) ERROR: this is the analog representation of the error between
the input and the output of the RD-19230
RD-19230
0.4 RV (SCALING)
VEL
3) D0: an input resolution control line to the RD-19230
1
4) BIT: built-in-test output pin of the RD-19230
When this system uses the switch resolution on the fly implementation, the velocity signal immediately assumes the pre-
FIGURE 15. VELOCITY TRIMMING
11
charged level of the second set of components, resulting in small
errors and reduced settling times. Notice that the BIT output
does not indicate a fault condition. (refer to FIGURE 17)
components to settle to the pre-charged level. This time will
depend on the time constant of the bandwidth components being
charged. If switching is limited to two adjacent resolutions (i.e.,
14 and 16) then the pre-charge amplifier can be set up to continuously maintain the appropriate velocity voltage on the deselected components, resulting in the fastest possible switching
times. See FIGURE 16 for an example of the input wiring connections necessary for switching on the fly between 14 and 16
bit resolution.
When this system type does not use the switch resolution on the
fly implementation, large errors and increased settling times
result. The errors exceed 100 LSBs causing the BIT to flag for a
fault condition.
SWITCH ON THE FLY IMPLEMENTATION
DUAL BANDWIDTHS
The following steps detail switching resolution on the fly.
With the second set of BW component pins, the user can set two
bandwidths for the RD-19230 and choose between them. To use
two bandwidths, proceed as follows:
1) The SHIFT pin should be controlled synchronously with the
change in resolution. When shift is logic high, the VEL1 components will be selected. When shift is logic 0, the VEL2 components will be selected.
1) Tie UP/DN to pin -5V.
2) The second set of BW components (CBW2, RB2, CBW2/10)
should typically be of the same value as the first set (CBW1, RB1,
CBW1/10,) and should be installed on VEL2 and VEL SJ2.
With Switch Resolution on the Fly Implemented
Note: Each set of bandwidth components must be chosen to
insure that the tracking rate to BW ratio (listed in TABLE 2)
is not exceeded for the resolution in which it will be used.
VEL
0V
-5V
3) UP/DN will program the direction of the gain. If the resolution
is increasing (UP/DN logic 0), the gain of the pre-charge amplifier should be set to four. If the resolution is decreasing
(UP/DN logic 1), the gain should be set to 1/4. The gain of the
pre-charge amplifier should be programmed prior to switching
the resolution of the converter, allowing enough time for the the
ERROR
0°
5V
D0
0V
5V
BIT
0V
ERROR = 13.6 LSBs per box
Without Switch Resolution on the Fly Implemented
VEL
+5V
0V
-5V
D1
ERROR
RD-19230
0°
5V
D0
0V
D0
58
27
5V
SHIFT
UP/DN
BIT
0V
ERROR = 1500 LSBs per box
FIGURE 17. BENEFIT OF SWITCHING
RESOLUTION ON THE FLY
FIGURE 16. INPUT WIRING - SWITCHING ON THE FLY
BETWEEN 14 AND 16 BIT RESOLUTION
12
The Converter Busy (CB) signal indicates that the tracking converter output angle is changing 1 LSB. As shown in FIGURE 20,
output data is valid 50 nS maximum after the middle of the CB
pulse. CB pulse width is 1/40 FS, which is nominally 375 ns.
2) Choose the two bandwidths following the guidelines in the
General Setup Considerations; the RV resistor must be the same
value for both bandwidths.
3) Use the SHIFT pin to choose between bandwidths. A logic 1
selects the VEL1 components and a logic 0 selects the VEL2
components.
INTERNAL ENCODER EMULATION
The RD-19230 can be programmed to encoder emulation mode
by connecting the A_QUAD_B input to GND. The U/B output pin
becomes B (LSB XOR LSB + 1) The A (LSB + 1) and B output
signals can be used in control systems that are designed to interface with incremental optical encoders. To enable the Zero Index
pulse, ZIP_EN should be tied to GND.
INHIBIT, ENABLE, AND CB TIMING
The Inhibit (INH) signal is used to freeze the digital output angle
in the transparent output data latch while data is being transferred. Application of an Inhibit signal does not interfere with the
continuous tracking of the converter. As shown in FIGURE 18,
angular output data is valid 150 ns maximum after the application of the negative inhibit pulse.
The resolution of the incremental outputs is latched from the D0
and D1 inputs on the low going edge of A_QUAD_B. The resolution of the parallel data outputs may be changed any time after
the encoder resolution is latched (see FIGURE 23).
Output angle data is enabled onto the tri-state data bus in two
bytes. Enable MSBs (EM) is used for the most significant 8 bits
and Enable LSBs (EL) is used for the least significant 8 bits. As
shown in FIGURE 19, output data is valid 150 ns maximum after
the application of a negative enable pulse. The tri-state data bus
returns to the high impedance state 100 ns maximum after the
rising edge of the enable signal.
Note: The encoder resolution must be less than or equal to
the resolution of the parallel data outputs. Refer to FIGURE
21.
The timing of the A, B and ZIP (or North Reference Pole [NRP])
output is dependent on the rate of change of the
synchro/resolver position (rps or degrees per second) and the
encoder resolution latched into the RD-19230 (refer to
FIGURE 22). The calculations for the timing is:
n = encoder resolution latched into RD-19230
INHIBIT
t = 1 / ( 2n* Velocity(RPS))
;; ;;;
T = 1 / ( Velocity(RPS))
150 nsec max
DATA
DATA
VALID
FIGURE 18. INHIBIT TIMING
250 to 750 nsec
CB
ENABLE
150 nsec MAX
DATA
HIGH Z
; ;
100 nsec MAX
DATA
VALID
HIGH Z
DATA
FIGURE 19. ENABLE TIMING
DATA
VALID
;
50 nsec
DATA
VALID
FIGURE 20. CONVERTER BUSY TIMING
13
SYNTHESIZED REFERENCE
BUILT-IN-TEST (BIT)
The synthesized reference section of the RD-19230 eliminates
errors due to phase shift between the reference and signal
inputs. Quadrature voltages in a resolver or synchro are by definition the resulting 90° fundamental signal in the nulled out error
voltage (e) in the converter. Due to the inductive nature of synchros and resolvers, their output signals lead the reference input
signal (RH and RL). When an uncompensated reference signal
is used to demodulate the control transformer’s output, quadrature voltages are not completely eliminated. As shown in FIGURE 1, the converter synthesizes its own internal reference signal based on the SIN and COS signal inputs. Therefore, the
phase of the synthesized (internal) reference is determined by
the signal input, resulting in reduced quadrature errors.
The BIT output is active low, and will be asserted during the following three error conditions:
Loss of Signal (LOS) - Sin and Cos inputs both less than 500mV.
Loss of Reference (LOR) - Reference Input less than 500 mV.
Excessive Error - This error is detected by monitoring the
demodulator output, which is proportional to the difference
between the analog input and digital output. When it exceeds
approximately 100 LSBs (in the selected resolution), BIT will be
asserted. This condition can occur any time the analog input
changes at a rate in excess of the maximum tracking rate.
During power up, the converter may see a large difference
between the sin/cos inputs and the digital output angle held in its
counter. BIT will be asserted until the converter settles within
~ 100 LSB’s of the final result.
RD-19230
1
0
1
2
1
4
1 MSB
2
3
4
5
6
7
8
9
10
11
12
13
14
15
BIT 16 LSB
1
6
A
B
FIGURE 21. INCREMENTAL ENCODER EMULATION RESOLUTION CONTROL
B(X- or LSB & LSB+1)
2t
D0/D1
A (LSB+1)
Data Valid
50 nsec
ZIP (NRP)
A QUAD B
t
0
T
359.95
FIGURE 23. TIMING FOR INCREMENTAL ENCODER
EMULATION RESOLUTION CONTROL
FIGURE 22. INCREMENTAL ENCODER EMULATION
14
LVDT MODE
As shown in TABLE 1 the RD-19230 unit can be made to operate as an LVDT-to-digital converter. In this mode the RD-19230
functions as a ratiometric tracking linear converter. When linear
AC inputs are applied from a LVDT the converter operates over
one quarter of its range. This results in two less bits of resolution
for LVDT mode than are provided in resolver mode.
Data output of the RD-19230 is Binary Coded in LVDT mode. The
most negative stroke of the LVDT is represented by ALL ZEROS
and the most positive stroke of the LVDT is represented by ALL
ONES. The most significant 2 bits (2 MSBs) may be used as overrange indicators. Positive overrange is indicated by code “01” and
negative overrange is indicated by code “11“ (see TABLE 7).
LDVT output signals need to be scaled to be compatible with the
converter input. FIGURE 25 is a schematic of an input scaling
circuit applicable to 3-wire LVDTs. The value of the scaling constant “a” is selected to provide an input of 2 Vrms at full stroke of
the LVDT. The value of scaling constant “b” is selected to provide
an input of 1 Vrms at null of the LVDT. Suggested components
for implementing the input scaling circuit are a quad op-amp,
such as a OP11 type, and precision thin-film resistors of 0.1%
tolerance. FIGURE 24 illustrates a 2-wire LVDT configuration.
TABLE 7. 12-BIT LVDT OUTPUT CODE FOR FIGURE 25
LVDT OUTPUT
MSB
+ over full travel
+ full travel -1 LSB
+0.5 travel
+1 LSB
null
- 1 LSB
-0.5 travel
- full travel
- over full travel
01
00
00
00
00
00
00
00
11
xxxx
1111
1100
1000
1000
0111
0100
0000
xxxx
C1
SIN
aR
2 WIRE LVDT
REF IN
-S
R
-
R
R
+
C2
+S
FS = 2 V
aR
COS
bR
R
R
2R
-C
R
-
R
2R
+
2V
+C
R
bR
+RH
-RL
C1 = C2, set for phase lag = phase lead through the LVDT.
FIGURE 24. 2-WIRE LVDT DIRECT INPUT
15
LSB
xxxx
1111
0000
0000
0000
1111
0000
0000
xxxx
xxxx
1111
0000
0001
0000
1111
0000
0000
xxxx
aR
SIN
R
VB
-S
-
R'
R
+S
+
R'
aR
bR
R
2R'
R
R'
COS
-C
-
VA
R/2
+
2R'
R'
+C
+RH
bR
-RL
Notes:
1. R' ≥ 10 kΩ
2. Consideration for the value of R is LVDT loading.
b=
1 = 1
VAnull VBnull
a=
2
(VA - VB) max
LVDT
OUTPUT
VA
VB
+FS
NULL
-FS
RDC-19230
INPUT
2V
SIN
1V
SIN = 1+ a (VA - VB)
2
COS = 1- a (VA - VB)
2
FIGURE 25. 3-WIRE LVDT SCALING CIRCUIT
16
COS
-FS
NULL
+FS
TABLE 8. RD-19230 PINOUTS
#
NAME
#
NAME
#
NAME
#
NAME
1
VEL
17
VSS (-5V)
33
VDD (+5V)
49
Bit 8
2
-VCO
18
TP3 (test point)
34
N/C
50
Bit 16
3
SJ1
19
R CLK
35
Bit 9
51
A (LSB + 1)
4
SJ2
20
R SET
36
Bit 2
52
TP4 (test point)
5
SHIFT
21
ENM
37
Bit 10
53
N/C
6
VEL2
22
AGND
38
Bit 3
54
TP5 (test point)
7
TP1 (test point)
23
VSSP
39
Bit 11
55
ZIP_EN
8
VEL1
24
NCAP
40
Bit 4
56
TP6 (test point)
9
TP2 (test point)
25
GND
41
N/C
57
ENL
10
+C
26
PCAP
42
Bit 12
58
VDD (+5V)
11
COS
27
VDDP
43
Bit 5
59
UP/DN
12
-C
28
BIT
44
Bit 13
60
D0
13
+S
29
U/B
45
Bit 6
61
D1
14
SIN
30
A_QUAD_B
46
Bit 14
62
INH
15
-S
31
CB (ZI)
47
Bit 7
63
RH
16
VSS (-5V)
32
Bit 1
48
Bit 15
64
RL
Notes:
1. See FIGURE 5 for +5 V only operation.
0.078+0.004
-0.002
(2.00+0.10
-0.05 )
17
32
0.096MAX
(2.45MAX)
16
33
0.0098MIN,0.0197MAX
(0.25MIN,0.50MAX)
0.0197
(0.50)
0.520±0.010
(13.2±0.25)
RD- 1 9 230FX
- X XX
0.394±0.004
(10.00±0.10)
Da t e Code
pin1
48
49
0.096MAX
(2.45MAX)
64
0.394±0.004
(10.00±0.10)
0.0098MIN,0.0197MAX
(0.25MIN,0.50MAX)
0.007MAX
(0.17MAX)
0.520±0.010
(13.2±0.25)
0.008
(0.22)
0.035+0.006
-0.004
( 0.88+0.15
-0.10 )
Dimensions shown are in inches (millimeters)
FIGURE 26. RD-19230 MECHANICAL OUTLINE
17
TABLE 9. FRONT-END THIN-FILM RESISTOR NETWORKS
(SEE FIGURE 27)
DDC-49530, DDC-57470 RESISTOR VALUES (11.8 V INPUTS)
SYMBOL
ABS
VALUE
TOL
(%)
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
70.8 k
0.1
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
REL TO
REL
VALUE
TOL
(%)
TCR(PPM)
R1
12 k
0.02
R4
12 k
0.02
R1
70.8 k
0.02
R1
70.8 k
0.02
R1
35.4 k
0.02
R6
6.9282 k 0.02
R6
5.0718 k 0.02
R11
5.0718
0.02
R11
6.9282 k 0.02
R1
70.8 k
0.02
DDC-49590 RESISTOR VALUES (90 V INPUTS)
270 k
0.1
R1
6k
0.02
R4
6k
0.02
R1
270 k
0.02
R1
270 k
0.02
R1
135 k
0.02
R6
3.4641 k 0.02
R6
2.5359 k 0.02
R11
2.5359 k 0.02
R11
3.4641 k 0.02
R1
270 k
0.02
25
2
2
2
2
2
2
2
2
2
2
16
15
R11
R10
R1
R2
1
25
2
2
2
2
2
2
2
2
2
2
14
2
13
R9
11
R8
R3
3
4
R7
6
+0.64
(8.26 -0.38
)
0.100 TYP
(2.54)
8
0.014
(.36)
0.342
(8.7)
0.009
(0.23)
0.018 ±0.003
(0.46 ±0.08)
7
0.299 0.406
(7.6) (10.3)
0.101
(2.6)
0.13 ±0.005
(3.30 ±0.13)
0.075 ±0.015
(1.91 ±0.38)
R5
.405
45˚
+0.025
0.325 -0.015
R6
R4
5
9
7˚
0.250 ±0.005
(6.35 ±0.13)
0.015 ±0.009
(0.38 ±0.23)
10
FIGURE 27. (DDC-49530, DDC-49590, DDC-57470)
LAYOUT AND RESISTOR VALUES (SEE TABLE 9)
0.870 MAX
(22.10)
0.320 - 0.300
(8.13 - 7.62)
12
0.020 MIN
(0.51)
0.125 MIN
(3.18)
0.050
(1.27)
DIMENSIONS SHOWN ARE IN INCHES (MM).
0.092
(2.3)
0.016
(0.40)
DIMENSIONS SHOWN ARE IN INCHES (MM).
FIGURE 28. 16-PIN THIN-FILM RESISTOR NETWORK
DIP MECHANICAL OUTLINE
(DDC-49530, DDC-49590)
FIGURE 29. 16-PIN THIN-FILM RESISTOR NETWORK
FLAT-PACK MECHANICAL OUTLINE
(DDC-57470)
18
ORDERING INFORMATION
RD-19230FX-X X X X
Supplemental Process Requirements:
T = Tape and Reel (50 pc. min. order)
Accuracy:
2 = 4 min + 1 LSB
3 = 2 min + 1 LSB
Reliability:
0 = Standard DDC Procedures
Operating Temperature Range:
2 = -40° to +85°C
3 = 0° to +70°C
THIN-FILM RESISTOR NETWORKS:
DDC-49530 = 11.8 V inputs DIP package
DDC-57470 = 11.8 V inputs Flat-pack package
DDC-49590 = 90 V inputs DIP package
COMPONENT SELECTION SOFTWARE:
Component selection software can be downloaded from our website ( www.ddc-web.com )
19
The information in this data sheet is believed to be accurate; however, no responsibility is
assumed by Data Device Corporation for its use, and no license or rights are
granted by implication or otherwise in connection therewith.
Specifications are subject to change without notice.
105 Wilbur Place, Bohemia, New York 11716-2482
For Technical Support - 1-800-DDC-5757 ext. 7402 or 7413
Headquarters - Tel: (631) 567-5600 ext. 7402 or 7413, Fax: (631) 567-7358
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World Wide Web - http://www.ddc-web.com
PRINTED IN THE U.S.A.
D-05/00-500
20