ETC RM3182A

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Description
www.fairchildsemi.com
RM3182
ARINC 429 Differential Line Driver
Features
Description
•
•
•
•
•
•
•
•
The RM3182 consists of a bus interface line driver circuit
plus auxiliary gating and synchronization circuitry. Designed
to address the ARINC 429 standard, the RM3182 has output
rise and fall times adjustable by the selection of two external
capacitor values, and the output voltage swing range can be
adjusted through an externally applied VREF signal.
The logic inputs as well as the sync control inputs are
TTL-CMOS compatible. The device is constructed on a
monolithic IC using a junction-isolated bipolar process.
Sputtered SiCr resistors are used in the internal bias circuitry, providing stable internal bias currents. The RM3182
is available in 16-lead ceramic DIP and 28-pad LCC, and can
be ordered with MIL-STD883B high reliability screening.
Adjustable rise and fall times
Adjustable output voltage swing
Short circuit protected
Output overvoltage protected
Sync and clock enable inputs
TTL and CMOS compatible inputs
MIL-STD-883B types available
100 Kbits/second data rate
Block Diagram
V REF
+VS
(1)
CA
(9)
(5)
(4)
Level Shifter
And Slope
Control (A)
Data (A)
(14)
(6)
Output
Driver
(A)
A OUT
R OUT /2
Clock
(8)
RL
Gnd
(3)
CL
Sync
Level Shifter
And Slope
Control (B)
(13)
Data (B)
R OUT /2
Output
Driver
(B)
B OUT
(11)
(16)
V1
Power
Enable
Current
Regulator
(2)
(7)
(12)
-V S
OverVoltage
Clamps
CB
Notes:
1. RL and CL are external. Full load values are: RL = 400½, CL = 0.03µF.
2. Pin numbers are for 16-lead DIP.
65-3182-01
Rev. 1.0.0
RM3182
PRODUCT SPECIFICATION
Sync
PWR Enable
NC
VREF
V1
NC
NC
Pin Assignments
Sidebraze DIP
1
16
V1
PWR Enable
2
15
NC
Sync
3
14
Clock
Data (A)
4
13
Data (B)
CA
5
12
CB
AOUT
6
11
BOUT
–VS
7
10
NC
GND
8
9
+VS
NC
Data (A)
NC
NC
CA
NC
NC
Clock
NC
Data (B)
CB
NC
NC
NC
28
1
LCC
NC
AOUT
–VS
GND
+VS
BOUT
NC
VREF
65-3182-03
65-3182-02
Absolute Maximum Ratings
Parameter
Max.
Units
Supply Voltage (+VS to –VS)
36
V
V1 Voltage
+7
V
VREF Voltage
+6
V
+VS + 0.3
V
Logic Input Voltage
Min.
-0.3
Output Short Circuit Duration
See Note 1
Output Overvoltage
–6.5
+6.5
V
Storage Temperature Range
-65
+150
°C
Operating Temperature Range (see Note 2)
-55
+125
°C
+300
°C
Lead Soldering Temperature (60 sec.)
Notes:
1. Heatsinking may he required for output short circuit at +125°C.
2. Heatsinking may be required depending on load and signal frequencies
Thermal Characteristics
(Still air, soldered into PC board)
Sidebrazed DIP
LCC
+175°C
+175°C
1470 mW
1040 mW
Thermal Resistance qJC
25°C/W
25°C/W
Thermal Resistance qJA
85°C/W
120°C/W
For TA > 50°C Derate at
11.7 mW/°C
8.3 mW/°C
Maximum Junction Temperature
Max. PD TA < 50°C
2
PRODUCT SPECIFICATION
RM3182
Electrical Characteristics
(VS = ±15V, VREF = V1 = +5V, PWR Enable = 0V, RL = open circuit, -55°C £ TA £ +125°C)
Parameters
Test Conditlons
Positive Supply Current
Data Rate = 0 to 100 Kbits/sec
Negative Supply Current
Data Rate = 0 to 100 Kbits/sec
V1 Supply Current
Data Rate = 0 to 100 Kbits/sec
VREF Supply Current
Data Rate = 0 to 100 Kbits/sec
Min.
Input Logic Level High
Typ.
Max.
Units
11
16
mA
-16
-10
mA
200
975
mA
-1.0
-0.4
-0.15
mA
2.0
V
Input Logic Level Low
0.5
V
V
Output Voltage High
With Respect to Ground
4.75
5.0
5.25
Output Voltage Low
With Respect to Ground
-5.25
-5.0
-4.75
V
Output Voltage Null
Both Data Input = Logic 0
-250
0
+250
mV
Input Current High
VIN = 2.0V
1
10
mA
Input Current Low
VIN = 0.5V
Output Short Circuit Current
Output in High State, to Gnd
-20
Output Short Circuit Current
Output in Low State, to Gnd
Positive Supply Current
Output High and Shorted to Gnd
Negative Supply Current
Output Low and Shorted to Gnd
Input
-133
80
mA
-1
-80
mA
150
mA
133
mA
-150
Capacitance1
mA
5
15
pF
Note:
1. Guaranteed by design.
Typical Power Dissipation Characteristics
(VS = ±15V, V1 = VREF = +5V, Pwr Enable = 0V, TA = + 25°C)
Data Rate
(Kbits/sec)
0 to 100
12.5 to 14
100
Load
Positive
Supply
Current
Negative
Supply
Current
Pin V1
Supply
Current
Internal
Power
Dissipatlon
Load
Power
Dissipatlon
Open Circuit
11 mA
-10 mA
200 mA
325 mW
0
Full
Load1
24 mA
-24 mA
200 mA
660 mW
60 mW
Full
Load1
46 mA
-46 mA
200 mA
1000 mW
325 mW
Note:
1. RL = 400W, CL = 0.03 mF (see Block Diagram).
3
RM3182
PRODUCT SPECIFICATION
Principles of Operation
low, AOUT will swing to +VREF and BOUT will swing to
VREF (constituting a logic high state). Reversing the data
input states will cause AOUT to swing to -VREF and BOUT
to +VREF. With both data input signals at a logic low state,
the outputs will both swing to 0V (output in null state).
Each device consists of one differential driver and associated
gating circuitry. The gating circuitry consists of clock and
sync signal inputs which are ANDed with the two data
inputs. See the block diagram and truth table. Three power
supplies are required to operate the RM3182 in a typical
ARINC 429 bus application: +15V, -15V, and +5V. The +5V
supply, in addition to powering the internal bus current
regulator, provides a reference voltage that determines the
output voltage swing. The differential output swing will
equal 2 VREF. If a value of VREF other than +5V is used,
then a separate +5V supply is required for pin V1.
The slew rate of the outputs, and consequently rise and fall
times, can be adjusted through the selection of two external
capacitor values. Typical values are CA = CB = 75 pF for
high-speed operation (100 Kbits/sec) and CA = CB = 500 pF
for low-speed operation (12.5 to 14 Kbits/sec).
The device can be powered down by applying a logic high
signal to the Power Enable pin. If the power down feature is
not used, then the Power Enable pin should be tied directly
to ground.
Figure 1 depicts connections for the ARINC 429 application.
The driver output impedance is nominally 75W. With the
Data(A) input at a logic high and Data (B) input at a logic
+15V
+5V
1
V REF 16
V1
4
Data (A)
3
Sync
14
9
Clock
+V S
6
RM3182
A OUT
Inputs
To Bus
13
Power
Enable
Data (B) Gnd
CB
8
CA
12
-VS
11
B OUT
7
2
5
Note: Pin numbers are for
the 16-lead DIP.
-15V
65-3182-04
Figure 1. ARINC 429 Bus Application
4
PRODUCT SPECIFICATION
RM3182
0V
Data A
0V
Data B
Adjust By CB or Rate Select
+VREF
Out A or
Amp A
-VREF
Adjust By CA or Rate Select
Out B
or Amp B
+V REF
-VREF
High = +VREF
Differential
Output
Out A- Out B
or
Amp Out AAmp Out B
Null
0V
Low = -VREF
Note: Outputs unloaded
65-3182-05
Figure 1. Switching Waveforms
Truth Table
Sync
Clock
Data (A)
Data (B)
AOUT
BOUT
Comments
X
L
X
X
0V
0V
Null
L
X
X
X
0V
0V
Null
H
H
L
L
0V
0V
Null
H
H
L
H
-VREF
+VREF
Low
H
H
H
L
+VREF
-VREF
High
H
H
H
H
0V
0V
Null
5
RM3182
PRODUCT SPECIFICATION
Mechanical Dimensions
16-Lead Sidebraze DIP
Inches
Symbol
Min.
A
b1
b2
c1
D
E
e
eA
L
L1
Q
s1
s2
Notes:
Millimeters
Max.
Min.
—
.200
.014
.023
.045
.065
.008
.015
—
.860
.280
.310
.100 BSC
.300 BSC
.125
.200
.140
—
.015
.070
.005
—
.005
—
Notes
Max.
—
5.08
.36
.58
1.14
1.65
.20
.38
—
21.84
7.11
7.87
2.54 BSC
7.62 BSC
3.18
5.08
3.56
—
.38
1.78
.13
—
.13
—
7
2
7
4, 8
6
1. Index area: a notch or a pin one identification mark shall be located
adjacent to pin one. The manufacturer's identification shall not be
used as pin one identification mark.
2. The minimum limit for dimension "b2" may be .023 (.58mm) for leads
number 1, 8, 9 and 16 only.
3. Dimension "Q" shall be measured from the seating plane to the base
plane.
4. The basic pin spacing is .100 (2.54mm) between centerlines. Each
pin centerline shall be located within ±.010 (.25mm) of its exact
longitudinal position relative to pins 1 and 16.
5. Applies to all four corners (leads number 1, 8, 9, and 16).
6. "eA" shall be measured at the centerline of the leads.
3
5
7. All leads – Increase maximum limit by .003 (.08mm) measured at the
center of the flat, when lead finish applied.
8. Fourteen spaces.
D
8
1
9
16
NOTE 1
E
s1
S2
eA
A
Q
L
b2
6
b1
e
L1
c1
PRODUCT SPECIFICATION
RM3182
Mechanical Dimensions (continued)
28 Terminal Leadless Chip Carrier (LCC)
Inches
Symbol
A
A1
B1
B3
D/E
D1/E1
D2/E2
e
h
j
L1
L2
L3
Min.
Max.
Min.
Max.
.060
.050
.022
.006
.100
.088
.028
.022
1.52
1.27
.56
.15
2.54
2.24
.71
.56
.442
.460
.300 BSC
.150 BSC
11.23
11.68
7.62 BSC
3.81 BSC
.050 BSC
.040 REF
.020 REF
1.27 BSC
1.02 REF
.51 REF
.045
.075
.003
Notes:
Millimeters
.055
.095
.015
1.14
1.91
.08
Notes
3, 6
3, 6
2
2, 5
7
7
N
28
28
2. Unless otherwise specified, a minimum clearance of .015 inch
(0.38mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.).
3. Dimension "A" controls the overall package thickness. The maximum
"A" dimension is the package height before being solder dipped.
4
4
1.40
2.41
.38
ND/NE
1. The index feature for terminal 1 identification, optical orientation or
handling purposes, shall be within the shaded index areas shown on
planes 1 and 2. Plane 1 terminal 1 identification may be an extension
of the length of the metallized terminal which shall not be wider than
the B1 dimension.
5
4. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer's option, from that shown on the drawing. The index
corner shall be clearly unique.
5. Dimension "B3" minimum and "L3" minimum and the appropriately
derived castellation length define an unobstructed three dimensional
space traversing all of the ceramic layers in which a castellation was
designed. Dimension "B3" maximum and "L3" maximum define the
maximum width and depth of the castellation at any point on its
surface. Measurement of these dimensions may be made prior to
solder dripping.
6. Chip carriers shall be constructed of a minimum of two ceramic layers.
LID
PLANE 2
PLANE 1
D
See Note 1
A1
L3
B3
B1
E
DETAIL "A"
A
Index Corner
(j) x 45¡
(h) x 45¡
4
3 PLCS
DETAIL "A"
D2
e
D1
L2
L1
7
PRODUCT SPECIFICATION
RM3182
Ordering Information
Part Number
Package
Operating Temperature Range
RM3182S
S
-55°C to +125°C
RM8182S/883B
S
-55°C to +125°C
RM3182L
L
-55°C to +125°C
RM3182L/883B
L
-55°C to +125°C
Notes:
/883B suffix denotes MIL-STD-883, Level B processing
S = 16 Lead sidebraze ceramic DIP
L = 28 Terminal Leadless Chip Carrier
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
5/20/98 0.0m 001
Stock# DS30003182
Ó 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RM3182A
ARINC 429 Differential Line Driver
Features
Description
•
•
•
•
•
•
•
•
•
•
The RM3182A is a complete differential line driver IC.
When Data A = Data B or Sync or Clock Signal is low, the
driver forces the output to a Voltage Null level
(0V ± 250 mV). Designed to address the ARINC 429 standard, the RM3182A has output rise and fall times that can be
adjusted by the selection of an external capacitor (CA or CB)
and an output voltage range adjustable through an externally
applied VREF signal. All logic inputs and sync control inputs
are TTL/CMOS compatible. The device is constructed on a
monolithic IC using a junction-isolated bipolar process.
Sputtered SiCr resistors in the internal bias circuitry provide
for stable bias currents and a tighter tolerance of output
impedance. The RM3182A is available in 16-lead ceramic
sidebrazed DIP, 28-Terminal LCC and can be ordered with
MIL-STD-883B high reliability screening.
Adjustable rise and fall times
Low supply current
Capable of driving 30 nF || 400W
Digitally selectable 12.5 or 100 kbit/sec data rate
Adjustable output voltages swing
Output overvoltage protected
Short circuit protected
TTL and CMOS compatible inputs
MIL-STD-883B screening available
Available in 16-lead ceramic sidebrazed DIP and
28-Terminal LCC
Block Diagram
Cap (A)
VCC
9
5
VCC
3 pF
10
Amp A
Charge Pumps
Data (A)
Clock
Sync
VREF
Data (B)
4
14
3
1
13
Data (A)
Rate
Select
Cap (A)
Sync
ISET (A)
6
10K
10K
VREF
VEE
Data B
16
2
Out A
37.5W
Clock
VLOGIC
VLOGIC
10K
10K
10K
ISET (B)
11
37.5W
VLOGIC
ISET (A)
Rate
Select
ISET (B)
CL
RL
VCC
10K
Cap (B)
Out B
10K
10K
Amp B
15
3 pF
12
8
Cap B
GND
7
VEE
65-5890A
VEE
Note: Pin numbers are for the DIP package.
Rev. 1.0.0
RM3182A
PRODUCT SPECIFICATION
Functional Description
The device contains three main functional blocks. The first
block is a digital section used to decode the ARINC Clock,
Synchronization, and Data inputs as shown in Block Dia-
gram. This block takes these inputs and channels the data to
the charge pump circuits. The logical relationship for these
pins is presented in Table 1.
Table 1. I/O Truth Table
Sync
Clock
Data A
Data B
Out A
Out B
Comments
X
L
X
X
0V
0V
Null
L
X
X
X
0V
0V
Null
H
H
L
L
0V
0V
Null
H
H
L
H
-VREF
+VREF
Low
H
H
H
L
+VREF
-VREF
High
H
H
H
H
0V
0V
Null
The second functional block is a charge pump circuit that is
used to control the output waveform and its timing characteristics. This is achieved through charging and discharging a
capacitor with a known current. The capacitor is user selectable, and is connected between CA or CB pins and ground.
A rate select pin (digital input) enables to set the rise and fall
time. If this pin is tied to ground, the device functions in the
high rate. This mode is recommended if the user does not
have an application requiring data rate switching. In the table
below, recommended capacitor values are given for each
possible data combination.
Table 2. Rate Select Pin Truth Table
CA
CB
(pF)
10% to 90%
Rlse/Fall time
(m S)
Logic 0
56
Logic 1
56
Logic 0
Logic 1
Rate Select
Data Rate
(Kbits/sec)
Comments
1.5
100
High Rate
10
12-14.5
Low Rate
390
10
12-14.5
Low Rate
390
N/A
N/A
Not Used
The last functional block of the device consists of a voltage
follower and a high power output differential amplifier.
The voltage follower buffers the signals presented at the
charge caps and presents the mirrored signal to the difference
amplifier to drive the ARINC line. Two different outputs
are available from the differential amplifiers: Amp A, Amp
B, and Out A, Out B. The outputs Amp A and Amp B are the
direct outputs of the power amplifier. The outputs Out A and
Out B include 37.5W series resistors added to minimize bus
2
reflections by matching the power amplifier’s output impedance to the cable’s impedance of 75W. Amp A and Amp B
may be used to customize the output impedance of the
device. These outputs can also be used to enhance the
device’s drive capability. For example, driving the standard
30 nF || 400W load defined in the ARINC specifications (see
output drive capability and capacitive loads for more details).
All outputs are protected from voltage spikes with diodes
connected between the output pins and the supply lines.
PRODUCT SPECIFICATION
RM3182A
Output Drive Capability and
Capacitive Loads
Using equation 1.2, a time constant can be determined for
the given application which is shown in equation 1.3.
The Traditional Approach
1.3
The RM3182A is capable of driving a high capacitive/resistive load. If complete ARINC compliance is required then
Out A and Out B pins are recommended to maintain the
output impedance. In this configuration, driving the full
ARINC load of 30nF || 400W the output characteristic takes
on the transfer function of a low pass filter due to the internal
37.5W resistor, the line resistance and the capacitance associated with the cable. This will result in a lower rise/fall time
of the device. Equation 1.1 relates the output voltage at Out
A and Out B to the voltage at the power amplifier’s output.
Output A is taken for this example:
So, for the maximum loading condition of 30nF || 400W the
resulting time constant is 1.9 ms. This shows that with a
maximum load, the output waveform is greatly affected by
the low pass filter combinabon of the ROUT || RL resistor and
the load capacitance.
1.1
AmpA Z L ¤ 2
Out A = -------------------------------------( Z L ¤ 2 ) + R OUT
Where: ROUT = 37.5W and ZL = RL || CL
The output as a function of frequency is given by equation
1.2.
R
R L + 2R OUT ( 1 + jwC L R L )
L
1.2 A OUT ( jw ) = Amp A ( jw ) ------------------------------------------------------------------
t = ( R OUT || R L )C L
A New Option: Amp A/Amp B
The RM3182A also provides the user the option of connecting the data line directly to the power output amplifiers thus
bypassing the internal 37.5W resistance of the device and
matching the line more precisely. For example, using a 1%
37.5W resistor allows better control of the output impedance.
By applying the load directly to the power amplifiers output
pins, the resulting waveform is virtually unchanged when
driving other loads. There may be applications where these
pins present a more desirable result. For instance, if the line
that the chip is driving is short, then the parasitic components of the line can be neglected, and power amplifier can
be tied directly to the lines. This option can be utilized to
achieve a greater noise immunity through bypassing the
internal resistors.
Sync
Rate Select
NC
VREF
VLOGIC
NC
Amp B
Pin Assignments
VLOGIC
Rate Select
Amp B
Sync
Clock
Data A
Data B
CA
CB
Out A
Out B
VEE
Amp A
GND
VCC
65-4192
NC
Data A
NC
NC
CA
NC
NC
Clock
NC
Data B
CB
NC
Amp A
NC
NC
Out A
VEE
GND
VCC
Out B
NC
VREF
65-4193
3
RM3182A
PRODUCT SPECIFICATION
Absolute Maximum Ratings
Parameter
Min.
Max.
Units
Supply Voltage (VCC to VEE)
+36
V
VLOGIC Theshold Voltage
+7
V
+VCC
V
VREF Voltage
Logic Input Voltage
-0.3
VLOGIC + 0.3
V
Storage Temperature Range
-65
+150
°C
Operating Temperature Range
-55
+125
°C
Junction Temperature
-55
+175
°C
+300
°C
Lead Soldering Temperature (60 sec.)
Thermal Characteristics
(Still air, soldered into PC board)
Parameter
16-Lead Sidebrazed DIP
28-Terminal LCC
Maximum Junction Temperature
+175°C
+175°C
Thermal Resistance, qJC
70°C/W
60°C/W
Thermal Resistance, qJA
28°C/W(1)
25°C/W
For TA > 50°C Derate at
14.3 mW/°C
13.3 mW/°C
Electrical Characteristics
(VCC = +15V, VEE = -15V, VREF = +5V, VLOGIC = +5V, Rate Select = 0V, RL = Open Circuit, CL = 0 pF,
and -55°C < TA < +125°C)
Symbol
Parameters
ICC
Positive Supply Current
IEE
Negative Supply Current
Data Rate = 0 to 100 Kbits/sec
4.0
ILOGIC
VLOGIC Supply Current
Data Rate = 0 to 100 Kbits/sec
150
IREF
VREF Supply Current
Data Rate = 0 to 100 Kbits/sec
-500
-294
VIH
Input Logic Level High
Dependent on VLOGIC
VIL
Input Logic Level Low
VOH
Output Voltage High
With Respect to Ground
4.75
VOL
Output Voltage Low
With Respect to Ground
-5.25
VNULL
Output Voltage Null
Both Data Inputs = Logic 0
-250
0
IIH
Input Current High
VIN = 2.0V
IIL
Input Current Low
VIN = 0.5V
-645
100
1
Data Rate = 0 to 100 Kbits/sec
Min.
Typ.
Max.
Units
4.0
5.7
6.9
mA
4.9
6.9
mA
214
300
mA
-100
mA
Vlogic
V
0.5
V
5.0
5.25
V
-5.0
-4.75
V
+250
mV
1
mA
-161
-50
nA
15
pF
133
156
mA
2.0
CI
Input Capacitance
ISC
Output Short Circuit Current
AOUT and/or BOUT shorted line to
line or to GND
ISCVCC
VCC Short Circuit Current
AOUT and/or BOUT shorted line to
line or to GND
140
165
mA
ISCVEE
VEE Short Circuit Current
AOUT and/or BOUT shorted line to
line or to GND
140
165
mA
Note:
1. Guaranteed by design.
4
Test Conditlons
PRODUCT SPECIFICATION
RM3182A
Typical Power Dissipation Characteristics
(VCC = +15V, VEE = -15V, VREF = +5V, TA = + 25°C, CA = CB = 56pF)
Data Rate
(Kbits/sec)
Load
Rate
Select
Positive
Supply
Current
Negative
Supply
Current
Pin VLOGIC
Supply
Current
Total
Power
Dissipatlon
0 - 100
Open Circuit
Logic 1,0
5.7 mA
4.9 mA
214 mA
160 mW
12.5 - 14
Full Load1
Logic 1
19.6 mA
22.7 mA
200 mA
655 mW
100
Full Load1
Logic 0
39.1 mA
38.4 mA
200 mA
1165 mW
Note:
1. RL = 400W, CL = 0.03 mF (see Block Diagram).
Typical Performance Characteristics
7
500
I EE
400
CC
4
3
2
1
0
-55
25
I REF
300
200
I LOGIC
100
0
-55
125
Temperature ( C)
65-5955
I
Current (µA)
5
65-5954
Current (mA)
6
25
125
Temperature ( C)
Figure 1. Supply Current vs. Temperature
(CL = 0 pF, RL = Open Circuit)
Figure 2. IREF, ILOGIC vs. Temperature
4.0
2.5
3.5
0.5
0
12.5
50
100
150
Frequency (Hz)
Figure 3. AmpA, AmpB Output Impedance Typical
3.0
2.5
Rate Select = 0
2.0
1.5
1.0
Rate Select = 5V
0.5
0
0
65-5957
1.0
Slew Rate (V/µS)
1.5
65-5956
ZO (Ohms)
2.0
50 100 150 200 250 300 350 400 450 500
External Capacitor (pF)
Figure 4. Slew Rate vs. CA, CB
5
RM3182A
PRODUCT SPECIFICATION
Applications
Power Supply Considerations
Heat Sinking /Air Flow and Short Circuit
Protection
The user application will determine if and how much heat
sinking/air flow will be required for the RM3182A.
Consideration must be given to ambient temperature, load
conditions and output voltage swing. In addition, power
consumption increases with increased operating frequency.
Use the numbers given in the Thermal Characteristics Table
to determine that the maximum allowable junction temperature of 175°C is not exceeded.
Outputs Out A and Out B are short circuit protected by the
internal 37.5W back termination resistors. During a short
circuit of the output to either power supply or ground, the
device must be able to dissipate the generated heat. For
example, if the output is shorted to ground and VCC = +15V,
the device must dissipate 15V x 0.165A = 2.5W. An appropriate heat sink is required in this situation.
Note that the Amp A and Amp B outputs are not short circuit
protected. Shorting these pins to either power supply or
ground will cause failure of the device. An added external
resistor will protect the circuit by limiting the current.
Each power supply pin should be decoupled to ground using
a high quality 10 mF tantalum capacitor. This is especially
true when driving a large capacitive or resistive loads. The
decoupling capacitors should be located as close to the
device pins as possible to eliminate the wiring inductance.
Typical ARINC 429 Application
Figure 5 shows typical switching waveform for the
RM3182A in any configuration.
Figure 6 depicts connections for a ARINC 429 high speed
bus driver application. This circuit shows the complete
configuration for a 100 Kbits/sec, 10V differential output
swing using the terminated output pins.
0V
Data A
0V
Data B
+VREF
Out A or
Amp A
Adjust By CA or Rate Select
Out B
or Amp B
Three power supplies are required to operate the RM3182A
in a typical ARINC 429 bus application: +15V for VCC,
-15V for VEE, and +5V for both VREF and VLOGIC. The differential output swing of the RM3182A is equal to 2 x VREF.
Using +5V gives a differential output swing of 10V.
If a different output voltage swing is required, an additional
power supply is needed to set VLOGIC.
Adjust By CB or Rate Select
-VREF
+V REF
-VREF
High = +VREF
Differential
Output
Out A- Out B
or
Amp Out AAmp Out B
0V
Null
Low = -VREF
Note: Outputs unloaded
65-4188
Figure 5. Switching Waveforms
6
PRODUCT SPECIFICATION
RM3182A
+15V
+5V
10 µF
Tantalum
10 µF
Tantalum
VCC
VLOGIC
Data A
VREF
NC
Sync
Clock
Amp A
Input
Out A
Out B
Amp B
RM3182A
To
Bus
CB
Rate
Select
Data B
CA
GND
NC
56 pF
VEE
56 pF
10 µF
Tantalum
-15V
NC = No Connection
65-5891A
Figure 6. ARINC 429 Bus Driver Applications (100 kb/s Mode)
7
RM3182A
Notes:
8
PRODUCT SPECIFICATION
PRODUCT SPECIFICATION
RM3182A
Notes:
9
RM3182A
PRODUCT SPECIFICATION
Mechanical Dimensions
16-Lead SideBraze Ceramic DIP
Inches
Symbol
Min.
A
b1
b2
c1
D
E
e
eA
L
L1
Q
s1
s2
Notes:
Millimeters
Max.
Min.
—
.200
.014
.023
.045
.065
.008
.015
—
.860
.280
.310
.100 BSC
.300 BSC
.125
.200
.140
—
.015
.070
.005
—
.005
—
Notes
Max.
—
5.08
.36
.58
1.14
1.65
.20
.38
—
21.84
7.11
7.87
2.54 BSC
7.62 BSC
3.18
5.08
3.56
—
.38
1.78
.13
—
.13
—
7
2
7
4, 8
6
1. Index area: a notch or a pin one identification mark shall be located
adjacent to pin one. The manufacturer's identification shall not be
used as pin one identification mark.
2. The minimum limit for dimension "b2" may be .023 (.58mm) for leads
number 1, 8, 9 and 16 only.
3. Dimension "Q" shall be measured from the seating plane to the base
plane.
4. The basic pin spacing is .100 (2.54mm) between centerlines. Each
pin centerline shall be located within ±.010 (.25mm) of its exact
longitudinal position relative to pins 1 and 16.
5. Applies to all four corners (leads number 1, 8, 9, and 16).
6. "eA" shall be measured at the centerline of the leads.
3
5
7. All leads – Increase maximum limit by .003 (.08mm) measured at the
center of the flat, when lead finish applied.
8. Fourteen spaces.
D
8
1
9
16
NOTE 1
E
s1
S2
eA
A
Q
L
b2
10
b1
e
L1
c1
PRODUCT SPECIFICATION
RM3182A
Mechanical Dimensions (continued)
28-Terminal LCC
Inches
Symbol
A
A1
B1
B3
D/E
D1/E1
D2/E2
e
h
j
L1
L2
L3
Min.
Max.
Min.
Max.
.060
.050
.022
.006
.100
.088
.028
.022
1.52
1.27
.56
.15
2.54
2.24
.71
.56
.442
.460
.300 BSC
.150 BSC
11.23
11.68
7.62 BSC
3.81 BSC
.050 BSC
.040 REF
.020 REF
1.27 BSC
1.02 REF
.51 REF
.045
.075
.003
Notes:
Millimeters
.055
.095
.015
1.14
1.91
.08
Notes
3, 6
3, 6
2
2, 5
7
7
N
28
28
2. Unless otherwise specified, a minimum clearance of .015 inch
(0.38mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.).
3. Dimension "A" controls the overall package thickness. The maximum
"A" dimension is the package height before being solder dipped.
4
4
1.40
2.41
.38
ND/NE
1. The index feature for terminal 1 identification, optical orientation or
handling purposes, shall be within the shaded index areas shown on
planes 1 and 2. Plane 1 terminal 1 identification may be an extension
of the length of the metallized terminal which shall not be wider than
the B1 dimension.
5
4. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer's option, from that shown on the drawing. The index
corner shall be clearly unique.
5. Dimension "B3" minimum and "L3" minimum and the appropriately
derived castellation length define an unobstructed three dimensional
space traversing all of the ceramic layers in which a castellation was
designed. Dimension "B3" maximum and "L3" maximum define the
maximum width and depth of the castellation at any point on its
surface. Measurement of these dimensions may be made prior to
solder dripping.
6. Chip carriers shall be constructed of a minimum of two ceramic layers.
LID
PLANE 2
PLANE 1
D
See Note 1
A1
L3
B3
B1
E
DETAIL "A"
A
Index Corner
(j) x 45¡
(h) x 45¡
4
3 PLCS
DETAIL "A"
D2
e
D1
L2
L1
11
RM3182A
PRODUCT SPECIFICATION
Ordering Information
Part Number
Package
Operating Temperature Range
RM3182AS
16-Lead Sidebraze Ceramic DIP
-55°C to +125°C
RM3182AL
28-Terminal Leadless Chip Carrier
-55°C to +125°C
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
5/20/98 0.0m 001
Stock# DS3003182A
Ó 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RM3183
Dual ARINC 429 Line Receiver
Features
•
•
•
•
•
•
•
•
clamping diodes. Self-test logic inputs are provided for
internal system tests. These inputs force the outputs to
either a high, a low, or a null state for off-line system tests.
Converts ARINC levels to serial data
Adjustable noise filters
TTL and CMOS compatible outputs
Built-in test inputs
Input protection circuitry
Mil-Std-883B screening available
20-pin DIP and LCC packages available
Dice with Mil visual screening available
Input noise filtering is accomplished with external capacitors. Two are required for each channel and can be adjusted
for best noise immunity at a specific data rate.
Three power supplies are needed plus ground. The input
thresholds depend only on the logic supply, so a wide range
of dual supplies can be accommodated.
Description
The RM3183 is a dual line receiver designed to meet all
requirements of the ARINC 429 interface specification.
It contains two independent receiver channels which accept
differential input signals and converts them to serial TTL
data.
Input overvoltage protection is provided by special circuitry
including dielectrically-isolated thin-film resistors and
The Fairchild RM3183 line receiver is the companion chip to
the RM3182 line driver. Together they provide all the
analog functions needed for the ARINC 429 interface.
Digital data processing involving serial-to-parallel conversion and clock recovery can be accomplished using one of
the ARINC interface ICs available or by discrete or gate
array implementations.
Block Diagram
+VL
+VS
11
In 1A
In 1B
Cap 1A
Cap 1B
18
19
Test B
Cap 2B
12
C1B
20
Cap 2A
15
C1A
Out 1A
Out 1B
17
2
In 2B
Input
Protection
& Level
Shift
16
Test A
In 2A
9
Test
Interface
8
C2A
6
Input
Protection
& Level
Shift
4
7
5
C2B
Out 2A
Out 2B
3
1
-VS
14
Gnd
65-3183-01
Rev. 1.0.0
RM3183
PRODUCT SPECIFICATION
Functional Description
The RM3183 contains two discrete ARINC 429 receiver
channels. Each channel contains three main sections: a
resistor-diode input network, a window comparator, and a
logic output buffer stage. The first stage provides overvoltage protection and biases the signal using voltage dividers
and current sources which are internally connected to the
+VL logic supply. This configuration provides excellent
input common mode rejection and a stable reference voltage
for the window comparators. Because the threshold for
switching is determined by this circuitry, ±5% tolerance is
recommended for the +VL supply. The test inputs will set the
outputs to a predetermined state for built-in test capability.
The ARINC inputs must be forced to 0V when using the test
inputs. If the test inputs are not used, they should be
grounded.
The window comparator stage generates two serial data
streams, one having logic 1 states corresponding to ARINC
“High” states (OUTA), and the other having logic 1 states
corresponding to ARINC “Low” states (OUTB). An ARINC
“Null” state at the inputs forces both outputs to logic 0.
Thus, the ARINC clock signal is recovered by applying a
NOR function to OUTA and OUTB.
The output stage generates a TTL compatible logic output
capable of driving several gate inputs.
Pin Assignments
Cap2B
3
18
In1A
In2B
4
17
Cap1B
Out2B
5
16
In1B
6
15
Out1A
Cap2A
7
14
GND
Out2A
8
13
NC
+VL
9
12
Out1B
NC
10
11
+VS
In2B 4
18
In1A
Out2B 5
17
Cap1B
In2A 6
16
In1B
Cap2A 7
15
Out1A
Out2A 8
14
GND
+VL
9
In2A
19 Cap1A
Cap1A
NC 13
19
1 -VS
20 TestB
2
Out1B 12
TestA
+VS 11
TestB
3 Cap2B
20
NC 10
-VS
2 TestA
LCC
Top View
Ceramic Dip
Top View
65-3183-03
65-3183-02
Absolute Maximum Ratings
Parameter
Supply Voltage
Max.
Units
+VS
+20
VDC
–VS
–20
VDC
+VL
+7
VDC
Operating Temperature Range
-55
+125
°C
Storage Temperature Range
-65
+150
°C
±50
V
Input Voltage Range
Output Short Circuit Duration
2
Min.
Not protected
Internal Power Dissipation
900
mW
Lead Soldering Temperature (60 seconds)
+300
°C
PRODUCT SPECIFICATION
RM3183
Thermal Characteristics
(Still air, soldered into PC board)
Ceramic DIP
LCC
+175°C
+175°C
Maximum PD TA < 50°C
1042 mW
925 mW
Thermal Resistance, qJC
60°C/W
37°C/W
Thermal Resistance, qJC
120°C/W
105°C/W
Maximum Junction Temperature
DC Electrical Characteristics
TA = -55°C to +125°C, ±12V £ VS ±15V, VL = +5V, unless otherwise noted
Symbol
Parameter
Conditlons
Min.
Typ.
Max.
Units
13
V
VIH
V(A)-V(B)
OUTA = 1
6.5
10
VIL
V(A)-V(B)
OUTB = 1
-6.5
-10
-13
V
VIN
V(A)-V(B)
OUTA and OUTB = 0
-2.5
0
+2.5
V
VIC
V(A) and V(B)-GND
Maximum common mode
frequency = 80 kHz
RI
Input resistance, Input A to Input B
RH
RG
(2)
(1, 2)
V
30
50
kW
Input resistance, Input A to Gnd
19
25
kW
Input resistance, B to Gnd
19
25
kW
Input capacitance, A to B
Filter caps disconnected
3
10
pF
(1, 2)
Input capacitance, A to Gnd
Filter caps disconnected
3
10
pF
(1, 2)
Input capacitance, B to Gnd
Filter caps disconnected
3
10
pF
CI
CH
±5
CG
Test Inputs (TESTA, TESTB)
VIH
Logic 1 input voltage
2.7
VIL
Logic 0 input voltage
IIH
Logic 1 input current
VIH = 2.7V
IIL
Logic 0 input current
VIL = 0.0V
IOH = 100 mA
TA = 25°C
4.0
4.3
V
IOH = 2.8 mA
Full temperature range
3.5
4.0
V
IOL = 100 mA
TA = 25°C
0.02
0.08
V
IOL = 2.0 mA
Full temperature range
0.3
0.8
V
V(A) = 0V
V(B) = 0V
V
0.0
V
5
15
mA
0.5
1.0
mA
Outputs
VOH
VOL
Tr
Rise Time
CL = 50 pF, TA = 25°C
40
70
ns
Tf
Fall Time
CL = 50 pF, TA = 25°C
30
70
ns
TPLH
Propagation delay
Output low to high
CL = 50 pF, fO = 400 kHz
Filter caps = 39 pF
800
ns
TPHL
Output high to low
TA = 25°C
320
ns
3
RM3183
PRODUCT SPECIFICATION
DC Electrical Characteristics (continued)
TA = -55°C to +125°C, ±12V £ VS ±15V, VL = +5V, unless otherwise noted
Symbol
Parameter
Conditlons
Min.
Typ.
Max.
Units
±VS = 15V, TA = 15°C
3.7
7.0
mA
±VS = 12V, TA = 15°C
3.0
6.0
mA
±VS = 15V, TA = 15°C
8.7
15.0
mA
±VS = 12V, TA = 15°C
7.4
14.0
mA
±VS = 15V, TA = 15°C
9.0
20.0
mA
±VS = 12V, TA = 15°C
8.6
18.0
mA
Supply Current
ICC
(+VS)
Test inputs = 0V
IEE
(-VS)
Test inputs = 0V
IDD
(+VL)
Test inputs = 0V
Notes:
1. With noise filter capacitors disconnected.
2. Guaranteed by design.
Truth Table
ARINC Inputs
V(A) - V(B)
4
Test Inputs
TESTA
Outputs
TESTB
OUTA
OUTB
Null
0
0
0
0
Low
0
0
0
1
High
0
0
1
0
V(A) = 0V, V(B) = 0V
0
1
0
1
V(A) = 0V, V(B) = 0V
1
0
1
0
V(A) = 0V, V(B) = 0V
1
1
0
0
PRODUCT SPECIFICATION
RM3183
12
900
11
800
10
T PLH
600
500
T PHL
400
300
200
100
0
-60
-35
-10
15
40
65
90
-VS (I EE )
9
8
VS = 15V
VL = +5V
7
6
5
+V S (I CC )
4
3
-60
140
115
VL (I DD )
65-3183-05
700
Supply Current (mA)
1000
65-3183-04
Prop Delay (ns)
Typical Performance Characteristics
-35
-10
15
Temperature (¡C)
40
65
90
115
140
Temperature (¡C)
Figure 1. Propagation Delay vs. Temperature
CL = 50 pF, CFILTER = 39 pF
Figure 2. Supply Current vs. Temperature
1.00
4.5
+125¡C
4.3
+125¡C
+25¡C
0.50
65-3183-06
0.25
+55¡C
0
0
0.5
1.0
1.5
2.0
2.5
+25¡C
4.1
3.9
-55¡C
65-3183-07
VOH (Volts)
VOL (Volts)
0.75
3.7
3.5
3.0
0
0.5
1.0
IOL (mA)
2.5
3.0
Figure 4. Output Voltage High vs. Output Current
3.0
70
40
TF
30
65-3183-08
20
10
-10
15
40
65
90
115
Temperature (¡C)
Figure 5. TR and TF vs. Temperature
140
Prop Delay (µs)
50
-35
T A = +25 C
2.5
TR
T PLH
2.0
T PHL
1.5
1.0
65-3183-09
60
Rise/Fall Time (ns)
2.0
IOH (mA)
Figure 3. Output Voltage Low vs. Output Current
0
-60
1.5
0.5
0
0
50
100
150
200
250
300
350
400
Filter Capacitance (pF)
Figure 6. Propagation Delay vs. Filter Capacitance
TA = 25°C
5
RM3183
PRODUCT SPECIFICATION
AC Test Waveforms
+10V
ARINC In
(Differential) 0V
Logic
Out
Logic Out
(A Output)
90%
90%
10%
10%
TPLH
TPHL
TF
TR
65-3183-10
65-3183-16
Figure 7. Propagation Delay
Figure 8. Rise/Fall Times
Test Circuit
+15V
VIN1
-15V
0.01 mF
0.1 mF
+5V
0.01 mF
11
18
9
1
VOUT1
15
50 pF
VIN2
6
50 pF
RM3183
16
VREF
VOUT2
12
VOUT3
8
4
50 pF
19
17
3
7
14
VOUT4
5
50 pF
39pF 39pF
39pF
39pF
Notes:
1. VIN = 400 kHz square wave, -3.5V to +3.5V.
2. Set VREF = +3.5 V to test VOUT1 and VOUT3.
Set VREF = -3.5 V to test VOUT2 and VOUT4.
3. 50 pF load capacitance includes probe and wiring capacitance.
Figure 9. AC Test Schematic Diagram
6
65-3183-11
PRODUCT SPECIFICATION
Applications Information
The standard connections for the RM3183 are shown in
Figure 1. Dual supplies from ±12 to ±15 VDC are recommended for the ±VS supplies. Decoupling of all supplies
should be done near the IC to avoid propagation of noise
spikes due to switching transients. The ground connections
should be sturdy and isolated from large switching currents
to provide as quiet a ground reference as possible.
The noise filter capacitors are optional and are added to
provide extra noise immunity by limiting the noise bandwidth of the input signal before it reaches the comparator.
Two capacitors are required for each channel and they must
all be the same value. The suggested capacitor value for a
100 KHz operation is 39 pF, which will give a noise bandwidth of approximately 800 KHz. For lower data rates, larger
values of capacitance may be used to yield better noise
performance. To get optimum performance, the following
equation should be used to calculate capacitor value for a
specific data rate:
RM3183
The RM3183 can be used with Fairchild’s RM3182 Line
Driver to provide a complete analog ARINC 429 interface.
A simple application which can be used for systems requiring a repeater-type circuit for long transmissions or test
interfaces is given in Figure 2. More RM3182 drivers may be
added to test multiple ARINC channels, as shown.
An all digital IC is available which forms a complete
receiver system when combined with the RM3183. The
Thomson EF4442 is a four channel ARINC 429 receiver IC
which contains all the digital circuitry required to interface
with an 8-bit processor. Each channel consists of a 32-bit
register, an 8-bit status word comparator, and a 24-bit latch.
A multiplexer and 8-bit data bus buffer form the interface to
the system microprocessor. Figure 3 shows a typical ARINC
application having both transmit and receive functions using
four ICs: the EF4442, the RM3182 driver and two RM3183
dual receivers.
–6
3.95 ´ 10
C = --------------------------FO
F O = Data Rate (bits/sec)
7
RM3183
PRODUCT SPECIFICATION
Applications
+5V
+15V
9
11
RM3183
18
ARINC
Channel
1
16
39 pF
19
17
In 1A
15
In 1B
Cap 1A
12
A
B
Channel 1
Data Out
To Logic
Cap 1B
39 pF
6
ARINC
Channel
2
4
In 2A
8
A
In 2B
39 pF
7
3
5
Cap 2A
Channel 2
Data Out
To Logic
B
Cap 2B
39 pF
2
Logic
Test
Inputs
20
Test A
Test B
1
14
65-3183-12
-15V
Figure 9. ARINC Receiver Standard Connections
ARINC
Test
Channel
Input
A
In 1A
Out 1A
Data (B)
In 1B
B
A OUT
Data (A)
A
RM3182
B
Out 2A
B OUT
1/2
RM3183
A OUT
Data (A)
A
RM3182
Data (B)
To Additional
Channels
Figure 10. Repeater Circuit
8
Test
Channel
1
B OUT
B
Test
Channel
2
65-3183-13
PRODUCT SPECIFICATION
RM3183
Applications (continued)
+5V
+15V
Inputs
VCC
+V L
VSS
V R V I Sync Clk +VS
Mode
RM3182
ARINC
Channel
0
In 1A
Out 1A
H0
In 1B
Out 1B
L0
A OUT
RM3183
ARINC
Channel
1
In 2A
Out 2A
H1
In 2B
Out 2B
L1
N1
Data (A)
N0
Data (B)
-VS
Gnd PE
+VS GND -VS
EF4442
75 pF
From
Microprocessor
IRQ
+VS GND -VS
In 1A
Out 1A
H2
R/W
In 1B
Out 1B
L2
Clock
RM3183
ARINC
Channel
3
-15V
CB
Reset
+15V
ARINC
Channel
2
CA
75 pF
-15V
ARINC
Line Out
B OUT
Microprocessor
Data Bus
D0 - D8
In 2A
Out 2A
H3
In 2B
Out 2B
L3
A0
From
Address
Decoder
A1
+VL
65-3183-14
CS
To +5V
Figure 11. Four-Channel ARINC Receiver Circuit
-15V
10 W
1/2 W
+15V
1
4
10K
18
5
10K
16
RM3183
6
10K
15
10K
14
8
11
9
12
10K
10K
10 W
1/2 W
10W
1/2 W
65-3183-15
+5V
+15V
Figure 12. Burn-In Circuit
9
PRODUCT SPECIFICATION
RM3183
Mechanical Dimensions
20-Lead Ceramic DIP
Symbol
Inches
Min.
A
b1
b2
c1
D
E
e
eA
L
Q
s1
a
Max.
—
.200
.014
.023
.045
.065
.008
.015
—
1.060
.220
.310
.100 BSC
.300 BSC
.125
.200
.015
.060
.005
—
90¡
105¡
Millimeters
Min.
Notes
Max.
—
5.08
.36
.58
1.14
1.65
.20
.38
—
25.92
5.59
7.87
2.54 BSC
7.62 BSC
3.18
5.08
.38
1.52
.13
—
90¡
105¡
8
2, 8
8
4
4
5, 9
7
3
6
Notes:
1. Index area: a notch or a pin one identification mark shall be located
adjacent to pin one. The manufacturer's identification shall not be
used as pin one identification mark.
2. The minimum limit for dimension "b2" may be .023(.58mm) for leads
number 1, 10, 11 and 20 only.
3. Dimension "Q" shall be measured from the seating plane to the
base plane.
4. This dimension allows for off-center lid, meniscus and glass overrun.
5. The basic pin spacing is .100 (2.54mm) between centerlines. Each
pin centerline shall be located within ±.010 (.25mm) of its exact
longitudinal position relative to pins 1 and 20.
6. Applies to all four corner's (leads number 1, 10, 11, and 20).
7. "eA" shall be measured at the center of the lead bends or at the
centerline of the leads when "a" is 90¡.
8. All leads – Increase maximum limit by .003(.08mm) measured at the
center of the flat, when lead finish is applied.
9. Eighteen spaces.
D
Note 1
E
s1
eA
e
A
Q
L
b2
a
c1
b1
10
RM3183
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
20-Terminal LCC
Inches
Symbol
Notes:
Millimeters
Notes
Min.
Max.
Min.
Max.
A
A1
B1
B3
.060
.050
.022
.100
.088
1.52
1.27
.56
2.54
2.24
3, 6
3, 6
.71
.56
2
2, 5
D/E
D1/E1
D2/E2
.342
.358
.200 BSC
8.69
9.09
5.08 BSC
.100 BSC
—
.358
.050 BSC
2.54 BSC
—
9.09
1.27 BSC
.040 REF
1.02 REF
4
.020 REF
.045
.055
.51 REF
1.14
1.40
4
.075
.003
1.91
.08
.028
.022
.006
D3/E3
e
h
j
L1
L2
L3
ND/NE
N
.15
.095
.015
5
20
20
2. Unless otherwise specified, a minimum clearance of .015 inch
(0.38mm) shall be maintained between all metallized features (e.g.,
lid, castellations, terminals, thermal pads, etc.).
3. Dimension "A" controls the overall package thickness. The
maximum "A" dimension is the package height before being solder
dipped.
2.41
.38
5
1. The index feature for terminal 1 identification, optical orientation or
handling purposes, shall be within the shaded index areas shown
on planes 1 and 2. Plane 1, terminal 1 identification may be an
extension of the length of the metallized terminal which shall not be
wider than the B1 dimension.
5
4. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer's option, from that shown on the drawing. The index
corner shall be clearly unique.
5. Dimension "B3" minimum and "L3" minimum and the appropriately
derived castellation length define an unobstructed three
dimensional space traversing all of the ceramic layers in which a
castellation was designed. Dimensions "B3" and "L3" maximum
define the maximum width and depth of the castellation at any point
on its surface. Measurement of these dimensions may be made
prior to solder dripping.
6. Chip carriers shall be constructed of a minimum of two ceramic
layers.
PLANE 1
PLANE 2
E
LID
E3
D
1
A1
D3
(h) X 45¡
3 PLCS
4
(j) X 45¡
4
A
INDEX
CORNER
E1
E2
B1
e
D2
L3
D1
B3
L2
L1
DETAIL "A"
DETAIL "A"
11
PRODUCT SPECIFICATION
RM3183
Ordering Information
Part Number
Package
Operating Temperature Range
RM3183S
20 Lead Ceramic DIP
-55°C to +125°C
RM3183L
20 Terminal Leadless Chip Carrier
-55°C to +125°C
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
5/20/98 0.0m 001
Stock# DS30003183
Ó 1998 Fairchild Semiconductor Corporation
www.fairchildsemi.com
RM3283
Dual ARINC 429 Line Receiver
Features
•
•
•
•
•
•
•
•
•
Two separate analog receiver channels
Converts ARINC 429 levels to serial data
Built-in TTL compatible complete channel test inputs
TTL and CMOS compatible outputs
Low power dissipation
Internal bandgap
Short circuit protected
MIL-STD-883B screening available for ceramic packages
Available in 20-Lead ceramic DIP, 20-Terminal LCC, and
20-Lead SOIC
Description
The RM3283 consists of two analog ARINC 429 receivers
which take differentially encoded ARINC level data and
convert it to serial TTL level data. The RM3283 provides
two complete analog ARINC receivers and no external
components are required.
Input level shifting thin film resistors and bipolar technology
allow ARINC input voltage transients up to ±100V without
damage to the RM3283.
Each channel is identical, featuring symmetrical propagation
delays for better high speed performance. Input common
mode rejection is excellent and threshold voltage is stable,
independent of supply voltage. Data outputs are TTL and
CMOS compatible.
Two TTL compatible test inputs used to test the ARINC
channels are available. They can be used to override the
ARINC input data and set the channel outputs to a known
state.
The Fairchild RM3182/RM3182A line driver is the
companion chip to the RM3283 line receiver. Together they
provide the analog functions needed for the ARINC 429
interface. Digital data processing involving serial-to-parallel
conversion and clock recovery can be accomplished using
one of the ARINC interface IC’s available or by an
equivalent gate array implementation.
Block Diagram
+VL
+VS
11
RM3283
In 1A
In 1B
Cap 1A
Cap 1B
Test A
Test B
Cap 2A
Cap 2B
In 2A
In 2B
9
Bit
Detection
and Level
Shifting
Hysteresis
18
16
15
Output
Driver
12
Out 1A
Out 1B
19
17
2
20
Channel
Test
Circuitry
Bandgap Voltage
Reference
Threshold
Generator
7
3
Bit Detection
and Level
Shifting
Hysteresis
6
4
1
-VS
8
Output
Driver
5
Out 2A
Out 2B
14
Gnd
65-3283-01
Rev. 1.0.0
RM3283
PRODUCT SPECIFICATION
Functional Description
The RM3283 contains two discrete ARINC 429 receiver
channels. Each channel contains three main sections: a
resistor input network, a window comparator, and a logic
output buffer stage. The first stage provides overvoltage
protection and biases the signal using voltage dividers and
current sources, providing excellent input common mode
rejection. The test inputs are provided to set the outputs to a
predetermined state for built-in channel test capability. If the
test inputs are not used, they should be grounded.
The window comparator section detects data from the resistor input network. A Logic 1 corresponds to ARINC “High”
state (OUTA) and a Logic 0, to ARINC “Low” state (OutB).
An ARINC “Null” state at the inputs forces both outputs to
Logic 0. Threshold and hysteresis voltages are generated by
a bandgap voltage reference to maintain stable switching
characteristics over temperature and power supply
variations.
The output stage generates a TTL compatible logic output
capable of driving 3mA of load.
Pin Assignments
Cap2B
3
18
In1A
In2B
4
17
Cap1B
5
16
In1B
In2A
6
15
Out1A
Cap2A
7
14
GND
Out2A
8
13
NC
+VL
9
12
Out1B
NC
10
11
+VS
In2B 4
18
In1A
Out2B 5
17
Cap1B
In2A 6
16
In1B
Cap2A 7
15
Out1A
Out2A 8
14
GND
+VL
9
Out2B
19 Cap1A
Cap1A
NC 13
19
1 -VS
20 TestB
2
Out1B 12
TestA
+VS 11
TestB
3 Cap2B
20
NC 10
-VS
2 TestA
LCC
Top View
DIP and SOIC
Top View
65-3283-03
65-3283-02
Absolute Maximum Ratings
Parameter
Max.
Units
Supply Voltage (VCC to VEE)
Min.
+36
V
VLOGIC Voltage
+7
V
-0.3
VLOGIC + 0.3
V
Storage
-65
+150
°C
Operating
-55
+125
°C
-55
+175
°C
60 sec., DIP, LCC
+300
°C
10 sec., SOIC
+260
°C
Logic Input Voltage
Temperature Range
Junction Temperature
Lead Soldering Temperature
2
PRODUCT SPECIFICATION
RM3283
Thermal Characteristics (Still air, soldered on a PC board)
Parameter
LCC
DIP
SOIC
Maximum Junction Temperature
+175°C
+175°C
+125°C
Thermal Resistance, qJC
85°C/W
70°C/W
85°C/W
Thermal Resistance, qJC
20°C/W1
28°C/W1
30°C/W
Note:
1. MIL-STD-1835.
DC Electrical Characteristics
TA = -55°C to +125°C, ±12V £ VS ±15V, VL = +5V, unless otherwise noted.
Symbol
ICC (+VS)
IEE (-VS)
IL (VL)
VTL2
VTH2
VIN
VIC3
Parameter
Test inputs = 0V
Test inputs = 0V
Test inputs = 5V
V(A)-V(B)
V(A)-V(B)
V(A)-V(B)
V(A) and V(B)-GND
Input resistance, Input A to Input B
RI
Input resistance, Input A to Gnd
RH
Input resistance, B to Gnd
RG
Input capacitance, A to B
CI1,4
1,4
CH
Input capacitance, A to Gnd
CG1,4
Input capacitance, B to Gnd
Test Inputs (TestA, TestB)
VIH5
Logic 1 input voltage
5
VIL
Logic 0 input voltage
IIH
Logic 1 input current
Logic 0 input voltage
IIL
Outputs
VOH
VOL
Tr6
Tf6
TPLH
TPHL
IOH = 100 mA
IOH = 2.8 mA
IOL = 100 mA
IOL = 2.0 mA
Rise Time
Fall Time
Propagation delay
Output low to high
Output high to low
Conditlons
Min.
Low threshold
High threshold
OutA and OutB = 0
4.7
5.7
-2.5
Maximum common mode
frequency = 80 kHz
Filter caps disconnected
35
20
20
Typ.
4.3
10.1
14.0
5.0
6.0
0
V
50
25
25
kW
kW
kW
pF
pF
pF
10
10
10
2.7
0
VIH = 5V
VIL = 0.8V
120
15
4.0
3.5
Units
mA
mA
mA
V
V
V
±5
Filter caps disconnected
Filter caps disconnected
TA = 25°C
Full temperature range
TA = 25°C
Full temperature range
CL = 50 pF, @ 25°C
CL = 50 pF, @ 25°C
CL = 50 pF, f = 400 kHz
Filter caps = 39 pF
TA = 25°C
Max.
6.0
12.0
17.5
5.3
6.3
2.5
0.8
300
40
4.3
4.0
V
V
mA
mA
V
V
0.02
0
0.1
0.8
V
V
50
40
700
70
70
ns
ns
ns
700
ns
Notes:
1. As stated in ARINC429.
2. VT refers ot the threshold voltage at which the channels output switches from low to high or from high to low.
3. Common mode voltage present at both ARINC inputs.
4. Guaranteed by design.
5. Test inputs should be connected to ground if not used.
6. Sample tested.
3
RM3283
PRODUCT SPECIFICATION
Typical Performance Characteristics
20
900
TPHL
800
16
TPLH
Current (mA)
500
400
300
12
10
100
25
I EE
8
6
65-3283-04
200
0
-55
IL
14
600
I CC
4
65-3283-05
700
TPHL, TPLH (ns)
18
2
0
-55
125
25
125
Temperature (¡C)
Temperature (¡C)
Figure 1. Propagation Delay vs. Temperature
CL = 50 pF, CFILTER = 39 pF
Figure 2. Supply Current vs. Temperature
1.00
4.5
+125¡C
4.3
+125¡C
+25¡C
0.50
65-3283-06
0.25
+55¡C
0
0
0.5
1.0
1.5
2.0
2.5
+25¡C
4.1
3.9
-55¡C
65-3283-07
VOH (Volts)
VOL (Volts)
0.75
3.7
3.5
3.0
0
0.5
1.0
IOL (mA)
3.0
TF
TR
30
65-3283-08
20
10
25
Temperature ( C)
Figure 5. TR and TF vs. Temperature
125
T PLH
2.0
T PHL
1.5
1.0
65-3283-09
50
40
T A = +25 C
2.5
Prop Delay (µs)
60
Rise/Fall Time (ns)
3.0
2.5
Figure 4. Output Voltage High vs. Output Current
70
4
2.0
IOH (mA)
Figure 3. Output Voltage Low vs. Output Current
0
-55
1.5
0.5
0
0
50
100
150
200
250
300
350
400
Filter Capacitance (pF)
Figure 6. Propagation Delay vs. Filter Capacitance
TA = 25°C
PRODUCT SPECIFICATION
RM3283
AC Test Waveforms
+10V
ARINC In
(Differential)
0V
Logic Out
(A Output)
90%
90%
Logic
Out
10%
10%
T PLH
TF
TR
T PHL
65-3283-10
65-3283-11
Figure 7. Propagation Delay
Figure 8. Rise/Fall Times
Test Circuit
+15V
0.1 mF
-15V
0.01 mF
+5V
0.01 mF
In1 A
11
18
9
1
Out 1A
15
50 pF
In2 A
6
50 pF
RM3283
16
VREF
Out 1B
12
Out 2A
8
4
50 pF
19
17
3
7
14
Out 2B
5
50 pF
39pF 39pF
39pF
39pF
Notes:
1. VIN = 400 kHz square wave, -3.5V to +3.5V.
2. Set VREF = +3.5 V to test VOUT1 and VOUT3.
Set VREF = -3.5 V to test VOUT2 and VOUT4.
65-3283-12
3. 50 pF load capacitance includes probe and wiring capacitance.
Figure 9. AC Test Schematic Diagram
5
RM3283
PRODUCT SPECIFICATION
Truth Table
ARINC nputs
V(A) - V(B)
Test Inputs
Outputs
TESTA
TESTB
OUTA
OUTB
Output
State
Null
0
0
0
0
Null
Low
0
0
0
1
Low
High
0
0
1
0
High
X
0
1
0
1
Low
X
1
0
1
0
High
X
1
1
0
0
Null
Applications Discussion
The standard connections for the RM3283 are shown in
Figure 10. Dual supplies from ±12 to ±15 VDC are recommended for the ±VS supplies. Decoupling of all supplies
should be done near the IC to avoid propagation of noise
spikes due to switching transients. The ground connection
should be sturdy and isolated from large switching currents
to provide as quiet a ground reference as possible.
The noise filter capacitors are optional and are added to
provide extra noise immunity by limiting bandwidth of the
input signal before it reaches the window comparator stage.
Two capacitors are required for each channel and they must
all be the same value. The suggested capacitor value for a
100 kHz operation is 39 pF. For lower data rates, larger values of capacitance may be used to yield better node perfor-
6
mance. To get optimum performance, the following equation
can be used to calculate capacitor value for a specific data
rate:
–6
3.95 ´ 10
C FILTER = --------------------------FO
Where CFILTER is the capacitor value in pF, and FO is the
input frequency (10 kHz £ FO £ 150 kHz).
The RM3283 can be used with the Fairchild RM3182/
RM3182A line driver to provide a complete analog ARINC
429 interface. A simple application which can be used for
systems requiring a repeater-type circuit for long transmissions is given in Figure 11. More RM3182 drivers may be
added to test multiple ARINC channels, as shown.
RM3283
PRODUCT SPECIFICATION
Applications
+5V
+15V
9
11
RM3283
18
ARINC
Channel
1
16
39 pF
19
In 1A
15
In 1B
Cap 1A
12
A
B
Channel 1
Data Out
To Logic
17 Cap 1B
39 pF
6
ARINC
Channel
2
4
In 2A
8
A
In 2B
39 pF
7
3
5
Cap 2A
Channel 2
Data Out
To Logic
B
Cap 2B
39 pF
2
Logic
Test
Inputs
20
Test A
Test B
1
14
65-3283-13
-15V
Figure 10. ARINC Receiver Standard Connections
ARINC
Test
Channel
Input
A
In 1A
Out 1A
Data (B)
In 1B
B
1/2
RM3283
A OUT
Data (A)
A
RM3182
B
Out 2A
B OUT
A OUT
Data (A)
A
RM3182
Data (B)
To Additional
Channels
Figure 11. Repeater Circuit
7
B OUT
B
Test
Channel
1
Test
Channel
2
65-3282-14
PRODUCT SPECIFICATION
RM3283
Applications (continued)
+5V
+15V
Inputs
VCC
+V L
ARINC
Channel
0
In 1A
Out 1A
H0
In 1B
Out 1B
L0
VSS
RM3283
ARINC
Channel
1
In 2A
Out 2A
H1
In 2B
Out 2B
L1
V R V I Sync Clk +VS
RM3182
RM3182A
A OUT
Mode
N1
Data (A)
N0
Data (B)
-VS
Gnd PE
+VS GND -VS
EF4442
-15V
CB
75 pF
Reset
+15V
From
Microprocessor
IRQ
+VS GND -VS
In 1A
Out 1A
H2
R/W
In 1B
Out 1B
L2
Clock
RM3283
ARINC
Channel
3
CA
75 pF
-15V
ARINC
Channel
2
ARINC
Line Out
B OUT
Microprocessor
Data Bus
D0 - D8
In 2A
Out 2A
H3
In 2B
Out 2B
L3
A0
From
Address
Decoder
A1
+VL
65-3283-15
CS
To +5V
Figure 12. Four-Channel ARINC Receiver Circuit
-15V
10 W
1/2 W
+15V
1
4
10K
18
5
10K
16
RM3283
6
10K
15
10K
8
14
11
9
12
10K
10K
10 W
1/2 W
10 W
1/2 W
65-3283-16
+5V
+15V
Figure 13. Burn-In Circuit
8
PRODUCT SPECIFICATION
RM3283
Mechanical Dimensions
20-Lead SOIC
Inches
Symbol
Min.
A
A1
B
C
D
E
e
H
h
L
N
a
ccc
Notes:
Millimeters
Max.
Min.
Notes
.093
.104
.004
.012
.013
.020
.009
.013
.496
.512
.291
.299
.050 BSC
2.35
2.65
0.10
0.30
0.33
0.51
0.23
0.32
12.60
13.00
7.40
7.60
1.27 BSC
.394
.010
.016
10.00
0.25
0.40
.419
.029
.050
20
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
Max.
10.65
0.75
1.27
20
0¡
8¡
0¡
8¡
—
.004
—
0.10
2. "D" and "E" do not include mold flash. Mold flash or
protrusions shall not exceed .010 inch (0.25mm).
3. "L" is the length of terminal for soldering to a substrate.
4. Terminal numbers are shown for reference only.
5
2
2
5. "C" dimension does not include solder finish thickness.
6. Symbol "N" is the maximum number of terminals.
3
6
11
20
E
H
10
1
h x 45¡
D
C
A1
A
e
B
SEATING
PLANE
–C–
LEAD COPLANARITY
a
L
ccc C
9
RM3283
PRODUCT SPECIFICATION
Mechanical Dimensions (continued)
20-Lead Ceramic DIP
Symbol
Inches
Min.
A
b1
b2
c1
D
E
e
eA
L
Q
s1
a
Max.
—
.200
.014
.023
.045
.065
.008
.015
—
1.060
.220
.310
.100 BSC
.300 BSC
.125
.200
.015
.060
.005
—
90¡
105¡
Millimeters
Min.
Notes
Max.
—
5.08
.36
.58
1.14
1.65
.20
.38
—
25.92
5.59
7.87
2.54 BSC
7.62 BSC
3.18
5.08
.38
1.52
.13
—
90¡
105¡
8
2, 8
8
4
4
5, 9
7
3
6
Notes:
1. Index area: a notch or a pin one identification mark shall be located
adjacent to pin one. The manufacturer's identification shall not be
used as pin one identification mark.
2. The minimum limit for dimension "b2" may be .023(.58mm) for leads
number 1, 10, 11 and 20 only.
3. Dimension "Q" shall be measured from the seating plane to the
base plane.
4. This dimension allows for off-center lid, meniscus and glass overrun.
5. The basic pin spacing is .100 (2.54mm) between centerlines. Each
pin centerline shall be located within ±.010 (.25mm) of its exact
longitudinal position relative to pins 1 and 20.
6. Applies to all four corner's (leads number 1, 10, 11, and 20).
7. "eA" shall be measured at the center of the lead bends or at the
centerline of the leads when "a" is 90¡.
8. All leads – Increase maximum limit by .003(.08mm) measured at the
center of the flat, when lead finish is applied.
9. Eighteen spaces.
D
Note 1
E
s1
eA
e
A
Q
L
b2
10
b1
a
c1
PRODUCT SPECIFICATION
RM3283
Mechanical Dimensions (continued)
20-Terminal LCC
Inches
Symbol
Notes:
Millimeters
Notes
Min.
Max.
Min.
Max.
A
A1
B1
B3
.060
.050
.022
.100
.088
1.52
1.27
.56
2.54
2.24
3, 6
3, 6
.71
.56
2
2, 5
D/E
D1/E1
D2/E2
.342
.358
.200 BSC
8.69
9.09
5.08 BSC
.100 BSC
—
.358
.050 BSC
2.54 BSC
—
9.09
1.27 BSC
.040 REF
1.02 REF
4
.020 REF
.045
.055
.51 REF
1.14
1.40
4
.075
.003
1.91
.08
.028
.022
.006
D3/E3
e
h
j
L1
L2
L3
ND/NE
N
.15
.095
.015
5
20
20
2. Unless otherwise specified, a minimum clearance of .015 inch
(0.38mm) shall be maintained between all metallized features (e.g.,
lid, castellations, terminals, thermal pads, etc.).
3. Dimension "A" controls the overall package thickness. The
maximum "A" dimension is the package height before being solder
dipped.
2.41
.38
5
1. The index feature for terminal 1 identification, optical orientation or
handling purposes, shall be within the shaded index areas shown
on planes 1 and 2. Plane 1, terminal 1 identification may be an
extension of the length of the metallized terminal which shall not be
wider than the B1 dimension.
5
4. The corner shape (square, notch, radius, etc.) may vary at the
manufacturer's option, from that shown on the drawing. The index
corner shall be clearly unique.
5. Dimension "B3" minimum and "L3" minimum and the appropriately
derived castellation length define an unobstructed three
dimensional space traversing all of the ceramic layers in which a
castellation was designed. Dimensions "B3" and "L3" maximum
define the maximum width and depth of the castellation at any point
on its surface. Measurement of these dimensions may be made
prior to solder dripping.
6. Chip carriers shall be constructed of a minimum of two ceramic
layers.
PLANE 1
PLANE 2
E
LID
E3
D
1
A1
D3
(h) X 45¡
3 PLCS
4
(j) X 45¡
4
A
INDEX
CORNER
E1
E2
B1
e
D2
L3
D1
B3
L2
L1
DETAIL "A"
DETAIL "A"
11
PRODUCT SPECIFICATION
RM3283
Ordering Information
Part Number
Package
Operating Temperature Range
RV3283M
20 Lead SOIC
-40°C to +85°C
RM3283D
20 Lead Ceramic DIP
-55°C to +125°C
RM3283L
20 Terminal Leadless Chip Carrier
-55°C to +125°C
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
5/20/98 0.0m 001
Stock# DS30003283
Ó 1998 Fairchild Semiconductor Corporation