RM5271™ Microprocessor with External Cache Interface Document Rev. 1.3 Date: 02/2000 FEATURES • High-performance floating point unit - up to 700 MFLOPS — Single cycle repeat rate for common single precision operations and some double precision operations — Two cycle repeat rate for double precision multiply and double precision combined multiply-add operations — Single cycle repeat rate for single precision combined multiply-add operation • MIPS IV instruction set — Floating point multiply-add instruction increases performance in signal processing and graphics applications — Conditional moves to reduce branch frequency — Index address modes (register + register) • Embedded application enhancements — Specialized DSP integer Multiply-Accumulate instructions and 3-operand multiply instruction — Instruction and Data cache locking by set — Optional dedicated exception vector for interrupts • Fully static CMOS design with power down logic — Standby reduced power mode with WAIT instruction — 2.5V core with 3.3V IO’s • 304-pin SBGA package (31x31mm) • Dual Issue superscalar microprocessor — 200, 250, 266, 300, 350 MHz operating frequencies — 420 Dhrystone 2.1 MIPS maximum • High-performance system interface — 64-bitmultiplexed system address/data bus for optimum price/performance with up to 125MHz operation frequency — High-performance write protocols to maximize uncached write bandwidth — Processor clock multipliers 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9 — IEEE 1149.1 JTAG boundary scan • Integrated on-chip caches — 32KB instruction and 32KB data - 2-way set associative — Virtually indexed, physically tagged — Write-back and write-through on a per-page basis — Pipeline restart on first doubleword for data cache misses • Integrated secondary cache controller (R5000 compatible) — Supports 512K or 2MByte block write-through secondary • Integrated memory management unit — Fully associative joint TLB (shared by I and D translations) — 48 dual-entries map 96 pages — Variable page size (4KB to 16MB in 4x increments) BLOCK DIAGRAM Extenal Cache Controller Primary Data Cache 2-way Set Associative DTag DTLB ITag ITLB Primary Instruction Cache 2-way Set Associative A/D Bus Pad Bus Store Buffer Pad Buffer Write Buffer Instruction Dispatch Unit Address Buffer FP Instruction Register Read Buffer Integer Instruction Register FP Bus Integer Bus D Bus Packer/Unpacker Floating-Point MultAdd, Add, Sub, Cvt, Div, Sqrt www.qedinc.com Integer Register File Integer Address/Adder System/Memory Control Shifter/Store Aligner IVA Logic Unit PC Incrementer FA Bus Branch PC Adder ITLB Virtual Program Counter Quantum Effect Devices Load Aligner DVA Coprocessor 0 Integer Control Floating-Point Register File Joint TLB Floating-Point Control Floating-Point Load/Align DTLB Virtual PLL/Clocks RM5271 Microprocessor, Document Rev. 1.3 Int Mult, Div, Madd 1 DESCRIPTION The QED RM5271 is a highly integrated superscalar microprocessor that is ideally suited for high-end embedded control applications such as internetworking, high-performance image manipulation, high-speed printing, and 3-D visualization.The RM5271 is also applicable to the low end workstation market where its balanced integer and floating-point performance and direct support for a large secondary cache (up to 2MB) provide outstanding price/performance HARDWARE OVERVIEW The RM5271 offers a high-level of integration targeted at high-performance embedded applications. The key elements of the RM5271 are briefly described below. Superscalar Dispatch The RM5271 has an asymmetric superscalar dispatch unit which allows it to issue an integer instruction and a floatingpoint computation instruction simultaneously. With respect to superscalar issue, integer instructions include alu, branch, load/store, and floating-point load/store, while floating-point computation instructions include floating-point add, subtract, combined multiply-add, converts, etc. In combination with its high-throughput fully pipelined floatingpoint execution unit, the superscalar capability of the RM5271 provides unparalleled price/performance in computationally intensive embedded applications. CPU Registers The RM5271 CPU contains 32 general purpose registers, two special purpose registers for integer multiplication and division, a program counter, and no condition code bits. Figure 1 shows the user visible state. Pipeline For integer operations, loads, stores, and other non-floating-point operations, the RM5271 uses a 5-stage pipeline. In addition to the 5-stage integer pipeline, the RM5271 uses an extended 7-stage pipeline for floating-point operations. Figure 2 shows the RM5271 integer pipeline. Up to five integer instructions can be executing simultaneously. General Purpose Registers 63 Multiply/Divide Registers 0 0 63 r1 HI r2 63 • LO 0 0 • Program Counter • • 63 r29 PC 0 r30 r31 Figure 1 CPU Registers 2 RM5271 Microprocessor, Document Rev. 1.3 Quantum Effect Devices www.qedinc.com I0 1I 2I I1 1R 2R 1A 2A 1D 2D 1W 2W 1I 2I 1R 2R 1A 2A 1D 2D 1W 2W 1I 2I 1R 2R 1A 2A 1D 2D 1W 2W 1I 2I 1R 2R 1A 2A 1D 2D 1W 2W 1I 2I 1R 2R 1A 2A 1D 2D I2 I3 I4 1W 2W one cycle 1I-1R: Instruction cache access 2I: Instruction virtual to physical address translation 2R: Register file read, Bypass calculation, Instruction decode, Branch address calculation 1A: Issue or slip decision, Branch decision 1A: Data virtual address calculation 1A-2A: Integer add, logical, shift 2A: Store Align 2A-2D: Data cache access and load align 1D: Data virtual to physical address translation 2W: Register file write Figure 2 Pipeline Integer Unit The RM5271 implements the MIPS IV Instruction Set Architecture, and is therefore fully upward compatible with applications that run on processors implementing the earlier generation MIPS I-III instruction sets. Additionally, the RM5271 includes two implementation-specific instructions not found in the baseline MIPS IV ISA but that are useful in the embedded market place. These instructions are integer multiply-accumulate (MAD) and 3-operand integer multiply (MUL). performs shifts and store alignment operations. Each of these units is optimized to perform all operations in a single processor cycle. Integer Multiply/Divide The RM5271 has a dedicated integer multiply/divide unit optimized for high-speed multiply and multiply-accumulate operations. Table 1 shows the performance of the multiply/ divide unit on each operation. Table 1: Integer Multiply/Divide Operations The RM5271 integer unit includes thirty-two general purpose 64-bit registers, a load/store architecture with single cycle ALU operations (add, sub, logical, shift) and an autonomous multiply/divide unit. Additional register resources include: the HI/LO result registers for the twooperand integer multiply/divide operations, and the program counter (PC ). MULT/U, MAD/U 16 bit 3 2 0 32 bit 4 3 0 MUL 16 bit 3 2 1 32 bit 4 3 2 Register File DMULT, DMULTU any 7 6 0 DIV, DIVD any 36 36 0 DDIV, DDIVU any 68 68 0 The RM5271 has thirty-two general purpose registers with register location 0 (r0) hard wired to a zero value. These registers are used for scalar integer operations and address calculation. The register file has two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. ALU The RM5271 ALU consists of an integer adder/subtractor, a logic unit, and a shifter. The adder performs address calculations in addition to arithmetic operations. The logic unit performs all logical and zero shift data moves. The shifter Quantum Effect Devices www.qedinc.com Opcode Operand Size Repeat Rate Latency Stall Cycles The baseline MIPS IV ISA specifies that the results of a multiply or divide operation be placed in the Hi and Lo registers. These values can then be transferred to the general purpose register file using the Move-from-Hi and Movefrom-Lo (MFHI/MFLO) instructions. In addition to the baseline MIPS IV integer multiply instructions, the RM5271 also implements the 3-operand multiply instruction, MUL. This instruction specifies that the multiply RM5271 Microprocessor, Document Rev. 1.3 3 result go directly to the integer register file rather than the Lo register. The portion of the multiply that would have normally gone into the Hi register is discarded. For applications where it is known that the high half of the multiply result is not required, using the MUL instruction eliminates the necessity of executing an explicit MFLO instruction. The multiply-add instructions (MAD) multiplies two operands and adds the resulting product to the current contents of the Hi and Lo registers. The multiply-accumulate operation is the core primitive of almost all signal processing algorithms, allowing the RM5271 to eliminate the need for a separate DSP engine in many embedded applications. Floating-Point Co-Processor The RM5271 incorporates a high-performance fully pipelined floating-point coprocessor which includes a floatingpoint register file and autonomous execution units for multiply/add/convert and divide/square root. The floating-point coprocessor is a tightly coupled execution unit, decoding and executing instructions in parallel with, and in the case of floating-point loads and stores, in cooperation with the integer unit. The superscalar capabilities of the RM5271 allow floating-point computation instructions to be issued concurrently with integer instructions. Floating-Point Unit The RM5271 floating-point execution unit supports single and double precision arithmetic, as specified in the IEEE Standard 754. The execution unit is broken into a separate divide/square root unit and a pipelined multiply/add unit. Overlap of the divide/square root and multiply/add instruction is supported. The RM5271 maintains fully precise floating-point exceptions while allowing both overlapped and pipelined operations. Precise exceptions are extremely important in objectoriented programming environments and highly desirable for debugging in any environment. Floating-point operations include; • • • • • • • • • • • 4 add subtract multiply divide square root reciprocal reciprocal square root conditional moves conversion between fixed-point and floatingpoint format conversion between floating-point formats floating-point compare Table 2 gives the latencies of the floating-point instructions in internal processor cycles. Table 2: Floating-Point Instruction Cycles Operation fadd Latency Repeat Rate 4 1 fsub 4 1 fmult 4/5 1/2 fmadd 4/5 1/2 fmsub 4/5 1/2 fdiv 21/36 19/34 fsqrt 21/36 19/34 frecip 21/36 19/34 frsqrt 38/68 36/66 fcvt.s.d 4 1 fcvt.s.w 6 3 fcvt.s.l 6 3 fcvt.d.s 4 1 fcvt.d.w 4 1 fcvt.d.l 4 1 fcvt.w.s 4 1 fcvt.w.d 4 1 fcvt.l.s 4 1 fcvt.l.d 4 1 fcmp 1 1 fmov 1 1 fmovc 1 1 fabs 1 1 fneg 1 1 Floating-Point General Register File The floating-point general register file (FGR) is made up of thirty-two 64-bit registers. With the floating-point load double (LDC1) and store double (SDC1) instructions, the floating-point unit can take advantage of the 64-bit wide data cache and issue a floating-point co-processor load or store doubleword instruction in every cycle. The floating-point control register space contains two registers; one for determining configuration and revision information for the coprocessor and one for control and status information. These are primarily used for diagnostic software, exception handling, state saving and restoring, and control of rounding modes. To support superscalar operation, the FGR has four read ports and two write ports, and is fully bypassed to minimize operation latency in the pipeline. Three of the read ports and one write port are used to support the combined multiply-add instruction while the fourth read and second write port allows a concurrent floating-point load or store. RM5271 Microprocessor, Document Rev. 1.3 Quantum Effect Devices www.qedinc.com System Control Co-processor (CP0) Virtual to Physical Address Mapping The system control co-processor, also called co-processor 0 or CP0 in the MIPS architecture, is responsible for the virtual memory sub-system, the exception control system, and the diagnostics capability of the processor. The RM5271 CP0 is logically identical to the RM5200. The RM5271 provides three modes of virtual addressing: The memory management unit controls the virtual memory system page mapping. It consists of an instruction address translation buffer, ITLB, a data address translation buffer, DTLB, a Joint instruction and data address translation buffer, JTLB, and coprocessor registers used by the virtual memory mapping sub-system. System Control Co-Processor Register The RM5271 incorporates all system control coprocessor (CP0) registers on-chip. These registers provide the path through which the virtual memory system’s page mapping is examined and modified, exceptions are handled, and operating modes are controlled (kernel vs. user mode, interrupts enabled or disabled, cache features). In addition, the RM5271 includes registers to implement a real-time cycle counting facility to aid in cache diagnostic testing and to assist in data error detection. • • • user mode kernel mode supervisor mode This mechanism is available to system software to provide a secure environment for user processes. Bits in the CP0 Status register determine which virtual addressing mode is used. In the user mode, the RM5271 provides a single, uniform virtual address space of 256GB (2GB in 32-bit mode). When operating in the kernel mode, four distinct virtual address spaces, totalling 1024GB (4GB in 32-bit mode), are simultaneously available and are differentiated by the high-order bits of the virtual address. The RM5271 processors also support a supervisor mode in which the virtual address space is 256.5GB (2.5GB in 32bit mode), divided into three regions based on the highorder bits of the virtual address. Figure 4 shows the address space layout for 32-bit operations. Figure 3 shows the CP0 registers. PageMask 5* EntryLo0 2* EntryHi 10* EntryLo1 3* 47 Index 0* Context 4* BadVAddr 8* Count 9* Compare 11* Status 12* Cause 13* EPC 14* TLB Random 1* Wired 6* (entries protected from TLBWR) 0 LLAddr 17* TagLo 28* TagHi 29* XContext 20* ECC 26* PRId 15* CacheErr 27* ErrorEPC 30* Config 16* Used for memory management Used for exception processing * Register number Figure 3 CP0 Registers Quantum Effect Devices www.qedinc.com RM5271 Microprocessor, Document Rev. 1.3 5 0xFFFFFFFF Kernel virtual address space (kseg3) Mapped, 0.5GB 0xE0000000 0xDFFFFFFF Supervisor virtual address space (ksseg) Mapped, 0.5GB 0xC0000000 0xBFFFFFFF Uncached kernel physical address space (kseg1) Unmapped, 0.5GB 0xA0000000 0x9FFFFFFF Cached kernel physical address space (kseg0) Unmapped, 0.5GB 0x80000000 0x7FFFFFFF User virtual address space (kuseg) Mapped, 2.0GB 0x00000000 Figure 4 Kernel Mode Virtual Addressing (32-bit) When the RM5271 is configured as a 64-bit microprocessor, the virtual address space layout is an upward compatible extension of the 32-bit virtual address space layout. Joint TLB For fast virtual-to-physical address translation, the RM5271 uses a large, fully associative TLB that maps 96 virtual pages to their corresponding physical addresses. As indicated by its name, the joint TLB, or JTLB, is used for both instruction and data translations. The JTLB is organized as 48 pairs of even-odd entries, and maps a virtual address and address space identifier into the large, 64GB physical address space. Two mechanisms are provided to assist in controlling the amount of mapped space and the replacement characteristics of various memory regions. First, the page size can be configured, on a per-entry basis, to use page sizes in the range of 4KB to 16MB (in multiples of 4). The CP0 PageMask register is loaded with the desired page size of a mapping, and that size is stored into the TLB along with the virtual address when a new entry is written. Thus, operating systems can create special purpose maps. For example, a entire frame buffer can be memory mapped using only one TLB entry. The second mechanism controls the replacement algorithm when a TLB miss occurs. The RM5271 provides a random replacement algorithm to select the TLB entry to be written 6 with a new mapping. However, the processor also provides a mechanism whereby a system specific number of mappings can be locked into the TLB, thereby avoiding random replacement. This mechanism allows the operating system to guarantee that certain pages are always mapped for performance reasons and for deadlock avoidance. This mechanism also facilitates the design of real-time systems by allowing deterministic access to critical software. The JTLB also contains information that controls the cache coherency protocol for each page. Specifically, each page has attribute bits to determine whether the coherency algorithm is one of the following: • • • • • • • uncached non-coherent write-back] non-coherent write-through with write-allocate non-coherent write-through without write-allocate sharable exclusive update Note that both of the write-through protocols bypass the secondary cache since the secondary does not support writes of less than a complete cache line. The non-coherent protocols are used for both code and data on the RM5271 with data using write-back or write-through depending on the application. The coherency attributes generate coherent transaction types on the system interface. However, cache coherency is not supported in the RM5271 and therefore the coherency attributes should never be used. Instruction TLB The RM5271 implements a 2-entry instruction TLB (ITLB) to minimize contention for the JTLB, eliminate the timing critical path of translating through a large associative array, and save power. Each ITLB entry maps a 4KB page. The ITLB improves performance by allowing instruction address translation to occur in parallel with data address translation. When a miss occurs on an instruction address translation by the ITLB, the least-recently used ITLB entry is filled from the JTLB. The operation of the ITLB is completely transparent to the user. Data TLB The RM5271 implements a 4-entry data TLB (DTLB). Each DTLB entry maps a 4KB page. The DTLB improves performance by allowing data address translation to occur in parallel with instruction address translation. When a miss occurs on a data address translation by the DTLB, the DTLB is filled from the JTLB. The DTLB refill is pseudoLRU: the least recently used entry of the least recently RM5271 Microprocessor, Document Rev. 1.3 Quantum Effect Devices www.qedinc.com used pair of entries is filled. The operation of the DTLB is completely transparent to the user. Cache Memory In order to keep the pipeline full and operating efficiently, the RM5271 incorporates on-chip instruction and data caches that can be accessed in a single processor cycle. Each cache has its own 64-bit data path and both caches can be accessed simultaneously. The cache subsystem provides the integer and floating-point units with an aggregate bandwidth over 4.2GB per second at an internal clock frequency of 266 MHz. For applications requiring even higher performance, the RM5271 also has a direct interface to a large external secondary cache. The data cache is protected with byte parity and its tag is protected with a single parity bit. The cache is virtually indexed and physically tagged to allow address translation to occur in simultaneously with the data cache access. The most commonly used write policy is write-back, which means that a store to a cache line does not immediately cause memory to be updated. This increases system performance by reducing bus traffic and eliminating the bottleneck of waiting for each store operation to finish before issuing a subsequent memory operation. Software can, however, select write-through on a per-page basis when appropriate, such as for frame buffers. Cache protocols supported for the data cache are: 1. Instruction Cache The RM5271 incorporates a two-way set associative onchip instruction cache. This virtually indexed, physically tagged cache is 32KB in size and is protected with word parity. Since the cache is virtually indexed, the virtual-to-physical address translation occurs in parallel with the cache access, further increasing performance by allowing these two operations to occur simultaneously. The cache tag contains a 24-bit physical address, a valid bit, and has a single parity bit. 2. 3. The instruction cache is 64-bits wide and can be accessed each processor cycle. Accessing 64 bits per cycle allows the instruction cache to supply two instructions per cycle to the superscalar dispatch unit. For typical code sequences where a floating-point load or store and a floating-point computation instruction are being issued together in a loop, the entire bandwidth available from the instruction cache is consumed. A cache miss refill writes 64 bits per cycle to minimize the cache miss penalty. The line size is eight instructions (32 bytes) to maximize the performance of communication between the processor and the memory system. The RM5271 supports cache locking. The contents of set A can be locked by setting a bit in the coprocessor 0 Status register. Locking set A prevents its contents from being overwritten by a subsequent cache miss. Refills occur only into set B. This mechanism allows the programmer to lock critical code into the cache, thereby guaranteeing deterministic behavior for the locked code sequence. Data Cache For fast, single cycle data access, the RM5271 includes a 32KB on-chip data cache that is two-way set associative with a fixed 32-byte (eight words) line size. Quantum Effect Devices www.qedinc.com 4. Uncached. Reads to addresses in a memory area identified as uncached do not access the cache. Writes to such addresses are written directly to main memory without updating the cache. Write-back. Loads and instruction fetches first search the cache, reading the next memory hierarchy level only if the desired data is not cache resident. On data store operations, the cache is first searched to determine if the target address is cache resident. If it is resident, the cache contents are updated and the cache line is marked for later write-back. If the cache lookup misses, the target line is first brought into the cache and the write is performed as above. Write-through with write allocate. Loads and instruction fetches first search the cache, reading from memory only if the desired data is not cache resident. Note that write-through data is never cached in the secondary cache. On data store operations, the cache is first searched to determine if the target address is cache resident. If it is resident, the cache contents are updated and main memory is written, leaving the writeback bit of the cache line unchanged. No secondary cache write occurs. If the cache lookup misses, the target line is first brought into the cache and the write is performed as above. Write-through without write allocate. Loads and instruction fetches first search the cache, reading from memory only if the desired data is not cache resident; write-through data is never cached in the secondary cache. On data store operations, the cache is first searched to determine if the target address is cache resident. If it is resident, the cache contents are updated and main memory is written, leaving the writeback bit of the cache line unchanged. No secondary cache write occurs. If the cache lookup misses, only main memory is written. Associated with the data cache is the store buffer. When the RM5271 executes a STORE instruction, this singleentry buffer is written with the store data while the tag comparison is performed. If the tag matches, data is written into the data cache in the next cycle that the data cache is not being accessed (the next non-load cycle). The store buffer RM5271 Microprocessor, Document Rev. 1.3 7 allows the RM5271 to execute a store every processor cycle and to perform back-to-back stores without penalty. In the event of a store immediately followed by a load to the same address, a combined merge and cache write occurs such that no penalty is incurred. Secondary Cache The RM5271 provides direct support for an external secondary cache. The secondary cache is direct mapped and block write-through with byte parity. The RM5271 secondary operates identically to that of the RM5270 and supports the same 512K and 2 MByte cache sizes (assuming nKx18 RAM organization due to capacitive loading constraints). The secondary interface uses the SysAD bus for transferring data and tags information. A separate bus, ScLine, is used for transferring address and certain secondary cache specific control signals (for the complete set of signals, see “Pin Descriptions” on page 13). A secondary read looks nearly identical to a standard processor read except that the tag chip enable signal, ScTCE*, is asserted concurrently with ValidOut* and Release*, initiating a tag probe and indicating to the external controller that a secondary cache access is being performed. As a result, the external controller monitors the secondary hit signal, ScMatch. If a hit is indicated the controller aborts the memory read and refrains from acquiring control of the system interface. Along with ScTCE*, the processor also asserts the tag data enable signal, ScTDE*, which causes the tag RAM’s to latch the SysAD address Master Processor Secondary(Hit) internally for use as the replacement tag if a cache miss occurs. On a secondary miss, a refill is accomplished with a two signal handshake between the data output enable signal, ScDOE*, which is deasserted by the controller and the tag and data write enable signal, ScCWE*, which is asserted by the processor. Figure 5 illustrates a hit followed by a miss in the secondary cache. Other capabilities of the secondary interface include block write, tag invalidate, and tag probe. For details of these transactions as well as detailed timing waveforms for all the secondary transactions, see the RM5200 Family User Manual. The secondary cache can be implemented with the Motorola MCM69T618 or its equivalent. The RM5271 cache attributes for the instruction, data, and optional external secondary caches are summarized in Table 3. Write buffer Writes to external memory, whether cache miss writebacks or stores to uncached or write-through addresses, use the on-chip write buffer. The write buffer holds up to four 64-bit address and data pairs. The entire buffer is used for a data cache write-back and allows the processor to proceed in parallel with the memory update. For uncached and write-through stores, the write buffer significantly increases performance by decoupling the SysAD bus transfers from the instruction execution stream. Processor Secondary(Miss) System SysClock SysAD Addr ScLine[19:2] Index ScWord[1:0] I0 Data0 Data1 Data2 Data3 Addr Data0 Data1 Data0 Data1 I2 I3 I0 I1 Index I1 I2 I3 I0 I1 ScTCE* ScMatch ScDCE* ScCWE* ScDOE* Figure 5 Secondary Cache Hit and Miss 8 RM5271 Microprocessor, Document Rev. 1.3 Quantum Effect Devices www.qedinc.com Table 3: there are 6 handshake signals and 6 interrupt inputs. The interface is capable of transferring data between the processor and memory at a peak rate of 1000MB/sec with a 125MHz SysClock. Cache Attributes Characteristics Instruction Data Secondary Size 32KB 32KB 512K, 1M or 2M Organization 2-way set associative 2-way set associative direct mapped Replacement Algorithm Pseudo-LRU Pseudo-LRU direct replacement Line size 32B 32B 32B Index vAddr11..0 vAddr11..0 pAddr20..0 Tag pAddr31..12 pAddr31..12 pAddr53..19 Write policy n.a. write-back/ block writewrite-through through Read order sub-block sub-block Figure 6 shows a typical embedded system using the RM5271. In this example, a bank of DRAMs, an optional secondary cache, and a memory controller ASIC share the processor’s SysAD bus while the memory controller provides separate ports to a boot ROM and an I/O system. System Address/Data Bus The 64-bit System Address Data (SysAD[63:0]) bus is used to transfer addresses and data between the RM5271 and the rest of the system. It is protected with an 8-bit parity check bus, SysADC[7:0]. sub-block Write order sequential sequential sequential miss restart after fetch of entire line first double NA Parity per-word per-byte per-byte Cache locking set A set A none The system interface is configurable to allow easy interfacing to memory and I/O systems of varying frequencies. The data rate and the bus frequency at which the RM5271 transmits data to the system interface are programmable via boot time mode control bits. The rate at which the processor receives data is also fully controlled by the external device. System Interface System Command Bus The RM5271 provides a high-performance 64-bit multiplexed address/data system interface for optimum price/ performance. This interface is backward compatible with the RM5270. However, unlike the RM5270 which provides only an integral multiplication factor between SysClock and the pipeline clock, the RM5271 allows half integral multipliers, thereby providing greater granularity in the designers choice of pipeline and system interface frequencies. The RM5271 interface contains a 9-bit System Command (SysCmd[8:0]) bus. The command bus indicates whether the SysAD bus carries address or data information on a per-clock basis. If the SysAD carries an address, then the SysCmd bus also indicates what type of transaction is to take place (for example, a read or write). The system interface consists of a 64-bit Address/Data bus with 8 parity bits and a 9-bit command bus. In addition, Flash/ Boot Rom DRAM Address Control x x 72 8 Latch SysAD Bus RM5271 72 72 SysCmd Memory I/O Controller PCI Bus 23 72 ScLine, etc. Secondary Cache (optional) MCM69T618 Figure 6 Typical Embedded System Block Diagram Quantum Effect Devices www.qedinc.com RM5271 Microprocessor, Document Rev. 1.3 9 If the SysAD carries data, then the SysCmd bus provides information about the data (for example, this is the last data word transmitted, or the data contains an error). The SysCmd bus is bidirectional to support both processor requests and external requests to the RM5271. Processor requests are initiated by the RM5271 and responded to by an external device. External requests are issued by an external device and require the RM5271 to respond. The RM5271 supports one- to eight-byte transfers as well as block transfers on the SysAD bus. In the case of a subdoubleword transfer, the three low-order address bits give the byte address of the transfer, and the SysCmd bus indicates the number of bytes being transferred. Handshake Signals There are six handshake signals on the system interface. Two of these, RdRdy* and WrRdy*, are used by an external device to indicate to the RM5271 whether it can accept a new read or write transaction. The RM5271 samples these signals before deasserting the address on read and write requests. ExtRqst* and Release* are used to transfer control of the SysAD and SysCmd buses from the processor to an external device. When an external device needs to control the interface, it asserts ExtRqst*. The RM5271 responds by asserting Release* to release the system interface to slave state. ValidOut* and ValidIn* are used by the RM5271 and the external device respectively to indicate that there is a valid command or data on the SysAD and SysCmd buses. The RM5271 asserts ValidOut* when it is driving these buses with a valid command or data, and the external device drives ValidIn* when it has control of the buses and is driving a valid command or data. Non-overlapping System Interface The RM5271 implements a non-overlapping system interface, where only one processor request may be outstanding at a time, and that the request must be serviced by an external device before the RM5271 issues another request. The RM5271 can issue read and write requests to an external device, whereas an external device can issue null and write requests to the RM5271. For processor reads the RM5271 asserts ValidOut* and simultaneously drives the address and read command on the SysAD and SysCmd buses respectively. If the system interface has RdRdy* asserted, then the processor tristates its drivers and releases the system interface to the slave state by asserting Release*. The external device can then begin sending data to the RM5271. Figure 7 shows a processor block read request and the external agent read response for a system with no external secondary cache. The read latency is 4 cycles (ValidOut* to ValidIn*), and the response data pattern is DDxxDD. Figure 8 shows a processor block write using write response pattern DDxxDDxx (code 2 of the boot time mode select options). This pattern indicates two data transfers back-toback, followed by two wait states. In the write case, there may be secondary cache present. SysClock SysAD Addr Data0 Data1 Data2 Data3 SysCmd Read NData NData NData NEOD ValidOut* ValidIn* RdRdy* WrRdy* Release* Figure 7 Processor Block Read 10 RM5271 Microprocessor, Document Rev. 1.3 Quantum Effect Devices www.qedinc.com SysClock SysAD Addr Data0 Data1 Data2 Data3 SysCmd Write NData NData NData NEOD ValidOut* ValidIn* RdRdy* WrRdy* Release* Figure 8 Processor Block Write Enhanced Write Modes The RM5271 implements two enhancements to the original R4000 write mechanism: Write Reissue and Pipeline Writes. The original R4000 allowed a write on the SysAD bus every four SysClock cycles. Hence for a non-block write, this meant that two out of every four cycles were wait states. Pipelined write mode eliminates these two wait states by allowing the processor to drive a new write address onto the bus immediately after the previous data cycle. This allows for higher SysAD bus utilization. However, at high frequencies the processor may drive a subsequent write onto the bus prior to the time the external agent deasserts WrRdy*, indicating that it can not accept another write cycle. This can cause the cycle to be aborted. Write reissue mode is an enhancement to pipelined write mode and allows the processor to reissue aborted write cycles. If WrRdy* is deasserted during the issue phase of a write operation, the cycle is aborted by the processor and reissued at a later time. register. A null request is executed when the external device wishes the processor to reassert ownership of the processor external interface (the external device wants the processor interface to go from slave state to master state). Typically, a null request is executed after an external device, that has acquired control of the processor interface via the assertion of ExtRqst*, has completed a transaction between itself and system memory in a system where memory is connected directly to the SysAD bus. Normally, this transaction would be a DMA read or write from the I/O system. Interrupt Handling In order to provide better real time interrupt handling, the RM5271 supports dedicated interrupt vectoring. When enabled by the real time executive (by setting a bit in the Cause register), interrupts vector to a specific address which is not shared with any of the other exception types. This capability eliminates the need to go through the normal software routine for exception decode and dispatch, thereby lowering interrupt latency. Standby Mode In write reissue mode, a write rate of one write every two bus cycles can be achieved. Pipelined writes have the same two bus cycle write repeat rate, but can issue one additional write following the deassertion of WrRdy*. External Requests The RM5271 can respond to certain requests issued by an external device. These requests take one of two forms: Write requests and Null requests. An external device executes a write request when it wishes to update one of the processors writable resources such as the internal interrupt Quantum Effect Devices www.qedinc.com The RM5271 provides a means to reduce the amount of power consumed by the internal core when the CPU would otherwise not be performing any useful operations. This state is known as Standby Mode. Executing the WAIT instruction enables interrupts and causes the processor to enter Standby Mode. When the wait instruction completes the W pipe stage, and if the SysAD bus is currently idle, the internal processor clocks stop, thereby suspending the pipeline. The phase lock loop, or PLL, internal timer/counter, and the “wake up” input pins: RM5271 Microprocessor, Document Rev. 1.3 11 Int[5:0]*, NMI*, ExtReq*, Reset*, and ColdReset* continue to operate in their normal fashion. If the SysAD bus is not idle when the WAIT instruction completes the W pipestage, then the WAIT is treated as a NOP until the bus operation is completed. Once the processor is in Standby, any interrupt, including the internally generated timer interrupt, causes the processor to exit Standby mode and resume operation where it left off. The WAIT instruction is typically inserted in the idle loop of the operating system or real time executive. Table 4: Mode bit 7:5 JTAG Interface 8 The RM5271 interface supports JTAG boundary scan in conformance with the IEEE 1149.1 specification. The JTAG interface is especially helpful for checking the integrity of the processor’s pin connections. 10:9 Boot-Time Options Fundamental operational modes for the processor are initialized by the boot-time mode control interface. This serial interface operating at a very low frequency (SysClock divided by 256). The low frequency operation allows the initialization information to be kept in a low cost EPROM. Alternatively, the mode stream bits could also be generated by the system interface ASIC. 12 reserved (must be zero) 4:1 Write-back data rate 0: DDDD 1: DDxDDx 2: DDxxDDxx 3: DxDxDxDx 4: DDxxxDDxxx 5: DDxxxxDDxxxx 6: DxxDxxDxxDxx 7: DDxxxxxxDDxxxxxx 8: DxxxDxxxDxxxDxxx 9-15 reserved Output driver strength - 100% = fastest 00: 67% strength 01: 50% strength 10: 100% strength 11: 83% strength Select external secondary cache Pipeline Burst SRAM type 0: Dual-cycle deselect 1: Single-cycle deselect 17:16 System configuration identifiers - software visible in processor Config[21..20] register 19:18 Reserved: Must be zero 20 Select Sysclock to Pclock Multiply Mode 0: Integer Multipliers 1: Half-Integer Multipliers 21 External Bus Width 0: 64-bit 1: 32-bit Boot-Time Mode Bit Stream 0 Non-Block Write Control 00: R4000 compatible non-block writes 01: reserved 10: pipelined non-block writes 11: non-block write re-issue Enable/Disable External Secondary Cache 0: Disable secondary cache 1: Enable secondary cache 15 Description Specifies byte ordering. Logically ORed with BigEndian input signal. 0: Little endian 1: Big endian 12 Boot-Time Modes Mode bit SysClock to Pclock Multiplier Mode Bit 20=0 / Mode Bit 20=1 0: Multiply by 2/x 1: Multiply by 3/x 2: Multiply by 4/x 3: Multiply by 5/2.5 4: Multiply by 6/x 5: Multiply by 7/3.5 6: Multiply by 8/x 7: Multiply by 9/4.5 Timer Interrupt Enable/Disable 0: Enable the timer interrupt on Int[5] 1: Disable the timer interrupt on Int[5] 14:13 Table 4: Description 11 Immediately after the VccOK signal is asserted, the processor reads a serial bit stream of 256 bits to initialize all the fundamental operational modes. ModeClock run continuously from the assertion of VccOK. The boot-time serial mode stream is defined in Table 4. Bit 0 is the first bit presented to the processor when VccOK is de-asserted; bit 255 is the last in the mode bit stream. Boot-Time Mode Bit Stream 255:22 Reserved: Must be zero RM5271 Microprocessor, Document Rev. 1.3 Quantum Effect Devices www.qedinc.com PIN DESCRIPTIONS The following is a list of interface, interrupt, and miscellaneous pins available on the RM5271. Pin Name Type Description System interface: ExtRqst* Input External request Signals that the system interface is submitting an external request. Release* Output Release interface Signals that the processor is releasing the system interface to slave state RdRdy* Input Read Ready Signals that an external agent can now accept a processor read. WrRdy* Input Write Ready Signals that an external agent can now accept a processor write request. ValidIn* Input Valid Input Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus. ValidOut* Output Valid output Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus. SysAD(63:0) Input/Output System address/data bus A 64-bit address and data bus for communication between the processor and an external agent. SysADC(7:0) Input/Output System address/data check bus An 8-bit bus containing parity check bits for the SysAD bus during data cycles. SysCmd(8:0) Input/Output System command/data identifier bus A 9-bit bus for command and data identifier transmission between the processor and an external agent. SysCmdP Input/Output Reserved for system command/data identifier bus parity For the RM5270, unused on input and zero on output. Clock/control interface: SysClock Input System clock Master clock input used as the system interface reference clock. All output timings are relative to this input clock. Pipeline operation frequency is derived by multiplying this clock up by the factor selected during boot initialization VccP Input Quiet Vcc for PLL Quiet Vcc for the internal phase locked loop. Must be connected to VccInt through a filter circuit. VssP Input Quiet VSS for PLL Quiet Vss for the internal phase locked loop. Must be connected to VssInt through a filter circuit. Secondary cache interface: ScCLR* Output Secondary Cache Block Clear Requests that all valid bits be cleared in the Tag RAMs. Many RAM’s may not support a block clear therefore the block clear capability is not required for the cache to operate. ScCWE*(1:0) Output Secondary Cache Write Enable Asserted to cause a write to the cache. Two identical signals are provided to balance the capacitive load relative to the remaining cache interface signals. ScDCE*(1:0) Output Secondary Cache Data RAM Chip Enable When asserted this signal causes the data RAM’s to read out their contents. Two identical signals are provided to balance the capacitive load relative to the remaining cache interface signals ScDOE* Input Secondary Cache Data RAM Output enable When asserted this signal causes the data RAM’s to drive data onto their I/O pins. This signal is monitored by the processor to determine when to drive the data RAM write enable in a secondary cache miss refill sequence. ScLine(15:0) Output Secondary Cache Line Index Quantum Effect Devices www.qedinc.com RM5271 Microprocessor, Document Rev. 1.3 13 Pin Name Type Description ScMatch Input Secondary Cache Tag Match This signal is asserted by the cache Tag RAM’s when a match occurs between the value on its data inputs and the contents of its RAM at the value on its address inputs. ScTCE* Output Secondary Cache Tag RAM Chip Enable When asserted this signal will cause either a probe or a write of the Tag RAM’s depending on the state of the Tag RAM’s write enable signal. This signal is monitored by the external agent and indicates to it that a secondary cache access is occurring. ScTDE* Output Secondary Cache Tag RAM Data Enable When asserted this signal causes the value on the data inputs of the Tag RAM to be latched into the RAM. If a refill of the RAM is necessary, this latched value will be written into the Tag RAM array. Latching the Tag allows a shared address/data bus to be used without incurring a penalty to re-present the Tag during the refill sequence. ScTOE* Output When asserted this signal causes the Tag RAM’s to drive data onto their I/O pins. ScWord(1:0) Input/Output Secondary Cache Double Word Index Driven by the processor on cache hits and by the external agent on cache miss refills. ScValid Input/Output Secondary Cache Valid This signal is driven by the processor as appropriate to make a cache line valid or invalid. On Tag read operations the Tag RAM will drive this signal to indicate the line state. Interrupt interface: Int*(5:0) Input Interrupt Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register. NMI* Input Non-maskable interrupt Non-maskable interrupt, ORed with bit 6 of the interrupt register. JTDI Input JTAG data in JTAG serial data in. JTCK Input JTAG clock input JTAG serial clock input. JTDO Output JTAG data out JTAG serial data out. JTMS Input JTAG command JTAG command signal, signals that the incoming serial data is command data. JTAG interface: Initialization interface: BigEndian Input Allows the system to change the processor addressing mode without rewriting the mode ROM. VccOK Input Vcc is OK When asserted, this signal indicates to the RM5270 that the 3.3V power supply has been above 3.0V for more than 100 milliseconds and will remain stable. The assertion of VccOk initiates the reading of the boot-time mode control serial stream. ColdReset* Input Cold reset This signal must be asserted for a power on reset or a cold reset. ColdReset must be de-asserted synchronously with SysClock. Reset* Input Reset This signal must be asserted for any reset sequence. It may be asserted synchronously or asynchronously for a cold reset, or synchronously to initiate a warm reset. Reset must be de-asserted synchronously with SysClock. ModeClock Output Boot mode clock Serial boot-mode data clock output at the system clock frequency divided by two hundred and fifty six. ModeIn Input Boot mode data in Serial boot-mode data input. Input/Output Reserved for RM7000 compatibility Reserved Pins Reserved 14 RM5271 Microprocessor, Document Rev. 1.3 Quantum Effect Devices www.qedinc.com ABSOLUTE MAXIMUM RATINGS1 Symbol Rating V 0 to +85 °C –55 to +125 °C DC Input Current 203 mA DC Output Current 504 mA Terminal Voltage with respect to Vss TCASE Operating Temperature TSTG Storage Temperature IOUT Note 1: Unit –0.52 to +3.9 VTERM IIN Limits Note 2: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. VIN minimum = -2.0V for pulse width less than 15ns. VIN should not exceed 3.9 Volts. Note 3: When VIN < 0V or VIN > VccIO Note 4: Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds. RECOMMENDED OPERATING CONDITIONS Grade Commercial Temperature Vss VccInt VccIO VccP 0°C to +85°C (Case) 0V 2.5V ± 5% 3.3V ± 5% 2.5V ± 5% Note: VCC I/O should not exceed VccInt by greater than 1.2V during the power-up sequence. Note: Applying a logic high state to any I/O pin before VccInt becomes stable is not recommended. Note: As specified in IEEE 1149.1 (JTAG), the JTMS pin must be held low during reset to avoid entering JTAG test mode. Refer to the RM7000 Family Users Manual, Appendix E. DC ELECTRICAL CHARACTERISTICS (VccIO = 3.3V ± 5%; TCASE = 0°C to +85°C) I/O Bus Speed 50/67/75/83/87/100/125 MHz Parameter Minimum VOL VOH 0.1V VccIO - 0.1V VOL Quantum Effect Devices www.qedinc.com Maximum 0.4V VOH 2.4V VIL -0.5V 0.2 x VccIO VIH 0.7 x VccIO VccIO + 0.5V IIN ±20 µA ±20 µA C IN 10pF COUT 10pF Conditions |IOUT|= 20 µA |IOUT| = 4 mA VIN = 0 VIN = VccIO RM5271 Microprocessor, Document Rev. 1.3 15 POWER CONSUMPTION CPU Clock Speed Conditions: Max: VccInt = 2.625 Typ: VccInt = 2.5V Parameter VccInt Power (mWatts) 200 MHz Typ1 250 MHz Max2 standby Typ1 350 active Max2 435 R4000 write protocol with no FPU operation 1600 3200 1850 3700 Write re-issue or pipelined writes with superscalar 1750 3500 2025 4050 CPU Clock Speed Conditions: Max: VccInt = 2.625 Typ: VccInt = 2.5V Parameter VccInt Power (mWatts) 266 MHz 350 MHz Typ1 Max2 Typ1 Max2 Typ1 Max2 standby active 300 MHz 450 550 650 R4000 write protocol with no FPU operation 1900 3800 2100 4200 2650 5300 Write re-issue or pipelined writes with superscalar 2075 4150 2300 4600 2850 5700 Note 1: Typical integer instruction mix and cache miss rates with worst case supply voltage. Note 2: Worst case instruction mix with worst case supply voltage. Note: I/O supply power is application dependant, but typically <10% of VccInt. AC ELECTRICAL CHARACTERISTICS Capacitive Load Deration Parameter Symbol Load Derate Min Max CLD IO Power Derate IO Power Derate @ 20pF load 16 4.0 RM5271 Microprocessor, Document Rev. 1.3 Units 2 ns/25pF 21 mW/25pF/MHz 5.5 mW/MHz Quantum Effect Devices www.qedinc.com Clock Parameters CPU Speed Parameter 200 MHz Test Conditions Symbol Min 250 MHz Max Min Max Units SysClock High tSCHigh Transition ≤ 5ns 3 3 ns SysClock Low tSCLow Transition ≤ 5ns 3 3 ns SysClock Frequency1 25 100 25 125 MHz tSCP 40 40 ns Clock Jitter for SysClock tJitterIn ±200 ±150 ps SysClock Rise Time tSCRise 2 2 ns SysClock Fall Time tSCFall 2 2 ns ModeClock Period tModeCKP 256 256 tSCP JTAG Clock Period tJTAGCKP 4 4 tSCP SysClock Period CPU Speed Parameter Test Conditions Symbol 266 MHz Min Max 300 MHz Min Max 350 MHz Min Max Units SysClock High tSCHigh Transition ≤ 5ns 3 3 3 ns SysClock Low tSCLow Transition ≤ 5ns 3 3 3 ns SysClock Frequency1 SysClock Period 30 106 33.3 120 33.3 116.6 MHz 30 tSCP 33 30 Slock Jitter for SysClock tJitterIn ±150 ±150 SysClock Rise Time tSCRise 2 2 2 ns SysClock Fall Time tSCFall 2 2 2 ns ModeClock Period tModeCKP 256 256 256 tSCP JTAG Clock Period tJTAGCKP 4 4 4 tSCP Note 1: ns ±150 ps 0peration of the RM5271 is only guaranteed with the Phase Lock Loop Enabled. Quantum Effect Devices www.qedinc.com RM5271 Microprocessor, Document Rev. 1.3 17 System Interface Parameters1 I/O Bus Speed 200 MHz Parameter Symbol Test Conditions Min Max Min Max 5 1.0 4.5 1.0 4.0 ns 5 1.0 5.0 1.0 4.0 ns mode14..13 = 005 1.0 5.5 1.0 4.0 ns mode14..13 = 015 (slowest) 1.0 6.0 1.0 4.5 ns tDS trise = see above table 2.5 2.5 ns tDH tfall = see above table 1.0 1.0 ns mode14..13 = 10 (fastest) Data Output2,3 Data Setup 4 Data Hold4 Note Note Note Note Note 1: 2: 3: 4: 5: 250–350 MHz tDO mode14..13 = 11 Units Timings are measured from 1.5V of the clock to 1.5V of the signal. Capacitive load for all output timings is 50pF. Data Output timing applies to all signal pins whether tristate I/O or output only. Setup and Hold parameters apply to all signal pins whether tristate I/O or input only. Only mode 14..13 = 10 (fastest) is tested and guaranteed. Boot-Time Interface Parameters I/O Bus Speed 50/67/75/83/87/100/125 MHz Parameter Symbol Test Conditions Min Max Units Mode Data Setup tDS(M) 4 SysClock cycles Mode Data Hold tDH(M) 0 SysClock cycles 18 RM5271 Microprocessor, Document Rev. 1.3 Quantum Effect Devices www.qedinc.com TIMING DIAGRAMS SysClock tRise tFall tHigh tLow ±tJitterIn Figure 9 Clock Timing System Interface Timing (SysAD, SysCmd, ValidIn*, ValidOut*, etc.) SysClock tDS Data tDH Data Figure 10 Input Timing SysClock tDOmax Data tDOmin Data Data Figure 11 Output Timing Quantum Effect Devices www.qedinc.com RM5271 Microprocessor, Document Rev. 1.3 19 PACKAGING INFORMATION 304 SBGA Drawing D 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 OO A1 ball corner A B C D E F G H J K L M N P R T U V W Y AA AB AC E A A2 TOP VIEW BOTTOM VIEW: bbb,ccc aaa SIDE VIEW A1 Body Size 31.0 x 31.0 mm Package Min. Nominal (mm) Max. NOTE A 1.41 1.54 1.67 Overall Thickness A1 0.56 0.63 0.70 Ball Height A2 0.85 0.91 0.97 Body Thickness D, E 30.90 31.00 31.10 Body Size D1, E1 27.84 27.94 28.04 Ball Footprint M,N 23 x 23 Ball Matrix M1 4 Number of Rows Deep b 0.60 0.75 0.90 Ball Diameter d 0.6 Min Distance Encap to Balls e 1.27 Ball Pitch aaa 0.15 bbb 0.15 Parallel ccc 0.20 Top Flatness Coplanarity ddd 0.15 0.33 0.50 Seating Plan Clearance P 0.20 0.30 0.35 Encapsulation Height 0.00 Solder Ball Placement S 20 Body Size Symbol Theta JC 0.72–1.08 Deg. C/Watt Theta JA 11.7–12.6 Deg. C/Watt RM5271 Microprocessor, Document Rev. 1.3 Quantum Effect Devices www.qedinc.com RM5271 304 SBGA PACKAGE PINOUT Pin Function Pin A1 VccIO A2 A5 Do Not Connect A9 SysAD32 A10 A13 VccInt A14 A17 SysAD61 A18 A21 VssIO B2 VccIO B6 B10 Function Function A3 VssIO VssIO A7 SysADC1 A11 VccInt Pin Function A4 ScLine11 Do Not Connect A8 VssIO Do Not Connect A12 VssIO A15 SysAD63 A16 VssIO VssIO A19 NC A20 ScLine4 A22 VssIO A23 VccIO B1 VssInt B3 VssInt B4 VssIO B5 ScLine10 SysAD35 B7 SysAD34 B8 VccInt B9 SysAD33 SysADC5 B11 SysADC0 B12 B13 SysADC7 A6 VssIO Pin Do Not Connect B14 SysADC6 B15 Do Not Connect B16 SysAD30 B17 SysAD29 B18 SysAD28 B19 ScLine5 B20 VssIO B21 VssInt B22 VccIO B23 VssIO C1 VssIO C2 VssInt C3 VccIO C4 VccIO C5 Do Not Connect C6 ScLine9 C7 SysAD3 C8 SysAD2 VccInt C10 SysAD0 C11 SysADC4 C12 VccInt C13 C9 SysADC3 C14 SysADC2 C15 SysAD62 C16 VccInt C17 SysAD60 C18 ScLine6 C19 Do Not Connect C20 VccIO C21 VccIO C22 VssInt C23 VssIO D1 ScLine13 D2 VssIO D3 VccIO D4 VccIO D5 VccIO D6 VccIO D7 ScLine8 D8 VccInt D9 VccIO D10 SysAD1 D11 VccInt D12 VccIO D13 VccInt D14 SysAD31 D15 VccIO D16 VccInt D17 ScLine7 D18 VccIO D19 VccIO D20 VccIO D21 VccIO D22 VssIO D23 Do Not Connect E1 VccInt E2 ScLine14 E3 ScLine12 E4 VccIO E20 VccIO E21 Do Not Connect E22 Do Not Connect E23 ScLine1 F1 VssIO F2 Reserved F3 ScLine15 F4 VccIO F20 VccIO F21 ScLine3 F22 ScLinE0 F23 VssIO G1 SysAD36 G2 SysAD4 G3 Reserved G4 VccInt G20 ScLine2 G21 G22 SysAD59 G23 VccInt SysAD58 H1 VssIO H2 SysAD37 H3 SysAD5 H4 H20 VccInt H21 SysAD27 H22 SysAD26 H23 VssIO Do Not Connect J1 SysAD7 J2 SysAD6 J3 VccInt J4 VccIO J20 VccIO J21 VccInt J22 SysAD57 J23 SysAD56 K1 SysAD40 K2 SysAD8 K3 SysAD39 K4 SysAD38 K20 SysAD25 K21 SysAD24 K22 SysAD55 K23 SysAD23 L1 SysAD10 L2 SysAD41 L3 SysAD9 L4 VccInt L20 VccInt L21 SysAD54 L22 SysAD22 L23 SysAD53 M1 VssIO M2 SysAD11 M3 SysAD42 M4 VccIO M20 VccIO M21 SysAD52 M22 SysAD21 M23 VssIO N1 SysAD43 N2 VccInt N3 SysAD12 N4 SysAD44 N20 SysAD19 N21 SysAD51 N22 VccInt N23 SysAD20 Note: Pins marked Reserved are for RM7000 compatibility. Do not connect to any signal or power planes. Quantum Effect Devices www.qedinc.com RM5271 Microprocessor, Document Rev. 1.3 21 Pin Function Pin Function Pin Function Pin Function P1 SysAD13 P2 SysAD45 P3 SysAD14 P4 VccInt P20 VccInt P21 SysAD49 P22 SysAD18 P23 SysAD50 R1 SysAD46 R2 SysAD15 R3 SysAD47 R4 VccIO R20 VccIO R21 SysAD16 R22 SysAD48 R23 SysAD17 T1 VssIO T3 Reserved T4 VccInt T20 ExtRqst* T21 T2 VccOK Reserved T22 BigEndian T23 VssIO U1 Reserved U2 VccInt U3 ModeClock U4 JTCK U20 VccInt U21 NMI* U22 Reset* U23 ColdReset* V1 VssIO V2 JTDO V3 JTMS V4 VccIO V20 VccIO V21 Reserved V22 VccInt V23 VssIO W1 JTDI W2 VccIO W3 Do Not Connect W4 VccIO W20 VccIO W21 Reserved W22 Reserved W23 VccInt Y1 Do Not Connect Y2 VssIO Y3 VccIO Y4 VccIO Y5 VccIO Y6 VccIO Y7 RdRdy* Y8 Release* Y9 VccIO Y10 ScWord0 Y11 VccInt Y12 VccIO Y13 SysCmd5 Y14 VccInt Y15 VccIO Y16 VccInt Y17 Int2* Y18 VccIO Y19 VccIO Y20 VccIO Y21 VccIO Y22 VssIO Y23 Reserved AA1 VssIO AA2 VssInt AA3 VccIO AA4 VccIO AA5 Do Not Connect AA6 ScMatch AA7 ValidOut* AA8 SysClock AA9 VccInt AA10 Do Not Connect AA11 Do Not Connect AA12 SysCmd0 AA13 SysCmd4 AA14 SysCmd8 AA15 ScTCE* AA16 ScValid AA17 VccInt AA18 Int3* AA19 Do Not Connect AA20 VccIO AA21 VccIO AA22 VssInt AA23 VssIO AB1 VssIO AB2 VccIO AB3 VssInt AB4 VssIO AB5 ModeIn AB6 ValidIn* AB7 VccP AB8 VccInt AB9 VccInt AB10 ScCWE0* AB11 ScDCE0* AB12 SysCmd1 AB13 SysCmd3 AB14 SysCmd7 AB15 ScClr* AB16 ScTDE* AB17 ScDOE* AB18 Int0* AB19 Int4* AB20 VssIO AB21 VssInt AB22 VccIO AB23 VssInt AC1 VccIO AC2 VssInt AC3 VssIO AC4 NC AC5 WrRdy* AC6 VssIO AC7 VssP AC8 VssIO AC9 ScWord1 AC10 ScCWE1* AC11 ScDCE1* AC12 VssIO AC13 SysCmd2 AC14 SysCmd6 AC15 SysCmdP AC16 VssIO AC17 ScTOE* AC18 VssIO AC19 Int1* AC20 Int5* AC21 VssIO AC22 VssIO AC23 VccIO Note: Pins marked Reserved are for RM7000 compatibility. Do not connect to any signal or power planes. 22 RM5271 Microprocessor, Document Rev. 1.3 Quantum Effect Devices www.qedinc.com ORDERING INFORMATION RM5271 -123 A I Temperature Grade: (blank) = commercial I=industrial Package Type: Q=Power Quad 4 (PQ-4) S=SBGA Device Maximum Speed Device Type Valid Combinations RM5271-200S RM5271-250S RM5271-266S RM5271-300S RM5271-350S Quantum Effect Devices www.qedinc.com RM5271 Microprocessor, Document Rev. 1.3 23 This document may, wholly or partially, be subject to change without notice. Quantum Effect Devices, Inc. reserves the right to make changes to its products or specifications at any time without notice, in order to improve design or performance and to supply the best possible product. All rights are reserved. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without QED's permission. QED will not be held responsible for any damage to the user or any property that may result from accidents, misuse, or any other causes arising during operation of the user's unit. LIFE SUPPORT POLICY: QED's products are not designed, intended, or authorized for use as components intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which failure of the product could create a situation where personal injury or death may occur. Should a customer purchase or use the products for any such unintended or unauthorized application, the customer shall indemnify and hold QED and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that QED was negligent regarding the design or manufacture of the part. QED does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a QED product. The company makes no representations that the circuitry described herein is free from patent infringement or other rights of third parties, which may result from its use. No license is granted by implication or otherwise under any patent, patent rights, or other rights, of QED. The QED logo and RISCMark are trademarks of Quantum Effect Devices, Inc. MIPS is a registered trademark of MIPS Technologies, Inc. All other trademarks are the respective property of the trademark holders. Document Number: RM5271-DS0012000001 Quantum Effect Devices 3255-3 Scott Blvd, Suite 200 Santa Clara, CA. 95054 phone (408) 565-0300 fax (408) 565-0330 [email protected] Quantum Effect Devices www.qedinc.com RM5271 Microprocessor, Document Rev. 1.3 24