a FEATURES Acquisition Time to 0.01%: 250 ns Typical Low Power Dissipation: 95 mW Low Droop Rate: 0.02 mV/ms Fully Specified and Tested Hold Mode Distortion Total Harmonic Distortion: –85 dB Aperture Jitter: 50 ps Maximum Internal Hold Capacitor Self-Correcting Architecture 8-Pin Mini Cerdip and SOIC Packages Complete Very High Speed Sample-and-Hold Amplifier AD783* FUNCTIONAL BLOCK DIAGRAM VCC 1 IN 2 8 OUT 7 S/H 6 NC 5 VEE X1 COMMON 3 NC 4 AD783 NC = NO CONNECT PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS The AD783 is a high speed, monolithic sample-and-hold amplifier (SHA). The AD783 offers a typical acquisition time of 250 ns to 0.01%. The AD783 is specified and tested for hold mode total harmonic distortion with input frequencies up to 100 kHz. The AD783 is configured as a unity gain amplifier and uses a patented self-correcting architecture that minimizes hold mode errors and ensures accuracy over temperature. The AD783 is self-contained and requires no external components or adjustments. 1. Fast acquisition time (250 ns), low aperture jitter (20 ps) and fully specified hold mode distortion make the AD783 an ideal SHA for sampling systems. The AD783 retains the held value with a droop rate of 0.02 µV/ µs. Excellent linearity and hold mode dc and dynamic performance make the AD783 ideal for high speed 12- and 14-bit analog-to-digital converters. 4. The AD783 requires no external components or adjustments. The AD783 is manufactured on Analog Devices’ ABCMOS process which merges high performance, low noise bipolar circuitry with low power CMOS to provide an accurate, high speed, low power SHA. 6. Fully specified and tested hold mode distortion guarantees the performance of the SHA in sampled data systems. 2. Low droop (0.02 µV/µs) and internally compensated hold mode error result in superior system accuracy. 3. Low power (95 mW typical), complete functionality and small size make the AD783 an ideal choice for a variety of high performance applications. 5. The AD783 is an excellent choice as a front-end SHA for high speed analog-to-digital converters such as the AD671, AD7586, AD674B, AD774B, AD7572 and AD7672. The J grade device is specified for operation from 0°C to +70°C and the A grade from –40°C to +85°C. The J and A grades are available in 8-pin cerdip and SOIC packages. The military temperature range version is specified for operation from –55°C to +125°C and is available in an 8-pin cerdip package. For details refer to the Analog Devices Military Products Databook or AD783/883B data sheet. *Protected by U.S. Patent Number 4,962,325. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD783–SPECIFICATIONS DC SPECIFICATIONS (TMIN to TMAX with VCC = +5 V 6 5%, VEE = –5 V 6 5%, CL = pF, unless otherwise noted) Parameter Min SAMPLING CHARACTERISTICS Acquisition Time 5 V Step to 0.01% 5 V Step to 0.1% Small Signal Bandwidth Full Power Bandwidth HOLD CHARACTERISTICS Effective Aperture Delay (+25°C) Aperture Jitter (+25°C) Hold Settling (to 1 mV, +25°C) Droop Rate Feedthrough (+25°C) (VIN = ± 2.5 V, 500 kHz) –30 AD783J/A Typ Max Units 250 200 15 2 375 350 ns ns MHz MHz 15 20 150 0.02 30 50 200 1 ns ps ns µV/µs –80 dB 1 ACCURACY CHARACTERISTICS Hold Mode Offset Hold Mode Offset Drift Sample Mode Offset Nonlinearity Gain Error OUTPUT CHARACTERISTICS Output Drive Current Output Resistance, DC Total Output Noise (DC to 5 MHz) Sampled DC Uncertainty Hold Mode Noise (DC to 5 MHz) Short Circuit Current Source Sink INPUT CHARACTERISTICS Input Voltage Range Bias Current Input Impedance Input Capacitance DIGITAL CHARACTERISTICS Input Voltage Low Input Voltage High Input Current High (VIN = 5 V) POWER SUPPLY CHARACTERISTICS Operating Voltage Range Supply Current +PSRR (+5 V ± 5%) –PSRR (–5 V ± 5%) Power Consumption TEMPERATURE RANGE Specified Performance (J) Specified Performance (A) –5 0 10 50 ± 0.005 ± 0.03 –5 0.3 150 85 125 –2.5 100 10 2 +5 200 ± 0.1 +5 0.6 mA Ω µV rms µV rms µV rms 20 13 mA mA +2.5 250 V nA MΩ pF 0.8 V V µA 2.0 ± 4.75 45 45 0 –40 mV µV/°C mV % FS % FS 2 10 ±5 9.5 65 65 95 ± 5.25 17 175 V mA dB dB mW +70 +85 °C °C NOTES 1 Specified and tested over an input range of ± 2.5 V. Specifications subject to change without notice. –2– REV. A AD783 HOLD MODE AC SPECIFICATIONS (T MIN to TMAX with VCC = +5 V 6 5%, VEE = –5 V 6 5%, CL = 50 pF, unless Parameter AD783J/A Typ Min otherwise noted) Max Units –80 dB dB TOTAL HARMONIC DISTORTION fIN = 100 kHz fIN = 500 kHz –85 –72 SIGNAL-TO-NOISE AND DISTORTION fIN = 100 kHz fIN = 500 kHz 77 70 dB dB INTERMODULATION DISTORTION (F1 = 99 kHz, F2 = 100 kHz) Second Order Products Third Order Products –80 –85 dB dB NOTES 1 fIN amplitude = 0 dB and f SAMPLE = 300 kHz unless otherwise indicated. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* Spec VCC VEE Analog Input Digital Input Output Short Circuit to Ground, VCC, or VEE Maximum Junction Temperature Storage Lead Temperature (10 sec max) PIN CONFIGURATION With Respect to Min Max Units COM COM COM COM –0.5 –6.5 –6.5 –0.5 +6.5 +0.5 +6.5 +6.5 V V V V VCC 1 IN 2 COMMON 3 NC 4 Indefinite –65 8 OUT AD783 7 S/H TOP VIEW (Not to Scale) 6 NC 5 VEE NC = NO CONNECT +175 °C +150 °C +300 °C *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD783 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ORDERING GUIDE Model1 Temperature Range Description Package Options2 AD783JQ AD783AQ AD783JR AD783AR 0°C to +70°C –40°C to +85°C 0°C to +70°C –40°C to +85°C 8-Pin Cerdip 8-Pin Cerdip 8-Pin SOIC 8-Pin SOIC Q-8 Q-8 R-8 R-8 NOTES 1 For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the 1 Analog Devices Military Products Databook or current AD783/883B data sheet. 2 Q = Cerdip, R = SOIC. REV. A –3– AD783–Typical Characteristics 10.0 V+ 60 V– DROOP RATE – µV/µs 1.0 PSRR – dB 50 40 0.1 0.01 30 0.001 0 1 10 100 1k 10k 100k 0 1M 25 50 75 100 TEMPERATURE – °C FREQUENCY – Hz Power Supply Rejection Ratio vs. Frequency 125 150 Droop Rate vs. Temperature, VIN = 0 V 200 ACQUISITION TIME – ns 150 BIAS CURRENT – nA 100 50 0 –50 –100 300 250 200 –150 0 –200 –2.5 0 INPUT VOLTAGE – V 0 +2.5 1 2 3 INPUT STEP – V 4 5 Acquisition Time (to 0.01%) vs. Input Step Size Bias Current vs. Input Voltage –4– REV. A AD783 Output Drive Current—The maximum current the SHA can source (or sink) while maintaining a change in hold mode offset of less than 2.5 mV. DEFINITIONS OF SPECIFICATIONS Acquisition Time—The length of time that the SHA must remain in the sample mode in order to acquire a full-scale input step to a given level of accuracy. Signal-To-Noise and Distortion (S/N+D) Ratio—S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. Small Signal Bandwidth—The frequency at which the held output amplitude is 3 dB below the input amplitude, under an input condition of a 100 mV p-p sine wave. Full Power Bandwidth—The frequency at which the held output amplitude is 3 dB below the input amplitude, under an input condition of a 5 V p-p sine wave. Total Harmonic Distortion (THD)—THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed in decibels. Effective Aperture Delay—The difference between the switch delay and the analog delay of the SHA channel. A negative number indicates that the analog portion of the overall delay is greater than the switch portion. This effective delay represents the point in time, relative to the hold command, that the input signal will be sampled. Hold Settling Time—The time required for the output to settle to within a specified level of accuracy of its final held value after the hold command has been given. Intermodulation Distortion (IMD)—With inputs consisting of sine waves at two frequencies, fa and fb, any device with nonlinearities will create distortion products, of order (m+n), at sum and difference frequency of mfa± nfb, where m, n = 0, 1, 2, 3. . . . Intermodulation terms are those for which m or n is not equal to zero. For example, the second order terms are (fa+fb) and (fa–fb), and the third order terms are (2fa+fb), (2fa–fb), (fa+2fb) and (fa–2fb). The IMD products are expressed as the decibel ratio of the rms sum of the measured input signals to the rms sum of the distortion terms. The two signals are of equal amplitude, and peak value of their sums is –0.5 dB from full scale. The IMD products are normalized to a 0 dB input signal. Droop Rate—The drift in output voltage while in the hold mode. FUNCTIONAL DESCRIPTION Aperture Jitter—The variations in aperture delay for successive samples. Aperture jitter puts an upper limit on the maximum frequency that can be accurately sampled. The AD783 is a complete, high speed sample-and-hold amplifier that provides high speed sampling to 12-bit accuracy in 250 ns. Feedthrough—The attenuated version of a changing input signal that appears at the output when the SHA is in the hold mode. The AD783 is completely self-contained, including an on-chip hold capacitor, and requires no external components or adjustments to perform the sampling function. Both input and output are treated as a single-ended signal, referred to common. Hold Mode Offset—The difference between the input signal and the held output. This offset term applies only in the hold mode and includes the error caused by charge injection and all other internal offsets. It is specified for an input of 0 V. The AD783 utilizes a proprietary circuit design which includes a self-correcting architecture. This sample-and-hold circuit corrects for internal errors after the hold command has been given, by compensating for amplifier gain and offset errors, and charge injection errors. Due to the nature of the design, the SHA output in the sample mode is not intended to provide an accurate representation of the input. However, in hold mode, the internal circuitry is reconfigured to produce an accurately held version of the input signal. Below is a block diagram of the AD783. Sample Mode Offset—The difference between the input and output signals when the SHA is in the sample mode. Nonlinearity—The deviation from a straight line on a plot of input vs. (held) output as referenced to a straight line drawn between endpoints, over an input range of –2.5 V and +2.5 V. Gain Error—Deviation from a gain of +1 on the transfer function of input vs. held output. Power Supply Rejection Ratio—A measure of change in the held output voltage for a specified change in the positive or negative supply. Sampled DC Uncertainty—The internal rms SHA noise that is sampled onto the hold capacitor. Hold Mode Noise—The rms noise at the output of the SHA while in the hold mode, specified over a given bandwidth. VCC 1 IN 2 OUT 7 S/H 6 NC 5 VEE X1 Total Output Noise—The total rms noise that is seen at the output of the SHA while in the hold mode. It is the rms summation of the sampled dc uncertainty and the hold mode noise. COMMON 3 NC 4 AD783 NC = NO CONNECT Functional Block Diagram REV. A 8 –5– AD783 DYNAMIC PERFORMANCE (VOUT HOLD – VIN ), mV VOUT ACQUISITION ACCURACY – % The AD783 is compatible with 12-bit A-to-D converters in terms of both accuracy and speed. The fast acquisition time, fast hold settling time and good output drive capability allow the AD783 to be used with high speed, high resolution A-to-D converters like the AD671 and AD7586. The AD783’s fast acquisition time provides high throughput rates for multichannel data acquisition systems. Typically, the AD783 can acquire a 5 V step in less than 250 ns. Figure 1 shows the settling accuracy as a function of acquisition time. +1 V IN , VOLTS –2.5 +2.5 NONLINEARITY 0.08 –1 GAIN ERROR 0.06 HOLD MODE OFFSET 0.04 Figure 2. Hold Mode Offset, Gain Error and Nonlinearity For applications where it is important to obtain zero offset, the hold mode offset may be nulled externally at the input to the A-to-D converter. Adjustment of the offset may be accomplished through the A-to-D itself or by an external amplifier with offset nulling capability (e.g., AD711). The offset will change less than 0.5 mV over the specified temperature range. 0.02 0 0 250 500 ACQUISITION TIME – ns Figure 1. VOUT Settling vs. Acquisition Time The hold settling determines the required time, after the hold command is given, for the output to settle to its final specified accuracy. The typical settling behavior of the AD783 is 150 ns. The settling time of the AD783 is sufficiently fast to allow the SHA, in most cases, to directly drive an A-to-D converter without the need for an added “start convert” delay. SUPPLY DECOUPLING AND GROUNDING CONSIDERATIONS As with any high speed, high resolution data acquisition system, the power supplies should be well regulated and free from excessive high frequency noise (ripple). The supply connection to the AD783 should also be capable of delivering transient currents to the device. To achieve the specified accuracy and dynamic performance, decoupling capacitors must be placed directly at both the positive and negative supply pins to common. Ceramic type 0.1 µF capacitors should be connected from VCC and VEE to common. HOLD MODE OFFSET The dc accuracy of the AD783 is determined primarily by the hold mode offset. The hold mode offset refers to the difference between the final held output voltage and the input signal at the time the hold command is given. The hold mode offset arises from a voltage error introduced onto the hold capacitor by charge injection of the internal switches. The nominal hold mode offset is specified for a 0 V input condition. Over the input range of –2.5 V to +2.5 V, the AD783 is also characterized for an effective gain error and nonlinearity of the held value, as shown in Figure 2. As indicated by the AD783 specifications, the hold mode offset is very stable over temperature. ANALOG P.S. +5V C 0.1µF DIGITAL P.S. –5V 0.1µF C 1µF 1µF +5V 1µF INPUT AD783 ANALOG-TO-DIGITAL CONVERTER DIGITAL DATA OUTPUT SIGNAL GROUND Figure 3. Basic Grounding and Decoupling Diagram –6– REV. A AD783 The accuracy in sampling high frequency signals is also constrained by the distortion and noise created by the sample-and-hold. The level of distortion increases with frequency and reduces the “effective number of bits” of the conversion. The AD783 does not provide separate analog and digital ground leads as is the case with most A-to-D converters. The common pin is the single ground terminal for the device. It is the reference point for the sampled input voltage and the held output voltage and also the digital ground return path. The common pin should be connected to the reference (analog) ground of the A-to-D converter with a separate ground lead. Since the analog and digital grounds in the AD783 are connected internally, the common pin should also be connected to the digital ground, which is usually tied to analog common at the A-to-D converter. Figure 3 illustrates the recommended decoupling and grounding practice. Measurements of Figures 6 and 7 were made using a 14-bit A/D converter with VIN = 5 V p-p and a sample frequency of 100 kSPS. 1% 1/2 BIT @ 8 BITS NOISE CHARACTERISTICS Designers of data conversion circuits must also consider the effect of noise sources on the accuracy of the data acquisition system. A sample-and-hold amplifier that precedes the A-to-D converter introduces some noise and represents another source of uncertainty in the conversion process. The noise from the AD783 is specified as the total output noise, which includes both the sampled wideband noise of the SHA in addition to the band limited output noise. The total output noise is the rms sum of the sampled dc uncertainty and the hold mode noise. A plot of the total output noise vs. the equivalent input bandwidth of the converter being used is given in Figure 4. 0.1% 1/2 BIT @ 10 BITS 1/2 BIT @ 12 BITS APERTURE JITTER TYPICAL AT 20ps 0.01% 1/2 BIT @ 14 BITS 1k 10k 1M 100k FREQUENCY – Hz Figure 5. Error Magnitude vs. Frequency 300 –70 200 –75 THD – dB OUTPUT NOISE – µV rms –65 100 –80 –85 –90 0 1k 10k 100k 1M 10M FREQUENCY – Hz –95 100 Figure 4. RMS Noise vs. Input Bandwidth of ADC 1k 100k 10k 1M FREQUENCY – Hz DRIVING THE ANALOG INPUTS Figure 6. Total Harmonic Distortion vs. Frequency For best performance, it is important to drive the AD783 analog input from a low impedance signal source. This enhances the sampling accuracy by minimizing the analog and digital crosstalk. Signals which come from higher impedance sources (e.g., over 5 kΩ) will have a relatively higher level of crosstalk. For applications where signals have high source impedance, an operational amplifier buffer in front of the AD783 is required. The AD711 (precision BiFET op amp) is recommended for these applications. 90 80 S/(N + D) – dB 70 HIGH FREQUENCY SAMPLING Aperture jitter and distortion are the primary factors which limit frequency domain performance of a sample-and-hold amplifier. Aperture jitter modulates the phase of the hold command and produces an effective noise on the sampled analog input. The magnitude of the jitter induced noise is directly related to the frequency of the input signal. 50 40 30 20 10 0 1k 10k 100k 1M FREQUENCY – Hz A graph showing the magnitude of the jitter induced error vs. frequency of the input signal is given in Figure 5. REV. A 60 Figure 7. Signal/(Noise and Distortion) vs. Frequency –7– AD783 TO AD670 INTERFACE The 15 MHz small signal bandwidth of the AD783 makes it a good choice for undersampling applications. Figure 8 shows the interface between the AD783 and the AD670 ADC, where the AD783 samples the incoming IF signal. For this particular application, the IF carrier was 10.7 MHz and the information signal was a 5 kHz FSK-modulated tone. The sample-and-hold signal is applied to the 8-bit AD670 ADC and then digitally processed for analysis. The CLKIN signal is connected directly to the S/H pin of the AD783 and must comply with the acquisition and settling requirements of the SHA. A delayed version of CLKIN is applied to the R/W input of the AD670 in order to accommodate the hold-mode settling requirements of the AD783. The 10 µs conversion speed of the AD670 combined with the 150 ns holdmode settling time of the AD783 result in a total system throughput of 10.15 µs. The low going one-shot output is connected to the clock input of flip-flop2. The D2 input of flip-flop2 is tied high. The rising edge of the low going pulse toggles the Q2 output of flip-flop2 to a high state. This output, which is tied to the ENCODE input of the AD671, initiates a conversion of the buffered output signal of the AD783. The AD671 issues the signal DAV when the conversion is complete. The DAV signal is tied to the asynchronous CLR1 and CLR2 inputs of both flip-flops. When DAV goes low, the Q1 output goes high returning the AD783 to the sample or acquisition mode. The Q2 output (ENCODE) returns low until it is again triggered by the rising edge of the one-shot output. VIN AD783 50 10.7MHz 255mV p-p AD783 8 AD671 Q1 +5V CLR1 CLR2 ONESHOT OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Pin Cerdip (Q-8) Package 18 +VIN HI 8 5 0.310 (7.87) 0.220 (5.59) 16 –VIN HI 17 –VIN LOW 4 1 AD670 ONE SHOT ENCODE Figure 9. AD783 to AD671 Interface 19 +VIN LOW CLK IN DAV Q2 10k 7 D1 D2 0.405 (10.29) MAX 21 R/W 0.200 (5.08) MAX Figure 8. AD783 to AD670 Interface 0.150 (3.81) MIN AD783 to AD671 (12-Bit, 500 ns ADC) Interface The AD783 to AD671 interface requires an op amp, a dual flip-flop, and a monostable multivibrator or “one-shot.” The op amp amplifies the ± 2.5 V output of the AD783 to the full-scale input of the AD671. Appropriate op amps include the AD841 and AD845 (see the AD671 data sheet for additional information). The flip-flops and one-shot are used to generate the AD671 ENCODE pulse and the appropriately timed AD783 S/H pulse. 0.320 (8.13) 0.290 (7.37) 0.060 (1.52) 0.015 (0.38) 0.023 (0.58) 0.014 (0.36) 0.015 (0.381) 0.008 (0.204) 0.100 (2.54) BSC 0.070 (1.78) 0.030 (0.76) 8-Pin SOIC (R-8) Package PRINTED IN U.S.A. 2 AIN AD84X CLOCK By keeping the 10.7 MHz IF input to the AD783 at a low amplitude, 255 mV p-p, the resultant distortion and jitterinduced noise result in approximately 45 dB of dynamic range. The AD670 can be conveniently configured such that its fullscale input range is 255 mV in order to retain the full 8-bit dynamic range of the converter. The maximum sample rate of the AD670 is 10 µs; therefore, to comply with the Nyquist criteria the maximum information bandwidth is 50 kHz. ANALOG INPUT C1733–12–10/92 AD783 0.198 (5.03) 0.188 (4.77) A master sampling clock is tied to the clock input of flip-flop1 and the input of the one-shot. The D1 input of flip-flop1 should be tied high and the one-shot should be configured to generate a pulse on a rising edge of the sampling clock. The rising edge of the sampling clock causes the Q1 output of the flip-flop to go low placing the AD783 into hold mode. Simultaneously, a low going pulse is generated at the one-shot output. The length of this pulse would usually be made long enough to allow the output of the AD783 to settle (hold-mode settling time), but because of the error-correcting ability of the AD671, the length of this pulse may be reduced to approximately 200 ns. 8 5 0.158 (4.01) 0.150 (3.81) 1 0.050 (1.27) BSC 0.248 (6.29) 0.224 (5.69) 4 0.022 (0.56) 0.014 (0.36) 0.205 (5.21) 0.195 (4.95) 0.107 (2.72) 0.011 (0.275) 0.005 (0.125) –8– 0.089 (2.26) 0.015 (0.38) 0.007 (0.18) 0.034 (0.86) 0.018 (0.46) REV. A