High Performance ISM Band ASK/FSK Transmitter IC ADF7901 Preliminary Technical Data is capable of Frequency Shift Keying (FSK) modulation on 8 different channels, selectable by 3 external control lines. OOK modulation is performed by modulating the PA control line. FEATURES Single chip low power UHF transmitter 369.5 MHz to 395.9 MHz frequency operation using Fractional-N PLL and fully integrated VCO 3.0 V supply voltage Data rates supported < 2.5 kbps Low current consumption 26 mA at 12 dBm Output at 384 MHz Power-down mode (< 1 µA) 24-Lead TSSOP package The on-chip VCO operates at 2 × the output frequency. The divide by 2 at the output of the VCO reduces the amount of PA feedthrough. As a result of this, OOK modulation depths of greater than 50 dB are easily achievable. The FSK_ADJ and ASK_ADJ resistors can be adjusted in the system to optimize output power, for each modulation scheme. An additional 1.5 dB of output power is provided for the lower bank of channels to adjust for antenna performance. The CE line allows the transmitter to be powered down completely. In this mode, the leakage current is typically 0.1 µA. GENERAL DESCRIPTION The ADF7901 is a low power OOK/FSK UHF transmitter designed for use in RF Remote Control Devices. The device FUNCTIONAL BLOCK DIAGRAM CREG2 OSC1 PA_EN OSC2 CVCO VDD VCO RFOUT PA R=1 RFGND PDF CHARGE PUMP LDO REGULATOR #1 ÷ FRACTIONAL N TXDATA LDO REGULATOR #2 SIGMA-DELTA FSK CHANNEL SELECT CE DGND FSK1 FSK2 FSK3 CREG1 CREG2 RS ET OOK_SEL RSET_FSK RSET_OOK 01975-001 DVDD Figure 1. Rev. PrD Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved. ADF7901 Preliminary Technical Data TABLE OF CONTENTS Specifications..................................................................................... 3 Decoupling.............................................................................. 10 Absolute Maximum Ratings............................................................ 5 Regulator Stability .................................................................. 10 ESD Caution.................................................................................. 5 Grounding............................................................................... 10 Pin Configuration and Function Descriptions............................. 6 Supply ...................................................................................... 10 Typical Performance Characteristics ............................................. 8 Digital Lines............................................................................ 10 Circuit Description........................................................................... 9 Outline Dimensions ....................................................................... 11 Internal Register Settings ............................................................ 9 Ordering Guide .......................................................................... 11 Loop Filter ..................................................................................... 9 Layout Guidelines....................................................................... 10 REVISION HISTORY 1/05—Revision PrD Rev. PrD | Page 2 of 12 Preliminary Technical Data ADF7901 SPECIFICATIONS VDD =3.0 V; GND = 0 V; TA = TMIN to TMAX unless otherwise noted. Typical specifications TA = 25°C. Table 1. Parameter1 RF CHARACTERISTICS Output Frequency Ranges Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 Channel 9 Phase Frequency Detector Frequency TRANSMISSION PARAMETERS Transmit Rate FSK OOK Frequency Shift Keying FSK Separation2 On/Off Keying Modulation Depth3 Output Power Min/Max Range4 fOUT ≤ 384 MHz fOUT > 384 MHz Occupied 20 dB BW OOK at 1 kbits/s FSK (PA Off/On) at10 Hz5 LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance POWER SUPPLIES Voltage Supply DVDD Transmit Current Consumption 369.5–376.9 MHz at +12 dBm 384 MHz at +12 dBm 388.3–395.9 MHz at +10.5 dBm 384 MHz at +5 dBm Power-Down Mode Low Power Sleep Mode6 Min Typ 10 7 Max Unit 369.5 371.1 375.3 376.9 384.0 388.3 391.5 394.3 395.9 9.8304 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 2 2.5 kbps kbps −34.8 +34.8 kHz, Data = 1 kHz, Data = 0 83 dB, Output Power = 12 dBm 15 12 10.5 dB dBm dBm ±28 ±26 ±461.9 ±461.9 kHz kHz 0.2 × VDD ±1 10 V V µA pF 2.124 3.0 V 26 26 21 17 mA mA mA mA 0.2 Rev. PrD | Page 3 of 12 1 µA ADF7901 Preliminary Technical Data Parameter1 PHASE-LOCKED LOOP VCO Gain Spurious7, Integer Boundary Reference Harmonics Second Harmonic VDD = 3.0 V Third Harmonic VDD = 3.0 V All Other Harmonics REFERENCE INPUT Crystal Reference POWER AMPLIFIER PA Output Impedance Min Typ Max Unit –45 −70 −23 −23 MHz/V at 384 MHz 100 kHz loop BW dBc dBc −24 −14 −21 −11 −18 dBc dBc dBc 30 3 3 TIMING INFORMATION Crystal Oscillator to PLL Lock PA Enable to PA ready–PLL Settle8 TEMPERATURE RANGE – TA 9.8304 MHz 97 Ω + 6.4 pF At 384 MHz 2 100 3 0 1 3 250 50 ms µs °C Operating temperature range is as follows: 0°C to +50°C. Frequency Deviation = 34 × (9.8304 MHz )/214. Error in the crystal will be reflected in variation in the desired deviation. 3 Not production tested. Based on characterization. 4 The output power can be varied in both ASK/FSK mode by altering the relevant external resistor. 5 Measured using Spectrum Analyzer, 1 MHz span, 100 kHz RBW, MAX HOLD enabled. 6 Maximum power-down current spec applies for the OSC2 pin grounded. 7 Measured > 461.9 kHz away from channel. 8 This spec refers to the time taken for the PLL to regain lock after the PA has been enabled. The PA is should only be enabled after the PLL has settled to the correct frequency. 2 Rev. PrD | Page 4 of 12 Preliminary Technical Data ADF7901 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 2. Parameter1 VDD to GND2 RFVDD to GND Digital I/O Voltage to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature TSSOP θJA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Value −0.3 V to +4.0 V −0.3 V to +4.0 V −0.3 V to VDD + 0.3 V 0°C to +50°C −65°C to +125°C 125°C 150.4°C/W 235°C 240°C 1 This device is a high performance RF integrated circuit with an ESD rating of <1 kV and it is ESD sensitive. Proper precautions should be taken for handling and assembly. 2 GND = RFGND = DGND = 0 V. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrD | Page 5 of 12 ADF7901 Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DVDD 1 24 CREG2 CREG1 2 23 RSET CPOUT 3 22 PA_EN TxDATA 4 21 DVDD DGND 5 NC 6 DGND 7 OSC1 8 17 CVCO OSC2 9 16 RSET_FSK 20 RFOUT 19 RFGND TOP VIEW (Not to Scale) 18 VCOIN 15 RSET_OOK FSK1 11 14 CE FSK2 12 13 FSK3 01975-002 OOK_SEL 10 ADF7901 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 Mnemonic DVDD Function Positive Supply for the Digital Circuitry. This must be 3.0 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. A 2.2 µF capacitor should be added at CREG to reduce regulator noise and improve stability. A reduced capacitor will improve regulator power-on time but may cause higher spurious. Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated current changes the control voltage on the input to the VCO. 2 CREG1 3 CPOUT 4 TxDATA Digital FSK data to be transmitted is inputted on this pin. 5 6 7 8 DGND NC DGND OSC1 Ground for Digital Section. 9 OSC2 10 OOK_SEL A high on this pin selects operation in OOK mode at 384 MHz when CE is high. 11 FSK1 FSK Channel Select Pin. This represents the LSB of the channels select pins 12 FSK2 13 FSK3 FSK Channel Select Pin. FSK Channel Select Pin. 14 CE Bringing CE low puts the ADF7901 into power-down drawing < 1 µA of current. 15 RSET_OOK The value of this resistor sets the output power for data = 1 in OOK mode. A resistor of 3.6 kΩ will provide the maximum output power. Increasing the resistor will reduce the power and the current consumption. A lower resistor value than 3.6 kΩ can be used to increase the power to a maximum of +14 dBm. The PA will not be operating efficiently in this mode. 16 RSET_FSK 17 CVCO 18 VCOIN 19 20 RFGND RFOUT 21 DVDD The value of this resistor sets the output power in FSK mode. A resistor of 3.6 kΩ will provide max output power. Increasing the resistor will reduce the power and the current consumption. A lower resistor value than 3.6 kΩ can be used to increase the power to a maximum of +14 dBm. The PA will not be operating efficiently in this mode. A 220 nF capacitor should be tied between CVCO and CREG2 pin. This line should run underneath the ADF7901. This capacitor is necessary to ensure stable VCO operation. The tuning voltage on this pin determines the output frequency of the Voltage Controlled Oscillator (VCO). The higher the tuning voltage the higher the output frequency. The output of the loop filter is connected here. Ground for Output Stage of Transmitter. The modulated signal is available at this pin. Output power levels are from –5 dBm to +12 dBm. The output should be impedance matched using suitable components to the desired load. Voltage Supply for VCO, and PA section. This should be supplied with 3.0 V. Decoupling capacitors to the ground No Connect. Ground for Digital Section. The reference crystal should be connected between this pin and OSC2. The necessary crystal load capacitor should be tied between this pin and ground. The reference crystal should be connected between this pin and OSC1. The necessary crystal load capacitor should be tied between this pin and ground. Rev. PrD | Page 6 of 12 Preliminary Technical Data Pin No. Mnemonic 22 PA_EN 23 24 RSET CREG2 ADF7901 Function plane should be placed as close as possible to this pin. This pin is used to enable the Power Amplifier. This should be modulated with the OOK data in OOK mode. In FSK mode, it should be enabled when the PLL is locked. External resistor to set charge pump current and some internal bias currents. Use 3.6 kΩ as default. A 2.2 µF capacitor should be added at CREG to reduce regulator noise and improve stability. A reduced capacitor will improve regulator power-on time but may cause higher spurious. Rev. PrD | Page 7 of 12 ADF7901 Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS Ref 15dBm Avg Log 10 dB/ OUTPUT POWER (dBm) 16 Mkr1 10.00kHz Noise –89.55dB/Hz Atten 30dB 1R 12 RBW 300.0000000Hz 8 PAvg 1 W1 S2 S3 FS AA 4 2 3 4 5 6 RSET 7 8 9 10 Center 395.948 29MHz #Res BW 300Hz Figure 5. Phase Noise at Channel 9 Figure 3. Output Power vs. RSET FSK, Upper FSK Channels, Measured into 50 Ω Mkr4 1.59GHz –21.30dB Atten 30dB Ref 15dBm Peak Log 10 4R dB/ 35 Span 50kHz Sweep 2.118 s (601 pts) VBW 300Hz 01975-006 0 01975-004 £(f): f<50k Swp 2 30 4 1 Marker Trace Type 1 (1) Freq 2 (1) Freq 3 (1) Freq 4 (1) Freq X Axis 400MHz 800MHz 1.19GHz 1.59GHz Amplitude –25.56dB –13.89dB –34.53dB –21.30dB IDD (mA) 3 25 20 15 5 6 7 8 OUTPUT POWER (dBm) 9 10 Figure 4. Current Consumption vs. Output Power, Upper FSK Channels, Measured into 50 Ω Center 5.50GHz #Res BW 1MHz VBW 1MHz Span 10.5GHz Sweep 17.52 ms (601 pts) 01975-007 4 01975-005 LgAv 10 Figure 6. Harmonic Levels–Up to 4th Harmonic. Measured at Channel 9 in to 50 Ω Rev. PrD | Page 8 of 12 Preliminary Technical Data ADF7901 CIRCUIT DESCRIPTION Table 4. FSK3 0 0 0 0 X 1 1 1 1 FSK2 0 0 1 1 X 0 0 1 1 INTERNAL REGISTER SETTINGS Based on PFD = 9.8304 MHz REG0 Error Correction 0 R Value 1 XOE 1 (Enabled) Clock Out 0 (Disabled) REG1 Ch #1 Integer = 37, Frac = 2406 Ch #2 Integer = 37, Frac = 3073 Ch #3 Integer = 38, Frac = 727 Ch #4 Integer = 38, Frac = 1394 Ch #5(OOK) Integer = 39, Frac = 256 Ch #6 Integer = 39, Frac = 2048 Ch #7 Integer = 39, Frac = 3381 Ch #8 Integer = 40, Frac = 452 Ch #9 Integer = 40, Frac = 1118 VCO Band 1 (Divide-by-2) LD Precision 1 (Don’t care) REG2 Mod Scheme 0 (FSK) PA (External R) Mod Deviation 58 (±35 kHz) Prescaler 0 (4/5) FSK1 0 1 0 0 X 0 1 0 1 OOK_SEL 0 0 0 0 1 0 0 0 0 REG3 PLL Enable 1 PA Enable (PA_EN Line) CLKout EN 0 (Off) Data Invert 0 Charge Pump 1 (3/7) CP Bleed 0 MuxOut 0 VCOBias 3 PA Bias External R VCO Band (Switched) LOOP FILTER The loop filter integrates the current pulses from the charge pump to form a voltage that tunes the output of the VCO to the desired frequency. It also attenuates spurious levels generated by the PLL. The loop filter design recommended on this design is 300 kHz. This is based on the trade-off between attenuation of beat note spurious and the need to minimize chirp when the PA is turned on. CHARGE PUMP OUT VCO 01975-008 Frequency MHz 369.5 371.1 375.3 376.9 384.0 388.3 391.5 394.3 395.9 Figure 7. C1 = 680 pF C2 = 15 nF C3 = 150 pF R1 = 120 Ω R2 = 3.3 kΩ Rev. PrD | Page 9 of 12 ADF7901 Preliminary Technical Data 220nF 2.2mF 2.2mF MATCHING RFOUT TO 50V CVCO CREG2 DVDD CREG1 RSET 27nH 5TH ORDER LOW PASS FILTER 3.6kΩ 22nH 5.6pF 1.5pF 22nH RFOUT VCOIN CPOUT ANTENNA 3pF VCOIN 8pF 3pF ADF7901 36nH MATCHING 50 V TO ANTENNA RSET_FSK 3.6kΩ RSET_OOK 3.6kΩ FSK1 FSK2 OSC2 FSK3 OOK_SEL 9.8304MHz OSC1 PA_EN CE 33pF 33pF GND NOTES 1. DECOUPLING CAPACITORS HAVE BEEN OMITTED FOR CLARITY. 01975-003 TxDATA Figure 8. Applications Diagram for the ADF7901 in a Remote Control System LAYOUT GUIDELINES Grounding The layout of the board is crucial to ensuring low levels of spurious and harmonics. Emphasis should be placed on the grounding once the decoupling capacitors have been added. The PA stage switches currents of 15 mA in max power mode. This will cause changes in the ground resulting in large return currents which can radiate to other parts of the board. The shortest and least obstructed ground from RFGND back to the ground of the battery should be ensured. A 4-layer board will help, as well as flooding of the top layer. The ground paths should not have any vias, and should be wide tracks. Decoupling Decoupling capacitors (high frequency 22 pF, low frequency 100 nF) should be placed as close as possible to the supply pins on the part. Low size 0402 and 0603 components are recommended for the high frequency rejection on the supply. Regulator Stability A minimum of 1 µF is needed on both CREG1 and CREG2 to ensure stability. An additional 22 pF capacitor can be added to reject higher frequency noise. Since many of the internal block run off the regulator it is critical to reduce the noise on this. Low size 0402 and 0603 components are recommended for the high frequency rejection on the supply. Supply The supply tracks can be routed through vias, as these act as free inductors on the board and make layout easier on a 2-layer board. See the Decoupling section. Tracks should be wide. Digital Lines Any digital lines should contain a large resistor in series. This impedance will block signals of many frequencies including harmonics and the carrier frequency. Long control lines can act as an antenna. It can be useful to add capacitance to ground. There will be some capacitance to ground provided by the lines, and at the input of the digital pins. Rev. PrD | Page 10 of 12 Preliminary Technical Data ADF7901 OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 1.20 MAX SEATING PLANE 0.20 0.09 8° 0° 0.75 0.60 0.45 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153AD Figure 9. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters ORDERING GUIDE Model ADF7901BRU Temperature Range 0°C to +50°C Package Description 24-Lead Thin Shrink Small Outline Pacakage [TSSOP] Rev. PrD | Page 11 of 12 Package Option RU-24 ADF7901 Preliminary Technical Data NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR05349–0–1/05(PrD) Rev. PrD | Page 12 of 12