áç XR17C158 PCI BUS OCTAL UART SEPTEMBER 2001 REV. 1.1.3 GENERAL DESCRIPTION The XR17C1581 (158) is an octal Universal Asynchronous Receiver and Transmitter (UART). The device is designed to meet the 32-bit PCI Bus and high bandwidth requirement in communication systems. The global interrupt source register provides a complete interrupt status indication for all 8 channels to speed up interrupt parsing. Each UART has its own 16C550 compatible set of configuration registers, transmit and receive FIFOs of 64 bytes, fully programmable transmit and receive FIFO level triggers, transmit and receive FIFO level counters, automatic RTS/ CTS or DTR/DSR hardware flow control with programmable hysteresis, automatic software (Xon/Xoff) flow control, IrDA (Infrared Data Association) encoder/decoder, 8 multi-purpose definable inputs/outputs, and a 16-bit general purpose timer/counter. NOTE: 1 Covered by U.S. Patents #5,649,122 and #5,949,787 FEATURES • High Performance Octal UART • 32-bit PCI Bus Interface with EEPROM Interface - Interrupt Source Register for all 8 UARTs - Data Transfer in Byte, Word and Double-word - Read/Write Burst Operation • Each UART Includes - 16C550 Compatible Registers - 64-byte Transmit and Receive FIFOs - Transmit and Receive FIFO Level Counters - Automatic RTS/CTS or DTR/DSR Flow Control - Automatic Xon/Xoff Software Flow Control - RS485 Half-duplex Control with Selectable Delay - Infrared (IrDA 1.0) Data Encoder/Decoder - Programmable Data Rate with Prescaler - Up to 6.25 Mbps Serial Data Rate APPLICATIONS • Remote Access Servers • Eight Multi-Purpose Inputs/outputs • Ethernet Network to Serial Ports • A General Purpose 16-bit Timer/Counter • Network Management • Sleep Mode with Automatic Wake-up • Factory Automation and Process Control • 5V Operation (PCI Compliance) • Point-of-Sale Systems • 3.3V Operation with 5V Tolerant Inputs • Multi-port RS-232/RS-422/RS-485 Cards • 144-pin TQFP Package (20x20x1.4mm) FIGURE 1. BLOCK DIAGRAM CLK RST# A D [31 :0 ] C /B E [3:0 ]# FRAME# IR D Y # TRDY# DEVSEL# STOP# IN T A # ID S E L PERR# SERR# PAR U A R T C ha nn el 0 UA RT Regs BR G IR ENDEC T X 0, R X 0 , D T R 0 #, D S R 0 # , R T S 0# , C T S 0# , C D 0 #, R I0 # 64 Byte RX FIFO U A R T C ha nn el 1 P C I L oca l B us In te rface D e vice C o nfig ura tion R e giste rs U A R T C ha nn el 2 U A R T C ha nn el 3 U A R T C ha nn el 4 U A R T C ha nn el 5 U A R T C ha nn el 6 C o nfig ura tion S pa ce R e giste rs EECK EEDI EEDO EECS 64 Byte TX FIFO TX & R X EEPROM In te rface U A R T C ha nn el 7 1 6-bit T im er/C o un te r M ulti-p urpo . se In pu ts/O u tpu ts C rysta l O sc/B uffer T X 7, R X 7 , D T R 7 #, D S R 7 # , R T S 7# , C T S 7# , C D 7 #, R I7 # M P IO 0 - M P IO 7 XTAL1 XTAL2 TMRCK EXAR Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com áç XR17C158 PCI BUS OCTAL UART REV. 1.1.3 DSR5# MPIO2 MPIO3 73 CD5# 74 RI5# 76 75 RTS5# 77 TX5 80 78 RX4 81 79 DTR5# DSR4# CTS4# 82 CD4# 83 RI4# 84 DTR4# 87 85 TX4 88 86 RTS4# VCC CTS3# 92 GND DSR3# 93 89 CD3# 94 90 RI3# 95 91 RX3 DTR3# RTS3# 96 TX3 98 97 RX2 99 100 CTS2# CD2# 101 DSR2# 103 RI2# 102 DTR2# 105 104 RTS2# TX2 106 MPIO0 108 107 MPIO1 FIGURE 2. PIN OUT OF THE DEVICE XTAL2 109 72 CTS5# XTAL1 110 71 RX5 TEST# 111 70 ENIR VCC 112 69 TMRCK MPIO4 EEDO 113 68 EEDI 114 67 MPIO5 EECS 115 66 MPIO6 EECK 116 65 MPIO7 TX1 117 64 VCC D T R 1 # 118 63 GND R T S 1 # 119 62 TX6 RI1# 120 61 DTR6# CD1# 121 60 RTS6# D S R 1 # 122 59 RI6# CTS1# 123 58 CD6# RX1 124 57 DSR6# TX0 125 56 CTS6# XR17C158 D T R 0 # 126 RTS0# 127 55 RX6 54 TX7 34 35 36 VCC GND CBE0 33 AD8 31 AD10 32 30 AD11 AD9 29 PAR TRDY# 28 AD7 AD12 AD6 37 AD13 38 144 27 143 AD25 AD14 AD26 26 AD5 AD15 39 24 142 CBE1 25 AD4 AD27 SERR# 23 AD3 40 STOP 21 # PERR# 22 41 141 20 140 AD28 19 AD29 GND AD2 VCC 42 DEVSEL# 18 139 17 AD1 AD30 IRDY# 16 43 CBE2 14 138 FRAME# 15 AD0 AD31 13 VCC 44 AD16 45 137 12 136 VCC AD17 GND 11 GND AD18 46 9 135 10 RX7 CLK AD19 47 AD20 134 8 CTS7# RST# AD21 DSR7# 48 7 49 133 6 132 INTA# AD23 RX0 AD22 CD7# 5 50 GND 131 4 RI7# CTS0# 3 51 VCC 130 IDSEL RTS7# DSR0# 2 DTR7# 1 53 52 CBE3 128 129 AD24 RI0# CD0# ORDERING INFORMATION PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE XR17C158CV 144-TQFP 0°C to +70°C XR17C158IV 144-TQFP -40°C to +85°C 2 XR17C158 áç PCI BUS OCTAL UART REV. 1.1.3 PIN DESCRIPTIONS Pin Description NAME PIN # TYPE DESCRIPTION PCI LOCAL BUS INTERFACE RST# 134 I Bus reset input (active low). It resets the PCI local bus configuration space registers, device configuration registers and UART channel registers to the default condition, see Table 19 on page 40. Bus clock input of up to 33MHz. CLK 135 I AD31-AD0 1 6-13 26-33 37-44 138-144 IO FRAME# 15 I Bus transaction cycle frame (active low). It indicates the beginning and duration of an access. C/BE0#-C/BE3# 36,25,14,2 I Bus Command/Byte Enable [3:0] (active low). This line is multiplexed for bus Command during the address phase and Byte Enables during the data phase. IRDY# 16 I Initiator Ready (active low). During a write, it indicates that valid data is present on data bus. During a read, it indicates the master is ready to accept data. TRDY# 17 O Target Ready (active low). STOP# 21 O Target request to stop current transaction (active low). Address data lines [31:0] (bidirectional). IDSEL 3 I Initialization device select (active high). DEVSEL# 18 O Device select to the XR17C158 (active low). INTA# 133 OD Device interrupt from XR17C158 (open drain, active low). PAR 24 IO Parity is even across AD[31:0] and C/BE[3:0]#. (bidirectional, active high). PERR# 22 O Data Parity error indicator, except for Special Cycle transactions (active low). Optional in bus target application. SERR# 23 OD System error indicator, Address parity or Data parity during Special Cycle transactions (open drain, active low). Optional in bus target application. MODEM OR SERIAL I/O INTERFACE TX0 125 O UART channel 0 Transmit Data or infrared transmit data. RX0 132 I UART channel 0 Receive Data or infrared receive data. Normal RXD input idles at logic 1 condition. The infrared pulses can be inverted internally prior the decoder by FCTR[4]. RTS0# 127 O UART channel 0 Request to Send or general purpose output (active low). CTS0# 131 I UART channel 0 Clear to Send or general purpose input (active low). DTR0# 126 O UART channel 0 Data Terminal Ready or general purpose output (active low). DSR0# 130 I UART channel 0 Data Set Ready or general purpose input (active low). CD0# 129 I UART channel 0 Carrier Detect or general purpose input (active low). RI0# 128 I UART channel 0 Ring Indicator or general purpose input (active low). TX1 117 O UART channel 1 Transmit Data or infrared transmit data. RX1 124 I UART channel 1 Receive Data or infrared receive data. Normal RXD input idles at logic 1 condition. The infrared pulses can be inverted internally prior the decoder by FCTR[4]. RTS1# 119 O UART channel 1 Request to Send or general purpose output (active low). 3 áç PCI BUS OCTAL UART XR17C158 REV. 1.1.3 Pin Description NAME PIN # TYPE DESCRIPTION CTS1# 123 I UART channel 1 Clear to Send or general purpose input (active low). DTR1# 118 O UART channel 1 Data Terminal Ready or general purpose output (active low). DSR1# 122 I UART channel 1 Data Set Ready or general purpose input (active low). CD1# 121 I UART channel 1 Carrier Detect or general purpose input (active low). RI1# 120 I UART channel 1 Ring Indicator or general purpose input (active low). TX2 106 O UART channel 2 Transmit Data or infrared transmit data. RX2 99 I UART channel 2 Receive Data or infrared receive data. Normal RXD input idles at logic 1 condition. The infrared pulses can be inverted internally prior the decoder by FCTR[4]. RTS2# 104 O UART channel 2 Request to Send or general purpose output (active low). CTS2# 100 I UART channel 2 Clear to Send or general purpose input (active low). DTR2# 105 O UART channel 2 Data Terminal Ready or general purpose output (active low). DSR2# 101 I UART channel 2 Data Set Ready or general purpose input (active low). CD2# 102 I UART channel 2 Carrier Detect or general purpose input (active low). RI2# 103 I UART channel 2 Ring Indicator or general purpose input (active low). TX3 98 O UART channel 3 Transmit Data or infrared transmit data. RX3 91 I UART channel 3 Receive Data or infrared receive data. Normal RXD input idles at logic 1 condition. The infrared pulses can be inverted internally prior the decoder by FCTR[4]. RTS3# 96 O UART channel 3 Request to Send or general purpose output (active low). CTS3# 92 I UART channel 3 Clear to Send or general purpose input (active low).d. DTR3# 97 O UART channel 3 Data Terminal Ready or general purpose output (active low). DSR3# 93 I UART channel 3 Data Set Ready or general purpose input (active low). CD3# 94 I UART channel 3 Carrier Detect or general purpose input (active low). RI3# 95 I UART channel 3 Ring Indicator or general purpose input (active low). TX4 88 O UART channel 4 Transmit Data or infrared transmit data. RX4 81 I UART channel 4 Receive Data or infrared receive data. Normal RXD input idles at logic 1 condition. The infrared pulses can be inverted internally prior the decoder by FCTR[4]. RTS4# 86 O UART channel 4 Request to Send or general purpose output (active low). CTS4# 82 I UART channel 4 Clear to Send or general purpose input (active low). DTR4# 87 O UART channel 4 Data Terminal Ready or general purpose output (active low). DSR4# 83 I UART channel 4 Data Set Ready or general purpose input (active low). CD4# 84 I UART channel 4 Carrier Detect or general purpose input (active low). RI4# 85 I UART channel 4 Ring Indicator or general purpose input (active low). TX5 80 O UART channel 5 Transmit Data or infrared transmit data. RX5 71 I UART channel 5 Receive Data or infrared receive data. Normal RXD input idles at logic 1 condition. The infrared pulses can be inverted internally prior the decoder by FCTR[4]. RTS5# 78 O UART channel 5 Request to Send or general purpose output (active low). CTS5# 72 I UART channel 5 Clear to Send or general purpose input (active low). DTR5# 79 O UART channel 5 Data Terminal Ready or general purpose output (active low). DSR5# 75 I UART channel 5 Data Set Ready or general purpose input (active low). 4 XR17C158 áç PCI BUS OCTAL UART REV. 1.1.3 Pin Description NAME PIN # TYPE DESCRIPTION CD5# 76 I UART channel 5 Carrier Detect or general purpose input (active low). RI5# 77 I UART channel 5 Ring Indicator or general purpose input (active low). TX6 62 O UART channel 6 Transmit Data or infrared transmit data. RX6 55 I UART channel 6 Receive Data or infrared receive data. Normal RXD input idles at logic 1 condition. The infrared pulses can be inverted internally prior the decoder by FCTR[4]. RTS6# 60 O UART channel 6 Request to Send or general purpose output (active low). CTS6# 56 I UART channel 6 Clear to Send or general purpose input (active low). DTR6# 61 O UART channel 6 Data Terminal Ready or general purpose output (active low). DSR6# 57 I UART channel 6 Data Set Ready or general purpose input (active low). CD6# 58 I UART channel 6 Carrier Detect or general purpose input (active low). RI6# 59 I UART channel 6 Ring Indicator or general purpose input (active low). TX7 54 O UART channel 7 Transmit Data or infrared transmit data. RX7 47 I UART channel 7 Receive Data or infrared receive data. Normal RXD input idles at logic 1 condition. The infrared pulses can be inverted internally prior the decoder by FCTR[4]. RTS7# 52 O UART channel 7 Request to Send or general purpose output (active low). CTS7# 48 I UART channel 7 Clear to Send or general purpose input (active low). DTR7# 53 O UART channel 7 Data Terminal Ready or general purpose output (active low). DSR7# 49 I UART channel 7 Data Set Ready or general purpose input (active low). CD7# 50 I UART channel 7 Carrier Detect or general purpose input (active low). RI7# 51 I UART channel 7 Ring Indicator or general purpose input (active low). MPIO0 108 I/O Multi-purpose input/output 0. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT MPIO1 107 I/O Multi-purpose input/output 1. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. MPIO2 74 I/O Multi-purpose input/output 2. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. MPIO3 73 I/O Multi-purpose input/output 3. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. MPIO4 68 I/O Multi-purpose input/output 4. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. MPIO5 67 I/O Multi-purpose input/output 5. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. MPIO6 66 I/O Multi-purpose input/output 6. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. MPIO7 65 I/O Multi-purpose input/output 7. The function of this pin is defined thru the Configuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT. EECK 116 O Serial clock to EEPROM. An internal clock of CLK divide by 256 is used for reading the vendor and sub-vendor ID during power up or reset. However, it can be manually clocked thru the Configuration Register REGB. ANCILLARY SIGNALS 5 áç PCI BUS OCTAL UART XR17C158 REV. 1.1.3 Pin Description NAME PIN # TYPE DESCRIPTION EECS 115 O Chip select to a EEPROM device like 93C46. It is manually selectable thru the Configuration Register REGB. Requires a pull-up 4.7K ohm resistor for external sensing of EEPROM during power up. See DAN112 for further details. EEDI 114 O Write data to EEPROM device. It is manually accessible thru the Configuration Register REGB. EEDO 113 I Read data from EEPROM device. It is manually accessible thru the Configuration Register REGB. XTAL1 110 I Crystal or external clock input. XTAL2 109 O Crystal or buffered clock output. TMRCK 69 I 16-bit timer/counter external clock input. ENIR 70 I Infrared mode enable (active high). This pin is sampled during power up, following a hardware reset (RST#) or soft-reset (register RESET). It can be used to start up all 8 UARTs in the infrared mode. The sampled logic state is transferred to MCR bit-6 in the UART. TEST# 111 I Factory Test. Connect to VCC for normal operation. VCC 4,19,34,45,64, 90,112,137 +5V (PCI Compliance) or +3.3V supply with 5V input tolerant. GND 5,20,35,46,63, 89,136 Power supply common, ground. NOTE: Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain. 6 XR17C158 áç PCI BUS OCTAL UART REV. 1.1.3 FUNCTIONAL DESCRIPTION PCI Local Bus Configuration Space Registers The XR17C158 (158) integrates the functions of 8 enhanced 16550 UARTs with the PCI Local Bus interface and a non-volatile memory interface for PCI bus’s plug-and-play auto-configuration, a 16-bit timer/ counter, 8 multi-purpose inputs/outputs, and an onchip oscillator. The PCI local bus is a synchronous timing bus where all bus transactions are associated to the bus clock of up to 33MHz. The 158 supports 32-bit wide read and write data transfer operations including data burst mode through the PCI Local Bus interface. Read and write data operations may be in byte, word or double-word (DWORD) format. A single 32-bit interrupt status register provides interrupts status for all 8 UARTs, timer/counter, multipurpose inputs/outputs, and a special sleep wake up indicator. There are three sets of register in the device. First, the PCI local bus configuration registers for PCI auto configuration. A set of device configuration registers for overall control, 32-bit wide transmit and receive data transfer, and monitoring of the 8 UART channels. Lastly, each UART channel has its own 16550 UART compatible configuration register set for individual channel control, status, and byte wide data transfer. A set of PCI local bus configuration space register is provided. These registers provide the PCI local bus operating system with the card’s vendor ID, device ID, sub-vendor ID, product model number, and resources and capabilities. The PCI local bus operating system collects this data from all the cards on the bus during the auto configuration phase that follows immediately after a power up or system reset/reboot. After it has sorted out all devices on the bus, it defines and download the operating conditions to the cards. One of the definitions is the base address loaded into the Base Address Register (BAR) where the card will be operating in the PCI local bus memory space. EEPROM Interface An external 93C46 EEPROM is only used to store the vendor’s ID and model number, and the sub-vendor’s ID and product model number. This information is only used with the plug-and-play auto configuration of the PCI local bus. These data provide automatic hardware installation onto the PCI bus. The EEPROM interface consists of 4 signals, EEDI, EEDO, EECS, and EECK. The EEPROM is not needed when auto configuration is not required in the application. However, If your design requires non-volatile memory for other purpose. It is possible to store and retrieve data on the EEPROM through a special PCI device configuration register. See application note DAN112 for its programming details. Each UART has 64-byte FIFOs, automatic RTS/CTS or DTR/DSR hardware flow control with hysteresis control, automatic Xon/Xoff and special character software flow control, programmable transmit and receive FIFO trigger level, FIFO level counters, infrared encoder and decoder (IrDA ver. 1.0), programmable baud rate generator with a prescaler of 1X or 4X, and data rate up to 6.25 Mbps at 8X sampling clock. The XR17C158 bus timing and drive capability meets the PCI local bus specification revision 2.2 for 5 volt operation over the temperature range. Although it does not meet the 3.3V speed specification, it is capable of operating up to 22MHz with 5 volt tolerant inputs. The XR17C158 is available in a thin 144-pin TQFP (20x20x1.0mm) package in commercial and industrial temperature ranges. 1.0 XR17C158 REGISTERS The XR17C158 UART has three different sets of registers as shown in Figure 3. The PCI local bus configuration space registers are for plug-and-play autoconfiguration when connecting the device to a the PCI bus. This auto-configuration feature makes installation very easy into a PCI system and it is part of the PCI local bus specification. The second register set is the device configuration registers that are accessible directly from the PCI bus for programming general operating conditions of the device and monitoring the status of various functions. These registers are mapped into 4K of the PCI bus memory address space. These functions include all 8 channel UART’s interrupt control and status, 16-bit general purpose timer control and status, multipurpose inputs/outputs control and status, sleep mode, soft-reset, and device identification and revision. And lastly, each UART channel has its own set of internal UART configuration registers for its own operation control and status reporting. All 8 sets of channel registers are embedded inside the device configuration registers space, which provides faster access. The following paragraphs describe all 3 sets of registers in detail. PCI LOCAL BUS INTERFACE This is the host interface and it meets the PCI Local Bus Specification revision 2.2. The PCI local bus operations are synchronous meaning each transaction is associated to the bus clock. The XR17C158 can operate with the bus clock of up to a 33MHz. Data transfers operation can be formatted in 8-bit, 16-bit, 24-bit or 32-bit wide. With 32-bit data operations, it pushes the data transfer rate on the bus up to 132 MByte/sec. This increases the overall system’s communication performance up to 16 times better than the 8-bit ISA bus. See PCI local bus specification revision 2.2 for bus operation details. 7 áç PCI BUS OCTAL UART XR17C158 REV. 1.1.3 FIGURE 3. THE XR17C158 REGISTER SETS D evic e C onfig ur ation and U AR T [7:0] C onfig ur ation R eg is ter s ar e mapped on to the Bas e Addr es s R eg is ter ( BAR ) in a 4Kbyte of memor y addr es s s pac e PC I Loc al Bus C onfig ur ation Spac e R eg is ter s for Plug and- Play Auto C onfig ur ation C hannel 0 IN T , M PIO , T IM ER ,R EG Vendor and Sub- vendor ID and Pr oduc t M odel N umber in Exter nal EEPR O M 0 x0 0 0 0 0 x0 0 8 0 C hannel 0 C hannel 1 PC I Loc al Bus Inter fac e C hannel 2 C hannel 3 0 x0 2 0 0 0 x0 6 0 0 C hannel 4 C hannel 6 C hannel 7 C onfig ur ation R eg is ter s c hannel Inter r upts , M ultipur pos e I/O s , 16- bit T imer /C ounter , Sleep, R es et, D VID , D R EV 0 x0 4 0 0 0 x0 8 0 0 C hannel 5 D evic e 8 0 x0 A 0 0 U AR T [7:0] C onfig ur ation R eg is ter s 16550 C ompatible and EXAR Enhanc ed R eg is ter s 0x0C 00 0x0E00 0x0F F F 1.1 PCI LOCAL BUS CONFIGURATION SPACE REGISTERS The PCI local bus configuration space registers are responsible for setting up the device’s operating environment in the PCI local bus. The pre-defined operating parameters of the device is read by the PCI bus plug-and-play auto-configuration manager in the operating system. After the PCI bus has collected all data from every device/card on the bus, it defines and P CI RE G S -1 downloads the memory mapping information to each device/card about their individual operation memory address location and conditions. The operating memory mapped address location is downloaded into the Base Address Register (BAR) register, 0x10. The plug-and-play auto configuration feature is only available when an external 93C46 EEPROM is used. The EEPROM contains the device vendor and sub-vendor data required by the auto-configuration setup. TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS ADDRESS 0x00 0x04 TYPE 31:16 RWR1 Device ID (Exar device ID number) 0x0158 15:0 RWR1 Vendor ID (Exar) specified by PCISIG 0x13A8 31 30 29:28 RWC RWC RO Parity error detected. Cleared by writing a logic 1. System error detected. Cleared by writing a logic 1. Unused 27 R-Reset DESCRIPTION RESET VALUE (HEX) BITS 0000 Target Abort. Set whenever 158 terminates with a target abort. 0 26:25 RO DEVSEL# timing. 00 24 RO Unemployments bus master error reporting bit 0 23 RO Fast back to back transactions are supported 1 22:16 RO Reserved Status bits 15:9,7, 5,4,3,2 RO Command bits (reserved) 8 RWR 000 0000 SERR# driver enable. Logic 1=enable driver and 0=disable driver 8 0x0000 0 XR17C158 áç PCI BUS OCTAL UART REV. 1.1.3 TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS TYPE DESCRIPTION RESET VALUE (HEX) 6 RWR Parity error enable. Logic 1=respond to parity error and 0=ignore 0 1 RWR Command controls a device’s response to mem space accesses: 0=disable mem space accesses, 1=enable mem space accesses 0 0 RO Device’s response to I/O space accesses is disabled. (0 = disable I/O space accesses) 0 31:8 RO Class Code (Simple 550 Communication Controller). 0x070002 7:0 RO Revision ID (Exar device revision number) 0x01 31:24 RO BIST (Built-in Self Test) 0x00 23:16 RO Header Type (a single function device with one BAR) 0x00 15:8 RO Unimplemented Latency Timer (needed only for bus master) 0x00 ADDRESS 0x08 0x0C BITS 7:0 0x10 0x14 RO Unimplemented Cache Line Size 0x00 Memory Base Address Register (BAR) 0x00 RO Claims a 4K address space for the memory mapped UARTs 0x000 RO Unimplemented Base Address Register (returns zeros) 31:12 RWR 11:0 31:0 0x00000000 0x18h 31:0 RO Unimplemented Base Address Register (returns zeros) 0x00000000 0x1C 31:0 RO Unimplemented Base Address Register (returns zeros) 0x00000000 0x20 31:0 RO Unimplemented Base Address Register (returns zeros) 0x00000000 0x24 31:0 RO Unimplemented Base Address Register (returns zeros) 0x00000000 0x28 31:0 RO Reserved 0x00000000 0x2C 31:16 RWR Subsystem ID (write from external EEPROM by customer) 0x0000 15:0 RWR1 Subsystem Vendor ID (write from external EEPROM by customer) 0x0000 0x30 31:0 RO Expansion ROM Base Address (Unimplemented) 0x00000000 0x34 31:0 RO Reserved (returns zeros) 0x00000000 0x38 31:0 RO Reserved (returns zeros) 0x00000000 0x3C 31:24 RO Unimplemented MAXLAT 0x00 23:16 RO Unimplemented MINGNT 0x00 15:8 RO Interrupt Pin, use INTA#. 0x01 7:0 RWR Interrupt Line. 0xXX 1 NOTE: RWR1=Read/Write from external EEPROM. RWR=Read/Write from AD[31:0]. RO= Read Only. RWC=Read/Write-Clear. set. These registers control or report on all 8 channel UARTs functions that include interrupt control and status, 16-bit general purpose timer control and status, multipurpose inputs/outputs control and status, sleep mode control, soft-reset control, and device identification and revision, and others. 1.2 DEVICE CONFIGURATION REGISTER SET The device configuration registers and a special way to access each of the UART’s transmit and receive data FIFOs are accessible directly from the PCI data bus. This provides easy programming of general operating parameters to the 158 UART and for monitoring the status of various functions. The registers occupy 4K of PCI bus memory address space. These addresses are offset onto the basic memory address, a value loaded into the Memory Base Address Register (BAR) in the PCI local bus configuration register The registers set is mapped into 8 address blocks where each UART channel occupies 512 bytes memory space for its own 16550 compatible configuration registers. The device configuration and control registers are embedded inside the UART channel zero’s address space between 0x0080 to 0x0093. All these registers can be accessed in 8, 16, 24 or 32 bit width depending on the starting address given by the host 9 áç PCI BUS OCTAL UART XR17C158 REV. 1.1.3 or dword. One special case applies to the receive data unloading when reading the receive data together with its LSR register content. The host must read them in 16 or 32 bits format in order to maintain integrity of the data byte with its associated error flags. at beginning of the bus cycle. Transmit and receive data may be loaded or unloaded in 8, 16, 24 or 32 bit format to the register’s address. Every time a read or write operation is made to the transmit or receive register, its FIFO data pointer is automatically bumped to the next sequential data location either in byte, word TABLE 2: XR17C158 DEVICE CONFIGURATION REGISTERS OFFSET ADDRESS MEMORY SPACE READ/WRITE DATA WIDTH (Table 10 & 11) 8/16/24/32 (Table 3) 8/16/24/32 COMMENT 0x000 - 0x00F UART channel 0 Regs 0x010 - 0x07F Reserved First 8 regs are 16550 compatible 0x080 - 0x093 DEVICE CONFIG. REGISTERS 0x094 - 0x0FF Reserved 0x100 UART 0 – Read FIFO Read-Only 8/16/24/32 64 bytes of RX FIFO data 0x100 UART 0 – Write FIFO Write-Only 8/16/24/32 64 bytes of TX FIFO data 0x140 - 0x17F Reserved 0x180 UART 0 – Read FIFO with errors Read-Only 16/32 64 bytes of RX FIFO data + LSR 0x200 - 0x20F UART channel 1 Regs (Table 10 & 11) 8/16//24/32 First 8 regs are 16550 compatible 0x210 - 0x2FF Reserved 0x300 UART 1 – Read FIFO Read-Only 8/16/24/32 64 bytes of RX FIFO data 0x300 UART 1 – Write FIFO Write-Only 8/16/24/32 64 bytes of TX FIFO data 0x340 - 0x37F Reserved 0x380 UART 1 – Read FIFO with errors Read-Only 16/32 64 bytes of RX FIFO data + LSR 0x400 - 0x40F UART channel 2 Regs (Table 10 & 11) 8/16/24/32 First 8 regs are 16550 compatible d 0x410 - 0x4FF Reserved 0x500 UART 2 – Read FIFO Read-Only 8/16/24/32 64 bytes of RX FIFO data 0x500 UART 2 – Write FIFO Write-Only 8/16/24/32 64 bytes of TX FIFO data 0x540 - 0x57F Reserved 0x580 UART 2 – Read FIFO with errors Read-Only 16/32 64 bytes of RX FIFO data + LSR 0x600 - 0x60F UART channel 3 Regs (Table 10 & 11) 8/16/24/32 First 8 regs are 16550 compatible 0x610 - 0x6FF Reserved 0x700 UART 3 – Read FIFO Read-Only 8/16/24/32 64 bytes of RX FIFO data 0x700 UART 3 – Write FIFO Write-Only 8/16/24/32 64 bytes of TX FIFO data 0x740 - 0x77F Reserved 0x780 UART 3 – Read FIFO with errors Read-Only 16/32 64 bytes of RX FIFO data + LSR 0x800 - 0x80F UART channel 4 Regs (Table 10 & 11) 8/16/24/32 First 8 regs are 16550 compatible 0x810 - 0x8FF Reserved 10 XR17C158 áç PCI BUS OCTAL UART REV. 1.1.3 TABLE 2: XR17C158 DEVICE CONFIGURATION REGISTERS OFFSET ADDRESS MEMORY SPACE READ/WRITE DATA WIDTH COMMENT 0x900 UART 4 – Read FIFO Read-Only 8/16/24/32 64 bytes of RX FIFO data 0x900 UART 4 – Write FIFO Write-Only 8/16/24/32 64 bytes of TX FIFO data 0x940 - 0x97F Reserved 0x980 UART 4 – Read FIFO with errors Read-Only 16/32 64 bytes of RX FIFO data + LSR 0xA00 - 0xA0F UART channel 5 Regs (Table 10 & 11) 8/16/24/32 First 8 regs are 16550 compatible 0xA10 - 0xAFF Reserved 0xB00 UART 5 – Read FIFO Read-Only 8/16/24/32 64 bytes of RX FIFO data 0xB00 UART 5 – Write FIFO Write-Only 8/16/24/32 64 bytes of TX FIFO data 0xB40 - 0xB7F Reserved 0xB80 UART 5 – Read FIFO with errors Read-Only 16/32 64 bytes of RX FIFO data + LSR 0xC00 - 0xC0F UART channel 6 Regs (Table 10 & 11) 8/16/24/32 First 8 regs are 16550 compatible 0xC10 - 0xCFF Reserved 0xD00 UART 6 – Read FIFO Read-Only 8/16/24/32 64 bytes of RX FIFO data 0xD00 UART 6 – Write FIFO Write-Only 8/16/24/32 64 bytes of TX FIFO data 0xD40 - 0xD7F Reserved 0xD80 UART 6 – Read FIFO with errors Read-Only 16/32 64 bytes of RX FIFO data + LSR 0xE00 - 0xE0F UART channel 7 Regs (Table 10 & 11) 8/16/24/32 First 8 regs are 16550 compatible 0xE10 - 0xEFF Reserved 0xF00 UART 7 – Read FIFO Read-Only 8/16/24/32 64 bytes of RX FIFO data 0xF00 UART 7 – Write FIFO Write-Only 8/16/24/32 64 bytes of TX FIFO data 0xF40 - 0xF7F Reserved 0xF80 UART 7 – Read FIFO with errors Read-Only 16/32 ite 11 64 bytes of RX FIFO data + LSR áç PCI BUS OCTAL UART XR17C158 REV. 1.1.3 TABLE 3: DEVICE CONFIGURATION REGISTERS SHOWN IN BYTE ALIGNMENT ADDRESS [A7:A0] REGISTER Ox080 INT0 [7:0] Read-only Interrupt [7:0] Bits 7-0 = 0x00 Ox081 INT1 [15:8] Read-only Bits 7-0 = 0x00 Ox082 INT2 [23:16] Read-only Bits 7-0 = 0x00 Ox083 INT3 [31:24] Read-only Bits 7-0 = 0x00 Ox084 TIMERCNTL Read/Write Timer Control Bits 7-0 = 0x00 Ox085 TIMER Reserved Bits 7-0 = 0x00 READ/WRITE COMMENT RESET STATE Ox086 TIMERLSB Read/Write Timer LSB Bits 7-0 = 0x00 Ox087 TIMERMSB Read/Write Timer MSB Bits 7-0 = 0x00 Ox088 8XMODE Read/Write Bits 7-0 = 0x00 Ox089 REGA Reserved Bits 7-0 = 0x00 Ox08A RESET Write-only Self clear bits after executing Reset Bits 7-0 = 0x00 Ox08B0 SLEEP Read/Write Sleep mode Bits 7-0 = 0x00 Ox08C DREV Read-only Device revision Bits 7-0 = 0x02 Ox08D DVID Read-only Device identification Bits 7-0 = 0x28 Ox08E REGB Write-only Bits 7-0 = 0x00 Ox08F MPIOINT Read/Write MPIO interrupt mask Bits 7-0 = 0x00 Ox090 MPIOLVL Read/Write MPIO level control Bits 7-0 = 0x00 Ox091 MPIO3T Read/Write MPIO output control Bits 7-0 = 0x00 Ox092 MPIOINV Read/Write MPIO input polarity select Bits 7-0 = 0x00 Ox093 MPIOSEL Read/Write MPIO select Bits 7-0 = 0xFF TABLE 4: DEVICE CONFIGURATION REGISTERS SHOWN IN DWORD ALIGNMENT ADDRESS REGISTER BYTE 3 [31:24] BYTE 2 [23:16] BYTE 1 [15:8] BYTE 0 [7:0] 0x080-083 INTERRUPT (read-only) INT3 INT2[ INT1 INT0 0x084-087 TIMER (read/write) TIMERMSB TIMERLSB TIMER (reserved) TIMERCNTL 0x088-08B ANCILLARY1 (read/write) SLEEP RESET REGA (reserved) 8XMODE 0x08C-08F ANCILLARY2 (read-only) MPIOINT REGB DVID DREV 0x090-093 MPIO (read/write) MPIOSEL MPIOINV MPIO3T MPIOLVL 1.2.1 The Interrupt Status Register The XR17C158 has a 32-bit wide register [INT0, INT1, INT2 and INT3] to provide interrupt information and supports two interrupt schemes. The first scheme is an 8-bitan 8-bit indicator representing all 8 channels with each bit representing each channel from 0 to 7. This permits the interrupt routine to quick- ly vector and serve that UART channel and determine the source(s) in each individual routines. INT0 bit-0 represents the interrupt status for UART channel 0 when its transmitter, receiver, line status, or modem port status requires service. Other bits in the INT0 register provide indication for the other channels with bit-7 representing UART channel 7 respectively. 12 XR17C158 áç PCI BUS OCTAL UART REV. 1.1.3 bit-7 indicates channel 7. Logic one indicates the channel N [7:0] has called for service. The interrupt bit clears after reading the appropriate register of the interrupting channel register, see Interrupt Clearing section. The second scheme provides detail about the source of the interrupts for each UART channel. All the interrupts are encoded into a 3-bit code. This 3-bit code represents 7 interrupts corresponding to individual UART’s transmitter, receiver, line status, modem port status. INT1, INT2 and INT3 registers provide the 24bit interrupt status for all 8 channels. Bits 8,9 and 10 representing channel 0 and bits 29, 30 and 31 representing channel 7 respectively. All 8 channel interrupts status are available with a single DWORD read operation. This feature allows the host quickly vectors and serves the interrupts, reducing service interval, hence, reduce host bandwidth requirement. The INT0 register provides individual status for each channel IN T0 R egister Ind ivid ua l U A R T C h an ne l Interrup t S tatus C h-7 C h-6 C h-5 C h-4 C h-3 C h-2 C h-1 C h-0 B it-7 B it-6 GLOBAL INTERRUPT REGISTER (DWORD) fault 0x00-00-00-00] INT3 [31:24] INT2 [23:16] INT1 [15:87] B it-5 B it-4 B it-3 B it-2 B it-1 B it-0 [deINT3, INT2 and INT1 [32:8] Twenty four bit encoded interrupt indicator. Each channel’s interrupt is encoded into 3 bits for receive, transmit, and status. Bit [10:8] represent channel 0 and go up to channel 7 with bits [31:29]. The 3 bit encoding and their priority order are shown below in Table 5. The Timer and MPIO interrupts are for the device and therefore they exist within channel 0 space and not in other channel interrupt. INT0 [7:0] All bits start up zero. A special interrupt condition is generated by the 158 upon awakening from sleep after all 8 channels were put to sleep mode earlier. Figure 4 shows the 4-byte interrupt register and its make up. INT0 [7:0] Channel Interrupt Indicator. Each bit gives an indication of the channel that has requested for service. Bit-0 represents channel 0 and . FIGURE 4. THE GLOBAL INTERRUPT REGISTER, INT0, INT1, INT2 AND INT3 Interrupt Registers, INT0, INT1, INT2 and INT3 INT3 Register R svd B it N +2 B it N +1 INT2 Register R svd B it N B it N +2 B it N +1 R svd B it N B it N +2 B it N +1 C ha n n el-3 R svd B it N B it N +2 B it N +1 INT1 Register B it N B it N +2 B it N +1 C ha n n el-2 B it N B it N +2 B it N +1 C ha n n el-1 B it N B it N +2 B it N +1 C ha n n el-0 B it N B it N +2 B it N +1 B it N INT0 Register R svd B it-7 13 R svd R svd B it-6 B it-5 R svd C h-3 C h-2 C h-1 C h-0 B it-4 B it-3 B it-2 B it-1 B it-0 áç PCI BUS OCTAL UART XR17C158 REV. 1.1.3 TABLE 5: UART CHANNEL [7:0] INTERRUPT SOURCE ENCODING PRIORITY BIT[N+2] BIT[N+1] BIT[N] INTERRUPT SOURCE(S) x 0 0 0 None 1 0 0 1 RXRDY and RX Line Status (logic OR of LSR[4:1]) 2 0 1 0 RXRDY Time-out 3 0 1 1 TXRDY, THR or TSR (auto RS485 mode) empty 4 1 0 0 MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon det. or special char. detected 5 1 0 1 Reserved. 6 1 1 0 MPIO pin(s). Available only within channel 0, reserved in other channels. 7 1 1 1 TIMER Time-out. Available only within channel 0, reserved in other channels. TABLE 6: UART CHANNEL [7:0] INTERRUPT CLEARING: RXRDY and RXRDY Time-out is clear by reading data in the RX FIFO until it falls below the trigger level. RX Line Status interrupt clears after reading the LSR register. TXRDY interrupt clears after reading ISR register that is in the UART channel register set. Modem Status Register interrupt clears after reading MSR register that is in the UART channel register set. RTS/CTS or DTR/DSR delta interrupt clears after reading MSR register that is in the UART channel register set. Xoff/Xon delta and special character detect interrupt clears after reading the ISR register that is in the UART channel register set. TIMER Time-out interrupt clears after reading the TIMERCNTL register that is in the Device Configuration register set. MPIO interrupt clears after reading the MPIOLVL register that is in the Device Configuration register set. 1.2.2 General Purpose 16-bit Timer/Counter. [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (DEFAULT 0XXX-XX-00-00) A 16-bit down-count timer for general purpose timer or counter. Its clock source may be selected from internal crystal oscillator or externally on pin TMRCK. The timer can be set to be a single-shot for a onetime event or re-triggerable for continue interval. An interrupt may be generated in the INT Register when the timer times out. It is controlled through 4 configuration registers [TIMERCNTL, TIMER, TIMELSB, TIMERMSB]. These registers provide start/stop and re-triggerable or one-shot operation. The time-out output of the Timer can be set to generate an interrupt for system or event alarm. FIGURE 5. TIMER/COUNTER CIRCUIT. TIMERMSB and TIMERLSB (16-bit Value) TMRCK OSC. CLOCK TIMERCNTL [3] TIMERCNTL [1] TIMERCNTL [2] TIMERCNTL [0] 1 0 Clock Select Time-out 16-Bit Timer/Counter 1 0 Timer Interrupt, Ch-0 INT=7 No Interrupt Re-trigger 0 1 Start/Stop Single/Re-triggerable Single-shot 1 0 MPIO[0] MPIOLVL[0] Timer Interrupt Enable TIMERCNTL [4] 14 XR17C158 áç PCI BUS OCTAL UART REV. 1.1.3 TABLE 7: TIMER CONTROL REGISTERS TIMERCNTL [0] Logic zero (default) disables Timer-Counter interrupt and logic one enables the interrupt, reading the TIMERCNTL clears the interrupt. TIMERCNLT [1] Logic zero (default) stops/pauses the timer and logic one starts/re-starts the timer/counter. TIMERCNTL [2] Logic zero (default) selects re-trigger timer function and logic one selects one-shot (timer function. TIMERCNTL [3] Logic zero (default) selects internal and logic one selects external clock to the timer/counter. TIMERCNTL [4] Routes the Timer-Counter interrupt to MPIO[0] if MPIOSEL[0]=0 for external event control. TIMERCNTL [7:5] Reserved (defaults to zero) TIM E R C N TL R egister B it-7 B it-6 R svd R svd B it-5 R svd B it-4 B it-3 B it-2 B it-1 M P IO [0 ] C lo c k S in g le / C o n tro l S e le c t R e -trig g e r TIMER [15:8] (default 0x00) S ta rt/ S to p B it-0 IN T E n a b le TIMERLSB with most-significant-bit being bit [7] in TIMERMSB. Notice that these registers do not hold the current counter value when read. Reading the TIMERCNTL register will clear its interrupt. Default value is zero (timer disabled) upon powerup and reset. Reserved. TIMERMSB [31:24] and TIMERLSB [23:16] TIMERMSB and TIMERLSB form a 16-bit value. The least-significant bit of the timer is being bit [0] of the 1 6 -B it T im e r/C o u n te r P ro g ra m m a b le R e g iste rs TIM E RM SB Reg ister B it-15 B it-14 B it-13 B it-1 2 B it-11 B it-10 TIM E RLS B Register B it-7 B it-9 B it-8 1.2.3 8XMODE [7:0] (default 0x00) Each bit selects 8X or 16X sampling rate for that UART channel, bit-0 is channel 0. Logic 0 (default) selects normal 16X sampling with logic one selects 8X sampling rate. Transmit and receive data rates will double by selecting 8X. B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0 1.2.5 RESET [23:16] (default 0x00) The 8-bit Reset register [RESET] provides the software with the ability to reset the UART(s) when there is a need. Each bit is self-resetting after it is written a logic 1 to perform a reset to that channel. All registers in that channel will be reset to the default condition, see Table 19 for details. Bit-0 =1 resets UART channel 0 with bit-7=1 resets channel 7. 8XMODE Register Individual UART Channel 8X Clock Mode Enabl e Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 RESET Register Individual UART Channel Reset Enable Ch-7 Ch-6 Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0 Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 Ch-7 Ch-6 Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0 1.2.4 REGA [15:8] is reserved (default 0x00) REGA [15:8] IS RESERVED (default 0x00) 15 áç PCI BUS OCTAL UART XR17C158 REV. 1.1.3 REGB [23:16] (default 0x00) 1.2.6 SLEEP [31:24](default 0x00) The 8-bit Sleep register enables each UART separately to enter Sleep mode. Sleep mode reduces power consumption when the system needs to put the UART(s) to idle. The UART enters sleep mode when there is no interrupt pending. When all 8 UARTs are put to sleep, the on-chip oscillator shuts off to further conserve power. In this case, the octal UART is awaken by any of the UART channel on from a receive data byte or a change on the serial port. The UART is ready after 32 crystal clocks to ensure full functionality. Also, a special interrupt is generated with an indication of no pending interrupt. Logic 0 (default) is disable and logic 1 is enable to sleep mode. REGB register provides a control for simultaneous write to all 8 UARTs configuration register or individually. This is very useful for device initialization in the power up and reset routines. Also, the register provides a facility to interface to the non-volatile memory device such as a 93C46 EEPROM. In embedded applications, the user can use this facility to store proprietary data. 1.2.8 REGB Register REGB[16] (Read/Write) Logic 0 (default) write to each UART configuration registers individually. Logic 1 enables simultaneous write to all 8 UARTs configuration register. S LE EP Register Individual U AR T C hannel S leep Enable C h-7 C h-6 C h-5 C h-4 C h-3 C h-2 C h-1 C h-0 B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0 1.2.7 Device Identification and Revision There are 2 internal registers that provide device identification and revision, DVID and DREV registers. The 8-bit content in the DVID register provides device identification. A return value of 0x28 from this register indicates the device is a XR17C158. The DREV register returns an 8-bit value of 0x01 for revision A with 0x02 equals to revision B and so forth. This information is very useful to the software driver for identifying which device it is communicating with and to keep up with revision changes. REGB[19:17] Reserved REGB[20] (Write-Only) Control the EECK, clock, output (pin 116) on the EEPROM interface. REGB[21] (Write-Only) Control the EECS, chips select, output (pin 115) to the EEPROM device. REGB[22] (Write-Only) EEDI (pin 114) data input. Write data to the EEPROM device. REGB[23] (Read-Only) EEDO (pin 113) data output. Read data from the EEPROM device. NOTE: REGB[22:20] is Write-Only. A logic 0 will be given when read. 1.2.9 Multi-Purpose Inputs and Outputs The 158 provides 8 multi-purpose inputs/outputs [MPIO7:0] for general use. Each pin can be programmed to be an input or output function. The input logic state can be set for normal or inverted level, and optionally set to generate an interrupt. The outputs can be set to be normal logic 1 or 0 state, or 3-state. Their functions and definitions are programmed through 5 registers: MPIOINT, MPIOLVL, MPIO3T, MPIOINV and MPIOSEL. If all 8 pins are set for inputs, all 8 interrupts would be Or’ed together. The Or’ed interrupt is reported in the channel 0 UART interrupt status, see Interrupt Status Register. The pins may also be programmed to be outputs and to the 3state condition for signal sharing. DVID [15:8] default 0x28) Device identification for the type of UART. The upper nibble indicates it is a XR17Cxxx series with lower nibble indicating the number of channels. Examples: XR17C158 = 0x28 XR17C154 = 0x24 XR17C152 = 0x22 DREV [7:0] (default (0x01) 1.2.10 MPIO REGISTER Bit 7 represents MPIO7 pin and bit 0 represents MPIO0 pin. There are 5 registers that select, control and monitor the 8 multipurpose inputs and outputs. Figure 6 shows the internal circuitry. Revision number of the XR17C158. A 0x01 represents "revision-A" with 0x02 for rev-B and so forth. 16 XR17C158 áç PCI BUS OCTAL UART REV. 1.1.3 FIGURE 6. MULTIPURPOSE INPUT/OUTPUT INTERNAL CIRCUIT M PIO IN T [7:0] IN T AND R ising Edge D etection AND 1 M PIO Pin [7:0] M PIO LVL [7:0] R ea d Inp ut L evel 0 M PIO IN V [7:0] (Inp ut In versio n En ab le =1 ) M PIO LVL [7:0] (O utp ut L evel) M PIO 3T [7:0] (3-sta te En ab le = 1) OR M PIO SE L [7:0] (S elect Inpu t=1 , O u tp ut=0 ) M P IO C KT MPIOINT [7:0] (default 0x00) MPIOLVL [7:0] (default 0x00) Enable multipurpose input pin interrupt. If the pin is selected by MPIOSEL as input then bit-0 enables input pin 0 for interrupt, and bit-7 enables input pin 7. No interrupt is enable if the pin is selected to be an output. The interrupt is edge sensing and determined by MPIOINV and MPIOLVL registers. The MPIO interrupt clears after a read to register MPIOLVL. The combination of MPIOLVL and MPIOINV determines the interrupt being active low or active high, it’s level trigger. Logic 0 (default) disables the pin’s interrupt and logic 1 enables it. Output pin level control and input level status. The status of the input pin(s) is read on this register and output pins are controlled on this register. A logic 0 (default) sets the output to low and a logic 1 sets the output pin to high. The MPIO interrupt will clear upon reading this register. M PIO INT Register M ultipurpose Input/O utput Interrupt E nable M P IO 7 M P IO 6 M P IO 5 M P IO 4 M P IO 3 M P IO 2 M P IO 1 M P IO 0 M P IO LVL Register M ultipurpose O utput Level C ontrol B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0 B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0 MPIO3T [7:0] (default 0x00) M P IO 7 M P IO 6 M P IO 5 M P IO 4 M P IO 3 M P IO 2 M P IO 1 M P IO 0 Output pin tri-state control. A logic 0 (default) sets the output to active level per register MPIOBIT settling, a logic 1 sets the output pin to tri-state. 17 áç PCI BUS OCTAL UART XR17C158 REV. 1.1.3 FIGURE 7. TYPICAL OSCILLATOR CONNECTIONS M PIO 3T Register M ultipurpose O utput 3-state E n able B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0 R =3 0 0 K to 40 0 K M P IO 7 M P IO 6 M P IO 5 M P IO 4 M P IO 3 M P IO 2 M P IO 1 M P IO 0 MPIOINV [7:0] (default 0x00) XTAL1 Input inversion control. A logic 0 (default) does not invert the input pin logic. A logic 1 inverts the input logic level. C1 2 2-4 7 pF 1 4.7 45 6 MHz XTAL2 C2 2 2-4 7 pF M PIO INV Register M ultipurpose Input S ignal Inversion E nable B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0 3.0 TRANSMIT AND RECEIVE DATA There are two methods to load transmit data and unload receive data from each UART channel. First, there is a transmit data register and receive data register for each UART channel in the device configuration register set to ease programming. These registers support 8, 16, 24 and 32 bits wide format. In the 32-bit format, it increases the data transfer rate on the PCI bus. Additionally, a special register location provides receive data byte with its associated error flags. This is a 16-bit or 32-bit read operation where the Line Status Register (LSR) content in the UART channel register is paired along with the data byte. This operation further facilitates data unloading with the error flags without having to read the LSR register separately. Furthermore, the XR17C158 supports PCI burst mode for read/write operation of up to 64 bytes of data. M P IO 7 M P IO 6 M P IO 5 M P IO 4 M P IO 3 M P IO 2 M P IO 1 M P IO 0 MPIOSEL [7:0] (default 0xFF) Multipurpose input/output pin select. This register defines the functions of the pins. A logic 1 (default) defines the pin for input and a logic "0" for output. MPIOSEL Register Multipurpose Input/Output Selection Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 MPIO7 MPIO6 MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0 2.0 CRYSTAL OSCILLATOR / BUFFER The 158 includes an on-chip oscillator (XTAL1 and XTAL2). The crystal oscillator provides the system clock to the Baud Rate Generators (BRG) in each of the 8 UARTs, the 16-bit general purpose timer/ counter and internal logics. XTAL1 is the input to the oscillator or external clock buffer input with XTAL2 pin being the output. See Programmable Baud Rate Generator in the UART section for programming details. The second method is through each UART channel’s transmit holding register (THR) and receive holding register (RHR). The THR and RHR registers are 16550 compatible so their access is limited to 8-bit format. The software driver must separately read the LSR content for the associated error flags before reading the data byte. 3.1 FIFO DATA LOADING AND UNLOADING THROUGH THE DEVICE CONFIGURATION REGISTERS IN 32-BIT FORMAT. The transmit and receive data registers are defined for channel 0 to channel 7 with each channel having it’s own address as shown in Table 2 for faster loading and unloading. The following paragraphs illustrate the receive and transmit data registers in more detail. The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant with 10-22 pF capacitance load, 100ppm) connected externally between the XTAL1 and XTAL2 pins (see Figure 7). Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal 8 baud rate generators for standard or custom rates. Typically, the oscillator connections are shown in Figure 7. For further reading on oscillator circuit please see application note DAN108 on EXAR’s web site. Each Channel Normal Receive Data FIFO Address for channels 0 to 7 are at 0x0100, 0x0300, 0x0500, 0x0700, 0x0900, 0x0B000, 0x0D00 and 0x0F00. 18 XR17C158 áç PCI BUS OCTAL UART REV. 1.1.3 READ RX FIFO, WITH NO ERRORS BYTE 3 BYTE 2 BYTE 1 BYTE 0 Read n+0 to n+3 FIFO Data n+3 FIFO Data n+2 FIFO Data n+1 FIFO Data n+0 Read n+4 to n+7 FIFO Data n+7 FIFO Data n+6 FIFO Data n+5 FIFO Data n+4 Etc. Channel 0 to 7 ReceiveData in 32-bit alignment through the Configuration Register Address 0x0100, 0x0300, 0x0500, 0x0700, 0x0900, 0x0B00, 0x0D00 and 0x0F00 Receive Data Byte n+3 B7 B6 B5 B4 B3 B2 B1 Receive Data Byte n+2 B0 B7 B6 B5 B4 B3 B2 B1 Receive Data Byte n+1 B0 B7 B6 B5 B4 B3 B2 B1 Receive Data Byte n+0 B0 B7 B6 B5 B4 B3 B2 PCI Bus Data Bit-31 B1 B0 PCI Bus Data Bit-0 Each Channel Normal Transmit Data FIFO Address for Channel 0 to 7 are at 0x0100, 0x0300, 0x0500, 0x0700, 0x0900, 0x0B00, 0x0D00 and 0x0F00. WRITE TX FIFO BYTE 3 BYTE 2 BYTE 1 BYTE 0 Write n+0 to n+3 FIFO Data n+3 FIFO Data n+2 FIFO Data n+1 FIFO Data n+0 Write n+4 to n+7 FIFO Data n+7 FIFO Data n+6 FIFO Data n+5 FIFO Data n+4 Etc. Channel 0 to 7 Transmit Data in 32-bit alignment through the Configuration Register Address 0x0100, 0x0300, 0x0500, 0x0700, 0x0900, 0x0B00, 0x0D00 and 0x0F00 Transmit Data Byte n+3 B7 B6 B5 B4 B3 B2 B1 Transmit Data Byte n+2 B0 B7 B6 B5 B4 B3 B2 B1 Transmit Data Byte n+1 B0 B7 B6 B5 B4 B3 B2 B1 Transmit Data Byte n+0 B0 B7 PCI Bus Data Bit-31 B6 B5 B4 B3 B2 B1 PCI Bus Data Bit-0 format to maintain data integrity. Please see the programming examples on how to use the Special Recive FIFO feature on page 41. Each Channel Special Receive FIFO Data Address for channel 0 to 7 are at 0x0180 0x-380, 0x0580, 0x0780, 0x0980, 0x0B80, 0x0D80 and 0x0F80. The Status and Data bytes must be read in 16 or 32 bits READ RX FIFO, ERRORS BYTE 3 BYTE 2 BYTE 1 BYTE 0 Read n+0 to n+1 FIFO Data n+1 LSR n+1 FIFO Data n+0 LSR n+0 Read n+2 to n+3 FIFO Data n+3 LSR n+3 FIFO Data n+2 LSR n+2 WITH LSR B0 Etc 19 áç XR17C158 PCI BUS OCTAL UART REV. 1.1.3 Channel 0 to 7 Receive Data with Line Status Register in a 32-bit alignment through the Configuration Register Address 0x0180, 0x0380, 0x0580, 0x0780, 0x0980, 0x0B80, 0x0D80 and 0x0F80 Receive Data Byte n+1 B7 B6 B5 B4 B3 B2 B1 Line Status Register n+1 B0 B7 B6 B5 B4 B3 B2 B1 Receive Data Byte n+0 B0 B7 B6 B5 B4 B3 B2 B1 Line Status Register n+0 B0 B7 B6 B5 B4 B3 B2 PCI Bus Data Bit-31 B1 B0 PCI Bus Data Bit-0 3.2 FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR AND RHR IN 8-BIT FORMAT. The THR and RHR register address for channel 0 to channel 7 is shown in Table 8 below. The THR and RHR for each channel 0 to 7 are located sequentially at address 0x0000, 0x0200, 0x0400, 0x0600, 0x0800, 0x0A000, 0x0C00 and 0x0E00. Transmit data byte is loaded to the THR when writing to that address and receive data is unloaded from the RHR register when reading that address. Both THR and RHR registers are 16C550 compatible in 8-bit format, so each bus operation can only write or read in bytes. TABLE 8: TRANSMIT AND RECEIVE DATA REGISTER IN BYTE FORMAT, 16C550 COMPATIBLE TH R and R H R A dd ress Locations F or C H0 to C H 7 (16C 550 Co m patib le) C H 0 0 x0 0 0 W rite T H R B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0 C H 0 0 x0 0 0 R e a d R H R B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0 C H 1 0 x2 0 0 W rite T H R B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0 C H 1 0 x2 0 0 R e a d R H R B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0 C H 2 0 x4 0 0 W rite T H R B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0 C H 2 0 x4 0 0 R e a d R H R B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0 C H 3 0 x6 0 0 W rite T H R B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0 C H 3 0 x6 0 0 R e a d R H R B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0 C H 4 0 x8 0 0 W rite T H R B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0 C H 4 0 x8 0 0 R e a d R H R B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0 C H 5 0 xA 0 0 W rite T H R B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0 C H 5 0 xA 0 0 R e a d R H R B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0 C H 6 0 xC 0 0 W rite T H R B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0 C H 6 0 xC 0 0 R e a d R H R B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0 C H 7 0 xE 0 0 W rite T H R B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0 C H 7 0 xE 0 0 R e a d R H R B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0 TH R R H R 1 4.0 UART There are 8 UARTs [channel 7:0] in the 158. Each has its own 64-byte of transmit and receive FIFO, a set of 16550 compatible control and status registers, and a baud rate generator for individual channel data rate setting. Eight additional registers per UART were added for the EXAR enhanced features. 4.1 PROGRAMMABLE BAUD RATE GENERATOR Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to 20 XR17C158 áç PCI BUS OCTAL UART REV. 1.1.3 is used by the transmitter for data bit shifting and receiver for data sampling. The BRG divisor (DLL and DLM registers) defaults to a random value upon power up. Therefore, the BRG must be programmed during initialization to the operating data rate. divide the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG further divides this clock by a programmable divisor between 1 and (216 -1) to obtain a 16X or 8X sampling clock of the serial data rate. The sampling clock FIGURE 8. BAUD RATE GENERATOR T o O ther C hannels D LL and D LM R egisters Prescaler D ivide by 1 M C R Bit-7=0 (default) C rystal O sc/ Buffer XT A L1 XT A L2 Baud R ate G enerator Logic Prescaler D ivide by 4 16X or 8X Sam pling R ate C lock to T ransm itter and R eceiver M C R Bit-7=1 clock at 16X clock rate. At 8X sampling rate, these data rates would double. When using a non-standard data rate crystal or external clock, the divisor value can be calculated with the following equation(s). Programming the Baud Rate Generator Registers DLM and DLL provides the capability for selecting the operating data rate. Table 9 shows the standard data rates available with a 14.7456 MHz crystal or external divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16), WITH 8XMODE [7:0] IS 0 divisor (decimal) = (XTAL1 clock frequency / prescaler / (serial data rate x 8), WITH 8XMODE [7:0] IS 1 TABLE 9: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING OUTPUT Data Rate OUTPUT Data Rate DIVISOR FOR 16x DIVISOR FOR 16x DLM PROGRAM DLL PROGRAM DATA RATE MCR Bit-7=1 MCR Bit-7=0 Clock (Decimal) Clock (HEX) VALUE (HEX) VALUE (HEX) ERROR (%) 100 400 2304 900 09 00 0 600 2400 384 180 01 80 0 1200 4800 192 C0 00 C0 0 2400 9600 96 60 00 60 0 4800 19.2k 48 30 00 30 0 9600 38.4k 24 18 00 18 0 19.2k 76.8k 12 0C 00 0C 0 38.4k 153.6k 6 06 00 06 0 57.6k 230.4k 4 04 00 04 0 115.2k 460.8k 2 02 00 02 0 230.4k 921.6k 1 01 00 01 0 21 áç PCI BUS OCTAL UART XR17C158 REV. 1.1.3 4.2 AUTOMATIC HARDWARE (RTS/CTS OR DTR/ DSR) FLOW CONTROL OPERATION Automatic hardware or RTS/DTR and CTS/DSR flow control is used to prevent data overrun to the local receiver FIFO and remote receiver FIFO. The RTS#/ DTR# output pin is used to request remote unit to suspend/restart data transmission while the CTS#/ DSR# input pin is monitored to suspend/restart local transmitter. The auto RTS/DTR and auto CTS/DSR flow control features are individually selected to fit specific application requirement and enabled through EFR bit-6 and 7 and MCR bit-2 for either RTS/CTS or DTR/DSR control signals. The auto RTS/DTR function must be started by asserting RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after it is enabled. Figure 9 below explains how it works. Two interrupts associated with RTS/DTR and CTS/ DSR flow control have been added to give indication when RTS/DTR# pin or CTS/DSR# pin is de-asserted during operation. The RTS/DTR and CTS/DSR interrupts must be first enabled by EFR bit-4, and then enabled individually by IER bit-6 and 7, and chosen with MCR bit-2. Automatic hardware flow control is selected by setting bits 6 (RTS) and 7 (CTS) of the EFR register to logic 1. If CTS# pin transitions from logic 0 to logic 1 indicting a flow control request, ISR bit-5 will be set to logic 1, (if enabled via IER bit 6-7), and the UART will suspend TX transmissions as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input returns to logic 0, indicating more data may be sent. 22 XR17C158 áç PCI BUS OCTAL UART REV. 1.1.3 FIGURE 9. AUTO RTS/DTR AND CTS/DSR FLOW CONTROL OPERATION Local UART UARTA Remote UART UARTB Receiver FIFO Trigger Reached Auto RTS Trigger Level TXB RTSA# CTSB# Auto CTS Monitor RXB Receiver FIFO Trigger Reached TXA Transmitter CTSA# Auto CTS Monitor RTSA# RXA RTSB# Assert RTS# to Begin Transmission 1 ON Auto RTS Trigger Level 10 OFF ON 7 2 ON CTSB# Transmitter 8 3 11 OFF ON TXB Data Starts 6 Suspend Restart 9 4 RXA FIFO INTA (RXA FIFO Interrupt) Receive Data RX FIFO Trigger Level 5 RTS High Threshold RTS Low Threshold 12 RX FIFO Trigger Level RTSCTS1 The local UART (UARTA) starts data transfer by asserting -RTSA# (1). RTSA# is normally connected to CTSB# (2) of remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO (4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and continues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows (7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its transmit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9), UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB with RTSB# and CTSA# controlling the data flow. 4.3 INFRARED MODE Each UART in the 158 includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. The input pin ENIR conveniently activates all 8 UART channels to start up in the infrared mode. This global control pin enables the MCR bit-6 function in every UART channel register. After power up or a reset, the software can overwrite MCR bit-6 if so desired. ENIR and MCR bit-6 also disable its receiver while the transmitter is sending data. This prevents the echoed data from going to the receiver. The global activation ENIR pin prevents the infrared emitter from turning on and drawing large amount of current while the system is starting up. When the infrared feature is enabled, the transmit data outputs, TX[7:0], would idle at logic zero level. Likewise, the RX [7:0] inputs assume an idle level of logic zero. The infrared encoder sends out a 3/16 of a bit wide pulse for each “0” bit in the transmit data stream. This signal encoding reduces the on-time of the infrared LED, hence reduces the power consumption. See Figure 10 below. The infrared decoder receives the input pulse from the infrared sensing diode on RX pin. Each time it senses a light pulse, it returns a logic zero to the data bit stream. The RX input signal may be inverted prior 23 áç PCI BUS OCTAL UART XR17C158 REV. 1.1.3 delivered to the input of the decoder. This option supports active low instead of normal active high pulse from some infrared modules on the market. FIGURE 10. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING TX Data 0 Stop Start Character Data Bits 1 1 0 0 1 0 1 1 0 Transmit IR Pulse (TX Pin) 1/2 Bit Time Bit Time 3/16 Bit Time IrEncoder-1 Receive IR Pulse (RX pin) Bit Time 1/16 Clock Delay 1 0 1 0 0 Data Bits 1 1 0 1 Stop 0 Start RX Data Character IRdecoder-1 4.4 INTERNAL LOOPBACK Each UART channel provides an internal loopback capability for system diagnostic. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally. Figure 11 shows how the modem port signals are reconfigured. Transmit data from the transmit shift register output is internally routed to the receive shift reg- ister input allowing the system to receive the same data that it was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and CTS#, DSR# CD# and RI# inputs are ignored. NOTE: MCR bits 2 and 3 (OP1 and OP2 outputs) are not available in the XR17C158. They are present for 16C550 compatibility during Internal loopback, see Figure 11. 24 XR17C158 áç PCI BUS OCTAL UART REV. 1.1.3 FIGURE 11. INTERNAL LOOP BACK VCC T X [7 :0 ] T ra n sm it S h ift R e g iste r R e ce ive S h ift R e g iste r R X [7 :0 ] VCC R T S # [7 :0 ] Modem / General Purpose Control Logic Internal Bus Lines and Control Signals M C R bit-4= 1 RTS# CTS# C T S # [7 :0 ] VCC D T R # [7 :0 ] DTR# DSR# D S R # [7 :0 ] O P 1# R I# R I# [7 :0 ] O P 2# CD# 4.5 UART CHANNEL CONFIGURATION REGISTERS AND ADDRESS DECODING. The 8 sets of UART configuration registers are decoded using address lines A8 to A11 as shown below. Address lines A0 to A3 select the 16 registers in each channel. The first 8 registers are 16550 compatible with EXAR enhanced feature registers located on the upper 8 addresses. 25 C D # [7 :0 ] A11 A10 A9 A8 UART CHANNEL SELECTION 0 0 0 0 0 0 0 1 0 1 0 1 0 0 2 0 1 1 0 3 1 0 0 0 4 1 0 1 0 5 1 1 0 0 6 1 1 1 0 7 áç PCI BUS OCTAL UART XR17C158 REV. 1.1.3 TABLE 10: UART CHANNEL CONFIGURATION REGISTERS. ADDRESS REGISTER READ/WRITE COMMENTS Read-only Write-only LCR[7] = 0 A3 A2 A1 A0 16550 COMPATIBLE 0 0 0 0 RHR - Receive Holding Reg THR - Transmit Holding Register 0 0 0 0 DLL - Div Latch Low Read/Write LCR[7] = 1 0 0 0 1 DLM - Div Latch High Read/Write LCR[7] = 1 0 0 0 1 IER - Interrupt Enable Reg Read/Write LCR[7] = 0 0 0 1 0 ISR - Interrupt Status Reg FCR - FIFO Control Reg Read-only Write-only 0 0 1 1 LCR - Line Control Reg Read/Write 0 1 0 0 MCR - Modem Control Reg Read/Write 0 1 0 1 LSR - Line Status Reg reserved Read-only Write-only 0 1 1 0 MSR - Modem Status Reg - Auto RS485 Delay Read-only Write-only 0 1 1 1 SPR - Scratch Pad Reg Read/Write ENHANCED REGISTER 1 0 0 0 FCTR Read/Write 1 0 0 1 EFR - Enhanced Function Reg Read/Write 1 0 1 0 TXCNT - Transmit FIFO Level Counter TXTRG - Transmit FIFO Trigger Level Read-only Write-only 1 0 1 1 RXCNT - Receive FIFO Level Counter RXTRG - Receive FIFO Trigger Level Read-only Write-only 1 1 0 0 Xoff-1 - Xoff Character 1 Xchar Write-only Read-only 1 1 0 1 Xoff-2 - Xoff Character 2 reserved Write-only Read-only 1 1 1 0 Xon-1 - Xon Character 1 reserved Write-only Read-only 1 1 1 1 Xon-2 - Xon Character 2 reserved Write-only Read-only 26 Xon,Xoff Rcvd. Flags XR17C158 áç PCI BUS OCTAL UART REV. 1.1.3 TABLE 11: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY EFR BIT-4. ADDRESS A3-A0 REG NAME READ/ WRITE BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 COMMENT 0000 RHR R Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 LCR[7]=0 0000 THR W Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 LCR[7]=0 0000 DLL R/W Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 LCR[7]=1 0001 DLM R/W Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 LCR[7]=1 0001 IER R/W 0010 ISR R 0010 FCR W 0011 LCR R/W 0100 MCR R/W 0/ 0/ BRG IR Prescaler Enable 0101 LSR R/W RX FIFO ERROR TSR Empty 0110 MSR R CD RI DSR MSR W 0/ RS485 DLY-3 0/ RS485 DLY-2 0/ RS485 DLY-1 0111 SPR R/W Bit-7 Bit-6 Bit-5 1000 FCTR R/W TRG Table Bit-1 TRG Table Bit-0 Auto RS485 Enable 1001 EFR R/W 1010 TFCNT R Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 1010 TFTRG W Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 0 0/ 0/ 0/ CTS/DSR# RTS/DTR# Xon/Xoff/ Int. Enable Int. Enable Sp. Char. Int. Enable 0/ FIFOs Enable 0/ 0/ INT 0/ Delta- Xoff/spe- Source FIFOs Bit-3 Enable Flow Cntl cial char 0/ 0/ 0/ 0/ RX FIFO RX FIFO TX FIFO TX FIFO Trigger Trigger Trigger Trigger Divisor Enable Modem RX Line TX Empty RX Data Status Int. Status Int. Int. Int. Enable Enable Enable Enable Set TX Set Parity Break Even Parity 0/ Internal XonAny Lopback Enable DMA Mode INT Source Bit-2 INT Source Bit-1 TX FIFO RX FIFO FIFOs Reset Reset Enable Parity Stop Bits Word Enable Length Bit-1 OP21 INT Source Bit-0 Word Length Bit-0 OP11/ RTS# Pin DTR# Pin RTS/DTR Control Control Flow Sel THR RX Break RX Fram- RX Parity RX Over- RX Data Empty ing Error Error run Ready Auto Auto Special CTS/DSR RTS/DTR Char Enable Enable Select CTS Delta CD# Delta RI# Delta DSR# Delta CTS# 0/ Reserved Reserved Reserved Reserved RS485 DLY-0 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 User Data Invert IR RTS/DTR RTS/DTR RTS/DTR RTS/DTR RX Input Hyst Bit-3 Hyst Bit-2 Hyst Bit-1 Hyst Bit-0 Enable IER [7:5], ISR [5:4], FCR[5:4], MCR[7:5,2] MSR[7:4] Software Software Software Software Flow Cntl Flow Cntl Flow Cntl Flow Cntl Bit-3 Bit-2 Bit-1 Bit-0 1011 RFCNT R Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 1011 RFTRG W Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 1100 XCHAR R 1100 XOFF1 W Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 1101 XOFF2 W Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 1110 XON1 W Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 1111 XON2 W Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 Xon Det. Xoff Det. Self-clear Indicator Indicator after read 27 áç PCI BUS OCTAL UART XR17C158 REV. 1.1.3 4.6 TRANSMITTER The transmitter section comprises of a 64 bytes of FIFO, a byte-wide Transmit Holding Register (THR) and an 8-bit Transmit Shift Register (TSR). THR receives a data byte from the host (non-FIFO mode) or a data byte from the FIFO when the FIFO is enabled by FCR bit-0. TSR shifts out every data bit with the 16X or 8X internal clock. A bit time is 16 or 8 clock periods. The transmitter sends the start bit followed by the number of data bits, inserts the proper parity bit if enable, and adds the stop bit(s). The status of the THR and TSR are reported in the Line Status Register (LSR bit-5 and bit-6). writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). The least-significant-bit (Bit0) becomes first data bit to go out. The THR is also the input register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. A THR empty interrupt can be generated when it is enabled in IER bit-1. 4.6.2 Transmitter Operation in non-FIFO The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty. 4.6.1 Transmit Holding Register (THR) The transmit holding register is an 8-bit register providing a data interface to the host processor. The host FIGURE 12. TRANSMITTER OPERATION IN NON-FIFO MODE D a ta B y te T ra n s m it H o ld in g R e g is te r (T H R ) T H R In te rru p t (IS R b it-1 ) E n a b le d b y IE R b it-1 16X or 8X C lo c k (8 X M O D E R e g is te r) T ra n s m it S h ift R e g is te r (T S R ) M S B L S B T X N O F IF O 1 4.6.4 Auto RS485 Operation The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled by FCTR bit-5. It de-asserts RTS# or DTR# after a specified delay indicated in MSR[7:4] following the last stop bit of the last character that has been transmitted. This helps in turning around the transceiver to receive the remote station’s response. The delay optimizes the time needed for the last transmission to reach the farthest station on a long cable network before switching off the line driver. This delay prevents undesirable line signal disturbance that causes signal degradation. It also changes the transmitter empty interrupt to TSR empty instead of THR empty. 4.6.3 Transmitter Operation in FIFO The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the amount of data in the FIFO falls below its programmed trigger level (see TXTRG register). The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty. Furthermore, with the RS485 half-duplex direction control enabled (FCTR bit-5=1) the source of the transmit empty interrupt changes to TSR empty instead of THR empty. This is to ensure the RTS# output is not changed until the last stop bit of the last character is shifted out. 28 XR17C158 áç PCI BUS OCTAL UART REV. 1.1.3 FIGURE 13. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE T ra n sm it D a ta B yte T ra n sm it F IF O (6 4-B yte ) F lo w C o ntrol C h ara cte rs (X off1 /2 an d X o n 1/2 R e g . T H R In terru p t (IS R b it-1 ) falls b e lo w P ro g ra m m e d T rig g e r L e ve l (T X T R G ) a n d th e n w h e n b e co m e s e m p ty. F IF O is E n a b led by F C R b it-0 = 1 A uto S o ftw a re F low C o n tro l 1 6 X or 8 X C lock (8 X M O D E R eg iste r) T ra n sm it D a ta S h ift R e g iste r (T S R ) A uto C T S F lo w C o n tro l (C T S # pin ) T XF IF O 1 4.7 RECEIVER The receiver section contains an 8-bit Receive Shift Register (RSR) and Receive Holding Register (RHR). The RSR uses the 16X or 8X clock for timing. It verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts counting at the 16X or 8X clock rate. After 8 or 4 clocks the start bit period should be at the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. If there were any error(s), they are reported in the LSR register bits 1- 4. Upon unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the error flags are immediately updated to reflect the status of the data byte in RHR register. RHR can generate a receive data ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready time-out function when receive data does not reach the receive FIFO trigger level. This time-out delay is 4 word lengths as defined by LCR[1,0] plus 12 bits time. The RHR interrupt is enabled by IER bit0. 29 áç PCI BUS OCTAL UART XR17C158 REV. 1.1.3 4.7.1 Receiver Operation in non-FIFO Mode FIGURE 14. RECEIVER OPERATION IN NON-FIFO MODE 1 6 X o r 8 X C lo ck (8 X M O D E R e g iste r) R e ce ive D a ta S h ift R e g iste r (R S R ) E rror F la gs in LS R bits 4:2 R e ce ive D a ta B yte a n d E rro rs D a ta B it V a lid a tio n R e ce ive D a ta H o ld in g R e g iste r (R H R ) R e ce ive D ata C ha ra cte rs R H R In te rru p t (IS R b it-2 ) R X F IF O 1 4.7.2 Receiver Operation with FIFO FIGURE 15. RECEIVER OPERATION IN FIFO AND FLOW CONTROL MODE 1 6 X o r 8 X S a m p lin g C lo ck (8 X M O D E R e g .) R e ce ive D a ta S h ift R e g iste r (R S R ) D a ta B it V a lid a tio n R e ce ive D a ta C ha ra cte rs E xa m p le : - F IF O trig g e r le ve l se t a t 4 8 b yte s - R T S /D T R h ya ste re sis se t a t +/-8 ch a rs. 6 4 b yte s b y 1 1 b it w id e F IF O Error Flags (64-sets) D a ta fa lls to 4 0 R e ce ive D a ta F IF O (6 4 -b yte ) F IF O T rig g e r= 4 8 R e ce ive D a ta B yte a n d E rro rs Error Flags in LSR bits 4:2 D a ta fills to 5 6 R T S # /D T R # re -a s se rts w h e n d a ta fa lls b e lo w th e trig g e r le v e l to re sta rt re m o te tra n sm itte r. E n a b le b y E F R b it-6 = 1 , M C R b it-2 . R H R In te rru p t (IS R b it-2 ) is p ro g ra m m e d a t F IF O trig g e r le ve l (R X T R G ). F IF O is E n a b le b y F C R b it-0 = 1 R T S # /D T R # d e -a sse rts w h e n d a ta fills a b o ve th e trig g e r le v e l to su sp e n d re m o te tra n sm itte r. E n a b le b y E F R b it-6 = 1 , M C R b it-2 . R e c e ive D a ta R X F IF O 1 4.8 REGISTERS Receive Holding Register (RHR) flags to be in LSR register. When the FIFO is enabled by FCR bit-0, it acts as the first-out register of the FIFO as new data are put over the first-in register. The receive FIFO pointer is bumped after the RHR register is read. Also, the error flags associated with the data byte are immediately updated onto the line status register (LSR) bits 1-4. The receive holding register is an 8-bit register that holds a receive data byte from the receive shift register (RSR). It provides the receive data interface to the host processor. The host reads the receive data byte on this register whenever a data byte is transferred from the RSR. RHR also part of the receive FIFO of 64 bytes by 11-bit wide, 3 extra bits are for the error 30 XR17C158 áç PCI BUS OCTAL UART REV. 1.1.3 Baud Rate Generator Divisors (DLL and DLM) IER[0]: RHR Interrupt Enable The Baud Rate Generator (BRG) is a 16-bit counter that generates the data rate for the transmitter and receiver. The rate is programmed through registers DLL and DLM which are only accessible when LCR bit-7 is set to logic 1. See Programmable Baud Rate Generator section for more detail. The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when the receive FIFO has reached the programmed trigger level in the FIFO mode. Interrupt Enable Register (IER) Logic 1 = Enable the receiver data ready interrupt. The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR) register and also encoded in INT (INT0-INT3) register in the Device Configuration Registers. IER[1]: THR Interrupt Enable Logic 0 = Disable the receive data ready interrupt. (default) This interrupt is associated with bit-5 in the LSR register. An interrupt is issued whenever the THR becomes empty or when data in the FIFO falls below the programmed trigger level. Logic 0 = Disable Transmit Holding Register empty interrupt. (default) IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION Logic 1 = Enable Transmit Holding Register empty interrupt. When the receive FIFO (FCR BIT-0 = a logic 1) and receive interrupts (IER BIT-0 = logic 1) are enabled, the RHR interrupts (see ISR bits 3 and 4) status will reflect the following: IER[2]: Receive Line Status Interrupt Enable Any of the LSR register bits 1,2,3 or 4 becomes active will generate an interrupt to inform the host controller about the error status of the current data byte in FIFO. A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed trigger level. It will be cleared when the FIFO drops below the programmed trigger level. Logic 0 = Disable the receiver line status interrupt. (default) B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register status bit and the interrupt will be cleared when the FIFO drops below the trigger level. Logic 1 = Enable the receiver line status interrupt. IER[3]: Modem Status Interrupt Enable Logic 0 = Disable the modem status register interrupt. (default) C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to the receive FIFO. It is reset when the FIFO is empty. Logic 1 = Enable the modem status register interrupt. IER[4]: Reserved. IER[5]: Xoff Interrupt Enable (requires EFR bit4=1) IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the 158 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). Logic 0 = Disable the software flow control, receive Xoff interrupt. (default) Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for details. IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1) A. LSR BIT-0 indicates there is data in RHR or RX FIFO. Logic 0 = Disable the RTS# interrupt. (default). Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition. B. LSR BIT 1-4 provides the type of receive data errors encountered for the data byte in RHR, if any. C. LSR BIT-5 indicates THR is empty. IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1) D. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty. Logic 0 = Disable the CTS# interrupt. (default). E. LSR BIT-7 indicates the Or’ed function of errors in the RX FIFO. Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition. 31 áç PCI BUS OCTAL UART XR17C158 REV. 1.1.3 • Receive Xon/Xoff/Special character is by detection of a Xon, Xoff or Special character. Interrupt Status Register (ISR) The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will give the user the current highest pending interrupt level to be serviced, others queue up for next service. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt Source Table, Table 12, shows the data values (bit 05) for the six prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels. • CTS#/DSR# is by a change of state on the input pin with auto flow control enabled, EFR bit-7, and depending on selection on MCR bit-2. • RTS#/DTR# is when its receiver changes the state of the output pin during auto RTS/DTR flow control enabled by EFR bit-6 and selection of MCR bit-2. Interrupt Clearing: • LSR interrupt is cleared by a read to the LSR register. • RXRDY and RXRDY Time-out are cleared by reading data until FIFO falls below the trigger level. Interrupt Generation: • TXRDY interrupt is cleared by a read to the ISR register. • LSR is by any of the LSR bits 1, 2, 3 and 4. • RXRDY is by RX trigger level. • MSR interrupt is cleared by a read to the MSR register. • RXRDY Time-out is by the a 4-char plus 12 bits delay timer if data doesn’t reach FIFO trigger level. • Xon, Xoff or Special character interrupt is cleared by a read to ISR. • TXRDY is by LSR bit-5 (or bit-6 in auto RS485 control). • RTS#/DTR# and CTS#/DSR# status change interrupts are cleared by a read to the MSR register. • MSR is by any of the MSR bits, 0, 1, 2 and 3. TABLE 12: INTERRUPT SOURCE AND PRIORITY LEVEL PRIORITY ISR REGISTER STATUS BITS SOURCE OF THE INTERRUPT+ LEVEL BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 1 0 0 0 1 1 0 LSR (Receiver Line Status Register) 2 0 0 0 1 0 0 RXRDY (Received Data Ready) 3 0 0 1 1 0 0 RXRDY (Receive Data Time-out) 4 0 0 0 0 1 0 TXRDY (Transmitter Holding Register Empty) 5 0 0 0 0 0 0 MSR (Modem Status Register) 6 0 1 0 0 0 0 RXRDY (Received Xon/Xoff or Special character) 7 1 0 0 0 0 0 CTS#/DSR#, RTS#/DTR# change of state X 0 0 0 0 0 1 None (default) NOTE: Note that once set to a logic 1, the ISR bit-4 will stay a logic 1 until a Xon character is received. ISR bit-5 indicates that CTS#/DSR# or RTS#/DTR# has changed state. ISR[0]: Interrupt Status Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine. ISR[7:6]: FIFO Enable Status These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are enabled. Logic 1 = No interrupt pending. (default condition) ISR[3:1]: Interrupt Status These bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, 3 and 4 (See Interrupt Source Table 12). FIFO Control Register (FCR) This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and select the DMA mode. The DMA, and FIFO modes are defined as follows: ISR[5:4]: Interrupt Status These bits are enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match of the Xon or Xoff character(s). 32 XR17C158 áç PCI BUS OCTAL UART REV. 1.1.3 FCR BIT-0: TX and RX FIFO Enable FCR[3]: DMA Mode Select Logic 0 = Disable the transmit and receive FIFO. (default). This bit has no effect since TXRDY and RXRDY pins are not available in this device. It is provided for legacy software. Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are written or they will not be programmed. Logic 0 = Set DMA to mode 0. (default) Logic 1 = Set DMA to mode 1. FCR[1]: RX FIFO Reset FCR[5:4]: Transmit FIFO Trigger Select This bit is only active when FCR bit-0 is active. (logic 0 = default, TX trigger level = one) Logic 0 = No receive FIFO reset. (default) The FCTR Bits 6-7 are associated with these 2 bits by selecting one of the four tables. The 4 user selectable trigger levels in 4 tables are supported for compatibility reasons. These 2 bits set the trigger level for the transmit FIFO interrupt. The UART will issue a transmit interrupt when the number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the FIFO did not get filled over the trigger level on last re-load. Table 13 below shows the selections. Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not cleared or altered). This bit will return to a logic 0 after resetting the FIFO. FCR[2]: TX FIFO Reset This bit is only active when FCR bit-0 is active. Logic 0 = No transmit FIFO reset. (default) Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not cleared or altered). This bit will return to a logic 0 after resetting the FIFO. FCR[7:6]: Receive FIFO Trigger Select (logic 0 = default, RX trigger level =1) The FCTR Bits 6-7 are associated with these 2 bits. These 2 bits are used to set the trigger level for the receiver FIFO interrupt. Table 13 shows the complete selections. TABLE 13: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION FCTR BIT-7 FCTR BIT-6 0 0 0 FCR BIT-7 FCR BIT-6 0 0 1 1 0 1 0 1 1 1 FCR 0 0 0 1 0 1 X X 1 (default) 0 1 0 1 COMPATIBILITY Table-A. 16C550, 16C2550, 16C2552, 16C554, 16C580 compatible. 16 8 24 30 Table-B. 16C650A compatible. 8 16 32 56 Table-C. 16C654 compatible. 8 16 24 28 0 0 1 1 0 0 1 1 TRANSMIT RECEIVE TRIGGER LEVEL TRIGGER LEVEL 1 (default) 4 8 14 0 1 0 1 0 1 BIT-4 0 0 1 1 0 0 1 1 1 FCR BIT-5 0 1 0 1 8 16 56 60 X X Programmable Programmable Table-D. 16C850, 16c2850, 16C2852, 16C854, 16C864, 16C872 compatible. 33 áç XR17C158 PCI BUS OCTAL UART REV. 1.1.3 Line Control Register (LCR) • LCR BIT-5 = logic 0, parity is not forced. (default) The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. • LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. • LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive data. LCR[1-0]: TX and RX Word Length Select These two bits specify the word length to be transmitted or received. BIT-1 BIT-0 WORD LENGTH 0 0 5 (default) 0 1 6 1 0 7 1 1 8 TABLE 14: PARITY SELECTION LCR BIT-5 LCR BIT-4 LCR BIT-3 X X 0 0 0 1 Odd parity 0 1 1 Even parity 1 0 1 Force parity to mark, “1” 1 1 1 Forced parity to space, “0” LCR[2]: TX and RX Stop-bit Length Select WORD LENGTH STOP BIT LENGTH (BIT TIME(S)) 0 5,6,7,8 1 (default) 1 5 1-1/2 1 6,7,8 2 No parity LCR[6]: Transmit Break Enable The length of stop bit is specified by this bit in conjunction with the programmed word length. BIT-2 PARITY SELECTION • When enabled the Break control bit it causes a break condition to be transmitted (the TX output is forced to a “space’, logic 0, state). This condition remains until disabled by setting LCR bit-6 to a logic 0. • Logic 0 = No TX break condition. (default) • Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line break condition. LCR[3]: TX and RX Parity Select Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data integrity check. See Table 14 for parity selection summary below. LCR[7]: Baud Rate Divisors Enable • Logic 0 = No parity. • Logic 1 = Divisor latch registers are selected. • Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the data character received. Modem Control Register (MCR) or General Purpose Outputs Control. Baud rate generator divisor (DLL/DLM) enable. • Logic 0 = Data registers are selected. (default) This register controls the serial interface signals with the modem or a peripheral device. LCR[4]: TX and RX Parity Select Modem Control Register (MCR) If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format. Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The receiver must be programmed to check the same format. (default). The MCR register is used for controlling the modem interface signals or general purpose inputs/outputs. MCR[0]: DTR# Pins The DTR# pin may be used for automatic hardware flow control enabled by EFR bit-6 and MCR bit-2=1. If the modem interface is not used, this output may be used for general purpose. • Logic 1 = EVEN Parity is generated by forcing an even the number of logic 1’s in the transmitted character. The receiver must be programmed to check the same format. • Logic 0 = Force DTR# output to a logic 1. (default) LCR[5]: TX and RX Parity Select • Logic 1 = Force DTR# output to a logic 0. If the parity bit is enabled, LCR BIT-5 selects the forced parity format. MCR[1]: RTS# Pins The RTS# pin may be used for automatic hardware flow control by enabled by EFR bit-6 and MCR bit34 XR17C158 áç PCI BUS OCTAL UART REV. 1.1.3 and feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth. 2=0. If the modem interface is not used, this output may be used for general purpose. • Logic 0 = Force RTS# output to a logic 1. (default) Line Status Register (LSR) • Logic 1 = Force RTS# output to a logic 0. This register provides the status of data transfers between the UART and the host. MCR[2]: DTR# or RTS# for Auto Flow Control LSR[0]: Receive Data Ready Indicator DTR# or RTS# auto hardware flow control select. This bit is in effect only when auto RTS/DTR is enabled by EFR bit-6. DTR# selection is associated with DSR# and RTS# is with CTS#. • Logic 0 = No data in receive holding register or FIFO. (default). • Logic 1 = Data has been received and is saved in the receive holding register or FIFO. • Logic 0 = Uses RTS# and CTS# pins for auto hardware flow control. LSR[1]: Receiver Overrun Flag • Logic 1 = Uses DTR# and DSR# pins for auto hardware flow control. • Logic 0 = No overrun error. (default) • Logic 1 = Enable local loopback mode, see loopback section and Figure 11. • Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into the FIFO, therefore the data in the FIFO is not corrupted by the error. MCR[5]: Xon-Any Enable LSR[2]: Receive Data Parity Error Flag • Logic 0 = Disable Xon-Any function (for 16C550 compatibility). (default). • Logic 0 = No parity error. (default) MCR[3]: Reserved. Logic zero is default. MCR[4]: Internal Loopback Enable • Logic 0 = Disable loopback mode. (default) • Logic 1 = Enable Xon-Any function. In this mode any RX character received will enable Xon, resume data transmission. • Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect. This error is associated with the character available for reading in RHR. MCR[6]: Infrared Encoder/Decoder Enable LSR[3]: Receive Data Framing Error Flag The state of this bit depends on the sampled logic level of pin ENIR during power up, following a hardware reset or a soft-reset. Afterward user can override this bit for desired operation. • Logic 0 = No framing error. (default) • Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with the character available for reading in RHR. • Logic 0 = Disable the infrared mode, operates in the normal serial character mode. LSR[4]: Receive Break Flag • Logic 0 = No break condition. (default) • Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. While in this mode, the TX/RX output/input are routed to the infrared encoder/ decoder. The data input and output levels will conform to the IrDA infrared interface requirement. As such, while in this mode the infrared TX output will be a logic 0 during idle data conditions. FCTR bit-4 may be selected to invert the RX input signal level going to the decoder for infrared modules that provide rather an inverted output. • Logic 1 = The receiver received a break signal (RX was a logic 0 for one character frame time). In the FIFO mode, only one break character is loaded into the FIFO. The break indication remains until the RX input returns to the idle condition, “mark” or logic 1. LSR[5]: Transmit Holding Register Empty Flag This bit is the Transmit Holding Register Empty indicator. This bit indicates that the transmitter is ready to accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to the host when the THR interrupt enable is set. The THR bit is set to a logic 1 when the last data byte is transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0 concurrently with the data loading to the transmit holding register by the host. In the FIFO mode this bit is set when MCR[7]: Clock Prescaler Select • Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable Baud Rate Generator without further modification, i.e., divide by one. (default). • Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four 35 áç PCI BUS OCTAL UART XR17C158 REV. 1.1.3 MSR[4]: CTS Input Status the transmit FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO. CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto CTS (EFR bit-7) and RTS/CTS flow control select (MCR bit-2). Auto CTS flow control allows starting and stopping of local data transmissions based on the modem CTS# signal. A logic 1 on the CTS# pin will stop UART transmitter as soon as the current character has finished transmission, and a logic 0 will resume data transmission. Normally MSR bit-4 bit is the compliment of the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR register. The CTS# input may be used as a general purpose input when the modem interface is not used. LSR[6]: Transmit Shift Register Empty Flag This bit is the Transmit Shift Register Empty indicator. This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or TSR contains a data character. In the FIFO mode this bit is set to one whenever the transmit FIFO and transmit shift register are both empty. LSR[7]: Receive FIFO Data Error Flag • Logic 0 = No FIFO error. (default) • Logic 1 = An indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error or break indication is in the FIFO data. This bit clears when there is no more error(s) in the FIFO. MSR[5]: DSR Input Status Modem Status Register (MSR) - Read Only DSR# (active high, logical 1). This input may be used for auto DTR/DSR flow control function, see auto \hardware flow control section. Normally this bit is the compliment of the DSR# input. In the loopback mode, this bit is equivalent to the DTR# bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is not used. This register provides the current state of the modem interface signals, or other peripheral device that the UART is connected. Lower four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a signal from the modem changes state. These bits may be used as general purpose inputs/outputs when they are not used with modem signals. MSR[6]: RI Input Status RI# (active high, logical 1). Normally this bit is the compliment of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the MCR register. The RI# input may be used as a general purpose input when the modem interface is not used. MSR[0]: Delta CTS# Input Flag • Logic 0 = No change on CTS# input (default). • Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt will be generated if MSR interrupt is enabled (IER bit-3. MSR[7]: CD Input Status CD# (active high, logical 1). Normally this bit is the compliment of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the MCR register. The CD# input may be used as a general purpose input MSR[1]: Delta DSR# Input Flag • Logic 0 = No change on DSR# input (default). • Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt will be generated if MSR interrupt is enabled (IER bit-3. when the modem interface is not used. Modem Status Register (MSR) - Write Only The upper four bits 4-7 of this register sets the delay in number of bits time for the auto RS485 turn around from transmit to receive. MSR[2]: Delta RI# Input Flag • Logic 0 = No change on RI# input (default). MSR [7:4] • Logic 1 = The RI# input has changed from a logic 0 to a logic 1, ending of the ringing signal. A modem status interrupt will be generated if MSR interrupt is enabled (IER bit-3. When Auto RS485 feature is enabled (FCTR bit-5=1) and RTS# output is connected to the enable input of a RS-485 transceiver. These 4 bits select from 0 to 15 bit-time delay after the end of the last stop-bit of the last transmitted character. This delay controls when to change the state of RTS# output. This delay is very useful in long-cable networks. Table 15 shows the selection. The bits are enabled by EFR bit-4. MSR[3]: Delta CD# Input Flag • Logic 0 = No change on CD# input (default). • Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem status interrupt will be generated if MSR interrupt is enabled (IER bit-3. 36 XR17C158 áç PCI BUS OCTAL UART REV. 1.1.3 TABLE 15: AUTO RS485 HALF-DUPLEX DIRECTION CONTROL DELAY FROM TRANSMIT-TO-RECEIVE MSR[7] MSR[6] MSR[5] MSR[4] DELAY IN DATA BIT(S) TIME 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 9 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 10 1 0 1 1 11 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15 • 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register (THR) becomes empty. Transmit Shift Register (TSR) may still be shifting data bit out. SCRATCH PAD REGISTER (SPR) This is an 8-bit general purpose register for the user to store temporary data. The content of this register is preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle. • 1 = Enable Auto RS485 half duplex direction control. RTS# output changes its logic level from 1 to 0 when finished sending the last stop bit of the last character out of the TSR register. It changes back to logic level 1 from 0 when a data byte is loaded into the THR or transmit FIFO. The change to logic 1 occurs prior sending the start-bit. It also changes the transmitter interrupt from transmit holding to transmit shift register (TSR) empty. FEATURE CONTROL REGISTER (FCTR) This register controls the UART enhanced functions that are not available on ST16C554 or ST16C654. FCTR [3:0] - Auto RTS/DTR Flow Control Hysteresis Select These bits select the auto RTS/DTR flow control hysteresis and only valid when TX and RX Trigger TableD is selected (FCTR bit-6 and 7 are set to logic 1). The RTS/DTR hysteresis is referenced to the RX FIFO trigger level. After reset, these bits are set to logic 0 selecting the next FIFO trigger level for hardware flow control. Table 16 below shows the 16 selectable hysteresis levels. FCTR[7:6]: TX and RX FIFO Trigger Table Select These 2 bits select the transmit and receive FIFO trigger level table A, B, C or D. When table A, B, or C is selected the auto RTS flow control trigger level is set to "next FIFO trigger level" for compatibility to ST16C550 and ST16C650 series. RTS/DTR# triggers on the next level of the RX FIFO trigger level, in another word, one FIFO level above and one FIFO level below. See in Table 13 for complete selection with FCR bit 4-5 and FCTR bit 6-7, i.e. if Table C is used on the receiver with RX FIFO trigger level set to 56 bytes, RTS/DTR# output will de-asserts at 60 and re-asserts at 16. FCTR[4]: Infrared RX Input Logic Select 0 = Select RX input as active high encoded IrDA data, normal, (default). 1 = Select RX input as active low encoded IrDA data, inverted. FCTR[5]: Auto RS485 Enable Auto RS485 half duplex control enable/disable. 37 áç PCI BUS OCTAL UART XR17C158 REV. 1.1.3 TABLE 16: 16 SELECTABLE HYSTERESIS LEVELS WHEN TRIGGER TABLE-D IS SELECTED FCTR BIT-3 FCTR BIT-2 FCTR BIT-1 FCTR BIT-0 RTS/DTR HYSTERESIS (CHARACTERS) 0 0 0 0 0 0 0 0 1 +/- 4 0 0 1 0 +/- 6 0 0 1 1 +/- 8 0 1 0 0 +/- 8 0 1 0 1 +/- 16 0 1 1 0 +/- 24 0 1 1 1 +/- 32 1 1 0 0 +/- 12 1 1 0 1 +/- 20 1 1 1 0 +/- 28 1 1 1 1 +/- 36 1 0 0 0 +/- 40 1 0 0 1 +/- 44 1 0 1 0 +/- 48 1 0 1 1 +/- 52 Enhanced Feature Register (EFR) MCR bits 5-7 are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 are set to a logic 0 to be compatible with ST16C554 mode. (default). Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive character software flow control selection (see Table 17 and Table 18). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before programming a new setting. • Logic 1 = Enables the enhanced functions. When this bit is set to a logic 1 all enhanced features are enabled. EFR[5]: Special Character Detect Enable • Logic 0 = Special Character Detect Disabled. (default) EFR BIT 0-3: Software Flow Control Select • Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with data in Xoff-2 register. If a match exists, the received data will be transferred to FIFO and ISR bit-4 will be set to indicate detection of the special character. Bit-0 corresponds with the LSB bit for the receive character. If flow control is set for comparing Xon1, Xoff1 (EFR [1:0]=10) then flow control and special character work normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]=01) then flow control works normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character interrupt. Combinations of software flow control can be selected by programming these bits. EFR[4]: Enhanced Function Bits Enable Enhanced function control bit. This bit enables the functions in IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values. This feature prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it is recommended to leave it enabled, logic 1. • Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and 38 XR17C158 áç PCI BUS OCTAL UART REV. 1.1.3 TABLE 17: SOFTWARE FLOW CONTROL FUNCTIONS TX S/W FLOW CONTROL RX S/W FLOW CONTROL EFR BIT-3 CONT-3 EFR BIT-2 CONT-2 EFR BIT-1 CONT-1 EFR BIT-0 CONT-0 0 0 X X No transmit flow control 0 1 X X Transmit Xon2, Xoff2 1 0 X X Transmit Xon1, Xoff1 SOFTWARE FLOW CONTROL FUNCTIONS 1 1 X X Transmit Xon1 and Xon2, Xoff1 and Xoff2 X X 0 0 No receive flow control X X 0 1 Receiver compares Xon2, Xoff2 X X 1 0 Receiver compares Xon1, Xoff1 0 1 1 1 Transmit Xon2, Xoff2 Receiver compares Xon1 or Xon2, Xoff1 or Xoff2 1 0 1 1 Transmit Xon1, Xoff1 Receiver compares Xon1 or Xon2, Xoff1 or Xoff2 0 0 1 1 No transmit flow control Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 1 1 1 1 Transmit Xon1 and Xon2, Xoff1 and Xoff2 Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 TABLE 18: TYPICAL APPLICATIONS OF SOFTWARE FLOW CONTROL FUNCTIONS TX S/W FLOW CONTROL RX S/W FLOW CONTROL EFR BIT-3 CONT-3 EFR BIT-2 CONT-2 EFR BIT-1 CONT-1 EFR BIT-0 CONT-0 0 0 0 0 No TX and RX flow control (default and reset) 0 1 0 1 Transmit Xon2, Xoff2 Receiver compares Xon2, Xoff2 1 0 1 0 Transmit Xon1, Xoff1 Receiver compares Xon1, Xoff1 1 1 1 1 Transmit Xon1 and Xon2, Xoff1 and Xoff2 Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 EFR[6]: AUTO RTS OR DTR FLOW CONTROL ENABLE RTS#/DTR# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS/DTR is selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and RTS/DTR# will de-assert to a logic 1 at the next upper trigger or selected hysteresis level. RTS/DTR# will return to a logic 0 when FIFO data falls below the next lower trigger or selected hysteresis level (see FCTR bits 4-7). The RTS# or DTR# output must be asserted (logic 0) before the auto RTS/ DTR can take effect. The selection for RTS# or DTR# is through MCR bit-2. RTS/DTR# pin will function as a general purpose output when hardware flow control is SOFTWARE FLOW CONTROL FUNCTIONS disabled. • Logic 0 = Automatic RTS/DTR flow control is disabled. (default) • Logic 1 = Enable Automatic RTS/DTR flow control. EFR[7]: Auto CTS Flow Control Enable Automatic CTS or DSR Flow Control. • Logic 0 = Automatic CTS/DSR flow control is disabled. (default) • Logic 1 = Enable Automatic CTS/DSR flow control. Transmission stops when CTS/DSR# pin deasserts to logic 1. Transmission resumes when CTS/DSR# pin returns to a logic 0. The selection for CTS# or DSR# is through MCR bit-2. 39 áç PCI BUS OCTAL UART XR17C158 REV. 1.1.3 TFCNT[7:0]: Transmit FIFO Level Counter, readonly TABLE 19: UART RESET CONDITIONS Transmit FIFO level byte count from 0x00 (zero) to 0x40 (64). This 8-bit register gives an indication of the number of characters in the transmit FIFO. The FIFO level Byte count register is read only. The user can take advantage of the FIFO level byte counter for faster data loading to the transmit FIFO, which reduces CPU bandwidth requirements. REGISTERS TXTRG [7:0]: Transmit FIFO Trigger Level, write only. An 8-bit value written to this register sets the TX FIFO trigger level from 0x00 (zero) to 0x40 (64). The TX FIFO trigger level generates an interrupt whenever the data level in the transmit FIFO falls below this preset trigger level. RFCNT[7:0]: Receive FIFO Level Counter, read only Receive FIFO level byte count from 0x00 (zero) to 0x40 (64). It gives an indication of the number of characters in the receive FIFO. The FIFO level byte count register is read only. The user can take advantage of the FIFO level byte counter for faster data unloading from the receiver FIFO, which reduces CPU bandwidth requirements. RXTRG[7:0]: Receive FIFO Trigger Level, write only An 8-bit value written to this register, sets the RX FIFO trigger level from 0x00 (zero) to 0x40 (64). The RX FIFO trigger level generates an interrupt whenever the receive FIFO level rises to this preset trigger level. RESET STATE DLL Bits 7-0 = 0xXX DLM Bits 7-0 = 0xXX RHR Bits 7-0 = 0xXX THR Bits 7-0 = 0xXX IER Bits 7-0 = 0x00 FCR Bits 7-0 = 0x00 ISR Bits 7-0 = 0x01 LCR Bits 7-0 = 0x00 MCR Bits 7-0 = 0x00 LSR Bits 7-0 = 0x60 MSR Bits 3-0 = logic 0 Bits 7-4 = logic levels of the inputs SPR Bits 7-0 = 0xFF FCTR Bits 7-0 = 0x00 EFR Bits 7-0 = 0x00 TFCNT Bits 7-0 = 0x00 TFTRG Bits 7-0 = 0x00 RFCNT Bits 7-0 = 0x00 RFTRG Bits 7-0 = 0x00 XCHAR Bits 7-0 = 0x00 XON1 Bits 7-0 = 0x00 XON2 Bits 7-0 = 0x00 XOFF1 Bits 7-0 = 0x00 XOFF2 Bits 7-0 = 0x00 I/O SIGNALS 40 RESET STATE TX[ch-7:0] Logic 1 IRTX[ch-7:0] Logic 0 RTS#[ch-7:0] Logic 1 DTR#[ch-7:0] Logic 1 EECK Logic 0 EECS Logic 0 EEDI Logic 0 XR17C158 áç PCI BUS OCTAL UART REV. 1.1.3 5.0 PROGRAMMING EXAMPLES 5.1 UNLOADING RECEIVE DATA USING THE SPECIAL RECEIVE FIFO DATA WITH STATUS It is suggested that before starting to read the Special Receive FIFO Data with Status to unload data from any UART channel (address 0x180 for channel 0), do a dummy read to the Device ID (DVID) register in the Configuration Register of the device. The Special Receive FIFO Data with Status register can then be read multiple times subsequently without any byte-swapping problem as long as no other register (except the Device ID register) is accessed in between data unload. If you must read or write to another register, make that dummy read to the DVID register again and continue with data unloading. A step by step procedure describing the sequence for a target channel is shown below. From the receive data service routine: • Do a dummy read to Device ID (DVID) register. Address 0x8D in BYTE alignment or address 0x8C in DWORD alignment. • Read the data byte and its associated error status from ‘Special Receive FIFO Data with Status’ register of the target channel until done or empty when one of the LSR status byte bit-0=0. NOTE: If you must do other Read/Write operations to other register(s) during data unloading, repeat steps 1 & 2 to continue unloading data plus status from the ‘Special Receive FIFO Data with Status’ register of the target channel. Some Examples of using the Special Receive FIFO Data with Status: EXAMPLE I: POLLING ..................... Read LSR Read DVID Read Special Receive FIFO Data with Status (address 0x180 for channel 0, etc) Read Special Receive FIFO Data with Status (address 0x180 for channel 0, etc)* Read Special Receive FIFO Data with Status (address 0x180 for channel 0, etc) .................... EXAMPLE 2: INTERRUPT SERVICE USING INTERRUPT INFORMATION IN DEVICE CONFIGURATION REGISTER SET ..................... Read Global Interrupt Register INT0 (address 0x080) Read INT1 through INT3 registers to identify interrupting channel (address 0x081 through 0x083) Read DVID Read Special Receive FIFO Data with Status (address 0x180 for channel 0, etc) Read Special Receive FIFO Data with Status (address 0x180 for channel 0, etc)* Read Special Receive FIFO Data with Status (address 0x180 for channel 0, etc) ................ EXAMPLE 3: INTERRUPT SERVICE USING INTERRUPT INFORMATION IN INDIVIDUAL CHANNEL’S REGISTERS ................ Read Global Interrupt Register INT0 (address 0x080) Read ISR register of interrupting channel Read DVID Read Special Receive FIFO Data with Status (address 0x180 for channel 0, etc) Read Special Receive FIFO Data with Status (address 0x180 for channel 0, etc)* Read Special Receive FIFO Data with Status (address 0x180 for channel 0, etc) ................ * In case some other registers need to be accessed in between ‘Special Receive FIFO Data with Status’ reads, a ‘Read DVID’ instruction has to be inserted before resuming ‘Special Receive FIFO Data with Status’ read operation. 41 áç PCI BUS OCTAL UART XR17C158 REV. 1.1.3 ABSOLUTE MAXIMUM RATINGS Power Supply Range 7 Volts Voltage at Any Pin -0.5 to 7V Operating Temperature -40o to +85o C Storage Temperature -65o to +150o C Package Dissipation 500 mW Thermal Resistance (20x20x1.0mm 144-TQFP) theta-ja = 42, theta-jc = 8 ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS FOR 5V SIGNALING TA=0o to 70oC (-40o to +85oC for industrial grade package), Vcc-5.0V +/-10% unless specified. SYMBOL PARAMETER MIN MAX UNITS CONDITION VIL Input Low Voltage -0.5 0.8 V VIH Input High Voltage 2.0 6.0 V VOL Output Low Voltage 0.55 V Iout=6 mA VOH Output High Voltage V Iout=-2 mA IIL Input Low Leakage Current -10 uA IIH Input High Leakage Current 10 uA ICL Input Clock Leakage +/-10 uA CIN Input Pin Capacitance 10 pF CCLK CLK Pin Capacitance 12 pF CIDSEL IDSEL Pin Capacitance 8 pF ICC Power Supply Current 5 mA PCIClk=2MHz EXT Clock=2MHz all inputs at VCC or GND and all outputs are unloaded. ISLEEP Sleep Current 400 uA Eight UARTs asleep. AD[31:0] at GND, all inputs at VCC or GND. 2.4 5 42 NOTES XR17C158 áç PCI BUS OCTAL UART REV. 1.1.3 AC ELECTRICAL CHARACTERISTICS FOR 5V SIGNALING TA=0o to 70oC (-40o to +85oC for industrial grade package), Vcc-5.0V +/-10% unless specified. SYMBOL PARAMETER MIN MAX UNITS NOTES CLK PCI Bus Clock 33 MHz XTAL1 UART Crystal Oscillator UART External Clock 24 50 MHz MHz IOH(AC) Switching Current High -44 mA 0<Vout<1.4 IOL(AC) Switching Current Low 95 mA Vout/0.023 SlewR Output Rise Slew Rate 1 4 V/ns 0.2Vcc-0.6Vccload SlewF Output Fall Slew Rate 1 4 V/ns 0.6Vcc-0.2Vccload TCYC CLK Cycle Time 30 (infinite) ns THI CLK High Time 11 ns TLO CLK Low Time 11 ns CLK Slew Rate 1 4 V/ns TVAL CLK to Signal Valid Delay 2 11 ns TON Float to Active Delay 2 TOFF Active to Float Delay TSETUP Input Setup Time to CLK bused signals 7 ns THOLD Input Hold Time from CLK 0 ns TPRST RST# Active Time After Power Stable 1 ms TCRST# RST# Active Time After CLK Stable 100 us RST# Slew Rate 50 mV/ns ns 28 43 ns áç PCI BUS OCTAL UART XR17C158 REV. 1.1.3 DC ELECTRICAL CHARACTERISTICS FOR 3.3V SIGNALING TA=0o to 70oC (-40o to +85oC for industrial grade package), Vcc-3.3V +/-10% unless specified. SYMBOL PARAMETER MIN MAX UNITS CONDITION VIL Input Low Voltage -0.5 0.7 V VIH Input High Voltage 2.0 6.0 V VOL Output Low Voltage 0.4 V Iout=4 mA VOH Output High Voltage V Iout=-1 mA IIL Input Low Leakage Current -10 uA IIH Input High Leakage Current 10 uA ICL Input Clock Leakage +/-10 uA CIN Input Pin Capacitance 10 pF CCLK CLK Pin Capacitance 12 pF CIDSEL IDSEL Pin Capacitance 8 pF ICC Power Supply Current 4 mA PCIClk=2MHz EXT Clock=2MHz all inputs at VCC or GND and outputs are unloaded. ISLEEP Sleep Current 400 uA Eight UARTs asleep. AD[31:0] at GND, all inputs at VCC or GND. 2.0 5 44 NOTES XR17C158 áç PCI BUS OCTAL UART REV. 1.1.3 AC ELECTRICAL CHARACTERISTICS FOR 3.3V SIGNALING TA=0o to 70oC (-40o to +85oC for industrial grade package), Vcc-3.3.0V +/-10% unless specified. SYMBOL PARAMETER MIN MAX UNITS NOTES CLK PCI Bus Clock 22 MHz XTAL1 UART Crystal Oscillator UART External Clock 20 33 MHz MHz IOH(AC) Switching Current High -20 mA 0<Vout<1.4 IOL(AC) Switching Current Low 70 mA Vout/0.023 SlewR Output Rise Slew Rate 1 10 V/ns 0.2Vcc-0.6Vccload SlewF Output Fall Slew Rate 1 10 V/ns 0.6Vcc-0.2Vccload TCYC CLK Cycle Time 50 (infinite) ns THI CLK High Time 18 ns TLO CLK Low Time 18 ns CLK Slew Rate 1 4 V/ns TVAL CLK to Signal Valid Delay 2 20 ns TON Float to Active Delay 2 TOFF Active to Float Delay TSETUP Input Setup Time to CLK bused signals 15 ns THOLD Input Hold Time from CLK 0 ns TPRST RST# Active Time After Power Stable 1 ms TCRST# RST# Active Time After CLK Stable 100 us RST# Slew Rate 50 mV/ns ns 28 45 ns áç PCI BUS OCTAL UART XR17C158 REV. 1.1.3 FIGURE 16. PCI BUS CONFIGURATION SPACE REGISTERS READ AND WRITE OPERATION C LK H ost 1 2 4 3 FR A M E# H ost ADDRESS A D[31:0] H ost D A TA Ta rg e t C FG -R D C /BE [3:0]# B Y TE E N A B L E # DATA TRANSFER H ost IR DY # H ost TR D Y# Ta rg e t D EV SEL # Ta rg e t P C IC FG _R D C LK H os t 1 2 4 3 FR A M E# H os t A D[31:0] H os t ADDRESS W R IT E D A T A T a rg e t C /BE [3:0]# C F G -W R B Y TE E N A B L E # DATA TRANSFER H os t IR DY # H os t TR D Y# T a rg e t D EV SEL # T a rg e t P C IC F G _W R 46 XR17C158 áç PCI BUS OCTAL UART REV. 1.1.3 FIGURE 17. DEVICE CONFIGURATION AND UART REGISTERS READ OPERATION FOR A BYTE OR DWORD CLK Host 1 2 3 5 4 7 6 8 9 10 11 FRAME# Host Byte Enable# = DWORD Byte Enable# = BYTE IRDY# WAIT WAIT WAIT Host DWORD TRANSFER Bus CMD WAIT Host WAIT C/BE[3:0]# Data WORD Data BYTE Address Target BYTE TRANSFER AD[31:0] Host TRDY# Target DEVSEL# Target PAR Host Target Data Parity Address Parity Data Parity Active PERR# Active Target SERR# Targe Active t Note: PERR# and SERR are optional in a bus target application. Even Parity is on AD[31:0], C/BE[3:0]#, and PAR PCI_RD1 47 áç PCI BUS OCTAL UART XR17C158 REV. 1.1.3 FIGURE 18. DEVICE CONFIGURATION REGISTERS, UART REGISTERS AND TRANSMIT DATA BURST WRITE OPERATION CLK H o st 1 2 3 5 4 7 6 8 9 10 11 FRAM E# H o st TRDY# Ta rg e t D ata DWORD D a ta D W O R D B yte E nable# = D W O R D DWORD TRANSFER IRDY# H o st B us CMD D ata DWORD DWORD TRANSFER H o st D ata DWORD DWORD TRANSFER C/BE[3:0]# D ata DWORD DWORD TRANSFER A ddress Ta rg e t DWORD TRANSFER AD[31:0] H o st DEVSEL# Ta rg e t PAR H o st Ta rg e t A ddress P arity D ata P arity PERR# D ata P arity D ata P arity D ata P arity A ctive A ctive A ctive D ata P arity A ctive A ctive Ta rg e t SERR# Ta rg e t A ctive N o te : P E R R # a n d S E R R a re o p tio n a l in a b u s ta rg e t a p p lica tio n . E ve n P a rity is o n A D [3 1 :0 ], C /B E [3 :0 ]# , a n d P A R P C I_B W R 48 XR17C158 áç PCI BUS OCTAL UART REV. 1.1.3 FIGURE 19. DEVICE CONFIGURATION REGISTERS, UART REGISTERS AND RECEIVE DATA BURST READ OPERATION CLK H ost 1 18 13 8 23 FRAM E# H ost AD[31:0] D ata AD D ata D ata D ata Target Bus CMD Byte Enab le# = D W O R D DWORD TRANSFER IRDY# H ost TRDY# Target DWORD TRANSFER H ost DWORD TRANSFER C/BE[3:0]# DWORD TRANSFER H ost DEVSEL# Target PAR H ost AD D ata D ata D ata D ata Target Active PERR# Active Active Active Target SERR# Active Target N ote: PER R # and SER R are optional in a bus target application. Even Parity is on AD [31:0], C /BE[3:0]#, and PAR PC I_BR D 49 áç PCI BUS OCTAL UART XR17C158 REV. 1.1.3 FIGURE 20. PCI BUS CLOCK (DC TO 33MHZ) 4 nSec (max) 11 nSec (min) 4 nSec (max) 11 nSec (min) 2.4 V 2.0 V p-t-p (minimum) CLK 0.4 V Tvalid (2-11 nSec) Bused Signal Output Delay Ton (2 nSec min) Tri-State Output Toff (28 nSec Max) Tsetup (7 nSec min) Thold (0 nSec) Bused Signal Input Inputs Valid pci_clk 50 XR17C158 áç PCI BUS OCTAL UART REV. 1.1.3 FIGURE 21. TRANSMIT DATA INTERRUPT AT TRIGGER LEVEL START BIT TX Data STOP BIT DATA BITS (5-8) D0 D1 D2 D3 D4 D5 D6 D7 PARITY BIT 5 DATA BITS 6 DATA BITS NEXT DATA START BIT 7 DATA BITS TX Interrupt at Transmit Trigger Level Clear at Above Trigger Level Set at Below Trigger Level BAUD RATE CLOCK of 16X or 8X TXNOFIFO-1 FIGURE 22. RECEIVE DATA READY INTERRUPT AT TRIGGER LEVEL START BIT RX Data Input STOP BIT DATA BITS (5-8) D0 D1 D2 D3 D4 D5 D6 D7 PARITY BIT RX Data Ready Interrupt at Receive Trigger Level De-asserted at below trigger level First byte that reaches the trigger level Asserted at above trigger level RXFIFO1 ORDERING INFORMATION PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE XR17C158CV 144-TQFP 0°C to +70°C XR17C158IV 144-TQFP -40°C to +85°C 51 áç PCI BUS OCTAL UART XR17C158 REV. 1.1.3 PACKAGE DIMENSIONS 52 XR17C158 áç PCI BUS OCTAL UART REV. 1.1.3 REVISION HISTORY Rev. 1.0.1 March 2000, Preliminary Rev. 1.0.2 March 2001. Corrected patent number, front page; reference to DAN112; corrected CTS#, DSR#, RI# and CD# in figure 11 internal loopback; shaded MCR bit-2 and EFR bit-4 in table 11; fixed “(ISR bit=1)” in figure 12; clarified MCR bits 2 and 6; update 5V electrical characteristics tables with Icc and Isleep current, and added 3.3V electrical characteristics tables Rev. 1.1.0 Deleted ICH and ICL from Electrical tables. Finalized and changed values in 3.3V Electrical table. Corrected spelling. Changed data sheet from Preliminary to Final. Rev. 1.1.1 June 2001. Corrected VIH (2.0 to 2.4V) in DC Electrical Characteristics Tables. Rev. 1.1.2 August 2001. Clarified EECS, PERR# & SERR# hardware pin descriptions, MSR Register and Software Flow Control Functions. Added Programming Examples to explain unloading receive data using the Special Receive FIFO Data with Status. Rev. 1.1.3 Changed VIL max from 0.8 to 0.7V. Changed condition on ICC from CLK=50MHz to “ PCIClk=2MHz, EXT Clock=2Mhz”. Changed Condition on VOL from Iout=6mA to 4mA. Changed Condition on VOH from Iout=-2mA to -1mA. NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2001 EXAR Corporation Datasheet September 2001 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 53 áç XR17C158 PCI BUS OCTAL UART REV. 1.1.3 TABLE OF CONTENTS GENERAL DESCRIPTION ............................................................................................... 1 APPLICATIONS ........................................................................................................................................... FEATURES ................................................................................................................................................ Figure 1. Block Diagram ......................................................................................................................... Figure 2. Pin Out of the Device .............................................................................................................. ORDERING INFORMATION ........................................................................................................................... 1 1 1 2 2 PIN DESCRIPTIONS ....................................................................................................... 3 FUNCTIONAL DESCRIPTION ......................................................................................... 7 PCI Local Bus Interface ........................................................................................................ 7 1.0 XR17C158 REGISTERS ......................................................................................................................... 7 Figure 3. The XR17C158 Register Sets ................................................................................................. 8 1.1 PCI LOCAL BUS CONFIGURATION SPACE REGISTERS ............................................................................... 8 TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS ................................................................. 8 1.2 DEVICE CONFIGURATION REGISTER SET ................................................................................................................ 9 TABLE 2: XR17C158 DEVICE CONFIGURATION REGISTERS ..................................................................... 10 TABLE 3: DEVICE CONFIGURATION REGISTERS SHOWN IN BYTE ALIGNMENT ........................................... 12 TABLE 4: DEVICE CONFIGURATION REGISTERS SHOWN IN DWORD ALIGNMENT ....................................... 12 1.2.1 The Interrupt Status Register .................................................................................................................. 12 Figure 4. The Global Interrupt Register, INT0, INT1, INT2 and INT3 .................................................. 13 TABLE 5: UART CHANNEL [7:0] INTERRUPT SOURCE ENCODING ............................................................. 14 TABLE 6: UART CHANNEL [7:0] INTERRUPT CLEARING: ........................................................................... 14 1.2.2 General Purpose 16-bit Timer/Counter. [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (default 0xXX-XX-0000) 14 Figure 5. Timer/Counter circuit. ............................................................................................................ 14 TABLE 7: TIMER CONTROL REGISTERS ............................................................................................... 15 1.2.3 8XMODE [7:0] (default 0x00) .................................................................................................................. 1.2.4 REGA [15:8] is reserved (default 0x00) .................................................................................................. 1.2.5 RESET [23:16] (default 0x00) ................................................................................................................. 1.2.6 SLEEP [31:24]................................................................................................................... (default 0x00) 1.2.7 Device Identification and Revision .......................................................................................................... 1.2.9 Multi-Purpose Inputs and Outputs ........................................................................................................... 1.2.10 MPIO REGISTER .................................................................................................................................. 1.2.8 REGB Register ........................................................................................................................................ 15 15 15 16 16 16 16 16 Figure 6. Multipurpose input/output internal circuit .............................................................................. 17 2.0 CRYSTAL OSCILLATOR / BUFFER .................................................................................................... 18 3.0 TRANSMIT AND RECEIVE DATA ....................................................................................................... 18 3.1 FIFO DATA LOADING AND UNLOADING THROUGH THE DEVICE CONFIGURATION REGISTERS IN 32-BIT FORMAT. 18 Figure 7. Typical oscillator connections ............................................................................................... 18 3.2 FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR AND RHR IN 8BIT FORMAT. 20 TABLE 8: TRANSMIT AND RECEIVE DATA REGISTER IN BYTE FORMAT, 16C550 COMPATIBLE ..................... 20 4.0 UART ..................................................................................................................................................... 20 4.1 PROGRAMMABLE BAUD RATE GENERATOR ........................................................................................................... 20 Figure 8. Baud Rate Generator ............................................................................................................ 21 TABLE 9: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING .. 21 4.2 AUTOMATIC HARDWARE (RTS/CTS OR DTR/DSR) FLOW CONTROL OPERATION .................................................. 22 Figure 9. Auto RTS/DTR and CTS/DSR Flow Control Operation ........................................................ 23 4.3 INFRARED MODE ................................................................................................................................................. 23 Figure 10. Infrared Transmit Data Encoding and Receive Data Decoding .......................................... 24 4.4 INTERNAL LOOPBACK ........................................................................................................................................... 24 Figure 11. Internal Loop Back .............................................................................................................. 25 4.5 UART CHANNEL CONFIGURATION REGISTERS AND ADDRESS DECODING. ......................................... 25 I áç XR17C158 PCI BUS OCTAL UART REV. 1.1.3 TABLE 10: UART CHANNEL CONFIGURATION REGISTERS. ........................................................... 26 TABLE 11: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY EFR BIT-4. ........................................................................................................................................ 27 4.6 TRANSMITTER ...................................................................................................................................................... 28 4.6.1 Transmit Holding Register (THR) ............................................................................................................ 28 4.6.2 Transmitter Operation in non-FIFO ......................................................................................................... 28 Figure 12. Transmitter Operation in non-FIFO Mode ........................................................................... 28 4.6.3 Transmitter Operation in FIFO ................................................................................................................. 28 4.6.4 Auto RS485 Operation ............................................................................................................................ 28 Figure 13. Transmitter Operation in FIFO and Flow Control Mode ...................................................... 29 4.7 RECEIVER ........................................................................................................................................................... 29 4.7.1 Receiver Operation in non-FIFO Mode .................................................................................................. 30 Figure 14. Receiver Operation in non-FIFO Mode ............................................................................... 30 4.7.2 Receiver Operation with FIFO ................................................................................................................. 30 4.8 REGISTERS .......................................................................................................................................................... 30 Figure 15. Receiver Operation in FIFO and Flow Control Mode .......................................................... 30 IER versus Receive FIFO Interrupt Mode Operation ......................................................... 31 IER versus Receive/Transmit FIFO Polled Mode Operation ............................................. 31 TABLE 12: INTERRUPT SOURCE AND PRIORITY LEVEL .............................................................................. 32 TABLE 13: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION ..................................................... 33 TABLE 14: PARITY SELECTION ................................................................................................................. 34 TABLE 15: AUTO RS485 HALF-DUPLEX DIRECTION CONTROL DELAY FROM TRANSMIT-TO-RECEIVE .......... 37 SCRATCH PAD REGISTER (SPR) ....................................................................................................... 37 FEATURE CONTROL REGISTER (FCTR) .......................................................................................... 37 TABLE 16: 16 SELECTABLE HYSTERESIS LEVELS WHEN TRIGGER TABLE-D IS SELECTED ......................... 38 TABLE 17: SOFTWARE FLOW CONTROL FUNCTIONS ................................................................................. 39 TABLE 18: TYPICAL APPLICATIONS OF SOFTWARE FLOW CONTROL FUNCTIONS ....................................... 39 EFR[6]: AUTO RTS OR DTR FLOW CONTROL ENABLE ............................................................................. 39 TABLE 19: UART RESET CONDITIONS ............................................................................................... 40 5.0 programming Examples ...................................................................................................................... 41 5.1 UNLOADING RECEIVE DATA USING THE SPECIAL RECEIVE FIFO DATA WITH STATUS ............................................ 41 ABSOLUTE MAXIMUM RATINGS ................................................................................. 42 ELECTRICAL CHARACTERISTICS .............................................................................. 42 DC ELECTRICAL CHARACTERISTICS FOR 5V SIGNALING ............................................................. 42 AC ELECTRICAL CHARACTERISTICS FOR 5V SIGNALING .............................................................. 43 Figure 16. PCI Bus Configuration Space Registers Read and Write operation ................................... 46 Figure 17. Device Configuration and UART Registers Read Operation for a Byte or DWORD ........... 47 Figure 18. Device Configuration registers, UART Registers and Transmit Data Burst Write Operation 48 Figure 19. Device Configuration Registers, UART Registers and Receive Data Burst Read Operation 49 Figure 20. PCI Bus Clock (DC to 33MHz) ............................................................................................ 50 Figure 21. Transmit Data Interrupt at Trigger Level ............................................................................. 51 Figure 22. Receive Data Ready Interrupt at Trigger Level ................................................................... 51 ORDERING INFORMATION ........................................................................................... 51 PACKAGE DIMENSIONS ............................................................................................... 52 REVISION HISTORY .................................................................................................................................. 53 TABLE OF CONTENTS ................................................................................................................................. I II