ETC XRD54L12AID

XRD54L08/L10/L12
3V, Low Power, Voltage Output
Serial 8/10/12-Bit DAC Family
May 2000-2
FEATURES
APPLICATIONS
D 8/10/12-Bit Resolution
D Digital Calibration
D Operates from a Single 3V Supply
D Buffered Voltage Output: 13ms Typical Settling Time
D 145mW Total Power Consumption (typ)
D Battery Operated Instruments
D Remote Industrial Devices
D Cellular Telephones
D Guaranteed Monotonic Over Temperature
D Motion Control
D Flexible Output Range: 0V to VDD
D 8 Lead SOIC and PDIP Package
D VXCO Control
D Power On Reset
D Comparator Level Setting
D Serial Data Output for Daisy Chaining
GENERAL DESCRIPTION
The XRD54L08/L10/L12 are low power, voltage output
digital-to-analog converters (DAC) for +3V power supply
operation. The parts draw only 50mA of quiescent current
and are available in both an 8-lead PDIP and SOIC
package.
The XRD54L08/L10/L12 have a 3 wire serial port with an
output allowing the user to daisy chain several of them
together. The serial port will support both Microwiret,
SPIt, and QSPIt standards.
The outputs of the XRD54L08/L10/L12 are set at a gain of
+2. The output short circuit current is 7mA typical.
ORDERING INFORMATION
Part No.
Package
Operating
Temperature Range
XRD54L08AID
8 Lead 150 Mil JEDEC SOIC
-40°C to +85°C
XRD54L08AIP
8 Lead 300 Mil PDIP
-40°C to +85°C
XRD54L10AID
8 Lead 150 Mil JEDEC SOIC
-40°C to +85°C
XRD54L10AIP
8 Lead 300 Mil PDIP
-40°C to +85°C
XRD54L12AID
8 Lead 150 Mil JEDEC SOIC
-40°C to +85°C
XRD54L12AIP
8 Lead 300 Mil PDIP
-40°C to +85°C
Rev. 1.30
E2000
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z (510) 668-7017
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XRD54L08/L10/L12
BLOCK DIAGRAM
VREFIN
2n
Switch
Matrix
+
R
AGND
VOUT
R
VDD
CS
SCLK
SDIN
Shift Register
VDD
DOUT
Power On
Reset
Figure 1. Block Diagram
PIN CONFIGURATION
SDIN
1
8
VDD
SCLK
CS
DOUT
2
7
3
6
4
5
VOUT
VREFIN
AGND
SDIN
SCLK
CS
DOUT
8 Lead SOIC (Jedec, 0.150”)
Symbol
1
SDIN
Serial Data Input
2
SCLK
Serial Data Clock
Description
3
CS
4
DOUT
Serial Data Output
5
AGND
Analog Ground
6
VREFIN
Voltage Reference Input
7
VOUT
DAC Output
8
VDD
Supply Voltage
Chip Select (Active High)
Rev. 1.30
2
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8
2
7
3
6
4
5
VDD
VOUT
VREFIN
AGND
8 Lead PDIP (0.300”)
PIN DESCRIPTION
Pin #
1
XRD54L08/L10/L12
ELECTRICAL CHARACTERISTICS
Test Conditions: VDD= 3V, GND= 0V, REFIN= 1.000V (External), RL= 10kW, CL= 100pF, TA= TMIN to TMAX,
Unless Otherwise Noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
Static Performance XRD54L08
N
Resolution
8
Bits
INL
Relative Accuracy
0.25
0.5
LSB
DNL
Differential Nonlinearity
0.25
0.5
±LSB
VOS
Offset Error
3
8
mV
0
TCVOS
Offset Tempco
PSRR
Offset-Error Power-Supply
Rejection Ratio
0.5
1
mV
Gain Error
0.1
0.4
%FS
TCGE
Gain-Error Tempco
10
PSRR
Power-Supply
Rejection Ratio
0.1
GE
2
Guaranteed Monotonic
ppm/°C
2.5V ± VDD ± 3.5V
ppm/°C
1.25
mV
2.5V ± VDD ± 3.5V, Measured at
FS
Static Performance XRD54L10
N
Resolution
10
Bits
INL
Relative Accuracy
0.5
1
LSB
DNL
Differential Nonlinearity
0.50
0.75
±LSB
VOS
Offset Error
3
8
0
mV
TCVOS
Offset Tempco
PSRR
Offset-Error Power-Supply
Rejection Ratio
0.5
1
mV
Gain Error
0.1
0.4
%FS
GE
2
TCGE
Gain-Error Tempco
10
PSRR
Power-Supply
Rejection Ratio
0.1
Guaranteed Monotonic
ppm/°C
2.5V ± VDD ± 3.5V
ppm/°C
1.25
mV
2.5V ± VDD ± 3.5V, Measured at
FS
Static Performance XRD54L12
N
Resolution
INL
Relative Accuracy
DNL
Differential Nonlinearity
VOS
Offset Error
12
Bits
2
0.5
0
3
4
LSB
-1
LSB
1.25
LSB
8
mV
TCVOS
Offset Tempco
PSRR
Offset-Error Power-Supply
Rejection Ratio
1.0
1.25
mV
Gain Error
0.1
0.4
%FS
TCGE
Gain-Error Tempco
10
PSRR
Power-Supply
Rejection Ratio
0.1
GE
2
Rev. 1.30
3
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Guaranteed Monotonic
ppm/°C
2.5V ± VDD ± 3.5V
ppm/°C
1.25
mV
2.5V ± VDD ± 3.5V, Measured at
FS
XRD54L08/L10/L12
ELECTRICAL CHARACTERISTICS (CONT’D)
Test Conditions: VDD= 3V, GND= 0V, REFIN= 1.000V (External), RL= 10kW, CL= 100pF, TA= TMIN to TMAX,
Unless Otherwise Noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
VDD--0.4
V
4
mV
VOUT = 2V, RL=2kW
Voltage Output (VOUT) XRD54L08/L10/L12
VO
Output Voltage Range
0
VREG
Output Load Regulation
2
+ISC
Short-Circuit Current, Sink
11
mA
VOUT = VDD
-ISC
Short-Circuit Current, Source
2.5
mA
VOUT = GND
Voltage Reference Input (VREFIN) XRD54L08/L10/L12
VREFIN
RIN
TCRIN
CIN
ACFT
Voltage Range
0
Input Resistance
40
Input Resistance Tempco
VDD
V
65
kW
1500
ppm/°C
Input Capacitance
32
AC Feedthrough
-80
40
Output Swing Limited, Not Code
Dependent
pF
Not Code Dependent
dB
REFIN = 1kHz, 2Vp-p, SDIN=000h
Digital Inputs (SDIN, SCLK, CS) XRD54L08/L10/L12
VIH
Input High
2.0
V
VIL
Input Low
0.8
V
IIN
Input Current
±1
mA
CIN
Input Capacitance
10
VIN=0V or VDD
pF
Digital Output (DOUT) XRD54L08/L10/L12
VOH
Output High
VOL
Output Low
VDD-1
0.4
V
ISOURCE=4mA
V
ISINK=4mA
V/ms
TA=+25°C
Dynamic Performance XRD54L08/L10/L12
SR
ts
DFT
SINAD
Voltage-Output Slew Rate
0.13
0.21
Voltage-Output Settling Time
13
Digital Feedthrough
1
15
nV-s
Signal-to-Noise Plus Distortion
68
dB
ms
±1/2LSB, VOUT=2V
CS=VDD, SDIN=SCLK=100kHz
VREFIN=1kHz, 2Vp-p F.S.,
SDIN=Full Scale
--3dB BW=250kHz
Power Supply XRD54L08/L10/L12
VDD
Positive Supply Voltage
IDD
Power Supply Current
2.5
35
3.5
V
60
mA
Switching Characteristics XRD54L08/L10/L12
tCSS
CS Setup Time
10
tCSH0
SCLK Fall to CS Fall Hold Time
5
20
ns
tCSH1
SCLK Fall to CS Rise Hold TIme
0
ns
Notes:
1 Total supply current consumption = I
DD + IREF + (VOUT / 70K.)
Rev. 1.30
4
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ns
All Inputs=0V or VDD,
Output=No Load, VO=0V,
IREF Not Included
XRD54L08/L10/L12
ELECTRICAL CHARACTERISTICS (CONT’D)
Test Conditions: VDD= 3V, GND= 0V, REFIN= 1.000V (External), RL= 10kW, CL= 100pF, TA= TMIN to TMAX,
Unless Otherwise Noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
tCH
SCLK High Width
20
35
ns
tCL
SCLK Low Width
20
35
ns
tDS
DIN Setup Time
10
45
ns
tDH
DIN Hold Time
0
tDO
DOUT Valid Propagation Delay
Conditions
ns
8
15
ns
tCSW
CS High Pulse Width
20
40
ns
tCS1
CS Rise to SCLK Rise Setup
Time
10
20
ns
CL= 50pF
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V, +5V
Package Power Dissipation Ratings (TA= +70°C)
PDIP (derate 9mW/°C above +70°C) . . . . 117mW
SOIC (derate 6mW/°C above +70°C) . . . 155mW
Operating Temperature Range . . . . . -40°C to + 85°C
Storage Temperature Range . . . . . . -65°C to +165°C
Lead Temperature (soldering, 10 sec) . . . . . . +300°C
Digital Input Voltage to GND . . . . . . -0.3V, VDD +0.3V
VREFIN . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V, VDD +0.3V
VOUT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD, GND
Continuous Current, Any Pin . . . . . . . . -20mA, +20mA
Notes
1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps
(HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short
transients outside the supplies of less than 100mA for less than 100ms.
Rev. 1.30
5
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XRD54L08/L10/L12
TIMING
CS
tCSW
tCSH0
tCSS
tCH
tCL
tCSH1
SCLK
tDS
tDH
tCS1
SDIN
tD0
DOUT
Figure 2. Timing Diagram
Input
Output
1111
1111
(0000)
+ 2 (VREFIN) 255
256
1000
0001
(0000)
+ 2 (VREFIN) 129
256
1000
0000
(0000)
0111
1111
(0000)
+ 2 (VREFIN) 127
256
0000
0001
(0000)
+ 2 (VREFIN) 1
256
0000
0000
(0000)
+ 2 (VREFIN) 128 = + VREFIN
256
0V
Note:
Write 8-bit data words with four sub-LSB 0s because the DAC input latch
is 12 bits wide.
Table 1. Binary Code Table
Rev. 1.30
6
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XRD54L08/L10/L12
THEORY OF OPERATION
Fixed Gain +2 Voltage Output Amplifier
XRD54L08/L10/L12 Description
A high open-loop gain operational amplifier buffers the
resistor string with a stable, fixed gain of +2. The voltage
output will settle within 13 s. The output is short circuit
protected and can regulate an output load of 2V into 2k
within 2mV at 25°C.
The XRD54L08/L10/L12 are micro-power, voltage
output, serial daisy-chain programmable DACs operating
from a single 3V power supply. The DACs are built on a
0.6 micron CMOS process. The features of these DACs
make it well suited for industrial control, low distortion
audio, battery operated devices and cost sensitive
designs that want to minimize pin count on ICs.
While the reference input will accept a voltage from
rail-to-rail, the linear input voltage range is constrained by
the output swing of the fixed +2 closed-loop gain amplifier.
Full scale output swing is achieved with an external
reference of approximately 1/2 VDD. The reference
voltage
must
be
positive
because
the
XRD54L08/L10/L12 DAC is non-inverting.
Resistor String DAC
A resistor string architecture converts digital data using a
switch matrix to an analog signal as shown in Figure 3.
Serial Daisy-Chainable Digital Interface
VREFIN
2n
AGND
CS
SCLK
SDIN
Switch
Matrix
+
R
The three wire serial interface includes a DOUT to enable
daisy-chaining of several DACs. This minimizes pin
count necessary of digital asics or controllers to address
multiple DACS. The serial interface is designed for
CMOS logic levels. Timing is shown in Figure 2. The
binary coding table (Table 1) shows the DAC transfer
function.
VOUT
R
VDD
Shift Register
VDD
DOUT
A power on reset circuit forces the DAC to reset to all “0”s
on power up.
Power On
Reset
APPLICATION NOTES
Figure 3. XRD54L08/L10/L12 DAC Architecture
Serial Interface
The resistor string architecture provides a non-inverted
output voltage (VOUT) of the reference input (VREFIN) for
single supply operation while maintaining a constant input
resistance. Unlike inverted R-2R architectures the
reference input resistance will remain constant
independent of code. This greatly simplifies the analog
driving source requirements for the reference voltage and
minimizes distortion. Similarly input capacitance varies
only approximately 4pF over all codes.
The XRD54L08/L10/L12 family has a three wire serial
interface that is compatible with Microwiret, SPIt and
QSPIt standards. Typical configurations are shown in
Figure 4 and Figure 5. Maximum serial port clock rate is
limited by the minimum pulse width of tCH and tCL.
Feedthrough noise from the serial port to the analog
output (VOUT) is minimized by lowering the frequency of
the serial port and holding the digital edges to >5ns.
Rev. 1.30
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XRD54L08/L10/L12
+5V
MP5010
1.25V
VREFIN
SK
Microwiret
Port
SCLK
XRD54L12
SO
SDIN
I/O
CS
VOUT
0-2.5V
VDD
GND
+3V
0.1mF
Figure 4. Typical Microwiret Application Circuit
+5V
MP5010
1.25V
VREFIN
SPI t
Port
SK
SCLK
MOSI
SDIN
XRD54L10
I/O
VOUT
CS
VDD
GND
0.1mF
Figure 5. Typical SPIt Application Circuit
Rev. 1.30
8
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0-2.5V
+3V
XRD54L08/L10/L12
DAC
n
SDIN
MSB
X
X
X
X
DOUT
Figure 6. Shift Register Format
The DACs are programmed by a 16 bit word of serial data.
The format of the serial input register is shown in Figure 6.
The leading 4 bits are not used to update the DAC. If the
DAC is not daisy-chained then only a 12 bit serial word is
needed to program the DAC. The next 8, 10 or 12 bits
after the 4 leading bits are data bits. The XRD54L08’s first
8 bits are valid data and the trailing 4 bits must be set to 0.
Figure 7 demonstrates the 16 bit digital word for the 8,
10,12 bit DACs.
Part
Leading
Unused
Bits
XRD54L12
XXXX
XXXXXXXX
None
XRD54L10
XXXX
XXXXXXXX
00
XRD54L08
XXXX
XXXXXXXX
0000
Data Bits
MSB
LSB
ACFT Feedthrough (DAC Code = 0)
AC Feedthrough from VREFIN to VOUT is minimized with
low impedance grounding as shown in Figure 7. If the
DAC data is set to all “0”s then VOUT is a function of the
divider between the DAC string impedance and ground
impedance. See the Power Supply and Grounding
section for recommendations.
The typical AC
feedthrough for a 1kHz 2Vpp signal with code = 0 is
-80dB.
Trailing
“0”
Bits
VREFIN
XRD54L08/L10/L12
RIN
--
Table 2. 16-Bit Digital Word Register for XRD54L08,
XRD54L10, XRD54L12.
+
VOUT
GND
SCLK should be held low when CS transitions low. Data is
clocked in on the rising edge of SCLK when CS is low.
SDIN data is held in a 16 bit serial shift register. The DAC
is updated with the data bits on the rising edge of CS.
When CS is high data is not shifted into the
XRD54L08/L10/L12.
RGND
Analog GND
Daisy-Chaining
Figure 7. ACFT Feedthrough Equivalent
Circuit, DAC Code =0
The digital output port (DOUT) has a 4mA drive for greater
fan-out capability when daisy-chaining. DOUT allows
cascading of multiple DACs with the same serial data
stream. The data at SDIN appears at DOUT after 16 clock
cycles plus one clock width (tCH) and a propagation delay
(tDO). DOUT remains in the state of the last data bit when
CS is high. DOUT changes on the falling edge of SCLK
when CS is low.
Compatible with MAX515 & MAX539
The XRD54L08/L10/L12 family of DACs are functionally
campatible with the MAX515 & MAX539 while providing
significant improvements.
The XRD54L08/L10/L12
DACs have lower power, faster serial ports, and a
constant reference impedance to minimize the reference
driving requirements and maximize system linearity while
Any number of DACs can be connected in this way by
connecting DOUT of one DAC to SDIN of the next DAC.
Rev. 1.30
9
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XRD54L08/L10/L12
operating from a 3V supply versus 5V for the MA515 and
MAX539. The DOUT port also has 4mA driving capability
for greater fan-out when daisy-chaning to other digital
inputs.
Power Supply and Grounding
Best parametric results are obtained by powering the
XRD54L08/L10/L12 family of DACs from an analog +3V
power supply and analog ground. Digital power supplies
and grounds should be separated or connected to the
analog supplies and grounds only at the low-impedance
power-supply source. This is best accomplished on a
multilayer PCB with dedicated planes to ground and
power. The DACs should be locally bypassed with both
0.1 F and 2.2 F capacitors mounted as close as possible
to the power supply pin (VDD). Surface mount ceramic
capacitors are recommended for low impedance, wide
band power supply bypass. If only one +3V power supply
is available for both analog and digital circuity isolate the
analog power supply to the XRD54L08/L10/L12 DAC with
an inductor or ferrite bead before the local bypass
capacitors.
Monotonicity
The XRD54L08/L10/L12 family of DACs are monotonic
over the entire temperature range.
Micro-Power Operation
The XRD54L08/L10/L12 are the lowest power DACs in
their class. The quiescent current rating does not include
the reference ladder current. Power can be saved when
the part is not in use by setting the DAC code to all “0”s
assuming the output load is referenced to ground. This
minimizes the DAC output load current. An analog switch
placed in series with the reference ladder can toggle the
reference voltage off when the circuit is inactive to
minimize power consumption.
PERFORMANCE CHARACTERISTICS
0.04
LSB
--0.04
--0.12
--0.20
0
64
128
192
255
CODE
Figure 8. XRD54L08 INL (For XRD54L10 and XRD54L12, Scale Axes Accordingly)
0.10
LSB
0.06
0.02
0
--0.02
--0.06
0
64
128
CODE
192
255
Figure 9. XRD54L08 DNL (For XRD54L10 and XRD54L12, Scale Axes Accordingly)
Rev. 1.30
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XRD54L08/L10/L12
Figure 10. Output Source Current
vs. Output Voltage
Figure 11. Output Sink Current
vs. Output Voltage
I (mA)
16
2mA/div
0
--4
3
.5V/div
Vout (V)
Figure 12. Output Sink and Source Current vs. Output Volatge
Rev. 1.30
11
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0
XRD54L08/L10/L12
Figure 13. Voltage Output Settling Time (ts),
VDD = 5V, VREFIN = 1V, No Load
40
38
36
34
Idd ( uA)
32
30
28
26
24
22
20
--40
--20
0
20
40
Temp ( C )
Figure 14. IDD vs. Temperature
Rev. 1.30
12
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60
85
100
XRD54L08/L10/L12
8
7
Gain (dB)
6
5
4
3
2
1
0
-1
-2
10
100
1000
Frequency (KHz)
Figure 15. Closed Loop Gain vs. Frequency
0
-20
Phase (°)
-40
-60
-80
-100
-120
10
100
Frequency (KHz)
Figure 16. Closed Loop Phase vs. Frequency
Microwiret
is a trademark of National Semiconductor Corproation.
SPIt and QSPIt are trademarks of Motorola Corporation.
Rev. 1.30
13
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1000
XRD54L08/L10/L12
8 LEAD PLASTIC DUAL-IN-LINE
(300 MIL PDIP)
Rev. 2.00
8
5
1
4
E1
E
D
A2
A
Seating
Plane
L
A1
B
e
eA
eB
B1
INCHES
SYMBOL
a
MILLIMETERS
MIN
MAX
MIN
A
0.145
0.210
3.68
MAX
5.33
A1
0.015
0.070
0.38
1.78
A2
0.115
0.195
2.92
4.95
B
0.014
0.024
0.36
0.56
B1
0.030
0.070
0.76
1.78
C
0.008
0.014
0.20
0.38
D
0.348
0.430
8.84
10.92
E
0.300
0.325
7.62
8.26
E1
0.240
0.280
6.10
7.11
e
0.100 BSC
2.54 BSC
eA
0.300 BSC
7.62 BSC
eB
0.310
0.430
7.87
10.92
L
0.115
0.160
2.92
4.06
a
0°
15°
0°
15°
Note: The control dimension is the inch column
Rev. 1.30
14
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C
XRD54L08/L10/L12
8 LEAD SMALL OUTLINE
(150 MIL JEDEC SOIC)
Rev. 1.00
D
8
5
E
H
4
C
A1
A
Seating
Plane
a
e
B
L
INCHES
SYMBOL
MILLIMETERS
MIN
MAX
MIN
MAX
A
0.053
0.069
1.35
1.75
A1
0.004
0.010
0.10
0.25
B
0.013
0.020
0.33
0.51
C
0.007
0.010
0.19
0.25
D
0.189
0.197
4.80
5.00
E
0.150
0.157
3.80
4.00
e
0.050 BSC
1.27 BSC
H
0.228
0.244
5.80
6.20
L
0.016
0.050
0.40
1.27
a
0°
8°
0°
8°
Note: The control dimension is the millimeter column
Rev. 1.30
15
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XRD54L08/L10/L12
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary
depending upon a user’s specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.
All trademarks and registered trademarks are property of their respective owners.
Copyright 2000 EXAR Corporation
Datasheet May 2000
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 1.30
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