XR-T5684 ...the analog plus company TM Low Power T1 Analog Interface June 1997-3 FEATURES APPLICATIONS Fully Integrated T1 Transceiver Interfacing T1 Network Equipment such as Multiplexers, Channel Banks and DSX-1 Switching Systems Low Power Consumption (normally 225mW) Recovered Data and Clock Outputs Interfacing Customer Premises Equipment such as CSUs, PBXs, T1 Measurement and Test Equipment Driver Performance Monitor Internal Transmit LBO for Line Lengths Between 0 to 655 Feet Compliance with TR-TSY-000499, 43802 and 43801 Input Jitter Tolerance Specifications GENERAL DESCRIPTION The XR-T5684 is a fully integrated PCM line transceiver intended for DSX-1 digital cross-connect applications. It combines both transmit and receive circuitry in a 28 pin PLCC or PDIP package. The receiver extracts data from AMI coded input signal, and outputs synchronized clock and unipolar RPOS and RNEG data by means of an external 8X or 16X oversampling clock. The oversampling clock is necessary only for applications where the clock recovery feature is required. The transmitter of the device pre-shapes the transmit pulse internally, providing the appropriate pulse shape at the cross-connect for line lengths ranging from 0 to 655 feet. The XR-T5684 is manufactured using advanced CMOS technology and requires only a single +5V power supply. ORDERING INFORMATION Part No. Package Operating Temperature Range XR-T5684IJ 28 Lead PLCC -40 to + 85°C XR-T5684IP 28 Lead 600 Mil PDIP -40 to + 85°C Rev. 1.01 1997 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 FAX (510) 668-7017 1 XR-T5684 BLOCK DIAGRAM 12 LOS Loss of Signal Detection Data Comparators 6 + – RPOS 19 RTIP Peak 20 RRING Det. Data Retiming Circuit 7 + – Clock Recovery 1 LCLK MODE PD CLKDIS RVDD 5 9 10 21 22 +5 RGND Figure 1. XR-T5684 Receive Side Rev 1.01 2 8 RNEG RCLK XR-T5684 2 TCLK 13 Transmit Control Logic 3 TPOS TNEG 4 Output Pulse Shaper TTIIP Output Driver 16 TRING 26 TEST 28 TAOS LEN0 23 24 LEN1 LEN2 25 17 Driver Performance Monitor MTIP MRING 18 15 TVDD GND NC +5 14 27 Figure 2. XR-T5684 Transmit Side Rev. 1.01 3 11 DPM XR-T5684 TNEG TPOS TCLK LCLK TAOS N/C TSET PIN CONFIGURATION 4 3 2 1 28 27 26 MODE 5 25 LEN2 RPOS 6 24 LEN1 RNEG 7 23 RCLK 8 22 PD 9 21 CLKDS 10 20 DPM 11 19 LEN0 RGND RVDD RRING RTIP 18 MRNG 17 MTIP 16 TRNG 15 TVDD LOS 14 TGND 13 TTIP 12 LCLK TCLK TPOS TNEG MODE RPOS RNEG RCLK PD CLKDS DPM 28 Lead PLCC 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 TAOS N/C TEST LEN2 LEN1 LEN0 RGND RVDD RRING RTIP MRING 10 19 11 18 LOS TTIP 12 17 13 16 MTIP TRING TGND 14 15 TVDD 28 Lead PDIP (0.600”) PIN DESCRIPTION Pin # Symbol Type Description 1 LCLK I Oversampling Clock. 8X or 16X input clock for receive clock recovery circuit. 8X=12.352MHz±200ppm with pin 9 set to low. 16X=24.704MHz ±200ppm with pin 9 set to high. 2 TCLK I Transmit Clock. T1=1.544MHz±50ppm. 3 TPOS I Transmit Positive Data. A positive NRZ data on this pin causes a positive pulse to be transmitted on TTIP. TPOS is sampled on the falling edge of TCLK. 4 TNEG I Transmit Negative Data. A positive NRZ data on this pin causes a negative pulse to be transmitted on TRING. TNEG is sampled on the falling edge of TCLK. 5 MODE I Receive Output Data Select. With this pin set to high, the extracted data at RPOS and RNEG are re-timed using the recovered clock RCLK. With this pin set to low, the received data have no relation to RCLK and are typically stretched by 80nS before being sent to the output. This pin is pulled down internally. 6 RPOS O Receive Positive Data Output. A positive pulse on this pin corresponds to a positive pulse on RTIP. 7 RNEG O Receive Negative Data Output. A positive pulse on this pin corresponds to a positive pulse on RRING. 8 RCLK O Receive Clock Output. Recovered clock using oversampling clock applied to pin 1. See MODE select of pin 5 and PD of pin 9. 9 PD I Programmable Divider. The state of this pin determines the oversampling clock applied to pin 1. When LCLK=16X1.544MHz, set PD to high. When LCLK=8X1.544MHz, set PD to low. This pin is pulled down internally. 10 CLKDS I Clock Disable. With this pin set to high, the recovered clock at pin 8 is disabled. This function is provided for applications where upon input data loss, the output clock can be inhibited by connecting LOS to CLKDS externally. This pin is pulled down internally. 11 DPM O Driver Performance Monitor. Used as an early warning signal on non-functioning T1 links. If no signal is present on MTIP and MRING for 63 clock cycles. DPM goes high until a next pulse is detected. Rev 1.01 4 XR-T5684 PIN DESCRIPTION (CONT’D) Pin # Symbol Type Description 12 LOS O Loss of Signal. This pin goes high either when the input signal at RTIP and RRING drops to below 0.4V peak or after 175 zeros are detected. The 175 zeros detection is active only when LCLK is applied. 13 TTIP O Transmit Positive Data. Transmit AMI signal is driven to the line via a step-up transformer from this pin. 14 TGND Transmitter Supply Ground. This pin can be connected to RGND externally. 15 TVDD O 5 V ±5% Transmitter Supply. 16 TRING O Transmit Negative Data. Transmit AMI signal is driven to the line via a step-up transformer from this pin. 17 MTIP I Driver Performance Monitor Input. This pin is normally connected to TTIP for monitoring the driver’s activity. It is pulled high internally. 18 MRING I Driver Performance Monitor Input. This pin is normally connected to TRING for monitoring the driver’s activity. It is pulled high internally. 19 RTIP I Receive Tip Input. The AMI receive signal is input to this pin via a centre-tapped transformer. 20 RRING I Receive Ring Input. The AMI receive signal is input to this pin via a centre-tapped transformer. 21 RVDD 22 RGND 23 LEN0 I Pulse Shaper Select Pin. Least significant bit. 24 LEN1 I Pulse Shaper Select Pin. Second significant bit. 25 LEN2 I Pulse Shaper Select Pin. Most significant bit. 26 TEST I Factory Test Pin. This pin must be grounded for normal operation. 27 N/C 28 TAOS 5 V ±5% Receive Supply. This pin can be connected to TVDD externally. Receive Supply Ground. This pin is also connected to the substrate of the device. No Connection Pin. This pin can be grounded or left floating. I Transmit All Ones Select. Setting TAOS high causes continuous AMI ones to be transmitted to the line at the frequency set by TCLK. Rev. 1.01 5 XR-T5684 ELECTRICAL CHARACTERISTICS Test Conditions: TA = -40 to + 85C, RVDD and TVDD = 5V ± 5%, RGND and TGND = 0V. Symbol Parameter Min. Typ. Max. Unit Conditions 4.75 5 5.25 V 400 mW 100% ones density & max. line length @ 5.25V and with 16X oversampling clock running. mW 50% ones density & 300 feet line length @5.0V and with over-sampling clock disabled. DC ELECTRICAL CHARACTERISTICS Recommended Operating Conditions VDD/TVDD DC Supply Voltage PD Total Power Disapation PD Normal Power Dissipation 225 Inputs VIH High Level Input1 VIL Low Level Input1 IIL Input Leakage Current 2.0 V 0.8 V 10 A Pins = TCLK, TPOS, TNEG, LEN0/1/2. Outputs VOH High Level Output2 VOL Output2 Low Level 2.4 V 0.4 V 3.6 V Analog Specifications VPA AMI Output Pulse Amplitudes TXJA Jitter added by the transmitter 2.4 10Hz - 40KHz3 Broad Receiver Sensitivity Below DSX(0dB=2.4V) RLOS Receiver Loss of Signal Threshold Number of Consecutive Zeros before LOS RTH 0.025 Band3 RXS 3.0 UI 0.05 UI 6 dB 0.4 160 Receiver Data Slicing Threshold 175 V 190 70 % of peak 1.544 MHz AC CHARACTERISTICS TCLKf Clock Frequency TCLK Clock Duty Cycle LCLKf LCLKf 40 Frequency 8X 50 16X 35 50 Notes 1 All input pins except RTIP, RRING, MTIP and MRING. 2 All output pins except TTIP and TRING. 3 Input clock to TCLK is jitter free. 4 Pin 5 Set to low. Rev 1.01 6 % MHz 24.704 LCLK Clock Tolerance LCLK Clock Duty Cycle 60 12.352 MHz 200 ppm 65 % Measured at DSX-1 using a 1:1.36 step up transformer with all line length select as shown in Table 1. XR-T5684 ELECTRICAL CHARACTERISTICS (CONT’D) Test Conditions: TA = -40 to + 85C, RVDD and TVDD = 5V ± 5%, RGND and TGND = 0V. Symbol Parameter Min. Typ. Max. Unit tsu TPOS/TNEG to TCLK Setup Time 25 ns tho TCLK to TPOS/TNEG Hold Time 25 ns tdr RTIP/RRING Rising to RPOS/ RNEG Rising4 15 30 120 ns tdf RTIP/RRING Falling to RPOS/ RNEG Falling4 60 120 250 ns RCLK Duty Cycle 50 % tsu RPOS/RNEG to RCLK Falling Setup Time 300 ns tho RCLK Falling to RPOS/RNEG Hold Time 324 ns Notes 1 All input pins except RTIP, RRING, MTIP and MRING. 2 All output pins except TTIP and TRING. 3 Input clock to TCLK is jitter free. 4 Pin 5 Set to low. ABSOLUTE MAXIMUM RATINGS Supply Voltage (continuous) . . . . . . . . . . . . -0.5V, +7V Supply Current (continuous) . . . . . . . 20mA to -20mA Storage Temperature . . . . . . . . . . . . -65°C to + 150°C Rev. 1.01 7 Conditions XR-T5684 SYSTEM DESCRIPTION A positive data at RPOS corresponds to a positive pulse received at RTIP and a positive data at RNEG corresponds to a positive pulse received at RRING. The device consists of receiver and transmitter circuitry with separate power supplies to reduce crosstalk between the two sections. With Mode Select (pin 5) set to high and an oversampling clock applied to pin 1, the recovered data can be synchronized with RCLK at pin 8. The clock recovery circuit extracts the timing contents from the incoming data transitions by means of an 8X or 16X divider. If there is no data on the input, the divider operates in its free running mode, generating a equal mark-and-space ratio output clock. This free running mode will be interrupted if a positive pulse is detected; the resultant mark-and-space ratio of the output clock is then determined by the position of the occurrence of the positive data relative to its free running position. See timing diagram in Figure 3 and Figure 4. RECEIVER The receiver is sensitive to the entire cable length from the cross-connect and requires no external equalization networks. The receive AMI input signal is applied to RTIP and RRING through a center-grounded transformer. The positive pulse is input to RTIP and the negative pulse is input to RRING. Comparators are used to slice the data on RTIP and RRING. The slicing level of the comparators are dynamically set at around 70% of peak level of the input signal to ensure optimum signal-to-noise ratio. With Mode Select (pin 5) set to low, the clock recovery feature is bypassed and the output data from the comparators are typically stretched by 80nS before output to RPOS and RNEG respectively. In all cases, the output data RPOS and RNEG remains stable on the falling edge of RCLK so as to be sampled correctly. The input jitter tolerance with an 8X oversampling clock is shown in Figure 6 and that with a 16X oversampling clock is shown in Figure 5. 8X OVERSAMPLING RTIP RRING 648nS RCLK RPOS RNEG tsu tho 6 Clk Cycles 6 Clk Cycles Figure 3. Receiver Clock and Data Switching Characteristics 16 X OVERSAMPLING RTIP RRING RCLK 8 Clk Cycles RPOS 8 Clk Cycles RNEG tsu tho Figure 4. Typical Receive Timing Diagram Using 8X Oversampling Clock. Rev 1.01 8 XR-T5684 Sinusodial Input Jitter Amplitude (PK-PK UI) -20db / Decade 10 UI 10 UI TR-TSY-000499 Issue 2 Dec., 1988 1.5 UI 0.6 UI 0.4 UI 0.3 UI 640 Hz 10 Hz 6430 Hz 20 KHz 40 KHz Jitter Frequency Figure 5. Typical Receive Timing Diagram Using 16X Oversampling Clock Sinusoidal Input Jitter Amplitude (PK-PK UI) -20db / Decade 10 UI 10 UI TR-TSY-000499 Issue 2 Dec., 1988 1.9 UI 0.7 UI 0.5 UI 0.3 UI 10 Hz 640 Hz 6430 Hz 20 KHz 40 KHz Jitter Frequency Figure 6. XR-T5684 Input Jitter Tolerance Using 8X Oversampling Clock Rev. 1.01 9 XR-T5684 Pulse shaping is selectable through input control pins LEN2, LEN1 and LEN0 for line lengths ranging from 0 to 655 feet of ABAM cable as illustrated in Table 1. Another function of the receiver is the signal quality monitor that reports loss of signal when the input level on RTIP and RRING falls below 0.4V or upon detection of 175 ± 15 consecutive zeros in the incoming data stream. The zero detection circuit is active only when LCLK clock is applied. In both cases, the receiver reports loss of signal by setting LOS high, and at the same time, RPOS and RNEG are forced to low. Under the loss of signal conditions, the receiver will continue to recover data and will return to its normal operation if a valid data is detected on RTIP and RRING. LEN2 LEN1 LEN0 Line Length Selected (ft.) 0 1 1 0 - 133 1 0 0 133 - 266 1 0 1 266 - 399 1 1 0 399 - 533 1 1 1 533 - 655 TRANSMITTER Table 1. ABAM or ALVYN Cable Type Line Length Selection The transmitter is designed to take dual rail NRZ data, plus a synchronized input clock and produces a bipolar signal with the appropriate shape for transmission to the line. The transmitter can be set to transmit a continuous AMI encoded all ones signal to the line by forcing TAOS high. In this mode, input data TPOS and TNEG are ignored and the frequency of the transmitted signal is determined by TCLK. After sampling by the falling edge of TCLK, TPOS and TNEG data are processed by a digital to analog converter together with a slew-control circuit to generate output pulses at TTIP and TRING with the appropriate amplitude and shape to meet the cross-connect template specified in CB 119. A typical output pulse is shown in Figure 7. In order to meet the amplitude requirement with a single +5V supply, the transmit signal is driven to the line differentially via a 1:1.36 step-up transformer. With TTIP connected to MTIP and TRING connected to MRING, the driver monitor can detect a non-functional T1 transmitter by monitoring the activity at its input. If no signal is presented on MTIP and MRING for 63 TCLK clock cycles, DPM goes high until the next AMI signal is detected. Normalized Amplitude T5684 Output Pulse Shape 1.0 CB119 Specification 0.5 0 -0.5 250 500 750 1000 Time (Nanoseconds) Figure 7. Receiver Clock and Data Switching Characteristics Rev 1.01 10 Loss of Signal Monitor Pin Drive Performance Monitor Pin R5 75 12.35MHz or 24.07MHz RPOS RNEG RCLK TNEG TPOS TCLK R6 75 10K Rev. 1.01 11 10 9 8 7 6 28 27 26 25 24 23 22 21 20 19 18 17 16 15 22F 16V 0.22F C1 + C2 TAOS RETIME X16 CLKDS TAOS N/C TEST LEN2 LEN1 LEN0 RGND RVDD RRING RTIP MRING MTIP TRING TVDD SWITCH 1 SIP1 1 2 3 4 5 LCLK TCLK TPOS TNEG MODE RPOS RNEG RCLK PD CLKDS DPM LOS TTIP TGND GND X5 1 2 3 4 5 SIP2 VCC (5V ± 5%) Figure 1. Application Schematic Diagram X5 X8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 XR-T5684 10K C3 10 9 8 7 6 0.47F SWITCH 2 LEN2 LEN1 LEN0 XFMR 1 PE64937 TX: SCHOTT 67121050 R1 220 R2 220 XFMR 2 PE64944 RX: SCHOTT 67121040 XR-T5684 XR-T5684 RRING, RTIP tdf tdr RPOS, RNEG Figure 2. Receiver Clock and Data Switching Characteristics TCLK tsu tho TPOS, TTNEG Figure 3. Receiver Clock and Data Switching Characteristics Rev 1.01 12 XR-T5684 Preliminary 28 LEAD PLASTIC LEADED CHIP CARRIER (PLCC) Rev. 1.00 D C D1 45° x H2 2 Seating Plane A2 45° x H1 28 1 B1 D D1 B D3 e R D3 A1 A INCHES SYMBOL MILLIMETERS MIN MAX MIN MAX A 0.165 0.180 4.19 4.57 A1 0.090 0.120 2.29 3.05 A2 0.020 –––. 0.51 ––– B 0.013 0.021 0.33 0.53 B1 0.026 0.032 0.66 0.81 C 0.008 0.013 0.19 0.32 D 0.485 0.495 12.32 12.57 D1 0.450 0.456 11.43 11.58 D2 0.390 0.430 9.91 10.92 D3 e 0.300 typ. 0.050 BSC 7.62 typ. 1.27 BSC H1 0.042 0.056 1.07 1.42 H2 0.042 0.048 1.07 1.22 R 0.025 0.045 0.64 1.14 Note: The control dimension is the inch column Rev. 13 D2 XR-T5684 28 LEAD PLASTIC DUAL-IN-LINE (600 MIL PDIP) Rev. 1.00 28 15 E1 1 14 E D Seating Plane A2 A L A1 α C B B1 e INCHES SYMBOL eA eB MILLIMETERS MIN MAX MIN A 0.160 0.250 4.06 6.35 A1 0.015 0.070 0.38 1.78 A2 0.125 0.195 3.18 4.95 B 0.014 0.024 0.36 0.56 B1 0.030 0.070 0.76 1.78 C 0.008 0.014 0.20 0.38 D 1.380 1.565 35.05 39.75 E 0.600 0.625 15.24 15.88 E1 0.485 0.580 12.32 14.73 e eA 0.100 BSC 0.600 BSC MAX 2.54 BSC 15.24 BSC eB 0.600 0.700 15.24 17.78 L 0.115 0.200 2.92 5.08 α 0° 15° 0° Note: The control dimension is the inch column 15° Rev 1.01 14 Preliminary Notes Rev. 15 XR-T5684 XR-T5684 NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1997 EXAR Corporation Datasheet June 1997 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev 1.01 16