24C01C 1K 5.0V I2C™ Serial EEPROM FEATURES PDIP/SOIC 1 A1 2 A2 3 Vss 4 8 Vcc 7 TEST 6 SCL 5 SDA TSSOP A0 A1 1 A2 VSS 3 4 24C01C DESCRIPTION The Microchip Technology Inc. 24C01C is a 1K bit Serial Electrically Erasable PROM with a voltage range of 4.5V to 5.5V. The device is organized as a single block of 128 x 8-bit memory with a 2-wire serial interface. Low current design permits operation with typical standby and active currents of only 10 µA and 1 mA respectively. The device has a page-write capability for up to 16 bytes of data and has fast write cycle times of only 1 mS for both byte and page writes. Functional address lines allow the connection of up to eight 24C01C devices on the same bus for up to 8K bits of contiguous EEPROM memory. The device is available in the standard 8-pin PDIP, 8-pin SOIC (150 mil), and TSSOP packages. A0 24C01C • Single supply with operation from 4.5 to 5.5V • Low power CMOS technology - 1 mA active current typical - 10 µA standby current typical at 5.5V • Organized as a single block of 128 bytes (128 x 8) • 2-wire serial interface bus, I2C compatible • 100 kHz and 400 kHz compatibility • Page-write buffer for up to 16 bytes • Self-timed write cycle (including auto-erase) • Fast 1 mS write cycle time for byte or page mode • Address lines allow up to eight devices on bus • 1,000,000 erase/write cycles guaranteed • ESD protection > 4,000V • Data retention > 200 years • 8-pin PDIP, SOIC or TSSOP packages • Available for extended temperature ranges - Commercial (C): 0°C to +70°C - Industrial (I): -40°C to +85°C - Automotive (E): -40°C to +125°C PACKAGE TYPES 2 8 7 VCC TEST 6 5 SCL SDA BLOCK DIAGRAM A0 A1 A2 I/O Control Logic HV Generator Memory Control Logic XDEC EEPROM Array SDA SCL Vcc YDEC Vss SENSE AMP R/W CONTROL I2C is a trademark of Philips Corporation. 1999 Microchip Technology Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 DS21201C-page 1 24C01C 1.0 1.1 ELECTRICAL CHARACTERISTICS TABLE 1-1: PIN FUNCTION TABLE Name Maximum Ratings* VCC ........................................................................7.0V All inputs and outputs w.r.t. VSS .....-0.6V to VCC +1.0V Storage temperature ..........................-65°C to +150°C Ambient temp. with power applied......-65°C to +125°C Soldering temperature of leads (10 seconds) .. +300°C ESD protection on all pins ..................................... ≥ 4 kV Function VSS Ground SDA Serial Data SCL Serial Clock VCC +4.5V to 5.5V Power Supply A0, A1, A2 Chip Selects Test Test Pin: may be tied high, low or left floating *Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-2: DC CHARACTERISTICS All parameters apply across the specified operating ranges unless otherwise noted. Parameter VCC = +4.5V to +5.5V Commercial (C): Industrial (I): Automotive (E): Symbol Min. SCL and SDA pins: High level input voltage VIH 0.7 VCC Low level input voltage VIL Hysteresis of Schmitt trigger inputs VHYS Low level output voltage 0.05 VCC VOL Tamb = 0°C to +70°C Tamb = -40°C to +85°C Tamb = -40°C to +125°C Max. Units Conditions V .3 VCC V — V (Note) .40 V IOL = 3.0 mA, VCC = 4.5V Input leakage current ILI -10 10 µA VIN = 0.1V to 5.5V, WP = Vss Output leakage current ILO -10 10 µA VOUT = 0.1V to 5.5V CIN, COUT — 10 pF VCC = 5.0V (Note) Tamb = 25°C, f = 1 MHz ICC Read — 1 mA VCC = 5.5V, SCL = 400 kHz ICC Write — 3 mA VCC = 5.5V ICCS — 50 µA VCC = 5.5V, SDA = SCL = VCC WP = VSS Pin capacitance (all inputs/outputs) Operating current Standby current Note: This parameter is periodically sampled and not 100% tested. DS21201C-page 2 Powered by ICminer.com Electronic-Library Service CopyRight 2003 1999 Microchip Technology Inc. 24C01C TABLE 1-3: AC CHARACTERISTICS All parameters apply across the specified operating ranges unless otherwise noted. Parameter Symbol Vcc = 4.5V to 5.5V Commercial (C): Industrial (I): Automotive (E): Tamb = 0°C to +70°C Tamb = -40°C to +85°C Tamb = -40°C to +125°C Tamb > +85°C -40°C ≤ Tamb ≤ +85°C Min. Max. Min. Max. Units Remarks Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time START condition hold time FCLK THIGH TLOW TR TF THD:STA — 4000 4700 — — 4000 100 — — 1000 300 — — 600 1300 — — 600 400 — — 300 300 — kHz ns ns ns ns ns START condition setup time TSU:STA 4700 — 600 — ns Data input hold time Data input setup time STOP condition setup time Output valid from clock Bus free time THD:DAT TSU:DAT TSU:STO TAA TBUF 0 250 4000 — 4700 — — — 3500 — 0 100 600 — 1300 — — — 900 — ns ns ns ns ns TOF — 250 20 +0.1 CB 250 ns (Note 2) Time the bus must be free before a new transmission can start (Note 1), CB ≤ 100 pF TSP — 50 — 50 ns (Note 3) TWR — 1M 1.5 — — 1M 1 — Output fall time from VIH minimum to VIL maximum Input filter spike suppression (SDA and SCL pins) Write cycle time Endurance (Note 1) (Note 1) After this period the first clock pulse is generated Only relevant for repeated START condition (Note 2) ms Byte or Page mode cycles 25°C, VCC = 5.0V, Block Mode (Note 4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and VHYS specifications are due to Schmitt trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our website. FIGURE 1-1: BUS TIMING DATA THIGH TF SCL TR TSU:STA TLOW SDA IN THD:DAT TSU:DAT TSU:STO THD:STA TSP TAA TBUF SDA OUT 1999 Microchip Technology Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 DS21201C-page 3 24C01C 2.0 PIN DESCRIPTIONS 3.0 2.1 SDA Serial Data The 24C01C supports a bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24C01C works as slave. Both master and slave can operate as transmitter or receiver but the master device determines which mode is activated. This is a bi-directional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pull-up resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for 400 kHz). For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions. 2.2 FUNCTIONAL DESCRIPTION SCL Serial Clock This input is used to synchronize the data transfer from and to the device. 2.3 A0, A1, A2 The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. Up to eight 24C01C devices may be connected to the same bus by using different chip select bit combinations. These inputs must be connected to either VCC or VSS. 2.4 Test This pin is utilized for testing purposes only. It may be tied high, tied low or left floating. 2.5 Noise Protection The 24C01C employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below 3.8 volts at nominal conditions. The SCL and SDA inputs have Schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. DS21201C-page 4 Powered by ICminer.com Electronic-Library Service CopyRight 2003 1999 Microchip Technology Inc. 24C01C 4.0 BUS CHARACTERISTICS The data on the line must be changed during the LOW period of the clock signal. There is one bit of data per clock pulse. The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (Figure 4-1). Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited, although only the last sixteen will be stored when doing a write operation. When an overwrite does occur it will replace data in a first in first out fashion. 4.1 4.5 Bus not Busy (A) Both data and clock lines remain HIGH. 4.2 Each receiving device, when addressed, is required to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. Start Data Transfer (B) A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition. 4.3 Acknowledge Note: Stop Data Transfer (C) The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition (Figure 4-2). A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition. 4.4 Data Valid (D) The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. FIGURE 4-1: SCL (A) The 24C01C does not generate any acknowledge bits if an internal programming cycle is in progress. DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS (B) (C) (D) START CONDITION ADDRESS OR ACKNOWLEDGE VALID (C) (A) SDA FIGURE 4-2: STOP CONDITION DATA ALLOWED TO CHANGE ACKNOWLEDGE TIMING Acknowledge Bit SCL 1 2 SDA 3 4 5 6 7 Data from transmitter Transmitter must release the SDA line at this point allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data. 1999 Microchip Technology Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 8 9 1 2 3 Data from transmitter Receiver must release the SDA line at this point so the Transmitter can continue sending data. DS21201C-page 5 24C01C 5.0 DEVICE ADDRESSING A control byte is the first byte received following the start condition from the master device (Figure 5-1). The control byte consists of a four bit control code; for the 24C01C this is set as 1010 binary for read and write operations. The next three bits of the control byte are the chip select bits (A2, A1, A0). The chip select bits allow the use of up to eight 24C01C devices on the same bus and are used to select which device is accessed. The chip select bits in the control byte must correspond to the logic levels on the corresponding A2, A1, and A0 pins for the device to respond. These bits are in effect the three most significant bits of the word address. The last bit of the control byte defines the operation to be performed. When set to a one a read operation is selected, and when set to a zero a write operation is selected. Following the start condition, the 24C01C monitors the SDA bus checking the control byte being transmitted. Upon receiving a 1010 code and appropriate chip select bits, the slave device outputs an acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24C01C will select a read or write operation. DS21201C-page 6 Powered by ICminer.com Electronic-Library Service CopyRight 2003 FIGURE 5-1: CONTROL BYTE FORMAT Read/Write Bit Chip Select Bits Control Code S 1 0 1 0 A2 A1 A0 R/W ACK Slave Address Start Bit 5.1 Acknowledge Bit Contiguous Addressing Across Multiple Devices The chip select bits A2, A1, A0 can be used to expand the contiguous address space for up to 8K bits by adding up to eight 24C01C devices on the same bus. In this case, software can use A0 of the control byte as address bit A8, A1 as address bit A9, and A2 as address bit A10. It is not possible to write or read across device boundaries. 1999 Microchip Technology Inc. 24C01C 6.0 WRITE OPERATIONS 6.1 Byte Write pointer bits are internally incremented by one. The higher order four bits of the word address remains constant. If the master should transmit more than 16 bytes prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received an internal write cycle will begin (Figure 6-2). Following the start signal from the master, the device code(4 bits), the chip select bits (3 bits), and the R/W bit which is a logic low is placed onto the bus by the master transmitter. The device will acknowledge this control byte during the ninth clock pulse. The next byte transmitted by the master is the word address and will be written into the address pointer of the 24C01C. After receiving another acknowledge signal from the 24C01C the master device will transmit the data word to be written into the addressed memory location. The 24C01C acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and during this time the 24C01C will not generate acknowledge signals (Figure 6-1). 6.2 Note: Page Write The write control byte, word address and the first data byte are transmitted to the 24C01C in the same way as in a byte write. But instead of generating a stop condition, the master transmits up to 15 additional data bytes to the 24C01C which are temporarily stored in the onchip page buffer and will be written into the memory after the master has transmitted a stop condition. After the receipt of each word, the four lower order address FIGURE 6-1: BYTE WRITE BUS ACTIVITY MASTER S T A R T SDA LINE S CONTROL BYTE WORD ADDRESS BUS ACTIVITY MASTER SDA LINE S T O P DATA P A C K BUS ACTIVITY FIGURE 6-2: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and end at addresses that are integer multiples of [page size - 1]. If a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. A C K A C K PAGE WRITE S T A R T WORD ADDRESS (n) CONTROL BYTE DATA n +1 DATA n S T O P DATA n + 15 S BUS ACTIVITY P A C K 1999 Microchip Technology Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 A C K A C K A C K A C K DS21201C-page 7 24C01C 7.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, then the start bit and control byte must be re-sent. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 7-1 for flow diagram. FIGURE 7-1: ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? NO YES Next Operation DS21201C-page 8 Powered by ICminer.com Electronic-Library Service CopyRight 2003 1999 Microchip Technology Inc. 24C01C 8.0 READ OPERATIONS address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W bit set to a one. The 24C01C will then issue an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24C01C discontinues transmission (Figure 8-2). After this command, the internal address counter will point to the address location following the one that was just read. Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read, and sequential read. 8.1 Current Address Read The 24C01C contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous read access was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with the R/W bit set to one, the 24C01C issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24C01C discontinues transmission (Figure 8-1). 8.2 8.3 Sequential reads are initiated in the same way as a random read except that after the 24C01C transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. This directs the 24C01C to transmit the next sequentially addressed 8-bit word (Figure 8-3). To provide sequential reads the 24C01C contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation. The internal address pointer will automatically roll over from address 7F to address 00. Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24C01C as part of a write operation. After the word FIGURE 8-1: CURRENT ADDRESS READ BUS ACTIVITY MASTER S T A R T SDA LINE S CONTROL BYTE P A C K N O A C K RANDOM READ BUS ACTIVITY MASTER S T A R T CONTROL BYTE S T A R T WORD ADDRESS (n) CONTROL BYTE S T O P DATA (n) S S SDA LINE P A C K A C K BUS ACTIVITY FIGURE 8-3: S T O P DATA BUS ACTIVITY FIGURE 8-2: Sequential Read A C K N O A C K SEQUENTIAL READ BUS ACTIVITY MASTER CONTROL BYTE DATA n DATA n + 1 DATA n + 2 S T O P DATA n + X P SDA LINE BUS ACTIVITY A C K 1999 Microchip Technology Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 A C K A C K A C K N O A C K DS21201C-page 9 24C01C NOTES: DS21201C-page 10 Powered by ICminer.com Electronic-Library Service CopyRight 2003 1999 Microchip Technology Inc. 24C01C 24C01C PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. 24C01C — /P Package: Temperature Range: Device: P = Plastic DIP (300 mil Body), 8-lead SN = Plastic SOIC, (150 mil Body), 8-lead ST = TSSOP (4.4 mm Body), 8-lead Blank = 0°C to +70°C I = –40°C to +85°C E = –40°C to +125°C 24C01C 24C01CT 1K I 2C Serial EEPROM 1K I 2C Serial EEPROM (Tape and Reel) Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System 4. Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 1999 Microchip Technology Inc. Powered by ICminer.com Electronic-Library Service CopyRight 2003 DS21201C-page 11 WORLDWIDE SALES AND SERVICE AMERICAS AMERICAS (continued) ASIA/PACIFIC (continued) Corporate Office Toronto Singapore Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602-786-7200 Fax: 602-786-7277 Technical Support: 602-786-7627 Web: http://www.microchip.com Microchip Technology Inc. 5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253 Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore 188980 Tel: 65-334-8870 Fax: 65-334-8850 Atlanta Hong Kong Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307 Microchip Asia Pacific Unit 2101, Tower 2 Metroplaza Kwai Fong, N.T., Hong Kong Tel: 852-2-401-1200 Fax: 852-2-401-3431 Boston Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508-480-9990 Fax: 508-480-8575 Chicago Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075 Dallas Microchip Technology Inc. 14651 Dallas Parkway, Suite 816 Dallas, TX 75240-8809 Tel: 972-991-7177 Fax: 972-991-8588 Dayton Microchip Technology Inc. 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Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-39-6899939 Fax: 39-39-6899883 Microchip Technology Inc. 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338 New York Microchip Technology Inc. 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 516-273-5305 Fax: 516-273-5335 San Jose Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955 All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 4/99 Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 München, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 03/15/99 Microchip received ISO 9001 Quality System certification for its worldwide headquarters, design, and wafer fabrication facilities in January, 1997. Our field-programmable PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, related specialty memory products and development systems conform to the stringent quality standards of the International Standard Organization (ISO). Printed on recycled paper. Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. DS21201C-page 12 Powered by ICminer.com Electronic-Library Service CopyRight 2003 1999 Microchip Technology Inc.