M 25AA040/25LC040/25C040 4K SPI™ Bus Serial EEPROM DEVICE SELECTION TABLE DESCRIPTION Part Number VCC Range Max. Clock Frequency Temp. Ranges 25AA040 1.8-5.5V 1 MHz I 25LC040 2.5-5.5V 2 MHz I 25C040 4.5-5.5V 3 MHz I,E The Microchip Technology Inc. 25AA040/25LC040/ 25C040 (25XX040*) is a 4 Kbit serial Electrically Erasable PROM. The memory is accessed via a simple Serial Peripheral Interface™ (SPI™) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input. FEATURES Communication to the device can be paused via the hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of chip select, allowing the host to service higher priority interrupts. Also, write operations to the device can be disabled via the write protect pin (WP). • Low power CMOS technology - Write current: 3 mA typical - Read current: 500 µA typical - Standby current: 500 nA typical • 512 x 8-bit organization • 16 byte page • Write cycle time: 5 ms max. • Self-timed ERASE and WRITE cycles • Block write protection - Protect none, 1/4, 1/2 or all of array • Built-in write protection - Power on/off data protection circuitry - Write enable latch - Write protect pin • Sequential read • High reliability - Endurance: 1M cycles - Data retention: > 200 years - ESD protection: > 4000V • 8-pin PDIP, SOIC, and TSSOP packages • Temperature ranges supported: - Industrial (I): -40°C to +85°C - Automotive (E) (25C040): -40°C to +125°C BLOCK DIAGRAM Status Register I/O Control Logic HV Generator Memory Control Logic EEPROM Array X Dec Page Latches SI SO Y Decoder CS SCK Sense Amp. R/W Control HOLD WP VCC VSS PACKAGE TYPES PDIP CS 1 VSS 4 CS 1 7 HOLD SO 2 6 SCK WP 3 5 SI VSS 4 TSSOP 8 VCC HOLD 1 7 HOLD VCC 2 6 SCK CS 3 5 SI SO 4 25XX040 3 VCC 25XX040 2 8 25XX040 SO WP SOIC 8 SCK 7 SI 6 VSS 5 WP *25XX040 is used in this document as a generic part number for the 25AA040/25LC040/25C040 devices. SPI™ is a trademark of Motorola Inc. 2001 Microchip Technology Inc. DS21204C-page 1 25AA040/25LC040/25C040 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings† VCC .............................................................................................................................................................................7.0V All inputs and outputs w.r.t. VSS .......................................................................................................... -0.6V to VCC+1.0V Storage temperature .................................................................................................................................-65°C to 150°C Ambient temperature under bias ...............................................................................................................-65°C to 125°C Soldering temperature of leads (10 seconds) .......................................................................................................+300°C ESD protection on all pins ......................................................................................................................................... 4 KV † NOTICE: Stresses above those listed under ‘Maximum ratings’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability 1.1 DC Characteristics DC CHARACTERISTICS Param. No. Sym. D001 VIH1 D002 VIH2 D003 VIL1 D004 VIL2 D005 VOL D006 VOL D007 VOH Characteristic Industrial (I): TAMB = -40°C to +85°C Automotive (E): TAMB = -40°C to +125°C VCC = 1.8V to 5.5V VCC = 4.5V to 5.5V (25C040 only) Min. Max. Units 2.0 VCC+1 V VCC ≥ 2.7V (Note) 0.7 VCC VCC+1 V VCC< 2.7V (Note) -0.3 0.8 V VCC ≥ 2.7V (Note) -0.3 0.3 VCC V VCC < 2.7V (Note) Low level output voltage — 0.4 V IOL = 2.1 mA — 0.2 V IOL = 1.0 mA, VCC < 2.5V High level output voltage VCC -0.5 — V IOH =-400 µA High level input voltage Low level input voltage Test Conditions D008 ILI Input leakage current -10 10 µA CS = VCC, VIN = VSS TO VCC D009 ILO Output leakage current -10 10 µA CS = VCC, VOUT = VSS TO VCC D010 CINT Internal Capacitance (all inputs and outputs) — 7 pF TAMB = 25°C, CLK = 1.0 MHz, VCC = 5.0V (Note) D011 ICC Read Operating Current — — 1 500 mA µA VCC = 5.5V; FCLK = 3.0 MHz; SO = Open VCC = 2.5V; FCLK = 2.0 MHz; SO = Open D012 ICC Write — — 5 3 mA mA VCC = 5.5V VCC = 2.5V D013 ICCS — — 5 1 µA µA CS = VCC = 5.5V, Inputs tied to VCC or VSS CS = VCC = 2.5V, Inputs tied to VCC or VSS Note: Standby Current This parameter is periodically sampled and not 100% tested. DS21204C-page 2 2001 Microchip Technology Inc. 25AA040/25LC040/25C040 1.2 AC Characteristics AC CHARACTERISTICS Industrial (I): TAMB = -40°C to +85°C Automotive (E): TAMB = -40°C to +125°C VCC = 1.8V to 5.5V VCC = 4.5V to 5.5V (25C040 only) Param. No. Sym. Characteristic Min. Max. Units 1 FCLK Clock Frequency — — — 3 2 1 MHz MHz MHz VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V 2 TCSS CS Setup Time 100 250 500 — — — ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V 3 TCSH CS Hold Time 150 250 475 — — — ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V Test Conditions 4 TCSD CS Disable Time 500 — ns — 5 TSU Data Setup Time 30 50 50 — — — ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V 6 THD Data Hold Time 50 100 100 — — — ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V 7 TR CLK Rise Time — 2 µs (Note 1) 8 TF CLK Fall Time — 2 µs (Note 1) 9 THI Clock High Time 150 230 475 — — — ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V 10 TLO Clock Low Time 150 230 475 — — — ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V — 11 TCLD Clock Delay Time 50 — ns 12 TCLE Clock Enable Time 50 — ns — 13 TV Output Valid from Clock Low — — — 150 230 475 ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V 14 THO Output Hold Time 0 — ns (Note 1) 15 TDIS Output Disable Time — — — 200 250 500 ns ns ns VCC = 4.5V to 5.5V (Note 1) VCC = 2.5V to 4.5V (Note 1) VCC = 1.8V to 2.5V (Note 1) 16 THS HOLD Setup Time 100 100 200 — — — ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V 17 THH HOLD Hold Time 100 100 200 — — — ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V 18 THZ HOLD Low to Output High-Z 100 150 200 — — — ns ns ns VCC = 4.5V to 5.5V (Note 1) VCC = 2.5V to 4.5V (Note 1) VCC = 1.8V to 2.5V (Note 1) 19 THV HOLD High to Output Valid 100 150 200 — — — ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V 20 TWC Internal Write Cycle Time — 5 ms — 21 — Endurance 1M — E/W Cycles (Note 2) Note 1: This parameter is periodically sampled and not 100% tested. 2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our website: www.microchip.com. 2001 Microchip Technology Inc. DS21204C-page 3 25AA040/25LC040/25C040 FIGURE 1-1: HOLD TIMING CS 17 16 17 16 SCK 18 SO n+2 SI n+2 n+1 n 19 high impedance n 5 don’t care n+1 n-1 n n n-1 HOLD FIGURE 1-2: SERIAL INPUT TIMING 4 CS 2 7 Mode 1,1 12 11 8 3 SCK Mode 0,0 5 SI 6 MSB in LSB in high impedance SO FIGURE 1-3: SERIAL OUTPUT TIMING CS 9 3 10 Mode 1,1 SCK Mode 0,0 13 14 SO SI DS21204C-page 4 MSB out 15 ISB out don’t care 2001 Microchip Technology Inc. 25AA040/25LC040/25C040 1.3 FIGURE 1-4: AC Test Conditions AC TEST CIRCUIT AC VCC AC Waveform: VLO = 0.2V — VHI = VCC - 0.2V (Note 1) VHI = 4.0V (Note 2) Timing Measurement Reference Level 2.25 KΩ SO Input 0.5 VCC Output 0.5 VCC 1.8 KΩ 100 pF Note 1: For VCC ≤ 4.0V 2: For VCC > 4.0V 2001 Microchip Technology Inc. DS21204C-page 5 25AA040/25LC040/25C040 2.0 PIN DESCRIPTIONS 2.4 PIN FUNCTION TABLE The SI pin is used to transfer data into the device. It receives instructions, addresses and data. Data is latched on the rising edge of the serial clock. 2.5 The descriptions of the pins are listed in Table 2-1. TABLE 2-1: Name PDIP SOIC TSSOP CS 1 1 3 Chip Select Input Description SO 2 2 4 Serial Data Output WP 3 3 5 Write Protect Pin VSS 4 4 6 Ground SI 5 5 7 Serial Data Input SCK 6 6 8 Serial Clock Input HOLD 7 7 1 Hold Input VCC 8 8 2 Supply Voltage 2.1 Chip Select (CS) A low level on this pin selects the device. A high level deselects the device and forces it into standby mode. However, a programming cycle which is already initiated or in progress will be completed, regardless of the CS input signal. If CS is brought high during a program cycle, the device will go in standby mode as soon as the programming cycle is complete. When the device is deselected, SO goes into the high impedance state, allowing multiple parts to share the same SPI bus. A low to high transition on CS after a valid write sequence initiates an internal write cycle. After power-up, a low level on CS is required prior to any sequence being initiated. 2.2 Serial Input (SI) Serial Clock (SCK) The SCK is used to synchronize the communication between a master and the 25XX040. Instructions, addresses or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin is updated after the falling edge of the clock input. 2.6 Hold (HOLD) The HOLD pin is used to suspend transmission to the 25XX040 while in the middle of a serial sequence without having to retransmit the entire sequence again at a later time. It must be held high any time this function is not being used. Once the device is selected and a serial sequence is underway, the HOLD pin may be pulled low to pause further serial communication without resetting the serial sequence. The HOLD pin must be brought low while SCK is low, otherwise the HOLD function will not be invoked until the next SCK high to low transition. The 25XX040 must remain selected during this sequence. The SI, SCK and SO pins are in a high impedance state during the time the part is paused and transitions on these pins will be ignored. To resume serial communication, HOLD must be brought high while the SCK pin is low, otherwise serial communication will not resume. Lowering the HOLD line at any time will tri-state the SO line. Serial Output (SO) The SO pin is used to transfer data out of the 25XX040. During a read cycle, data is shifted out on this pin after the falling edge of the serial clock. 2.3 Write Protect (WP) This pin is a hardware write protect input pin. When WP is low, all writes to the array or status register are disabled, but any other operation functions normally. When WP is high, all functions, including nonvolatile writes operate normally. WP going low at any time will reset the write enable latch and inhibit programming, except when an internal write has already begun. If an internal write cycle has already begun, WP going low will have no effect on the write. See Table 3-2 for Write Protect Functionality Matrix. DS21204C-page 6 2001 Microchip Technology Inc. 25AA040/25LC040/25C040 3.0 FUNCTIONAL DESCRIPTION 3.3 3.1 Principles of Operation Prior to any attempt to write data to the 25XX040, the write enable latch must be set by issuing the WREN instruction (Figure 3-4). This is done by setting CS low and then clocking out the proper instruction into the 25XX040. After all eight bits of the instruction are transmitted, the CS must be brought high to set the write enable latch. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set. The 25XX040 is a 512 byte Serial EEPROM designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families, including Microchip’s PIC16C6X/7X microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly with the software. The 25XX040 contains an 8-bit instruction register. The part is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire operation. The WP pin must be held high to allow writing to the memory array. Table 3-1 contains a list of the possible instruction bytes and format for device operation. The most significant address bit (A8) is located in the instruction byte. All instructions, addresses, and data are transferred MSB first, LSB last. Data is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input and place the 25XX040 in ‘HOLD’ mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted. 3.2 Read Sequence The part is selected by pulling CS low. The 8-bit read instruction with the A8 address bit is transmitted to the 25XX040 followed by the lower 8-bit address (A7 through A0). After the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (01FFh), the address counter rolls over to address 0000h allowing the read cycle to be continued indefinitely. The read operation is terminated by raising the CS pin (Figure 3-1). TABLE 3-1: Write Sequence Once the write enable latch is set, the user may proceed by setting the CS low, issuing a write instruction, followed by the address, and then the data to be written. Keep in mind that the most significant address bit (A8) is included in the instruction byte. Up to 16 bytes of data can be sent to the 25XX040 before a write cycle is necessary. The only restriction is that all of the bytes must reside in the same page. A page address begins with XXXX 0000 and ends with XXXX 1111. If the internal address counter reaches XXXX 1111 and the clock continues, the counter will roll back to the first address of the page and overwrite any data in the page that may have been written. For the data to be actually written to the array, the CS must be brought high after the least significant bit (D0) of the nth data byte has been clocked in. If CS is brought high at any other time, the write operation will not be completed. Refer to Figure 3-2 and Figure 3-3 for more detailed illustrations on the byte write sequence and the page write sequence respectively. While the write is in progress, the status register may be read to check the status of the WIP, WEL, BP1 and BP0 bits (Figure 3-6). A read attempt of a memory array location will not be possible during a write cycle. When the write cycle is completed, the write enable latch is reset. INSTRUCTION SET Instruction Name Instruction Format READ 0000 A8011 Read data from memory array beginning at selected address WRITE 0000 A8010 Write data to memory array beginning at selected address WRDI 0000 0100 Reset the write enable latch (disable write operations) WREN 0000 0110 Set the write enable latch (enable write operations) RDSR 0000 0101 Read status register 0000 0001 Write status register WRSR Note: A8 is the 9th Description address bit necessary to fully address 512 bytes. 2001 Microchip Technology Inc. DS21204C-page 7 25AA040/25LC040/25C040 FIGURE 3-1: READ SEQUENCE CS 0 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 8 SCK instruction 0 SI 0 0 0 lower address byte A8 0 1 1 A7 6 5 4 3 2 1 A0 don’t care data out high impedance 7 SO FIGURE 3-2: 6 5 4 3 2 1 0 BYTE WRITE SEQUENCE CS TWC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK instruction SI 0 0 0 0 A8 data byte lower address byte 0 0 1 A7 6 5 4 3 2 1 7 A0 6 5 4 3 2 1 0 high impedance SO FIGURE 3-3: PAGE WRITE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 24 SCK instruction SI 0 0 0 0 A8 lower address byte 0 1 0 A7 6 5 3 4 2 data byte 1 1 0 7 6 5 4 7 6 3 2 1 0 CS 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SCK data byte 2 SI 7 DS21204C-page 8 6 5 4 3 data byte n (16 max) data byte 3 2 1 0 7 6 5 4 3 2 1 0 5 4 3 2 1 0 2001 Microchip Technology Inc. 25AA040/25LC040/25C040 3.4 Write Enable (WREN) and Write Disable (WRDI) The following is a list of conditions under which the write enable latch will be reset: • • • • • The 25XX040 contains a write enable latch. See Table 3-3 for the Write Protect Functionality Matrix. This latch must be set before any write operation will be completed internally. The WREN instruction will set the latch, and the WRDI will reset the latch. FIGURE 3-4: Power-up WRDI instruction successfully executed WRSR instruction successfully executed WRITE instruction successfully executed WP line is low WRITE ENABLE SEQUENCE CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 1 0 high impedance SO FIGURE 3-5: WRITE DISABLE SEQUENCE CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 10 0 high impedance SO 2001 Microchip Technology Inc. DS21204C-page 9 25AA040/25LC040/25C040 3.5 Read Status Register (RDSR) 3.6 The RDSR instruction provides access to the status register. The status register may be read at any time, even during a write cycle. The status register is formatted as follows: 7 X 6 X 5 X 4 X 3 BP1 2 BP0 1 WEL Write Status Register (WRSR) The WRSR instruction allows the user to select one of four levels of protection for the array by writing to the appropriate bits in the status register. The array is divided up into four segments. The user has the ability to write protect none, one, two, or all four of the segments of the array. The partitioning is controlled as illustrated in Table 3-2. 0 WIP The Write-In-Process (WIP) bit indicates whether the 25XX040 is busy with a write operation. When set to a ‘1’, a write is in progress, when set to a ‘0’, no write is in progress. This bit is read only. See Figure 3-7 for WRSR timing sequence. TABLE 3-2: The Write Enable Latch (WEL) bit indicates the status of the write enable latch. When set to a ‘1’, the latch allows writes to the array, when set to a ‘0’, the latch prohibits writes to the array. The state of this bit can always be updated via the WREN or WRDI commands regardless of the state of write protection on the status register. This bit is read only. ARRAY PROTECTION BP1 BP0 Array Addresses Write Protected 0 0 none 0 1 upper 1/4 (0180h - 01FFh) 1 0 upper 1/2 (0100h - 01FFh) 1 1 all (0000h - 01FFh) The Block Protection (BP0 and BP1) bits indicate which blocks are currently write protected. These bits are set by the user issuing the WRSR instruction. These bits are nonvolatile. See Figure 3-6 for RDSR timing sequence. FIGURE 3-6: READ STATUS REGISTER SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK instruction SI 0 0 0 0 0 1 0 1 data from status register high impedance 7 SO FIGURE 3-7: 6 5 4 3 2 1 0 10 11 12 13 14 15 1 0 WRITE STATUS REGISTER SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 SCK instruction SI 0 0 0 0 0 data to status register 0 0 1 7 6 5 4 3 2 high impedance SO DS21204C-page 10 2001 Microchip Technology Inc. 25AA040/25LC040/25C040 3.7 Data Protection 3.8 The following protection has been implemented to prevent inadvertent writes to the array: • The write enable latch is reset on power-up • A write enable instruction must be issued to set the write enable latch • After a byte write, page write or status register write, the write enable latch is reset • CS must be set high after the proper number of clock cycles to start an internal write cycle • Access to the array during an internal write cycle is ignored and programming is continued • The write enable latch is reset when the WP pin is low TABLE 3-3: Power On State The 25XX040 powers on in the following state: • • • • The device is in low power standby mode (CS = 1) The write enable latch is reset SO is in high impedance state A low level on CS is required to enter active state WRITE PROTECT FUNCTIONALITY MATRIX WP WEL Protected Blocks Unprotected Blocks Status Register Low X Protected Protected Protected High 0 Protected Protected Protected High 1 Protected Writable Writable 2001 Microchip Technology Inc. DS21204C-page 11 25AA040/25LC040/25C040 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 8-Lead PDIP (300 mil) Example: 25AA040 I/PNNN YYWW XXXXXXXX XXXXXNNN YYWW 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN 8-Lead TSSOP Example: 25AA040 I/SNYYWW NNN Example: XXXX XYWW NNN Legend: Note: * XX...X Y YY WW NNN 5A4X IYWW NNN Customer specific information* Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. Standard PICmicro device marking consists of Microchip part number, year code, week code, and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. DS21204C-page 12 2001 Microchip Technology Inc. 25AA040/25LC040/25C040 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c A1 β B1 p eB B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L c § B1 B eB α β MIN .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 INCHES* NOM MAX 8 .100 .155 .130 .170 .145 .313 .250 .373 .130 .012 .058 .018 .370 10 10 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 2001 Microchip Technology Inc. DS21204C-page 13 25AA040/25LC040/25C040 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h α 45× c A2 A f β L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L f c B α β MIN .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 A1 INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 DS21204C-page 14 2001 Microchip Technology Inc. 25AA040/25LC040/25C040 8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 1 n B α A c A1 f β A2 L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L f c B α β MIN INCHES NOM MAX 8 .026 .033 .002 .246 .169 .114 .020 0 .004 .007 0 0 .035 .004 .251 .173 .118 .024 4 .006 .010 5 5 .043 .037 .006 .256 .177 .122 .028 8 .008 .012 10 10 MILLIMETERS* NOM MAX 8 0.65 1.10 0.85 0.90 0.95 0.05 0.10 0.15 6.25 6.38 6.50 4.30 4.40 4.50 2.90 3.00 3.10 0.50 0.60 0.70 0 4 8 0.09 0.15 0.20 0.19 0.25 0.30 0 5 10 0 5 10 MIN Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-086 2001 Microchip Technology Inc. DS21204C-page 15 25AA040/25LC040/25C040 ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape® or Microsoft® Explorer. Files are also available for FTP download from our FTP site. Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits. The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. Connecting to the Microchip Internet Web Site The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User’s Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: • Latest Microchip Press Releases • Technical Support Section with Frequently Asked Questions • Design Tips • Device Errata • Job Postings • Microchip Consultant Program Member Listing • Links to other useful web sites related to Microchip Products • Conferences for products, Development Systems, technical information and more • Listing of seminars and events DS21204C-page 16 2001 Microchip Technology Inc. 25AA040/25LC040/25C040 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: Technical Publications Manager RE: Reader Response Total Pages Sent From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: 25AA040/25LC040/25C040 Literature Number: DS21204C Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? 2001 Microchip Technology Inc. DS21204C-page 17 25AA040/25LC040/25C040 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X /XX Temperature Range Package Examples: a) b) Device: Temperature Range: 25AA040: 4096-bit 1.8V SPI Serial EEPROM 25AA040T: 4096-bit 1.8V SPI Serial EEPROM (Tape and Reel) 25AA040X: 4096-bit 1.8V SPI Serial EEPROM in alternate pinout (ST only) 25AA040XT:4096-bit 1.8V SPI Serial EEPROM in alternate pinout Tape and Reel (ST only) 25LC040: 4096-bit 2.5V SPI Serial EEPROM 25LC040T: 4096-bit 2.5V SPI Serial EEPROM (Tape and Reel) 25LC040X: 4096-bit 2.5V SPI Serial EEPROM in alternate pinout (ST only) 25LC040XT:4096-bit 2.5V SPI Serial EEPROM in alternate pinout Tape and Reel (ST only) 25C040: 4096-bit 5.0V SPI Serial EEPROM 25C040T: 4096-bit 5.0V SPI Serial EEPROM (Tape and Reel) 25C040X: 4096-bit 5.0V SPI Serial EEPROM in alternate pinout (ST only) 25C040XT: 4096-bit 5.0V SPI Serial EEPROM in alternate pinout Tape and Reel (ST only) I E -40 °C to+85 °C -40 °C to +125 °C = = c) d) e) f) g) h) i) j) k) l) m) n) Package: P SN ST = = = Plastic DIP (300 mil body), 8-lead Plastic SOIC (150 mil body), 8-lead Plastic TSSOP (4.4 mm body), 8-lead o) p) q) r) 25AA040-I/P: Industrial Temp., PDIP package 25AA040-I/SN: Industrial Temp., SOIC package 25AA040T-I/SN: Tape and Reel, Industrial Temp., SOIC package 25AA040X-I/ST: Alternate Pinout, Industrial Temp., TSSOP package 25AA040XT-I/ST: Alternate Pinout, Tape and Reel, Industrial Temp., TSSOP package 25LC040-I/P: Industrial Temp., PDIP package 25LC040-I/SN: Industrial Temp., SOIC package 25LC040T-I/SN: Tape and Reel, Industrial Temp., SOIC package 25LC040X-I/ST: Alternate Pinout, Industrial Temp., TSSOP package 25LC040XT-I/ST: Alternate Pinout, Tape and Reel, Industrial Temp., TSSOP package 25C040-I/P: Industrial Temp., PDIP package 25C040-I/SN: Industrial Temp., SOIC package 25C040T-I/SN: Tape and Reel, Industrial Temp., SOIC package 25C040X-I/ST: Alternate Pinout, Industrial Temp., TSSOP package 25C040XT-I/ST: Alternate Pinout, Tape and Reel, Industrial Temp., TSSOP package 25C040-E/P: Extended Temp., PDIP package 25C040-E/SN: Extended Temp., SOIC package 25C040T-E/SN: Tape and Reel, Extended Temp., SOIC package Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. DS21204C-page 18 2001 Microchip Technology Inc. 25AA040/25LC040/25C040 “All rights reserved. Copyright © 2001, Microchip Technology Incorporated, USA. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.” Trademarks The Microchip name, logo, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, KEELOQ, SEEVAL, MPLAB and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Total Endurance, ICSP, In-Circuit Serial Programming, FilterLab, MXDEV, microID, FlexROM, fuzzyLAB, MPASM, MPLINK, MPLIB, PICDEM, ICEPIC, Migratable Memory, FanSense, ECONOMONITOR, SelectMode and microPort are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Term Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2001, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. 2001 Microchip Technology Inc. DS21204C-page 19 M WORLDWIDE SALES AND SERVICE AMERICAS New York Corporate Office 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 631-273-5305 Fax: 631-273-5335 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com Rocky Mountain 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7966 Fax: 480-792-7456 Atlanta 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307 Austin Analog Product Sales 8303 MoPac Expressway North Suite A-201 Austin, TX 78759 Tel: 512-345-2030 Fax: 512-345-6085 Boston 2 Lan Drive, Suite 120 Westford, MA 01886 Tel: 978-692-3848 Fax: 978-692-3821 Boston Analog Product Sales Unit A-8-1 Millbrook Tarry Condominium 97 Lowell Road Concord, MA 01742 Tel: 978-371-6400 Fax: 978-371-0050 Chicago 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075 Dallas 4570 Westgrove Drive, Suite 160 Addison, TX 75001 Tel: 972-818-7423 Fax: 972-818-2924 Dayton Two Prestige Place, Suite 130 Miamisburg, OH 45342 Tel: 937-291-1654 Fax: 937-291-9175 Detroit Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260 Los Angeles 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338 Mountain View Analog Product Sales 1300 Terra Bella Avenue Mountain View, CA 94043-1836 Tel: 650-968-9241 Fax: 650-967-1590 ASIA/PACIFIC (continued) Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea Tel: 82-2-554-7200 Fax: 82-2-558-5934 San Jose Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955 Singapore Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-334-8870 Fax: 65-334-8850 Toronto 6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509 Taiwan Microchip Technology Taiwan 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 ASIA/PACIFIC Australia Microchip Technology Australia Pty Ltd Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 EUROPE China - Beijing Denmark Microchip Technology Beijing Office Unit 915 New China Hong Kong Manhattan Bldg. No. 6 Chaoyangmen Beidajie Beijing, 100027, No. China Tel: 86-10-85282100 Fax: 86-10-85282104 Microchip Technology Denmark ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910 France China - Shanghai Microchip Technology Shanghai Office Room 701, Bldg. B Far East International Plaza No. 317 Xian Xia Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060 Hong Kong Microchip Asia Pacific RM 2101, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India Microchip Technology Inc. India Liaison Office Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O’Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062 Japan Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Arizona Microchip Technology SARL Parc d’Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany Arizona Microchip Technology GmbH Gustav-Heinemann Ring 125 D-81739 Munich, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 Germany Analog Product Sales Lochhamer Strasse 13 D-82152 Martinsried, Germany Tel: 49-89-895650-0 Fax: 49-89-895650-22 Italy Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 United Kingdom Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 01/30/01 All rights reserved. © 2001 Microchip Technology Incorporated. Printed in the USA. 5/01 Printed on recycled paper. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. DS21204C-page 20 2001 Microchip Technology Inc.