ETC 2SJ146

Silicon MOS FETs (Small Signal)
2SJ146
Silicon P-Channel MOS FET
For switching
unit: mm
+0.2
2.8 –0.3
■ Features
+0.25
0.65±0.15
1.45
0.95
1.5 –0.05
1
0.95
3
+0.1
0.4 –0.05
+0.2
2.9 –0.05
● High-speed switching
● Mini-type package, allowing downsizing of the sets and automatic
insertion through the tape/magazine packing.
1.9±0.2
0.65±0.15
2
−50
V
Gate to Source voltage
VGSO
−8
V
Drain current
ID
−100
mA
Max drain current
IDP
−200
mA
Allowable power dissipation
PD
150
mW
Channel temperature
Tch
150
°C
Storage temperature
Tstg
−55 to +150
°C
+0.1
Symbol
0.16 –0.06
Unit
VDSS
0.1 to 0.3
0.4±0.2
0 to 0.1
Parameter
0.8
Ratings
Drain to Source breakdown voltage
+0.2
1.1 –0.1
■ Absolute Maximum Ratings (Ta = 25°C)
1: Gate
2: Source
3: Drain
JEDEC: TO-236
EIAJ: SC-59
Mini Type Package (3-pin)
Marking Symbol: 4D
■ Electrical Characteristics (Ta = 25°C)
Parameter
Symbol
Conditions
min
max
Unit
Drain to Source cut-off current
IDSS
VDS = −30V, VGS = 0
−10
µA
Gate to Source leakage current
IGSS
VGS = −8V, VDS = 0
−1
µA
Drain to Source breakdown voltage
VDSS
ID = −100µA, VGS = 0
−50
Gate threshold voltage
Vth
VDS = −5V, ID = −100µA
−1.5
Forward transfer admittance
| Yfs |
VDS = −10V, ID = −10mA, f = 1kHz
Drain to Source ON-resistance
RDS(on)
VGS = −5V, ID = −10mA
Input capacitance (Common Source) Ciss
Output capacitance (Common Source)
Coss
8
V
−3.5
13.5
V
mS
150
Ω
13
pF
VDS = −5V, VGS = 0, f = 1MHz
7
pF
Reverse transfer capacitance (Common Source) Crss
*
typ
3
pF
Turn-on time
ton*
VDD = −5V, VGS = 0 to −5V, RL = 400Ω
40
ns
Turn-off time
*
VDD = −5V, VGS = −5 to 0V, RL = 400Ω
60
ns
toff
ton, toff measurement circuit
Vout
400Ω
Vin
10%
50Ω
100µF
90%
VGS = –5V
90%
10%
VDD = –5V
Vout
ton
toff
1
Silicon MOS FETs (Small Signal)
2SJ146
PD  Ta
ID  VDS
24
Ta=25˚C
200
–50
160
120
80
VGS=–5.5V
–40
–5.0V
–30
–4.5V
–4.0V
–20
–3.5V
40
–10
0
0
20
40
60
80 100 120 140 160
–2.5V
–2.0V
0
Ambient temperature Ta (˚C)
–2
8
6
4
Coss
–10
–30
–100 –300 –1000
VIN  IO
–1000
VO=–5V
Ta=25˚C
–300
–100
Input voltage VIN (V)
VDS=–5V
–100
–80
Ta=–25˚C
–60
25˚C
75˚C
–40
0
–3
–30
–10
–3
–1
– 0.3
– 0.1
– 0.1 – 0.3
–1
–3
–10
–30
Output current IO (mA)
8
4
0
0
–2
–100
0
–2
–4
–6
–4
–6
–8
–10
–12
Gate to source voltage VGS (V)
RDS(on)  VGS
Crss
0
–1
12
–12
–20
Drain to source voltage VDS (V)
2
–10
–120
Drain current ID (mA)
Input capacitance (Common source), Output capacitance (Common source),
Reverse transfer capacitance (Common source) Ciss,Coss,Crss (pF)
Ciss
2
–8
16
ID  VGS
VGS=0
f=1MHz
Ta=25˚C
10
–6
VDS=–10V
f=1kHz
Ta=25˚C
20
Drain to source voltage VDS (V)
Ciss, Coss, Crss  VDS
12
–4
–8
–10
–12
Gate to source voltage VGS (V)
Drain to source ON-resistance RDS(on) (Ω)
0
–3.0V
Forward transfer admittance |Yfs| (mS)
–60
Drain current ID (mA)
Allowable power dissipation PD (mW)
240
| Yfs |  VGS
240
ID=–10mA
Ta=25˚C
200
160
120
Ta=75˚C
80
25˚C
–25˚C
40
0
0
–2
–4
–6
–8
–10
–12
Gate to source voltage VGS (V)