RENESAS LA3A

Datasheet
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
RENESAS MCU
R01DS0011EJ0100
Rev.1.00
Dec 21, 2010
1. Overview
1.1
Features
The R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, and R8C/LA8A Group of single-chip MCUs
incorporate the R8C CPU core, which implements a powerful instruction set for a high level of efficiency and
supports a 1 Mbyte address space, allowing execution of instructions at high speed. In addition, the CPU core
integrates a multiplier for high-speed operation processing.
Power consumption is low, and the supported operating modes allow additional power control. These MCUs are
designed to maximize EMI/EMS performance.
Integration of many peripheral functions, including multifunction timer and serial interface, helps reduce the
number of system components.
The R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, and R8C/LA8A Group have data flash (1 KB × 2
blocks).
1.1.1
Applications
Household appliances, office equipment, audio equipment, consumer products, etc.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 1 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
1.1.2
1. Overview
Differences between Groups
Table 1.1 lists the Differences between Groups, Tables 1.2 and 1.3 list the Programmable I/O Ports Provided for
Each Group, and Tables 1.4 and 1.5 list the LCD Display Function Pins Provided for Each Group.
Figures 1.9 to 1.12 show the pin assignment for each group, and Tables 1.9 to 1.12 list product information.
The explanations in the chapters which follow apply to the R8C/LA8A Group only. Note the differences shown
below.
Table 1.1
Differences between Groups
Item
Function
R8C/LA3A Group
R8C/LA5A Group
R8C/LA6A Group
Programmable I/O ports
26 pins
44 pins
56 pins
72 pins
High current drive ports
8 pins
8 pins
8 pins
10 pins
Interrupts
INT interrupt pins
5 pins
6 pins
8 pins
8 pins
Timer RJ
Timer RJ0 output pin
None
None
None
1 pin
Timer RJ1 output pin
None
None
None
1 pin
Timer RJ2 I/O pin
None
None
None
1 pin
Timer RJ2 output pin
None
None
None
1 pin
Timer RH output pin
None
1 pin
1 pin
1 pin
I/O Ports
Timer RH
R8C/LA8A Group
Serial interface
UART2
None
None
1 pin
1 pin
A/D Converter
Analog input pins
5 pins
7 pins
8 pins
12 pins
LCD Drive
Control Circuit
Segment output pins
Max. 11 pins
Max. 27 pins
Max. 32 pins
Max. 40 pins
Comparator B
Clock
Analog input voltage
1 pin
2 pins
2 pins
2 pins
Reference input voltage
1 pin
2 pins
2 pins
2 pins
XCIN pin
Shared with
XIN pin
Dedicated pin
Dedicated pin
Dedicated pin
XCOUT pin
Shared with
XOUT pin
Dedicated pin
Dedicated pin
Dedicated pin
32-pin LQFP
52-pin LQFP
64-pin LQFP
80-pin LQFP
Packages
Note:
1. I/O ports are shared with I/O functions, such as interrupts or timers.
Refer to Tables 1.13 to 1.17, Pin Name Information by Pin Number, for details.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 2 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 1.2
1. Overview
Programmable I/O Ports Provided for Each Group (R8C/LA3A Group, R8C/LA5A Group)
Programmable
I/O Port
P0
P2
P3
P5
P7
P8
P9
R8C/LA3A Group
R8C/LA5A Group
Total: 26 I/O pins
Total: 44 I/O pins
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
—
—
—
—
—
—
—
—
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
—
—
—
—
—
—
—
—
3
3
3
3
3
3
3
3
—
3
3
3
3
3
3
3
—
3
3
3
3
3
3
3
—
—
—
—
—
—
—
—
—
—
—
—
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
—
—
—
—
—
—
3
3
—
—
—
—
—
—
3
3
Notes:
1. The symbol “3” indicates a programmable I/O port.
2. The symbol “—” indicates the settings should be made as follows:
- Set 0 to the corresponding bits in the PDi (i = 0, 3, 5, 7, 9) register. When read, the content is 0.
- Set 0 to the corresponding bits in the Pi (i = 0, 3, 5, 7, 9) register. When read, the content is 0.
Table 1.3
Programmable I/O Ports Provided for Each Group (R8C/LA6A Group, R8C/LA8A Group)
Programmable
I/O Port
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
R8C/LA6A Group
R8C/LA8A Group
Total: 56 I/O pins
Total: 72 I/O pins
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
—
—
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
—
—
—
—
—
—
3
3
3
3
3
3
3
3
—
3
3
3
3
3
3
3
—
3
3
3
3
3
3
3
3
3
3
3
3
3
3
—
3
3
3
3
3
3
3
3
—
—
—
—
—
—
—
—
—
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
—
—
—
—
—
—
3
3
—
—
—
—
—
—
3
3
Notes:
1. The symbol “3” indicates a programmable I/O port.
2. The symbol “—” indicates the settings should be made as follows:
- Set 0 to the corresponding bits in the PDi (i = 1, 4 to 7, 9) register. When read, the content is 0.
- Set 0 to the corresponding bits in the Pi (i = 1, 4 to 7, 9) register. When read, the content is 0.
- Set 0 to the corresponding bits in the P7DRR register. When read, the content is 0.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
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R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 1.4
1. Overview
LCD Display Function Pins Provided for Each Group
(R8C/LA3A Group, R8C/LA5A Group)
R8C/LA3A Group
Common output: Max. 4
Segment output: Max. 11
Shared I/O Port
P0
—
P2
—
—
—
—
—
SEG SEG SEG SEG SEG SEG
15 14 13 12 11 10
P3
—
P5
—
—
—
—
—
—
COM
VL3 VL2 VL1 COM 1
(2)
(2)
(2)
0 SEG
26
SEG
7
SEG SEG SEG
9
8
15
SEG
—
—
23
COM COM
2
3
—
SEG SEG
25 24
—
—
R8C/LA5A Group
Common output: Max. 4
Segment output: Max. 27
SEG SEG SEG SEG SEG SEG
6
5
4
3
2
1
SEG SEG SEG SEG SEG SEG
14 13 12 11 10
9
SEG SEG SEG SEG SEG SEG
22 21 20 19 18 17
COM COM
VL3 VL2 VL1 COM 1
2
(2)
(2)
(2)
0 SEG SEG
26 25
SEG
0
SEG
8
SEG
16
COM
3
SEG
24
Notes:
1. The symbol “—” indicates there is no LCD display function. Set the corresponding bits to 0 by setting registers
LSE0, LSE2, and LSE5 for these pins.
2. When using the LCD drive control circuit, set the corresponding bit in the LSE5 register to 1.
Table 1.5
LCD Display Function Pins Provided for Each Group
(R8C/LA6A Group, R8C/LA8A Group)
Shared I/O Port
P0
P1
P2
P3
P4
P5
SEG
7
SEG
15
SEG
23
SEG
31
SEG
39
—
R8C/LA6A Group
Common output: Max. 4
Segment output: Max. 32
SEG SEG SEG SEG SEG SEG
6
5
4
3
2
1
SEG SEG SEG SEG SEG
—
14 13 12 11 10
SEG SEG SEG SEG SEG SEG
22 21 20 19 18 17
SEG SEG SEG SEG SEG SEG
30 29 28 27 26 25
SEG
—
—
—
—
—
38
VL3 VL2 VL1 COM COM COM
(2)
(2)
(2)
0
1
2
SEG SEG
0
7
SEG
—
15
SEG SEG
16 23
SEG SEG
24 31
SEG
—
39
COM
—
3
R8C/LA8A Group
Common output: Max. 4
Segment output: Max. 40
SEG SEG SEG SEG SEG SEG
6
5
4
3
2
1
SEG SEG SEG SEG SEG SEG
14 13 12 11 10
9
SEG SEG SEG SEG SEG SEG
22 21 20 19 18 17
SEG SEG SEG SEG SEG SEG
30 29 28 27 26 25
SEG SEG SEG SEG SEG SEG
38 37 36 35 34 33
VL3 VL2 VL1 COM COM COM
(2)
(2)
(2)
0
1
2
SEG
0
SEG
8
SEG
16
SEG
24
SEG
32
COM
3
Notes:
1. The symbol “—” indicates there is no LCD display function. Set the corresponding bits to 0 by setting registers
LSE1, LSE4 and LSE5 for these pins.
2. When using the LCD drive control circuit, set the corresponding bit in the LSE5 register to 1.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
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R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
1.1.3
1. Overview
Specifications
Tables 1.6 to 1.8 list the specifications.
Table 1.6
Specifications (1)
Item
CPU
Function
Central processing unit
Memory
ROM/RAM
Data flash
Voltage detection circuit
Power
Supply
Voltage
Detection
I/O Ports Programmable R8C/LA3A Group
I/O ports
R8C/LA5A Group
R8C/LA6A Group
R8C/LA8A Group
Clock
Clock generation circuits
Interrupts
R8C/LA3A Group
R8C/LA5A Group
R8C/LA6A Group
R8C/LA8A Group
Watchdog Timer
Specification
R8C CPU core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 2.7 V to 5.5 V)
125 ns (f(XIN) = 8 MHz, VCC = 1.8 V to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operating mode: Single-chip mode (address space: 1 Mbyte)
Refer to Tables 1.9 to 1.12 Product Lists.
• Power-on reset
• Voltage detection 3 (detection level of voltage detection 0 and
voltage detection 1 selectable)
• CMOS I/O ports: 26, selectable pull-up resistor (1)
• High current drive ports: 8
• CMOS I/O ports: 44, selectable pull-up resistor (1)
• High current drive ports: 8
• CMOS I/O ports: 56, selectable pull-up resistor (1)
• High current drive ports: 8
• CMOS I/O ports: 72, selectable pull-up resistor (1)
• High current drive ports: 10
4 circuits: XIN clock oscillation circuit
XCIN clock oscillation circuit (32 kHz)
High-speed on-chip oscillator (with frequency adjustment function)
Low-speed on-chip oscillator
• Oscillation stop detection:
XIN clock oscillation stop detection function
• Frequency divider circuit:
Division ratio selectable from 1, 2, 4, 8, and 16
• Low-power-consumption modes:
Standard operating mode (high-speed clock, low-speed clock, highspeed on-chip oscillator, low-speed on-chip oscillator), wait mode,
stop mode, power-off mode
Real-time clock (timer RH)
• Number of interrupt vectors: 69
• External Interrupt: 13 (INT × 5, key input × 8)
• Priority levels: 7 levels
• Number of interrupt vectors: 69
• External Interrupt: 14 (INT × 6, key input × 8)
• Priority levels: 7 levels
• Number of interrupt vectors: 69
• External Interrupt: 16 (INT × 8, key input × 8)
• Priority levels: 7 levels
• 14 bits × 1 (with prescaler)
• Selectable reset start function
• Selectable low-speed on-chip oscillator for watchdog timer
Note:
1. No pull-up resistor is provided in the pins P5_4 to P5_6.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
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R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 1.7
1. Overview
Specifications (2)
Item
Timer
Function
Specification
Timer RB0, Timer RB1 8 bits × 2 (with 8-bit prescaler)
Timer mode (period timer), programmable waveform generation mode
(PWM output), programmable one-shot generation mode, programmable wait
one-shot generation mode
Timer RC
16 bits × 1 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function),
PWM mode (output: 3 pins), PWM2 mode (PWM output: 1 pin)
Timer RH
Real-time clock mode (counting of seconds, minutes, hours, day of the week,
date, month, year), output compare mode
Timer RJ0 R8C/LA3A Timer RJ0,
16 bits × 2
Timer mode (period timer), pulse output mode
(output level inverted every period), event
Timer RJ1 Group
Timer RJ1
counter mode, pulse width measurement mode,
Timer RJ2 R8C/LA5A
pulse period measurement mode
Group
R8C/LA6A
Group
R8C/LA8A Timer RJ0,
16 bits × 3
Group
Timer RJ1,
Timer RJ2
Serial
UART0
1 channel
Interface
Clock synchronous serial I/O/UART
UART2
1 channel
Clock synchronous serial I/O/UART, I2C mode (I2C-bus), multiprocessor
communication function
Synchronous Serial
1 (shared with I2C-bus)
Communication Unit (SSU)
1 (shared with SSU)
I2C bus
A/D Converter
R8C/LA3A 10-bit resolution × 5 channels, including sample and hold function, with sweep
Group
mode, temperature sensor included (measurement temperature range:
−20 to 85 °C (N version)/ −40 to 85 °C (D version))
R8C/LA5A 10-bit resolution × 7 channels, including sample and hold function, with sweep
Group
mode, temperature sensor included (measurement temperature range:
−20 to 85 °C (N version)/ −40 to 85 °C (D version))
R8C/LA6A 10-bit resolution × 8 channels, including sample and hold function, with sweep
Group
mode, temperature sensor included (measurement temperature range:
−20 to 85 °C (N version)/ −40 to 85 °C (D version))
R8C/LA8A 10-bit resolution × 12 channels, including sample and hold function, with sweep
Group
mode, temperature sensor included (measurement temperature range:
−20 to 85 °C (N version)/ −40 to 85 °C (D version))
Comparator B
R8C/LA3A 1 circuit (comparator B1)
Group
R8C/LA5A 2 circuits (comparator B1, comparator B3)
Group
R8C/LA6A
Group
R8C/LA8A
Group
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 6 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 1.8
1. Overview
Specifications (3)
Item
Function
LCD Drive Control R8C/LA3A
Circuit
Group
R8C/LA5A
Group
R8C/LA6A
Group
R8C/LA8A
Group
Flash Memory
Specification
Common output: Max. 4 pins
Segment output: Max. 11 pins
Common output: Max. 4 pins
Segment output: Max. 27 pins • Bias: 1/2, 1/3
Common output: Max. 4 pins • Duty: static, 1/2, 1/3, 1/4
Segment output: Max. 32 pins
Common output: Max. 4 pins
Segment output: Max. 40 pins
• Programming and erasure voltage: VCC = 1.8 V to 5.5 V (data flash VCC = 1.8 V to
5.5 V)
• Programming and erasure endurance: 10,000 times (data flash)
10,000 times (program ROM)
• Program security: ROM code protect, ID code check
• On-chip debug function
• On-board flash rewrite function
Operating Frequency/
f(XIN) = 20 MHz (VCC = 2.7 V to 5.5 V)
Supply Voltage
f(XIN) = 8 MHz (VCC = 1.8 V to 5.5 V)
Current Consumption
Typ. 4.7 mA (VCC = 5.0 V, f(XIN) = 20 MHz)
Typ. 2.3 mA (VCC = 3.0 V, f(XIN) = 10 MHz)
Typ. 1.7 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz))
Typ. 0.5 µA (VCC = 3.0 V, stop mode)
Typ. 1.3 µA (VCC = 3.0 V, power-off 2 mode, timer RH enabled)
Typ. 0.01 µA (VCC = 3.0 V, power-off 0 mode, timer RH disabled)
Operating Ambient Temperature −20 to 85°C (N version)
−40 to 85°C (D version) (1)
Note:
1. Specify the D version if D version functions are to be used.
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Dec 21, 2010
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R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
1.2
1. Overview
Product Lists
Tables 1.9 to 1.12 list product information for each group. Figures 1.1 to 1.4 show the Correspondence of Part No.,
with Memory Size and Package for each group.
Table 1.9
Product List for R8C/LA3A Group
Part No.
R5F2LA32ANFP
R5F2LA34ANFP
R5F2LA36ANFP
R5F2LA38ANFP
R5F2LA32ADFP
R5F2LA34ADFP
R5F2LA36ADFP
R5F2LA38ADFP
Internal ROM Capacity
Program ROM
Data Flash
8 Kbytes
1 Kbyte × 2
16 Kbytes
1 Kbyte × 2
32 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
8 Kbytes
1 Kbyte × 2
16 Kbytes
1 Kbyte × 2
32 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
Current of Dec 2010
Internal RAM
Capacity
2 Kbytes
2 Kbytes
2 Kbytes
3.5 Kbytes
2 Kbytes
2 Kbytes
2 Kbytes
3.5 Kbytes
Package Type
PLQP0032GB-A
PLQP0032GB-A
PLQP0032GB-A
PLQP0032GB-A
PLQP0032GB-A
PLQP0032GB-A
PLQP0032GB-A
PLQP0032GB-A
Remarks
N Version
D Version
Part No. R 5 F 2L A3 8 A N FP
Package type:
FP: LQFP (0.8 mm pin-pitch)
Classification
N: Operating ambient temperature −20 to 85°C
D: Operating ambient temperature −40 to 85°C
DataFlash
A: DataFlash
ROM capacity
2: 8KB
4: 16KB
6: 32KB
8: 64KB
R8C/LA3A Group
R8C/Lx Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.1
Correspondence of Part No., with Memory Size and Package of R8C/LA3A Group
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 8 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 1.10
1. Overview
Product List for R8C/LA5A Group
Part No.
R5F2LA52ANFP
R5F2LA54ANFP
R5F2LA56ANFP
R5F2LA58ANFP
R5F2LA52ADFP
R5F2LA54ADFP
R5F2LA56ADFP
R5F2LA58ADFP
Internal ROM Capacity
Program ROM
Data Flash
8 Kbytes
1 Kbyte × 2
16 Kbytes
1 Kbyte × 2
32 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
8 Kbytes
1 Kbyte × 2
16 Kbytes
1 Kbyte × 2
32 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
Current of Dec 2010
Internal RAM
Capacity
2 Kbytes
2 Kbytes
2 Kbytes
3.5 Kbytes
2 Kbytes
2 Kbytes
2 Kbytes
3.5 Kbytes
Package Type
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
Remarks
N Version
D Version
Part No. R 5 F 2L A5 8 A N FP
Package type:
FP: LQFP (0.65 mm pin-pitch)
Classification
N: Operating ambient temperature −20 to 85°C
D: Operating ambient temperature −40 to 85°C
DataFlash
A: DataFlash
ROM capacity
2: 8KB
4: 16KB
6: 32KB
8: 64KB
R8C/LA5A Group
R8C/Lx Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.2
Correspondence of Part No., with Memory Size and Package of R8C/LA5A Group
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 9 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 1.11
1. Overview
Product List for R8C/LA6A Group
Part No.
R5F2LA64ANFP
R5F2LA64ANFA
R5F2LA66ANFP
R5F2LA66ANFA
R5F2LA67ANFP
R5F2LA67ANFA
R5F2LA68ANFP
R5F2LA68ANFA
R5F2LA64ADFP
R5F2LA64ADFA
R5F2LA66ADFP
R5F2LA66ADFA
R5F2LA67ADFP
R5F2LA67ADFA
R5F2LA68ADFP
R5F2LA68ADFA
Internal ROM Capacity
Program ROM
Data Flash
16 Kbytes
1 Kbyte × 2
16 Kbytes
1 Kbyte × 2
32 Kbytes
1 Kbyte × 2
32 Kbytes
1 Kbyte × 2
48 Kbytes
1 Kbyte × 2
48 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
16 Kbytes
1 Kbyte × 2
16 Kbytes
1 Kbyte × 2
32 Kbytes
1 Kbyte × 2
32 Kbytes
1 Kbyte × 2
48 Kbytes
1 Kbyte × 2
48 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
Current of Dec 2010
Internal RAM
Capacity
2 Kbytes
2 Kbytes
2 Kbytes
2 Kbytes
3.5 Kbytes
3.5 Kbytes
3.5 Kbytes
3.5 Kbytes
2 Kbytes
2 Kbytes
2 Kbytes
2 Kbytes
3.5 Kbytes
3.5 Kbytes
3.5 Kbytes
3.5 Kbytes
Package Type
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0064KB-A
PLQP0064GA-A
Remarks
N Version
D Version
Part No. R 5 F 2L A6 8 A N FP
Package type:
FP: LQFP (0.5 mm pin-pitch)
FA: LQFP (0.8 mm pin-pitch)
Classification
N: Operating ambient temperature −20 to 85°C
D: Operating ambient temperature −40 to 85°C
DataFlash
A: DataFlash
ROM capacity
4: 16KB
6: 32KB
7: 48KB
8: 64KB
R8C/LA6A Group
R8C/Lx Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.3
Correspondence of Part No., with Memory Size and Package of R8C/LA6A Group
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 10 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 1.12
1. Overview
Product List for R8C/LA8A Group
Part No.
R5F2LA84ANFP
R5F2LA84ANFA
R5F2LA86ANFP
R5F2LA86ANFA
R5F2LA87ANFP
R5F2LA87ANFA
R5F2LA88ANFP
R5F2LA88ANFA
R5F2LA84ADFP
R5F2LA84ADFA
R5F2LA86ADFP
R5F2LA86ADFA
R5F2LA87ADFP
R5F2LA87ADFA
R5F2LA88ADFP
R5F2LA88ADFA
Internal ROM Capacity
Program ROM
Data Flash
16 Kbytes
1 Kbyte × 2
16 Kbytes
1 Kbyte × 2
32 Kbytes
1 Kbyte × 2
32 Kbytes
1 Kbyte × 2
48 Kbytes
1 Kbyte × 2
48 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
16 Kbytes
1 Kbyte × 2
16 Kbytes
1 Kbyte × 2
32 Kbytes
1 Kbyte × 2
32 Kbytes
1 Kbyte × 2
48 Kbytes
1 Kbyte × 2
48 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
64 Kbytes
1 Kbyte × 2
Current of Dec 2010
Internal RAM
Capacity
2 Kbytes
2 Kbytes
2 Kbytes
2 Kbytes
3.5 Kbytes
3.5 Kbytes
3.5 Kbytes
3.5 Kbytes
2 Kbytes
2 Kbytes
2 Kbytes
2 Kbytes
3.5 Kbytes
3.5 Kbytes
3.5 Kbytes
3.5 Kbytes
Package Type
PLQP0080KB-A
PLQP0080JA-A
PLQP0080KB-A
PLQP0080JA-A
PLQP0080KB-A
PLQP0080JA-A
PLQP0080KB-A
PLQP0080JA-A
PLQP0080KB-A
PLQP0080JA-A
PLQP0080KB-A
PLQP0080JA-A
PLQP0080KB-A
PLQP0080JA-A
PLQP0080KB-A
PLQP0080JA-A
Remarks
N Version
D Version
Part No. R 5 F 2L A8 8 A N FP
Package type:
FP: LQFP (0.5 mm pin-pitch)
FA: LQFP (0.65 mm pin-pitch)
Classification
N: Operating ambient temperature −20 to 85°C
D: Operating ambient temperature −40 to 85°C
DataFlash
A: DataFlash
ROM capacity
4: 16KB
6: 32KB
7: 48KB
8: 64KB
R8C/LA8A Group
R8C/Lx Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.4
Correspondence of Part No., with Memory Size and Package of R8C/LA8A Group
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 11 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
1.3
1. Overview
Block Diagrams
Figure 1.5 shows a Block Diagram of R8C/LA3A Group. Figure 1.6 shows a Block Diagram of R8C/LA5A Group.
Figure 1.7 shows a Block Diagram of R8C/LA6A Group. Figure 1.8 shows a Block Diagram of R8C/LA8A Group.
I/O ports
8
7
Port P2
Port P5
Peripheral functions
I2C bus or SSU
(8 bits × 1)
1
8
Port P9
XIN-XOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
XCIN-XCOUT
Port P8
Timer RB (8 bits × 2)
Timer RC (16 bits × 1)
Timer RH
Timer RJ (16 bits × 2)
System clock generation
circuit
Port P7
Timers
UART or
clock synchronous serial I/O
(8 bits × 1)
2
Low-speed on-chip oscillator
for watchdog timer
Watchdog timer
(14 bits)
A/D converter
(10 bits × 5 channels)
Temperature Sensor
Voltage detection circuit
LCD drive control circuit
Common output: Max. 4 pins
Segment output: Max. 11 pins
Comparator B 1 ch
Memory
R8C CPU core
R0H
R1H
R2
R3
R0L
R1L
A0
A1
FB
ROM (1)
SB
USP
ISP
INTB
PC
RAM (2)
FLG
Multiplier
Notes:
1. ROM capacity varies with MCU type.
2. RAM capacity varies with MCU type.
Figure 1.5
Block Diagram of R8C/LA3A Group
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 12 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
I/O ports
1. Overview
8
8
8
7
Port P0
Port P2
Port P3
Port P5
Peripheral functions
I2C bus or SSU
(8 bits × 1)
3
8
Port P9
XIN-XOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
XCIN-XCOUT
Port P8
Timer RB (8 bits × 2)
Timer RC (16 bits × 1)
Timer RH
Timer RJ (16 bits × 2)
System clock generation
circuit
Port P7
Timers
UART or
clock synchronous serial I/O
(8 bits × 1)
2
Low-speed on-chip oscillator
for watchdog timer
Watchdog timer
(14 bits)
A/D converter
(10 bits × 7 channels)
Temperature Sensor
Voltage detection circuit
LCD drive control circuit
Common output: Max. 4 pins
Segment output: Max. 27 pins
Comparator B 2 ch
Memory
R8C CPU core
R0H
R1H
R2
R3
R0L
R1L
A0
A1
FB
ROM (1)
SB
USP
ISP
INTB
PC
RAM (2)
FLG
Multiplier
Notes:
1. ROM capacity varies with MCU type.
2. RAM capacity varies with MCU type.
Figure 1.6
Block Diagram of R8C/LA5A Group
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 13 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
I/O ports
1. Overview
8
6
8
8
2
7
7
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Peripheral functions
Timers
XIN-XOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
XCIN-XCOUT
UART,
clock synchronous serial I/O,
2
or I C bus (8 bits × 1)
Low-speed on-chip oscillator
for watchdog timer
Temperature Sensor
Voltage detection circuit
LCD drive control circuit
Memory
R8C CPU core
R0L
R1L
A0
A1
FB
2
Common output: Max. 4 pins
Segment output: Max. 32 pins
Comparator B 2ch
R0H
R1H
R2
R3
8
Port P9
I2C bus or SSU
(8 bits × 1)
Watchdog timer
(14 bits)
A/D converter
(10 bits × 8 channels)
System clock generation
circuit
Port P8
Timer RB (8 bits × 2)
Timer RC (16 bits × 1)
Timer RH
Timer RJ (16 bits × 2)
UART or
clock synchronous serial I/O
(8 bits × 1)
ROM (1)
SB
USP
ISP
INTB
PC
RAM (2)
FLG
Multiplier
Notes:
1. ROM capacity varies with MCU type.
2. RAM capacity varies with MCU type.
Figure 1.7
Block Diagram of R8C/LA6A Group
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 14 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
I/O ports
1. Overview
8
8
8
8
8
7
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Peripheral functions
UART,
clock synchronous serial I/O,
2
or I C bus (8 bits × 1)
Low-speed on-chip oscillator
for watchdog timer
Watchdog timer
(14 bits)
A/D converter
(10 bits × 12 channels)
Temperature Sensor
Voltage detection circuit
LCD drive control circuit
A0
A1
FB
2
Memory
R8C CPU core
R0L
R1L
8
Common output: Max. 4 pins
Segment output: Max. 40 pins
Comparator B 2ch
R0H
R1H
R2
R3
7
Port P9
I2C bus or SSU
(8 bits × 1)
XIN-XOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
XCIN-XCOUT
Port P8
Timer RB (8 bits × 2)
Timer RC (16 bits × 1)
Timer RH
Timer RJ (16 bits × 3)
System clock generation
circuit
Port P7
Timers
UART or
clock synchronous serial I/O
(8 bits × 1)
ROM (1)
SB
USP
ISP
INTB
PC
RAM (2)
FLG
Multiplier
Notes:
1. ROM capacity varies with MCU type.
2. RAM capacity varies with MCU type.
Figure 1.8
Block Diagram of R8C/LA8A Group
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 15 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
1.4
1. Overview
Pin Assignments
P2_2/SEG10/INT0
P2_3/SEG11/INT5
P2_4/SEG12(/INT1)/KI0
P2_5/SEG13(/INT2)/KI1
P2_6/SEG14(/INT3)/KI2
P2_7/SEG15/COMEXP/KI3
P5_0/COM3/SEG24/KI4
P5_1/COM2/SEG25/KI5
Figures 1.9 to 1.12 show pin assignments (top view). Tables 1.13 to 1.17 list the pin name information by pin
number.
24 23 22 21 20 19 18 17
P2_1/SEG9/TRB0O
P2_0/SEG8/TRB1O
P7_1/TRCCLK/INT2/AN5
P8_7(/TRCTRG)/TRCIOA/IVREF1/AN3
P8_6(/TRCIOB)/RXD0/AN2
P8_5/TRCIOC(/TRCIOB)/TXD0/AN1
P8_4/TRCIOD(/TRCIOB)/CLK0/AN0
WKUP0
25
16
26
15
27
R8C/LA3A Group
28
29
14
13
PLQP0032GB-A (32P6U-A)
30
31
12
11
(top view)
10
32
9
2
3
4
5
6
7
8
VREF
MODE
RESET
P9_1/XOUT(/XCOUT)
VSS/AVSS
P9_0/XIN(/XCIN)
VCC/AVCC
P8_3/TRJ0IO/SSO/SDA
1
P5_2/COM1/SEG26/KI6
P5_3/COM0/KI7
P5_4/VL1
P5_5/VL2
P5_6/VL3
P8_0/IVCMP1/SCS/INT1
P8_1/SSI/INT3
P8_2/TRJ1IO/SSCK/SCL
Notes:
1. The pin in parentheses can be assigned by a program.
2. Confirm the pin 1 position on the package by referring to the Package Dimensions.
Figure 1.9
Pin Assignment (Top View) of PLQP0032GB-A Package
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 16 of 102
1. Overview
P2_0/SEG8/TRB1O
P2_1/SEG9/TRB0O
P2_2/SEG10/INT0
P2_3/SEG11/INT5
P2_4/SEG12(/INT1)/KI0
P2_5/SEG13(/INT2)/KI1
P2_6/SEG14(/INT3)/KI2
P2_7/SEG15/COMEXP/KI3
P3_0/SEG16
P3_1/SEG17
P3_2/SEG18
P3_3/SEG19
P3_4/SEG20
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
39 38 37 36 35 34 33 32 31 30 29 28 27
P0_7/SEG7/TRHO
P0_6/SEG6/SCS
P0_5/SEG5/SSI
P0_4/SEG4/SSCK/SCL
P0_3/SEG3/SSO/SDA
P0_2/SEG2
P0_1/SEG1
P0_0/SEG0(/TRCTRG)/INT7/ADTRG
P7_2(/TRCTRG)/AN6
P7_1/TRCCLK/INT2/AN5
P7_0/IVREF3/WKUP1/AN4
P8_7(/TRCTRG)/TRCIOA/IVREF1/AN3
P8_6(/TRCIOB)/RXD0/AN2
40
26
41
25
42
24
43
23
R8C/LA5A Group
44
45
46
47
48
49
22
21
20
PLQP0052JA-A (52P6A-A)
(top view)
19
18
17
50
16
51
15
52
14
2
3
4
5
6
7
8
9 10 11 12 13
P8_5/TRCIOC(/TRCIOB)/TXD0/AN1
P8_4/TRCIOD(/TRCIOB)/CLK0/AN0
WKUP0
VREF
MODE
XCIN
XCOUT
RESET
P9_1/XOUT
VSS/AVSS
P9_0/XIN
VCC/AVCC
P8_3/TRJ0IO/SSO/SDA
1
P3_5/SEG21
P3_6/SEG22
P3_7/SEG23
P5_0/COM3/SEG24/KI4
P5_1/COM2/SEG25/KI5
P5_2/COM1/SEG26/KI6
P5_3/COM0/KI7
P5_4/VL1
P5_5/VL2
P5_6/VL3
P8_0/IVCMP1/SCS/INT1
P8_1/IVCMP3/SSI/INT3
P8_2/TRJ1IO/SSCK/SCL
Notes:
1. The pin in parentheses can be assigned by a program.
2. Confirm the pin 1 position on the package by referring to the Package Dimensions.
Figure 1.10
Pin Assignment (Top View) of PLQP0052JA-A Package
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 17 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 1.13
Pin Name Information by Pin Number (R8C/LA3A Group, R8C/LA5A Group)(1)
Pin Number
LA5A LA3A
I/O Pin Functions for Peripheral Modules
Control Pin
Port
Interrupt
Timer
TRCIOC/
(TRCIOB)
TRCIOD/
(TRCIOB)
1
30
P8_5
2
31
P8_4
3
32
4
5
6
7
1
2
8
3
9
4
10
5
11
6
12
13
14
7
8
9
15
10
P8_1
INT3
16
11
P8_0
INT1
17
18
19
20
12
13
14
15
P5_6
P5_5
P5_4
P5_3
KI7
21
16
P5_2
KI6
22
17
P5_1
KI5
23
18
P5_0
KI4
24
25
26
27
28
29
30
1. Overview
Serial Interface
SSU
I2C bus
A/D Converter,
Comparator B
TXD0
AN1
CLK0
AN0
LCD drive
Control
Circuit
WKUP0
VREF
MODE
XCIN
XCOUT
RESET
XOUT
(XCOUT) (2)
VSS/AVSS
XIN
(XCIN) (2)
VCC/AVCC
P9_1
P9_0
P8_3
P8_2
TRJ0IO
TRJ1IO
P3_7
P3_6
P3_5
P3_4
P3_3
P3_2
P3_1
SSO
SSCK
SSI
SCS
SDA
SCL
IVCMP3 (3)
IVCMP1
VL3
VL2
VL1
COM0
SEG26/
COM1
SEG25/
COM2
SEG24/
COM3
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
Note:
1. The pin in parentheses can be assigned by a program.
2. Pins (XCOUT) and (XCIN) are not available in the R8C/LA5A Group.
3. The IVCMP3 pin is not available in the R8C/LA3A Group.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 18 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 1.14
1. Overview
Pin Name Information by Pin Number (R8C/LA3A Group, R8C/LA5A Group)(2)
Pin Number
I/O Pin Functions for Peripheral Modules
Control
Pin
19
P2_7
KI3
LCD drive
Control
Circuit
SEG16
SEG15/
COMEXP
33
20
P2_6
(INT3)/KI2
SEG14
34
21
P2_5
(INT2)/KI1
SEG13
22
P2_4
(INT1)/KI0
SEG12
LA5A LA3A
31
32
35
Port
Interrupt
Serial Interface
SSU
I2C bus
A/D Converter,
Comparator B
P3_0
36
23
P2_3
37
24
P2_2
38
39
40
41
25
26
P2_1
P2_0
P0_7
P0_6
INT5
SEG11
INT0
SEG10
TRB0O
TRB1O
TRHO
P0_5
P0_4
P0_3
P0_2
P0_1
47
P0_0
INT7
P7_2
P7_1
INT2
48
27
50
WKUP1
SEG9
SEG8
SEG7
SCS
SSI
SSCK
SSO
42
43
44
45
46
49
Timer
(TRCTRG)
28
P8_7
52
29
P8_6
SEG5
SEG4
SEG3
SEG2
SEG1
SCL
SDA
SEG0
ADTRG
AN6
AN5
(TRCTRG)
TRCCLK
P7_0
51
SEG6
AN4/IVREF3
TRCIOA/
(TRCTRG)
(TRCIOB)
AN3/IVREF1
RXD0
AN2
Note:
1. The pin in parentheses can be assigned by a program.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 19 of 102
1. Overview
P1_2/SEG10/KI6
P1_3/SEG11/KI7
P1_4/SEG12/INT4
P1_5/SEG13/INT5
P1_6/SEG14/INT6
P1_7/SEG15
P2_0/SEG16
P2_1/SEG17
P2_2/SEG18
P2_3/SEG19
P2_4/SEG20
P2_5/SEG21
P2_6/SEG22
P2_7/SEG23
P3_0/SEG24(/INT0)
P3_1/SEG25(/INT1)
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P0_7/SEG7/TRHO/KI5
P0_6/SEG6/KI4
P0_5/SEG5/KI3
P0_4/SEG4/KI2
P0_3/SEG3/INT0/KI1
P0_2/SEG2(/TRCTRG)/KI0
P0_1/SEG1/INT7(/TRCCLK/TRCTRG)/ADTRG
P0_0/SEG0(/TRCIOA/TRCTRG)/AN11
P6_7(/TRCIOB)/AN10
P6_6(/TRCIOC/TRCIOB)/IVREF3(/TRB0O)/AN9
P6_5(/TRCIOD/TRCIOB)/IVREF1(/TRB1O)/AN8
P6_4(/SSO/SDA)/AN7
P6_3(/SSCK/SCL)/AN6
P6_2(/TRJ0IO/SSI)/AN5
P6_1(/TRJ1IO/SCS)/AN4
P8_7/TRB0O/INT2(/CTS2/RTS2)
49
32
50
31
51
30
52
29
53
28
54
27
R8C/LA6A Group
55
56
57
26
25
24
58
PLQP0064KB-A (64P6Q-A)
PLQP0064GA-A (64P6U-A)
(top view)
59
60
61
23
22
21
20
62
19
63
18
64
17
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
WKUP0
VREF
MODE
XCIN
XCOUT
RESET
P9_1/XOUT
VSS/AVSS
P9_0/XIN
VCC/AVCC
P8_6(/RXD0/RXD2/SCL2)
P8_5(/TXD0/TXD2/SDA2)
P8_4(/CLK0/CLK2)
P8_3/SSO/SDA(/TRJ0IO)
P8_2/SSCK/SCL(/TRJ1IO)
P8_1/SSI/IVCMP3/INT3
1
P3_2/SEG26(/INT2)
P3_3/SEG27(/INT3)
P3_4/SEG28(/INT4)
P3_5/SEG29(/INT5)
P3_6/SEG30(/INT6)
P3_7/SEG31(/INT7)
P4_6/SEG38
P4_7/SEG39/COMEXP
P5_0/COM3
P5_1/COM2
P5_2/COM1
P5_3/COM0
P5_4/VL1
P5_5/VL2
P5_6/VL3
P8_0/SCS/IVCMP1/INT1
Notes:
1. The pin in parentheses can be assigned by a program.
2. Confirm the pin 1 position on the package by referring to the Package Dimensions.
Figure 1.11
Pin Assignment (Top View) of PLQP0064KB-A and PLQP0064GA-A Packages
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 20 of 102
1. Overview
P0_7/SEG7/TRHO/KI5
P1_0/SEG8
P1_1/SEG9
P1_2/SEG10/KI6
P1_3/SEG11/KI7
P1_4/SEG12/INT4
P1_5/SEG13/INT5
P1_6/SEG14/INT6
P1_7/SEG15
P2_0/SEG16
P2_1/SEG17
P2_2/SEG18
P2_3/SEG19
P2_4/SEG20
P2_5/SEG21
P2_6/SEG22
P2_7/SEG23
P3_0/SEG24(/INT0)
P3_1/SEG25(/INT1)
P3_2/SEG26(/INT2)
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P0_6/SEG6/KI4
P0_5/SEG5/KI3
P0_4/SEG4/KI2
P0_3/SEG3/INT0/KI1
P0_2/SEG2(/TRCTRG)/KI0
P0_1/SEG1/INT7(/TRCCLK/TRCTRG)/ADTRG
P0_0/SEG0(/TRCIOA/TRCTRG)/AN11
P6_7(/TRCIOB)/AN10
P6_6(/TRCIOC/TRCIOB)/IVREF3(/TRB0O)/AN9
P6_5(/TRCIOD/TRCIOB)/IVREF1(/TRB1O)/AN8
P6_4(/SSO/SDA)/AN7
P6_3(/SSCK/SCL)/AN6
P6_2(/TRJ0IO/SSI)/AN5
P6_1(/TRJ1IO/SCS)/AN4
P6_0(/TRJ2IO)/AN3
P7_6(/TRB0O)/AN2
P7_5/TRB1O/AN1
P7_4/AN0
P7_3(/CTS2/RTS2)
P7_2(/TXD2/SDA2/RXD2/SCL2)/TRJ0O
61
40
62
39
63
38
64
37
65
36
66
35
67
34
R8C/LA8A Group
68
69
70
33
32
31
PLQP0080KB-A (80P6Q-A)
PLQP0080JA-A (FP-80W/FP-80WV)
(top view)
71
72
73
74
75
30
29
28
27
26
76
25
77
24
78
23
79
22
80
21
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
P7_1(/TXD2/SDA2/RXD2/SCL2)/TRJ1O
P7_0(/CLK2)/TRJ2O/WKUP1
P8_7/TRB0O/INT2(/CTS2/RTS2)
WKUP0
VREF
MODE
XCIN
XCOUT
RESET
P9_1/XOUT
VSS/AVSS
P9_0/XIN
VCC/AVCC
P8_6(/RXD0/RXD2/SCL2)
P8_5(/TXD0/TXD2/SDA2)
P8_4(/CLK0/CLK2)
P8_3/SSO/SDA(/TRJ0IO)
P8_2/SSCK/SCL(/TRJ1IO)
P8_1/SSI/IVCMP3/INT3
P8_0/SCS/IVCMP1/INT1
1
P3_3/SEG27(/INT3)
P3_4/SEG28(/INT4)
P3_5/SEG29(/INT5)
P3_6/SEG30(/INT6)
P3_7/SEG31(/INT7)
P4_0/SEG32
P4_1/SEG33
P4_2/SEG34
P4_3/SEG35
P4_4/SEG36
P4_5/SEG37
P4_6/SEG38
P4_7/SEG39/COMEXP
P5_0/COM3
P5_1/COM2
P5_2/COM1
P5_3/COM0
P5_4/VL1
P5_5/VL2
P5_6/VL3
Notes:
1. The pin in parentheses can be assigned by a program.
2. Confirm the pin 1 position on the package by referring to the Package Dimensions.
Figure 1.12
Pin Assignment (Top View) of PLQP0080KB-A and PLQP0080JA-A Packages
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R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 1.15
Pin Name Information by Pin Number (R8C/LA6A Group, R8C/LA8A Group)(1)
Pin Number
LA8A LA6A
I/O Pin Functions for Peripheral Modules
Control
Pin
1
2
WKUP1
3
64
4
1
5
6
7
8
2
3
4
5
9
6
10
7
11
8
12
9
13
10
14
15
16
17
18
11
12
13
14
15
1. Overview
Port
Timer
Serial Interface
P7_1
TRJ1O
(TXD2/SDA2/RXD2/
SCL2)
P7_0
TRJ2O
(CLK2)
TRB0O
(CTS2/RTS2)
P8_7
Interrupt
INT2
SSU
I2C bus
SSO
SSCK
SDA
SCL
A/D Converter,
Comparator B
LCD drive
Control
Circuit
WKUP0
VREF
MODE
XCIN
XCOUT
RESET
XOUT
VSS/
AVSS
XIN
VCC/
AVCC
P9_1
P9_0
P8_6
P8_5
P8_4
P8_3
P8_2
19
16
P8_1
20
17
P8_0
21
22
23
24
25
26
27
18
19
20
21
22
23
24
P5_6
P5_5
P5_4
P5_3
P5_2
P5_1
P5_0
28
25
P4_7
29
30
26
P4_6
P4_5
(RXD0/RXD2/SCL2)
(TXD0/TXD2/SDA2)
(CLK0/CLK2)
(TRJ0IO)
(TRJ1IO)
INT3
INT1
SSI
IVCMP3
SCS
IVCMP1
VL3
VL2
VL1
COM0
COM1
COM2
COM3
SEG39/
COMEXP
SEG38
SEG37
Note:
1. The pin in parentheses can be assigned by a program.
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R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 1.16
Pin Name Information by Pin Number (R8C/LA6A Group, R8C/LA8A Group)(2)
Pin Number
LA8A LA6A
31
32
33
34
35
1. Overview
I/O Pin Functions for Peripheral Modules
Control
Pin
Port
Interrupt
Timer
Serial Interface
SSU
I2C bus
A/D Converter,
Comparator B
P4_4
P4_3
P4_2
P4_1
P4_0
LCD drive
Control
Circuit
SEG36
SEG35
SEG34
SEG33
SEG32
36
27
P3_7
(INT7)
SEG31
37
28
P3_6
(INT6)
SEG30
38
29
P3_5
(INT5)
SEG29
39
30
P3_4
(INT4)
SEG28
40
31
P3_3
(INT3)
SEG27
41
32
P3_2
(INT2)
SEG26
42
33
P3_1
(INT1)
SEG25
43
34
P3_0
(INT0)
SEG24
44
45
46
47
48
49
50
51
52
35
36
37
38
39
40
41
42
43
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
P1_7
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
53
44
P1_6
INT6
SEG14
54
45
P1_5
INT5
SEG13
55
46
P1_4
INT4
SEG12
KI7
SEG11
KI6
SEG10
56
47
P1_3
57
48
P1_2
58
59
60
P1_1
P1_0
49
SEG9
SEG8
P0_7
KI5
TRHO
SEG7
61
50
P0_6
KI4
SEG6
62
51
P0_5
KI3
SEG5
63
52
P0_4
KI2
SEG4
64
53
P0_3
KI1/
INT0
SEG3
65
54
P0_2
KI0
66
55
P0_1
67
56
P0_0
68
57
P6_7
INT7
(TRCTRG)
(TRCTRG/
TRCCLK)
(TRCIOA/
TRCTRG)
(TRCIOB)
SEG2
ADTRG
SEG1
AN11
SEG0
AN10
Note:
1. The pin in parentheses can be assigned by a program.
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R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 1.17
Pin Name Information by Pin Number (R8C/LA6A Group, R8C/LA8A Group)(3)
Pin Number
LA8A LA6A
1. Overview
I/O Pin Functions for Peripheral Modules
Control
Pin
Port
Interrupt
Timer
Serial Interface
SSU
I2C
bus
(TRB0O/
TRCIOB/
TRCIOC)
(TRB1O/
TRCIOB/
TRCIOD)
69
58
P6_6
70
59
P6_5
71
72
73
60
61
62
P6_4
P6_3
P6_2
(TRJ0IO)
(SSO)
(SSCK)
(SSI)
74
63
(SCS)
P6_1
(TRJ1IO)
75
76
77
78
P6_0
P7_6
P7_5
P7_4
(TRJ2IO)
(TRB0O)
TRB1O
79
P7_3
80
P7_2
TRJ0O
A/D Converter,
Comparator B
LCD
drive
Control
Circuit
AN9/IVREF3
AN8/IVREF1
(SDA)
(SCL)
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
(CTS2/RTS2)
(RXD2/SCL2/
TXD2/SDA2)
Note:
1. The pin in parentheses can be assigned by a program.
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R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
1.5
1. Overview
Pin Functions
Tables 1.18 and 1.19 list Pin Functions for R8C/LA5A Group, and Tables 1.20 and 1.21 list Pin Functions for R8C/
LA8A Group.
Table 1.18
Pin Functions for R8C/LA5A Group (1)
Item
Pin Name
I/O Type
Description
Power supply input VCC, VSS
—
Apply 1.8 V to 5.5 V to the VCC pin.
Apply 0 V to the VSS pin.
Analog power
supply input
AVCC, AVSS
—
Power supply for the A/D converter.
Connect a capacitor between AVCC and AVSS.
Reset input
RESET
MODE
MODE
I
Connect this pin to VCC via a resistor.
WKUP0
I
This pin is provided for input to exit the mode used in power-off
0 mode. Connect to VSS when not using power-off 0 mode.
WKUP1
I
This pin is provided for input to exit the mode used in power-off
0 mode.
XIN clock input
XIN
I
XIN clock output
XOUT
O
These pins are provided for XIN clock generation circuit I/O.
Connect a ceramic oscillator or a crystal oscillator between pins
XIN and XOUT. (1) To use an external clock, input it to the XIN
pin and set XOUT as the I/O port P9_1. When the pin is not
used, treat it as an unassigned pin and use the appropriate
handling.
XCIN clock input
XCIN
I
XCIN clock output
XCOUT
O
INT interrupt input
INT0 to INT3,
INT5, INT7
I
INT interrupt input pins.
Key input interrupt
KI0 to KI7
I
Key input interrupt input pins
Timer RB
TRB0O, TRB1O
O
Timer RB output pin
Timer RC
TRCCLK
I
External clock input pin
Power-off 0 mode
exit input
TRCTRG
TRCIOA, TRCIOB,
TRCIOC, TRCIOD
I
I
Driving this pin low resets the MCU.
These pins are provided for XCIN clock generation circuit I/O.
Connect a crystal oscillator between pins XCIN and XCOUT. (1)
To use an external clock, input it to the XCIN pin and leave the
XCOUT pin open.
External trigger input pin
I/O
Timer RC I/O pins
Timer RH
TRHO
O
Timer RH output pin
Timer RJ
TRJ0IO, TRJ1IO
I/O
Timer RJ I/O pins
Serial interface
CLK0
I/O
RXD0
I
Serial data input pins
TXD0
O
Serial data output pins
Transfer clock I/O pins
I: Input
O: Output
I/O: Input and output
Note:
1. Contact the oscillator manufacturer for oscillation characteristics.
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R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 1.19
Pin Functions for R8C/LA5A Group (2)
Item
I2C
1. Overview
bus
SSU
Pin Name
I/O Type
Description
SCL
I/O
Clock I/O pin
SDA
I/O
Data I/O pin
SSI
I/O
Data I/O pin
SCS
I/O
Chip-select signal I/O pin
SSCK
I/O
Clock I/O pin
SSO
I/O
Reference voltage
input
VREF
I
Reference voltage input pin for the A/D converter
A/D converter
AN0 to AN6
I
A/D converter analog input pins
ADTRG
I
AD external trigger input pin
IVCMP1, IVCMP3
I
Comparator B analog voltage input pins
I
Comparator B reference voltage input pins
Comparator B
IVREF1, IVREF3
Data I/O pin
I/O ports
P0_0 to P0_7,
P2_0 to P2_7,
P3_0 to P3_7,
P5_0 to P5_6,
P7_0 to P7_2,
P8_0 to P8_7,
P9_0, P9_1
I/O
CMOS I/O ports. Each port has an I/O select direction register,
allowing each pin in the port to be directed for input or output
individually.
Any port set to input can be set to use a pull-up resistor or not
by a program.
Port P8 can be used as LED drive ports.
Segment output
SEG0 to SEG26
O
LCD segment output pins
Common output
COM0 to COM3,
COMEXP
O
LCD common output pins
LCD power supply
VL1
I
Apply the following voltage: 1 V ≤ VL1 ≤ VCC and VL1 ≤ VL2.
VL2
I
Apply the following voltage: VL2 ≤ 5.5 V and VL1 ≤ VL2 ≤ VL3.
VL3
I
Apply the following voltage: VL3 ≤ 5.5 V and VL2 ≤ VL3.
I: Input
O: Output
I/O: Input and output
Note:
1. Contact the oscillator manufacturer for oscillation characteristics.
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R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 1.20
1. Overview
Pin Functions for R8C/LA8A Group (1)
Item
Pin Name
I/O Type
Description
Power supply input VCC, VSS
—
Apply 1.8 V to 5.5 V to the VCC pin.
Apply 0 V to the VSS pin.
Analog power
supply input
AVCC, AVSS
—
Power supply for the A/D converter.
Connect a capacitor between AVCC and AVSS.
Reset input
RESET
I
Driving this pin low resets the MCU.
MODE
MODE
I
Connect this pin to VCC via a resistor.
Power-off 0 mode
exit input
WKUP0
I
This pin is provided for input to exit the mode used in power-off
0 mode. Connect to VSS when not using power-off 0 mode.
WKUP1
I
This pin is provided for input to exit the mode used in power-off
0 mode.
XIN clock input
XIN
I
XIN clock output
XOUT
O
These pins are provided for XIN clock generation circuit I/O.
Connect a ceramic oscillator or a crystal oscillator between pins
XIN and XOUT. (1) To use an external clock, input it to the XIN
pin and set XOUT as the I/O port P9_1. When the pin is not
used, treat it as an unassigned pin and use the appropriate
handling.
XCIN clock input
XCIN
I
XCIN clock output
XCOUT
O
INT interrupt input
These pins are provided for XCIN clock generation circuit I/O.
Connect a crystal oscillator between pins XCIN and XCOUT. (1)
To use an external clock, input it to the XCIN pin and leave the
XCOUT pin open.
INT0 to INT7
I
INT interrupt input pins.
Key input interrupt
KI0 to KI7
I
Key input interrupt input pins
Timer RB
TRB0O, TRB1O
O
Timer RB output pin
TRCCLK
I
External clock input pin
TRCTRG
I
External trigger input pin
Timer RC
TRCIOA, TRCIOB,
TRCIOC, TRCIOD
I/O
Timer RC I/O pins
Timer RH
TRHO
O
Timer RH output pin
Timer RJ
TRJ0IO, TRJ1IO,
TRJ2IO
I/O
Timer RJ I/O pins
TRJ0IO, TRJ1IO,
TRJ2IO
O
Timer RJ output pins
CLK0, CLK2
I/O
Transfer clock I/O pins
Serial interface
RXD0, RXD2
I
Serial data input pins
TXD0, TXD2
O
Serial data output pins
CTS2
I
Transmission control input pin
RTS2
O
Reception control output pin
SCL2
I/O
I2C mode clock I/O pin
SDA2
I/O
I2C mode data I/O pin
I: Input
O: Output
I/O: Input and output
Note:
1. Contact the oscillator manufacturer for oscillation characteristics.
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R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 1.21
Pin Functions for R8C/LA8A Group (2)
Item
I2C
1. Overview
bus
SSU
Pin Name
I/O Type
Description
SCL
I/O
Clock I/O pin
SDA
I/O
Data I/O pin
SSI
I/O
Data I/O pin
SCS
I/O
Chip-select signal I/O pin
SSCK
I/O
Clock I/O pin
SSO
I/O
Reference voltage
input
VREF
I
Reference voltage input pin for the A/D converter
A/D converter
AN0 to AN11
I
A/D converter analog input pins
ADTRG
I
AD external trigger input pin
Comparator B
IVCMP1, IVCMP3
I
Comparator B analog voltage input pins
I
Comparator B reference voltage input pins
I/O ports
P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_7,
P3_0 to P3_7,
P4_0 to P4_7,
P5_0 to P5_6,
P6_0 to P6_7
P7_0 to P7_6,
P8_0 to P8_7,
P9_0, P9_1
I/O
Segment output
SEG0 to SEG39
O
LCD segment output pins
Common output
COM0 to COM3,
COMEXP
O
LCD common output pins
LCD power supply
VL1
I
Apply the following voltage: 1 V ≤ VL1 ≤ VCC and VL1 ≤ VL2.
VL2
I
Apply the following voltage: VL2 ≤ 5.5 V and VL1 ≤ VL2 ≤ VL3.
VL3
I
Apply the following voltage: VL3 ≤ 5.5 V and VL2 ≤ VL3.
IVREF1, IVREF3
Data I/O pin
CMOS I/O ports. Each port has an I/O select direction register,
allowing each pin in the port to be directed for input or output
individually.
Any port set to input can be set to use a pull-up resistor or not
by a program.
Ports P7_0, P7_1 and P8 can be used as LED drive ports.
I: Input
O: Output
I/O: Input and output
Note:
1. Contact the oscillator manufacturer for oscillation characteristics.
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R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
2.
2. Central Processing Unit (CPU)
Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register banks.
b31
b15
R2
R3
b8b7
b0
R0H (high-order of R0) R0L (low-order of R0)
R1H (high-order of R1) R1L (low-order of R1)
Data registers (1)
R2
R3
A0
A1
FB
b19
b15
Address registers (1)
Frame base register (1)
b0
Interrupt table register
INTBL
INTBH
The 4 high-order bits of INTB are INTBH and
the 16 low-order bits of INTB are INTBL.
b19
b0
Program counter
PC
b15
b0
USP
User stack pointer
ISP
Interrupt stack pointer
SB
Static base register
b15
b0
FLG
b15
b8
IPL
b7
Flag register
b0
U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
Note:
1. These registers configure a register bank.
There are two sets of register banks.
Figure 2.1
CPU Registers
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Page 29 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
2.1
2. Central Processing Unit (CPU)
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is
analogous to R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the starting address of an interrupt vector table.
2.5
Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
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R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
2.8.7
2. Central Processing Unit (CPU)
Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10
Reserved Bit
If necessary, set to 0. When read, the content is undefined.
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R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
3.
3. Memory
Memory
Figure 3.1 is a Memory Map of each group. Each group has a 1-Mbyte address space from addresses 00000h to
FFFFFh. For example, a 48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt
routine is stored here.
The internal ROM (data flash) is allocated addresses 03000h to 037FFh.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 3.5-Kbyte internal
RAM area is allocated addresses 00400h to 011FFh. The internal RAM is used not only for data storage but also as a
stack area when a subroutine is called or when an interrupt request is acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh. Peripheral
function control registers are allocated here. All unallocated spaces within the SFRs are reserved and cannot be
accessed by users.
00000h
SFR
(Refer to 4. Special
Function Registers
(SFRs))
002FFh
00400h
Internal RAM
0FFD8h
0XXXXh
02C00h
02FFFh
03000h
Reserved area
SFR
(Refer to 4. Special
Function Registers
(SFRs))
0FFDCh
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Internal ROM
(data flash) (1)
037FFh
0YYYYh
Watchdog timer, oscillation stop detection, voltage monitor
Internal ROM
(program ROM)
Address break
(Reserved)
Reset
0FFFFh
0FFFFh
Internal ROM
(program ROM)
ZZZZZh
Notes:
1. Data flash indicates block A (1 Kbyte) and block B (1 Kbyte).
2. Blank spaces are reserved. No access is allowed.
FFFFFh
Internal ROM
Part Number
Internal RAM
Capacity
Address
0YYYYh
Address
ZZZZZh
Capacity
Address
0XXXXh
8 Kbytes
0E000h
0FFFFh
2 Kbytes
00BFFh
16 Kbytes
0C000h
0FFFFh
2 Kbytes
00BFFh
R5F2LA36ANFP, R5F2LA36ADFP,
R5F2LA56ANFP, R5F2LA56ADFP,
R5F2LA66ANFP, R5F2LA66ANFA, R5F2LA66ADFP, R5F2LA66ADFA,
R5F2LA86ANFP, R5F2LA86ANFA, R5F2LA86ADFP, R5F2LA86ADFA
32 Kbytes
08000h
0FFFFh
2 Kbytes
00BFFh
R5F2LA67ANFP, R5F2LA67ANFA, R5F2LA67ADFP, R5F2LA67ADFA,
R5F2LA87ANFP, R5F2LA87ANFA, R5F2LA87ADFP, R5F2LA87ADFA
48 Kbytes
04000h
0FFFFh
3.5 Kbytes
011FFh
R5F2LA38ANFP, R5F2LA38ADFP,
R5F2LA58ANFP, R5F2LA58ADFP,
R5F2LA68ANFP, R5F2LA68ANFA, R5F2LA68ADFP, R5F2LA68ADFA,
R5F2LA88ANFP, R5F2LA88ANFA, R5F2LA88ADFP, R5F2LA88ADFA
64 Kbytes
04000h
13FFFh
3.5 Kbytes
011FFh
R5F2LA32ANFP, R5F2LA32ADFP,
R5F2LA52ANFP, R5F2LA52ADFP
R5F2LA34ANFP, R5F2LA34ADFP,
R5F2LA54ANFP, R5F2LA54ADFP,
R5F2LA64ANFP, R5F2LA64ANFA, R5F2LA64ADFP, R5F2LA64ADFA,
Data
Flash
R5F2LA84ANFP, R5F2LA84ANFA, R5F2LA84ADFP, R5F2LA84ADFA
Figure 3.1
Available
Memory Map
R01DS0011EJ0100 Rev.1.00
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Page 32 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group 4. Special Function Registers (SFRs)
4.
Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.9 list SFR information
for R8C/LA5A Group, Tables 4.10 to 4.18 list SFR information for R8C/LA8A Group, and Table 4.19 lists the ID Code
Areas and Option Function Select Area. The description offered in this chapter is based on the R8C/LA8A Group.
Table 4.1
Address
0000h
0001h
0002h
0003h
0004h
0005h
SFR Information for R8C/LA5A Group (1) (1)
Register
Symbol
After Reset
Processor Mode Register 0
Processor Mode Register 1
PM0
PM1
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
System Clock Control Register 0
System Clock Control Register 1
Module Standby Control Register 0
System Clock Control Register 3
Protect Register
Reset Source Determination Register
Oscillation Stop Detection Register
CM0
CM1
MSTCR0
CM3
PRCR
RSTFR
OCD
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
Watchdog Timer Reset Register
Watchdog Timer Start Register
Watchdog Timer Control Register
Module Standby Control Register 1
WDTR
WDTS
WDTC
MSTCR1
Count Source Protection Mode Register
CSPR
00h
10000000b (5)
Power-Off Mode Control Register 0
POMCR0
XXXXXX00b
High-Speed On-Chip Oscillator Control Register 0
High-Speed On-Chip Oscillator Frequency Control Register 0
High-Speed On-Chip Oscillator Control Register 2
On-Chip Reference Voltage Control Register
FRA0
FRC0
FRA2
OCVREFCR
00h
When shipping
00h
00h
High-Speed On-Chip Oscillator 18 MHz Set Value Register 0
High-Speed On-Chip Oscillator 18 MHz Set Value Register 1
FR18S0
FR18S1
XXh
XXh
High-Speed On-Chip Oscillator Frequency Control Register 1
Voltage Monitor Circuit Control Register
Voltage Monitor Circuit Edge Select Register
FRC1
CMPA
VCAC
When shipping
00h
00h
Voltage Detect Register 1
Voltage Detect Register 2
VCA1
VCA2
00001000b
00h (6)
00100000b (7)
Voltage Detection 1 Level Select Register
VD1LS
00000111b
Voltage Monitor 0 Circuit Control Register
VW0C
1100X010b (6)
1100X011b (7)
10001010b
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
00h
00h
00000100b (2)
00100000b
00100000b
00h
00h
00h
XXh (3)
00000100b (4)
00h (4)
XXh
XXh
00111111b
00h
0039h
Voltage Monitor 1 Circuit Control Register
VW1C
X: Undefined
Notes:
1. Blank spaces are reserved. No access is allowed.
2. The CSPRO bit in the CSPR register is set to 1.
3. The CWR bit in the RSTFR register is set to 0 after power-on, voltage monitor 0 reset, or exit from power-off 0 mode. Hardware reset, software reset,
or watchdog timer reset does not affect this bit.
4. The reset value differs depending on the mode.
5. The CSPROINI bit in the OFS register is set to 0.
6. The LVDAS bit in the OFS register is set to 1.
7. The LVDAS bit in the OFS register is set to 0.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 33 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group 4. Special Function Registers (SFRs)
Table 4.2
Address
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
SFR Information for R8C/LA5A Group (2) (1)
Register
Voltage Monitor 2 Circuit Control Register
Symbol
VW2C
After Reset
10000010b
Flash Memory Ready Interrupt Control Register
FMRDYIC
XXXXX000b
INT7 Interrupt Control Register
INT7IC
XX00X000b
INT5 Interrupt Control Register
INT5IC
XX00X000b
Timer RC Interrupt Control Register
TRCIC
XXXXX000b
Timer RH Interrupt Control Register
TRHIC
XXXXX000b
Key Input Interrupt Control Register
A/D Conversion Interrupt Control Register
SSU Interrupt Control Register / IIC bus Interrupt Control Register (2)
KUPIC
ADIC
SSUIC/IICIC
XXXXX000b
XXXXX000b
XXXXX000b
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
S0TIC
S0RIC
XXXXX000b
XXXXX000b
INT2 Interrupt Control Register
Timer RJ0 Interrupt Control Register
Timer RB1 Interrupt Control Register
Timer RB0 Interrupt Control Register
INT1 Interrupt Control Register
INT3 Interrupt Control Register
Timer RJ1 Interrupt Control Register
INT2IC
TRJ0IC
TRB1IC
TRB0IC
INT1IC
INT3IC
TRJ1IC
XX00X000b
XXXXX000b
XXXXX000b
XXXXX000b
XX00X000b
XX00X000b
XXXXX000b
INT0 Interrupt Control Register
INT0IC
XX00X000b
LCD Interrupt Control Register
LCDIC
XXXXX000b
Voltage monitor 1 Interrupt Control Register
Voltage monitor 2 Interrupt Control Register
VCMP1IC
VCMP2IC
XXXXX000b
XXXXX000b
X: Undefined
Notes:
1. Blank spaces are reserved. No access is allowed.
2. Selectable by the IICSEL bit in the SSUIICSR register.
R01DS0011EJ0100 Rev.1.00
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Page 34 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group 4. Special Function Registers (SFRs)
Table 4.3
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
SFR Information for R8C/LA5A Group (3) (1)
Register
Timer RJ0 Control Register
Timer RJ0 I/O Control Register
Timer RJ0 Mode Register
Timer RJ0 Event Pin Select Register
Timer RJ0 Register
Symbol
TRJ0CR
TRJ0IOC
TRJ0MR
TRJ0ISR
TRJ0
After Reset
Timer RJ1 Control Register
Timer RJ1 I/O Control Register
Timer RJ1 Mode Register
Timer RJ1 Event Pin Select Register
Timer RJ1 Register
TRJ1CR
TRJ1IOC
TRJ1MR
TRJ1ISR
TRJ1
00h
00h
00h
00h
FFh
FFh
Timer RB1 Control Register
Timer RB1 One-Shot Control Register
Timer RB1 I/O Control Register
Timer RB1 Mode Register
Timer RB1 Prescaler Register
Timer RB1 Secondary Register
Timer RB1 Primary Register
TRB1CR
TRB1OCR
TRB1IOC
TRB1MR
TRB1PRE
TRB1SC
TRB1PR
00h
00h
00h
00h
FFh
FFh
FFh
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
UART0 Transmit Buffer Register
U0MR
U0BRG
U0TB
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
UART0 Receive Buffer Register
U0C0
U0C1
U0RB
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
00h
00h
00h
FFh
FFh
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 35 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group 4. Special Function Registers (SFRs)
Table 4.4
Address
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
00E1h
00E2h
00E3h
00E4h
00E5h
00E6h
00E7h
00E8h
00E9h
00EAh
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
SFR Information for R8C/LA5A Group (4) (1)
Register
Symbol
After Reset
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
A/D Register 0
AD0
A/D Register 1
AD1
A/D Register 2
AD2
A/D Register 3
AD3
A/D Register 4
AD4
A/D Register 5
AD5
A/D Register 6
AD6
A/D Register 7
AD7
A/D Mode Register
A/D Input Select Register
A/D Control Register 0
A/D Control Register 1
ADMOD
ADINSEL
ADCON0
ADCON1
00h
11000000b
00h
00h
A/D Control Register 2
ADCON2
00h
Port P0 Register
P0
XXh
Port P0 Direction Register
PD0
00h
Port P2 Register
Port P3 Register
Port P2 Direction Register
Port P3 Direction Register
P2
P3
PD2
PD3
XXh
XXh
00h
00h
Port P5 Register
P5
XXh
Port P5 Direction Register
PD5
00h
Port P7 Register
P7
XXh
Port P7 Direction Register
Port P8 Register
Port P9 Register
Port P8 Direction Register
Port P9 Direction Register
PD7
P8
P9
PD8
PD9
00h
XXh
XXh
00h
00h
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 36 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group 4. Special Function Registers (SFRs)
Table 4.5
Address
0100h
0101h
0102h
0103h
0104h
0105h
0106h
0107h
0108h
0109h
010Ah
010Bh
010Ch
010Dh
010Eh
010Fh
0110h
SFR Information for R8C/LA5A Group (5) (1)
Register
Symbol
After Reset
Timer RB0 Control Register
Timer RB0 One-Shot Control Register
Timer RB0 I/O Control Register
Timer RB0 Mode Register
Timer RB0 Prescaler Register
Timer RB0 Secondary Register
Timer RB0 Primary Register
TRB0CR
TRB0OCR
TRB0IOC
TRB0MR
TRB0PRE
TRB0SC
TRB0PR
00h
00h
00h
00h
FFh
FFh
FFh
Timer RH Second Data Register / Counter Data Register
TRHSEC
0111h
Timer RH Minute Data Register / Compare Data Register
TRHMIN
0112h
Timer RH Hour Data Register
TRHHR
0113h
Timer RH Day-of-the-Week Data Register
TRHWK
0114h
Timer RH Date Data Register
TRHDY
0115h
Timer RH Month Data Register
TRHMON
0116h
Timer RH Year Data Register
TRHYR
0117h
Timer RH Control Register
TRHCR
0118h
Timer RH Count Source Select Register
TRHCSR
0119h
Timer RH Clock Error Correction Register
TRHADJ
011Ah
Timer RH Interrupt Flag Register
TRHIFR
XXh
00h (2)
XXh
00h (2)
00XXXXXXb
00h (2)
00000XXXb
00h (2)
00XXXXXXb
00000001b (2)
000XXXXXb
00000001b (2)
XXh
00h (2)
XXX00X0Xb
000XX1X0b (2)
X0001000b
0XXXXXXXb (2)
XXh
00h (2)
00000XXXb
000XX000b (2)
XXh
00h (2)
XXh
00h (2)
XXh
00h (2)
X0000XXXb
00h (2)
00h
X0000000b (2)
01001000b
00h
01110000b
01110000b
10001000b
10001000b
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00011000b
00h
01111111b
00h
011Bh
Timer RH Interrupt Enable Register
TRHIER
011Ch
Timer RH Alarm Minute Register
TRHAMN
011Dh
Timer RH Alarm Hour Register
TRHAHR
011Eh
Timer RH Alarm Day-of-the-Week Register
TRHAWK
011Fh
Timer RH Protect Register
TRHPRC
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
Timer RC Mode Register
Timer RC Control Register 1
Timer RC Interrupt Enable Register
Timer RC Status Register
Timer RC I/O Control Register 0
Timer RC I/O Control Register 1
Timer RC Counter
TRCMR
TRCCR1
TRCIER
TRCSR
TRCIOR0
TRCIOR1
TRC
Timer RC General Register A
TRCGRA
Timer RC General Register B
TRCGRB
Timer RC General Register C
TRCGRC
Timer RC General Register D
TRCGRD
Timer RC Control Register 2
Timer RC Digital Filter Function Select Register
Timer RC Output Master Enable Register
Timer RC Trigger Control Register
TRCCR2
TRCDF
TRCOER
TRCADCR
X: Undefined
Notes:
1. Blank spaces are reserved. No access is allowed.
2. This is the reset value after reset by RTCRST bit in TRHCR register.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 37 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group 4. Special Function Registers (SFRs)
Table 4.6
SFR Information for R8C/LA5A Group (6) (1)
Address
0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
Register
Symbol
After Reset
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 38 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group 4. Special Function Registers (SFRs)
Table 4.7
Address
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
SFR Information for R8C/LA5A Group (7) (1)
Timer RJ Pin Select Register
Register
Symbol
TRJSR
00h
After Reset
Timer RC Pin Select Register 0
Timer RC Pin Select Register 1
TRCPSR0
TRCPSR1
00h
00h
UART0 Pin Select Register
U0SR
00h
SSU/IIC Pin Select Register
Timer RH Second Interrupt Control Register
SSUIICSR
TRHICR
INT Interrupt Input Pin Select Register
I/O Function Pin Select Register
INTSR
PINSR
00h
X0XXXXXXb
00000001b (3)
00h
00h
SS Bit Counter Register
SS Transmit Data Register L / IIC bus Transmit Data Register (2)
SS Transmit Data Register H (2)
SS Receive Data Register L / IIC bus Receive Data Register (2)
SS Receive Data Register H (2)
SS Control Register H / IIC bus Control Register 1 (2)
SS Control Register L / IIC bus Control Register 2 (2)
SS Mode Register / IIC bus Mode Register (2)
SS Enable Register / IIC bus Interrupt Enable Register (2)
SS Status Register / IIC bus Status Register (2)
SS Mode Register 2 / Slave Address Register (2)
SSBR
SSTDR/ICDRT
SSTDRH
SSRDR/ICDRR
SSRDRH
SSCRH/ICCR1
SSCRL/ICCR2
SSMR/ICMR
SSER/ICIER
SSSR/ICSR
SSMR2/SAR
11111000b
FFh
FFh
FFh
FFh
00h
01111101b
00010000b/00011000b
00h
00h/0000X000b
00h
Flash Memory Status Register
FST
10000X00b
Flash Memory Control Register 0
Flash Memory Control Register 1
Flash Memory Control Register 2
FMR0
FMR1
FMR2
00h
000000X0b
00h
X: Undefined
Notes:
1. Blank spaces are reserved. No access is allowed.
2. Selectable by the IICSEL bit in the SSUIICSR register.
3. This is the reset value after reset by RTCRST bit in TRHCR register.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 39 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group 4. Special Function Registers (SFRs)
Table 4.8
Address
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
01C6h
01C7h
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
SFR Information for R8C/LA5A Group (8) (1)
Address Match Interrupt Register 0
Register
Symbol
RMAD0
Address Match Interrupt Enable Register 0
Address Match Interrupt Register 1
AIER0
RMAD1
Address Match Interrupt Enable Register 1
AIER1
After Reset
XXh
XXh
0000XXXXb
00h
XXh
XXh
0000XXXXb
00h
Port P0 Pull-Up Control Register
P0PUR
00h
Port P2 Pull-Up Control Register
Port P3 Pull-Up Control Register
P2PUR
P3PUR
00h
00h
Port P5 Pull-Up Control Register
P5PUR
00h
Port P7 Pull-Up Control Register
Port P8 Pull-Up Control Register
Port P9 Pull-Up Control Register
P7PUR
P8PUR
P9PUR
00h
00h
00h
Port P8 Drive Capacity Control Register
P8DRR
00h
Input Threshold Control Register 0
Input Threshold Control Register 1
Input Threshold Control Register 2
Comparator B Control Register 0
VLT0
VLT1
VLT2
INTCMP
00h
00h
00h
00h
External Input Enable Register 0
External Input Enable Register 1
INT Input Filter Select Register 0
INT Input Filter Select Register 1
Key Input Enable Register 0
Key Input Enable Register 1
INTEN
INTEN1
INTF
INTF1
KIEN
KIEN1
00h
00h
00h
00h
00h
00h
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 40 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group 4. Special Function Registers (SFRs)
Table 4.9
Address
0200h
0201h
0202h
0203h
0204h
0205h
0206h
0207h
0208h
0209h
020Ah
020Bh
020Ch
020Dh
020Eh
020Fh
0210h
0211h
0212h
0213h
0214h
0215h
0216h
0217h
0218h
0219h
021Ah
021Bh
021Ch
021Dh
021Eh
021Fh
0220h
0221h
0222h
0223h
0224h
0225h
0226h
0227h
0228h
0229h
022Ah
022Bh
022Ch
022Dh
022Eh
022Fh
0230h
0231h
0232h
0233h
0234h
0235h
0236h
0237h
:
2FFFh
SFR Information for R8C/LA5A Group (9) (1)
Register
Symbol
After Reset
LCD Control Register
LCR0
00h
LCD Option Clock Control Register
LCD Clock Control Register
LCD Display Control Register
LCR2
LCR3
LCR4
00h
00h
00h
LCD Port Select Register 0
LCD Port Select Register 1
LCD Port Select Register 2
LSE0
LSE1
LSE2
00h
00h
00h
LCD Port Select Register 5
LSE5
00h
LCD Display Data Register
LRA0L
LRA1L
LRA2L
LRA3L
LRA4L
LRA5L
LRA6L
LRA7L
LRA8L
LRA9L
LRA10L
LRA11L
LRA12L
LRA13L
LRA14L
LRA15L
LRA16L
LRA17L
LRA18L
LRA19L
LRA20L
LRA21L
LRA22L
LRA23L
LRA24L
LRA25L
LRA26L
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 41 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group 4. Special Function Registers (SFRs)
Table 4.10
Address
0000h
0001h
0002h
0003h
0004h
0005h
SFR Information for R8C/LA8A Group (1) (1)
Register
Symbol
After Reset
Processor Mode Register 0
Processor Mode Register 1
PM0
PM1
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
System Clock Control Register 0
System Clock Control Register 1
Module Standby Control Register 0
System Clock Control Register 3
Protect Register
Reset Source Determination Register
Oscillation Stop Detection Register
CM0
CM1
MSTCR0
CM3
PRCR
RSTFR
OCD
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
Watchdog Timer Reset Register
Watchdog Timer Start Register
Watchdog Timer Control Register
Module Standby Control Register 1
WDTR
WDTS
WDTC
MSTCR1
Count Source Protection Mode Register
CSPR
00h
10000000b (5)
Power-Off Mode Control Register 0
POMCR0
XXXXXX00b
High-Speed On-Chip Oscillator Control Register 0
High-Speed On-Chip Oscillator Frequency Control Register 0
High-Speed On-Chip Oscillator Control Register 2
On-Chip Reference Voltage Control Register
FRA0
FRC0
FRA2
OCVREFCR
00h
When shipping
00h
00h
High-Speed On-Chip Oscillator 18 MHz Set Value Register 0
High-Speed On-Chip Oscillator 18 MHz Set Value Register 1
FR18S0
FR18S1
XXh
XXh
High-Speed On-Chip Oscillator Frequency Control Register 1
Voltage Monitor Circuit Control Register
Voltage Monitor Circuit Edge Select Register
FRC1
CMPA
VCAC
When shipping
00h
00h
Voltage Detect Register 1
Voltage Detect Register 2
VCA1
VCA2
00001000b
00h (6)
00100000b (7)
Voltage Detection 1 Level Select Register
VD1LS
00000111b
Voltage Monitor 0 Circuit Control Register
VW0C
Voltage Monitor 1 Circuit Control Register
VW1C
1100X010b (6)
1100X011b (7)
10001010b
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
00h
00h
00000100b (2)
00100000b
00100000b
00h
00h
00h
XXh (3)
00000100b (4)
00h (4)
XXh
XXh
00111111b
00h
X: Undefined
Notes:
1. Blank spaces are reserved. No access is allowed.
2. The CSPRO bit in the CSPR register is set to 1.
3. The CWR bit in the RSTFR register is set to 0 after power-on, voltage monitor 0 reset, or exit from power-off 0 mode. Hardware reset, software reset,
or watchdog timer reset does not affect this bit.
4. The reset value differs depending on the mode.
5. The CSPROINI bit in the OFS register is set to 0.
6. The LVDAS bit in the OFS register is set to 1.
7. The LVDAS bit in the OFS register is set to 0.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 42 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group 4. Special Function Registers (SFRs)
Table 4.11
Address
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
SFR Information for R8C/LA8A Group (2) (1)
Register
Voltage Monitor 2 Circuit Control Register
Symbol
VW2C
After Reset
10000010b
Flash Memory Ready Interrupt Control Register
FMRDYIC
XXXXX000b
INT7 Interrupt Control Register
INT6 Interrupt Control Register
INT5 Interrupt Control Register
INT4 Interrupt Control Register
Timer RC Interrupt Control Register
INT7IC
INT6IC
INT5IC
INT4IC
TRCIC
XX00X000b
XX00X000b
XX00X000b
XX00X000b
XXXXX000b
Timer RH Interrupt Control Register
UART2 Transmit Interrupt Control Register
UART2 Receive Interrupt Control Register
Key Input Interrupt Control Register
A/D Conversion Interrupt Control Register
SSU Interrupt Control Register / IIC bus Interrupt Control Register (2)
TRHIC
S2TIC
S2RIC
KUPIC
ADIC
SSUIC/IICIC
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
S0TIC
S0RIC
XXXXX000b
XXXXX000b
INT2 Interrupt Control Register
Timer RJ0 Interrupt Control Register
Timer RB1 Interrupt Control Register
Timer RB0 Interrupt Control Register
INT1 Interrupt Control Register
INT3 Interrupt Control Register
Timer RJ1 Interrupt Control Register
Timer RJ2 Interrupt Control Register
INT0 Interrupt Control Register
UART2 Bus Collision Detection Interrupt Control Register
INT2IC
TRJ0IC
TRB1IC
TRB0IC
INT1IC
INT3IC
TRJ1IC
TRJ2IC
INT0IC
U2BCNIC
XX00X000b
XXXXX000b
XXXXX000b
XXXXX000b
XX00X000b
XX00X000b
XXXXX000b
XXXXX000b
XX00X000b
XXXXX000b
LCD Interrupt Control Register
LCDIC
XXXXX000b
Voltage monitor 1 Interrupt Control Register
Voltage monitor 2 Interrupt Control Register
VCMP1IC
VCMP2IC
XXXXX000b
XXXXX000b
X: Undefined
Notes:
1. Blank spaces are reserved. No access is allowed.
2. Selectable by the IICSEL bit in the SSUIICSR register.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 43 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group 4. Special Function Registers (SFRs)
Table 4.12
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
SFR Information for R8C/LA8A Group (3) (1)
Register
Timer RJ0 Control Register
Timer RJ0 I/O Control Register
Timer RJ0 Mode Register
Timer RJ0 Event Pin Select Register
Timer RJ0 Register
Symbol
TRJ0CR
TRJ0IOC
TRJ0MR
TRJ0ISR
TRJ0
After Reset
Timer RJ1 Control Register
Timer RJ1 I/O Control Register
Timer RJ1 Mode Register
Timer RJ1 Event Pin Select Register
Timer RJ1 Register
TRJ1CR
TRJ1IOC
TRJ1MR
TRJ1ISR
TRJ1
00h
00h
00h
00h
FFh
FFh
Timer RJ2 Control Register
Timer RJ2 I/O Control Register
Timer RJ2 Mode Register
Timer RJ2 Event Pin Select Register
Timer RJ2 Register
TRJ2CR
TRJ2IOC
TRJ2MR
TRJ2ISR
TRJ2
00h
00h
00h
00h
FFh
FFh
Timer RB1 Control Register
Timer RB1 One-Shot Control Register
Timer RB1 I/O Control Register
Timer RB1 Mode Register
Timer RB1 Prescaler Register
Timer RB1 Secondary Register
Timer RB1 Primary Register
TRB1CR
TRB1OCR
TRB1IOC
TRB1MR
TRB1PRE
TRB1SC
TRB1PR
00h
00h
00h
00h
FFh
FFh
FFh
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
UART0 Transmit Buffer Register
U0MR
U0BRG
U0TB
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
UART0 Receive Buffer Register
U0C0
U0C1
U0RB
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Register
UART2 Transmit Buffer Register
U2MR
U2BRG
U2TB
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
UART2 Receive Buffer Register
U2C0
U2C1
U2RB
UART2 Digital Filter Function Select Register
URXDF
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
UART2 Special Mode Register 5
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
U2SMR5
U2SMR4
U2SMR3
U2SMR2
U2SMR
00h
00h
000X0X0Xb
X0000000b
X0000000b
00h
00h
00h
00h
FFh
FFh
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 44 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group 4. Special Function Registers (SFRs)
Table 4.13
Address
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
00E1h
00E2h
00E3h
00E4h
00E5h
00E6h
00E7h
00E8h
00E9h
00EAh
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
SFR Information for R8C/LA8A Group (4) (1)
Register
Symbol
After Reset
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
A/D Register 0
AD0
A/D Register 1
AD1
A/D Register 2
AD2
A/D Register 3
AD3
A/D Register 4
AD4
A/D Register 5
AD5
A/D Register 6
AD6
A/D Register 7
AD7
A/D Mode Register
A/D Input Select Register
A/D Control Register 0
A/D Control Register 1
ADMOD
ADINSEL
ADCON0
ADCON1
00h
11000000b
00h
00h
A/D Control Register 2
ADCON2
00h
Port P0 Register
Port P1 Register
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
Port P3 Register
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
Port P5 Register
Port P4 Direction Register
Port P5 Direction Register
Port P6 Register
Port P7 Register
Port P6 Direction Register
Port P7 Direction Register
Port P8 Register
Port P9 Register
Port P8 Direction Register
Port P9 Direction Register
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
P6
P7
PD6
PD7
P8
P9
PD8
PD9
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 45 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group 4. Special Function Registers (SFRs)
Table 4.14
Address
0100h
0101h
0102h
0103h
0104h
0105h
0106h
0107h
0108h
0109h
010Ah
010Bh
010Ch
010Dh
010Eh
010Fh
0110h
SFR Information for R8C/LA8A Group (5) (1)
Register
Symbol
After Reset
Timer RB0 Control Register
Timer RB0 One-Shot Control Register
Timer RB0 I/O Control Register
Timer RB0 Mode Register
Timer RB0 Prescaler Register
Timer RB0 Secondary Register
Timer RB0 Primary Register
TRB0CR
TRB0OCR
TRB0IOC
TRB0MR
TRB0PRE
TRB0SC
TRB0PR
00h
00h
00h
00h
FFh
FFh
FFh
Timer RH Second Data Register / Counter Data Register
TRHSEC
0111h
Timer RH Minute Data Register / Compare Data Register
TRHMIN
0112h
Timer RH Hour Data Register
TRHHR
0113h
Timer RH Day-of-the-Week Data Register
TRHWK
0114h
Timer RH Date Data Register
TRHDY
0115h
Timer RH Month Data Register
TRHMON
0116h
Timer RH Year Data Register
TRHYR
0117h
Timer RH Control Register
TRHCR
0118h
Timer RH Count Source Select Register
TRHCSR
0119h
Timer RH Clock Error Correction Register
TRHADJ
011Ah
Timer RH Interrupt Flag Register
TRHIFR
XXh
00h (2)
XXh
00h (2)
00XXXXXXb
00h (2)
00000XXXb
00h (2)
00XXXXXXb
00000001b (2)
000XXXXXb
00000001b (2)
XXh
00h (2)
XXX00X0Xb
000XX1X0b (2)
X0001000b
0XXXXXXXb (2)
XXh
00h (2)
00000XXXb
000XX000b (2)
XXh
00h (2)
XXh
00h (2)
XXh
00h (2)
X0000XXXb
00h (2)
00h
X0000000b (2)
01001000b
00h
01110000b
01110000b
10001000b
10001000b
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00011000b
00h
01111111b
00h
011Bh
Timer RH Interrupt Enable Register
TRHIER
011Ch
Timer RH Alarm Minute Register
TRHAMN
011Dh
Timer RH Alarm Hour Register
TRHAHR
011Eh
Timer RH Alarm Day-of-the-Week Register
TRHAWK
011Fh
Timer RH Protect Register
TRHPRC
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
Timer RC Mode Register
Timer RC Control Register 1
Timer RC Interrupt Enable Register
Timer RC Status Register
Timer RC I/O Control Register 0
Timer RC I/O Control Register 1
Timer RC Counter
TRCMR
TRCCR1
TRCIER
TRCSR
TRCIOR0
TRCIOR1
TRC
Timer RC General Register A
TRCGRA
Timer RC General Register B
TRCGRB
Timer RC General Register C
TRCGRC
Timer RC General Register D
TRCGRD
Timer RC Control Register 2
Timer RC Digital Filter Function Select Register
Timer RC Output Master Enable Register
Timer RC Trigger Control Register
TRCCR2
TRCDF
TRCOER
TRCADCR
X: Undefined
Notes:
1. Blank spaces are reserved. No access is allowed.
2. This is the reset value after reset by RTCRST bit in TRHCR register.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 46 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group 4. Special Function Registers (SFRs)
Table 4.15
SFR Information for R8C/LA8A Group (6) (1)
Address
0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
Register
Symbol
After Reset
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 47 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group 4. Special Function Registers (SFRs)
Table 4.16
Address
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
SFR Information for R8C/LA8A Group (7) (1)
Timer RJ Pin Select Register
Timer RB Pin Select Register
Timer RC Pin Select Register 0
Timer RC Pin Select Register 1
Register
Symbol
TRJSR
TRBSR
TRCPSR0
TRCPSR1
00h
00h
00h
00h
After Reset
UART0 Pin Select Register
U0SR
00h
UART2 Pin Select Register 0
UART2 Pin Select Register 1
SSU/IIC Pin Select Register
Timer RH Second Interrupt Control Register
U2SR0
U2SR1
SSUIICSR
TRHICR
INT Interrupt Input Pin Select Register
I/O Function Pin Select Register
INTSR
PINSR
00h
00h
00h
X0XXXXXXb
00000001b (3)
00h
00h
SS Bit Counter Register
SS Transmit Data Register L / IIC bus Transmit Data Register (2)
SS Transmit Data Register H (2)
SS Receive Data Register L / IIC bus Receive Data Register (2)
SS Receive Data Register H (2)
SS Control Register H / IIC bus Control Register 1 (2)
SS Control Register L / IIC bus Control Register 2 (2)
SS Mode Register / IIC bus Mode Register (2)
SS Enable Register / IIC bus Interrupt Enable Register (2)
SS Status Register / IIC bus Status Register (2)
SS Mode Register 2 / Slave Address Register (2)
SSBR
SSTDR/ICDRT
SSTDRH
SSRDR/ICDRR
SSRDRH
SSCRH/ICCR1
SSCRL/ICCR2
SSMR/ICMR
SSER/ICIER
SSSR/ICSR
SSMR2/SAR
11111000b
FFh
FFh
FFh
FFh
00h
01111101b
00010000b/00011000b
00h
00h/0000X000b
00h
Flash Memory Status Register
FST
10000X00b
Flash Memory Control Register 0
Flash Memory Control Register 1
Flash Memory Control Register 2
FMR0
FMR1
FMR2
00h
000000X0b
00h
X: Undefined
Notes:
1. Blank spaces are reserved. No access is allowed.
2. Selectable by the IICSEL bit in the SSUIICSR register.
3. This is the reset value after reset by RTCRST bit in TRHCR register.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 48 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group 4. Special Function Registers (SFRs)
Table 4.17
Address
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
01C6h
01C7h
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
SFR Information for R8C/LA8A Group (8) (1)
Address Match Interrupt Register 0
Register
Symbol
RMAD0
Address Match Interrupt Enable Register 0
Address Match Interrupt Register 1
AIER0
RMAD1
Address Match Interrupt Enable Register 1
AIER1
After Reset
XXh
XXh
0000XXXXb
00h
XXh
XXh
0000XXXXb
00h
Port P0 Pull-Up Control Register
Port P1 Pull-Up Control Register
Port P2 Pull-Up Control Register
Port P3 Pull-Up Control Register
Port P4 Pull-Up Control Register
Port P5 Pull-Up Control Register
Port P6 Pull-Up Control Register
Port P7 Pull-Up Control Register
Port P8 Pull-Up Control Register
Port P9 Pull-Up Control Register
P0PUR
P1PUR
P2PUR
P3PUR
P4PUR
P5PUR
P6PUR
P7PUR
P8PUR
P9PUR
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
Port P7 Drive Capacity Control Register
Port P8 Drive Capacity Control Register
P7DRR
P8DRR
00h
00h
Input Threshold Control Register 0
Input Threshold Control Register 1
Input Threshold Control Register 2
Comparator B Control Register 0
VLT0
VLT1
VLT2
INTCMP
00h
00h
00h
00h
External Input Enable Register 0
External Input Enable Register 1
INT Input Filter Select Register 0
INT Input Filter Select Register 1
Key Input Enable Register 0
Key Input Enable Register 1
INTEN
INTEN1
INTF
INTF1
KIEN
KIEN1
00h
00h
00h
00h
00h
00h
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 49 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group 4. Special Function Registers (SFRs)
Table 4.18
Address
0200h
0201h
0202h
0203h
0204h
0205h
0206h
0207h
0208h
0209h
020Ah
020Bh
020Ch
020Dh
020Eh
020Fh
0210h
0211h
0212h
0213h
0214h
0215h
0216h
0217h
0218h
0219h
021Ah
021Bh
021Ch
021Dh
021Eh
021Fh
0220h
0221h
0222h
0223h
0224h
0225h
0226h
0227h
0228h
0229h
022Ah
022Bh
022Ch
022Dh
022Eh
022Fh
0230h
0231h
0232h
0233h
0234h
0235h
0236h
0237h
:
2FFFh
SFR Information for R8C/LA8A Group (9) (1)
Register
Symbol
After Reset
LCD Control Register
LCR0
00h
LCD Option Clock Control Register
LCD Clock Control Register
LCD Display Control Register
LCR2
LCR3
LCR4
00h
00h
00h
LCD Port Select Register 0
LCD Port Select Register 1
LCD Port Select Register 2
LCD Port Select Register 3
LCD Port Select Register 4
LCD Port Select Register 5
LSE0
LSE1
LSE2
LSE3
LSE4
LSE5
00h
00h
00h
00h
00h
00h
LCD Display Data Register
LRA0L
LRA1L
LRA2L
LRA3L
LRA4L
LRA5L
LRA6L
LRA7L
LRA8L
LRA9L
LRA10L
LRA11L
LRA12L
LRA13L
LRA14L
LRA15L
LRA16L
LRA17L
LRA18L
LRA19L
LRA20L
LRA21L
LRA22L
LRA23L
LRA24L
LRA25L
LRA26L
LRA27L
LRA28L
LRA29L
LRA30L
LRA31L
LRA32L
LRA33L
LRA34L
LRA35L
LRA36L
LRA37L
LRA38L
LRA39L
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
X: Undefined
Note:
1. Blank spaces are reserved. No access is allowed.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 50 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group 4. Special Function Registers (SFRs)
Table 4.19
ID Code Areas and Option Function Select Area
Address
:
FFDBh
:
FFDFh
:
FFE3h
:
FFEBh
:
FFEFh
:
FFF3h
:
FFF7h
:
FFFBh
:
FFFFh
Area Name
Option Function Select Register 2
Symbol
OFS2
After Reset
(Note 1)
ID1
(Note 2)
ID2
(Note 2)
ID3
(Note 2)
ID4
(Note 2)
ID5
(Note 2)
ID6
(Note 2)
ID7
(Note 2)
Option Function Select Register
OFS
(Note 1)
Notes:
1. The option function select area is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program.
Do not write additions to the option function select area. If the block including the option function select area is erased, the option function select
area is set to FFh.
When blank products are shipped, the option function select area is set to FFh. It is set to the written value after written by the user.
When factory-programming products are shipped, the value of the option function select area is the value programmed by the user.
2. The ID code areas are allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program.
Do not write additions to the ID code areas. If the block including the ID code areas is erased, the ID code areas are set to FFh.
When blank products are shipped, the ID code areas are set to FFh. They are set to the written value after written by the user.
When factory-programming products are shipped, the value of the ID code areas is the value programmed by the user.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 51 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
5.
5. Electrical Characteristics
Electrical Characteristics
5.1
Electrical Characteristics (R8C/LA3A Group and R8C/LA5A Group)
5.1.1
Table 5.1
Absolute Maximum Ratings
Absolute Maximum Ratings
Symbol
Parameter
VCC/AVCC Supply voltage
VI
Input voltage
XIN
XIN
Condition
XIN-XOUT oscillation on
(oscillation buffer ON) (1)
XIN-XOUT oscillation on
(oscillation buffer OFF) (1)
P5_4/VL1
VO
P5_5/VL2
P5_6/VL3
Other pins
Output voltage XOUT
XOUT
Pd
Topr
COM0 to COM3
SEG0 to SEG26
Other pins
Power dissipation
Operating ambient temperature
Tstg
Storage temperature
XIN-XOUT oscillation on
(oscillation buffer ON) (1)
XIN-XOUT oscillation on
(oscillation buffer OFF) (1)
Rated Value
−0.3 to 6.5
−0.3 to 1.9
Unit
V
V
−0.3 to VCC + 0.3
V
−0.3 to VL2 (2)
V
VL1 to VL3
VL2 to 6.5
−0.3 to VCC + 0.3
−0.3 to 1.9
V
V
V
V
−0.3 to VCC + 0.3
V
−0.3 to VL3
V
V
V
mW
°C
−0.3 to VL3
−0.3 to VCC + 0.3
−40 °C ≤ Topr ≤ 85 °C
500
−20 to 85 (N version)/
−40 to 85 (D version)
−65 to 150
°C
Notes:
1. For the register settings for each operation, refer to 7. I/O Ports and 9. Clock Generation Circuit in the User’s Manual:
Hardware.
2. The VL1 voltage should be VCC or below.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 52 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
5.1.2
Recommended Operating Conditions
Table 5.2
Recommended Operating Conditions
(VCC = 1.8 to 5.5 V and Topr = −20 to 85 °C (N version)/ −40 to 85 °C (D version), unless
otherwise specified.)
Sum of all pins IOH(peak)
Min.
1.8
–
0.8 VCC
0.8 VCC
0.9 VCC
0.5 VCC
0.55 VCC
0.65 VCC
0.65 VCC
0.7 VCC
0.8 VCC
0.85 VCC
0.85 VCC
0.85 VCC
0
0
0
0
0
0
0
0
0
0
0
0
–
Standard
Typ.
–
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Max.
5.5
–
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
0.2 VCC
0.2 VCC
0.05 VCC
0.2 VCC
0.2 VCC
0.2 VCC
0.4 VCC
0.3 VCC
0.2 VCC
0.55 VCC
0.45 VCC
0.35 VCC
−160
Sum of all pins IOH(avg)
–
–
−80
mA
Port P8 (2)
Other pins
Average output Port P8 (2)
“H” current (1)
Other pins
Peak sum output Sum of all pins IOL(peak)
“L” current
Average sum
Sum of all pins IOL(avg)
output “L” current
Peak output “L” Port P8 (2)
current
Other pins
Average output Port P8 (2)
“L” current (1)
Other pins
XIN clock input oscillation frequency
–
–
–
–
–
–
–
–
–
–
−40
−10
−20
−5
160
mA
mA
mA
mA
mA
–
–
80
mA
–
–
–
–
2
2
–
–
18.432
0
0
–
–
–
–
–
–
32.768
–
–
-
40
10
20
5
20
8
–
50
20
20
8
20
8
20
8
mA
mA
mA
mA
MHz
MHz
kHz
kHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Symbol
Parameter
Conditions
VCC/AVCC Supply voltage
VSS/AVSS Supply voltage
Input “H” voltage Other than CMOS input
VIH
CMOS Input level
input
switching
function
(I/O port)
Input level selection
: 0.35 VCC
Input level selection
: 0.5 VCC
Input level selection
: 0.7 VCC
Input “L” voltage Other than CMOS input
VIL
CMOS Input level
input
switching
function
(I/O port)
Input level selection
: 0.35 VCC
Input level selection
: 0.5 VCC
Input level selection
: 0.7 VCC
IOH(sum)
IOH(sum)
IOH(peak)
IOH(avg)
IOL(sum)
IOL(sum)
IOL(peak)
IOL(avg)
f(XIN)
Peak sum output
“H” current
Average sum
output “H” current
Peak output “H”
current
XCIN oscillation frequency
XCIN external clock input frequency
fOCO20M When used as the count source for timer RC (3)
fOCO-F fOCO-F frequency
f(XCIN)
−
System clock frequency
f(BCLK)
CPU clock frequency
Notes:
1.
2.
3.
5. Electrical Characteristics
4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
1.8 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
The average output current indicates the average value of current measured during 100 ms.
This applies when the drive capacity of the output transistor is set to High by P8DRR register. When the drive capacity is set to Low, the value
of any other pin applies.
fOCO20M can be used as the count source for timer RC in the range of VCC = 2.7 V to 5.5V.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 53 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
P0
P2
P3
P5_0 to P5_6
P7_0 to P7_2
P8
P9_0 to P9_1
Figure 5.1
5. Electrical Characteristics
30 pF
Ports P0, P2, P3, P5_0 to P5_6, P7_0 to P7_2, P8, and P9_0 to P9_1 Timing
Measurement Circuit
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 54 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
5.1.3
Table 5.3
Peripheral Function Characteristics
A/D Converter Characteristics
(VCC/AVCC = Vref = 1.8 to 5.5 V, VSS = 0 V, and Topr = −20 to 85 °C (N version)/
−40 to 85 °C (D version), unless otherwise specified.)
Symbol
–
–
Parameter
Conditions
Resolution
Absolute accuracy
(2)
10-bit mode
8-bit mode
φAD
–
tCONV
tSAMP
IVref
Vref
VIA
5. Electrical Characteristics
A/D conversion clock
Tolerance level impedance
Conversion time
10-bit mode
8-bit mode
Sampling time
Vref current
Reference voltage
Analog input voltage (3)
OCVREF On-chip reference voltage
Vref = AVCC
Vref = AVCC = 5.0 V
Vref = AVCC = 2.2 V
Vref = AVCC = 1.8 V
Vref = AVCC = 5.0 V
AN0 to AN6 input
AN0 to AN6 input
AN0 to AN6 input
AN0 to AN6 input
Vref = AVCC = 2.2 V
Vref = AVCC = 1.8 V
AN0 to AN6 input
AN0 to AN6 input
Min.
–
–
–
–
–
Standard
Typ.
Max.
–
10
–
±3
–
±5
–
±5
–
±2
Unit
Bit
LSB
LSB
LSB
LSB
4.0 ≤ Vref = AVCC ≤ 5.5 V (1)
–
–
1
–
–
–
±2
±2
20
LSB
LSB
MHz
3.2 ≤ Vref = AVCC ≤ 5.5 V (1)
1
–
16
MHz
2.7 ≤ Vref = AVCC ≤ 5.5 V (1)
1
–
10
MHz
1.8 ≤ Vref = AVCC ≤ 5.5 V (1)
1
–
8
MHz
–
2.2
2.2
0.8
–
1.8
0
3
–
–
–
45
–
–
–
–
–
–
–
AVCC
Vref
kΩ
µs
ms
µs
µA
V
V
1.53
1.70
1.87
V
Vref = AVCC = 5.0 V, φAD = 20 MHz
Vref = AVCC = 5.0 V, φAD = 20 MHz
φAD = 20 MHz
Vcc = 5 V, XIN = f1 = φAD = 20 MHz
2 MHz ≤ φAD ≤ 4 MHz
Notes:
1. The A/D conversion result will be undefined in wait mode, stop mode, power-off mode, when the flash memory stops, and in
low-current-consumption mode. Do not perform A/D conversion in these states or transition to these states during A/D
conversion.
2. This applies when the peripheral functions are stopped.
3. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in
8-bit mode.
Table 5.4
Symbol
VTMP
–
–
ITMP
Temperature Sensor Characteristics
(VSS = 0 V and Topr = −20 to 85 °C (N version)/ −40 to 85 °C (D version), unless
otherwise specified.)
Parameter
Conditions
Temperature sensor output voltage 1.8 V ≤ Vref = AVCC ≤ 5.5 V
φAD = 1.0 MHz to 5.0 MHz
Ambient temperature = 25 °C
Temperature coefficient
1.8 V ≤ Vref = AVCC ≤ 5.5 V
φAD = 1.0 MHz to 5.0 MHz
Ambient temperature = 25 °C
Start-up time
1.8 V ≤ Vref = AVCC ≤ 5.5 V
φAD = 1.0 MHz to 5.0 MHz
Operating current
1.8 V ≤ Vref = AVCC ≤ 5.5 V
φAD = 1.0 MHz to 5.0 MHz
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Min.
550
Standard
Typ.
600
Max.
650
–
−2.1
–
mV/°C
–
–
200
µs
–
100
–
µA
Unit
mV
Page 55 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 5.5
Symbol
VGAIN
φAD
Table 5.6
Symbol
Vref
VI
−
td
ICMP
5. Electrical Characteristics
Gain Amplifier Characteristics
(VSS = 0 V and Topr = −20 to 85 °C (N version)/ −40 to 85 °C (D version), unless
otherwise specified.)
Parameter
Conditions
Gain amplifier operating range
A/D conversion clock
Min.
0.4
1
Standard
Typ.
Max.
—
AVCC − 1.0
—
5
Unit
V
MHz
Comparator B Characteristics
(VCC = 1.8 to 5.5 V and Topr = −20 to 85 °C (N version)/ −40 to 85 °C (D version), unless
otherwise specified.)
Parameter
Condition
IVREF1, IVREF3 input reference voltage
IVCMP1, IVCMP3 input voltage
Offset
Comparator output delay time (1)
Comparator operating current
VI = Vref ± 100 mV
VCC = 5.0 V
Min.
0
−0.3
–
–
–
Standard
Typ.
Max.
–
VCC − 1.4
–
VCC + 0.3
5
100
–
1
12
–
Unit
V
V
mV
µs
µA
Note:
1. When the digital filter is disabled.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 56 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 5.7
5. Electrical Characteristics
Flash Memory (Program ROM) Characteristics
(VCC = 1.8 to 5.5 V and Topr = 0 to 60 °C, unless otherwise specified.)
Symbol
Parameter
Conditions
Min.
–
–
–
td(SR-SUS)
–
td(CMDRST-READY)
–
–
–
–
Program/erase endurance (1)
Byte program time
Block erase time
Time delay from suspend request
until suspend
Time from suspend until erase
restart
Time from when command is forcibly
terminated until reading is enabled
Program, erase voltage
Read voltage
Program, erase temperature
Data hold time (6)
Ambient temperature = 85 °C
Standard
Typ.
Max.
–
–
Unit
times
10,000 (2)
–
80
–
µs
–
0.12
–
s
–
–
0.25 + CPU clock ms
× 3 cycles
µs
–
–
30 + CPU clock
× 1 cycle
–
–
30 + CPU clock
µs
× 1 cycle
1.8
–
5.5
V
1.8
–
5.5
V
°C
0
–
60
10
–
–
year
Notes:
1. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 1,000), each block can be erased n times. For example, if 1,024 1-byte
writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
2. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit
the number of erase operations to a certain number.
4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
5. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
6. The data hold time includes time that the power supply is off or the clock is not supplied.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 57 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 5.8
Flash Memory (Data flash Block A and Block B) Characteristics
(VCC = 1.8 to 5.5 V and Topr = −20 to 85 °C (N version)/ −40 to 85 °C (D version), unless
otherwise specified.)
Symbol
–
5. Electrical Characteristics
Parameter
Conditions
Program/erase endurance (1)
Min.
Standard
Typ.
Max.
–
–
–
150
–
time
s
µs
–
0.05
1
s
–
–
ms
–
–
–
–
1.8
1.8
−20 (6)
–
–
–
0.25 + CPU clock
× 3 cycles
30 + CPU clock
× 1 cycle
30 + CPU clock
× 1 cycle
5.5
5.5
85
10
–
–
year
10,000
(2)
–
–
td(SR-SUS)
–
Byte program time
(program/erase endurance ≤ 10,000 times)
Block erase time
(program/erase endurance ≤ 10,000 times)
Time delay from suspend request until
suspend
Time from suspend until erase restart
td(CMDRST-READY) Time from when command is forcibly
terminated until reading is enabled
–
Program, erase voltage
–
Read voltage
–
Program, erase temperature
–
Data hold
time (7)
Ambient temperature = 85 °C
Unit
µs
µs
V
V
°C
Notes:
1. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 10,000), each block can be erased n times. For example, if 1,024 1-byte
writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
2. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A and B can further
reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the
number of erase operations to a certain number.
4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
5. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
6. −40 °C for D version.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
Suspend request
(FMR21 bit)
FST7 bit
FST6 bit
Fixed time
Clock-dependent
time
Access restart
td(SR-SUS)
FST6, FST7: Bits in FST register
FMR21: Bit in FMR2 register
Figure 5.2
Time delay until Suspend
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 58 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 5.9
Symbol
Vdet0
Voltage Detection 0 Circuit Characteristics
(VCC = 1.8 to 5.5 V and Topr = −20 to 85 °C (N version)/ −40 to 85 °C (D version), unless
otherwise specified.)
Parameter
–
td(E-A)
Condition
Standard
Typ.
Max.
1.90
2.05
Unit
Voltage detection level Vdet0_0 (1)
Min.
1.8
(1)
2.15
2.35
2.50
V
Voltage detection level Vdet0_2 (1)
2.70
2.85
3.05
V
Voltage detection level Vdet0_3 (1)
Voltage detection 0 circuit
response time (3)
3.55
3.80
4.05
V
–
50
500
µs
–
100
500
µs
–
1.5
–
µA
–
–
100
µs
Voltage detection level Vdet0_1
–
5. Electrical Characteristics
Voltage detection circuit self power
consumption
Waiting time until voltage detection
circuit operation starts (2)
In operation
At the falling of Vcc from 5 V
to (Vdet0_0 − 0.1) V
In stop mode At the falling of Vcc from 5 V
to (Vdet0_0 − 0.1) V
VCA25 = 1, VCC = 5.0 V
V
Notes:
1. Select the voltage detection level with bits VDSEL0 and VDSEL1 in the OFS register.
2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2 register to 0.
3. Time until the voltage monitor 0 reset is generated after the voltage passes Vdet0.
Table 5.10
Symbol
Vdet1
–
–
–
td(E-A)
Voltage Detection 1 Circuit Characteristics
(VCC = 1.8 to 5.5 V and Topr = −20 to 85 °C (N version)/ −40 to 85 °C (D version), unless
otherwise specified.)
Parameter
Condition
Standard
Typ.
Max.
2.20
2.40
Unit
Voltage detection level Vdet1_0 (1)
At the falling of VCC
Min.
2.00
Voltage detection level Vdet1_1 (1)
At the falling of VCC
2.15
2.35
2.55
V
Voltage detection level Vdet1_2 (1)
At the falling of VCC
2.30
2.50
2.70
V
Voltage detection level Vdet1_3
(1)
At the falling of VCC
2.45
2.65
2.85
V
Voltage detection level Vdet1_4
(1)
At the falling of VCC
2.60
2.80
3.00
V
Voltage detection level Vdet1_5 (1)
At the falling of VCC
2.75
2.95
3.15
V
Voltage detection level Vdet1_6 (1)
At the falling of VCC
2.85
3.10
3.40
V
Voltage detection level Vdet1_7
(1)
At the falling of VCC
3.00
3.25
3.55
V
Voltage detection level Vdet1_8
(1)
At the falling of VCC
3.15
3.40
3.70
V
Voltage detection level Vdet1_9 (1)
At the falling of VCC
3.30
3.55
3.85
V
Voltage detection level Vdet1_A (1)
At the falling of VCC
3.45
3.70
4.00
V
Voltage detection level Vdet1_B
(1)
At the falling of VCC
3.60
3.85
4.15
V
Voltage detection level Vdet1_C
(1)
At the falling of VCC
3.75
4.00
4.30
V
Voltage detection level Vdet1_D (1)
At the falling of VCC
3.90
4.15
4.45
V
Voltage detection level Vdet1_E (1)
At the falling of VCC
4.05
4.30
4.60
V
(1)
At the falling of VCC
4.20
4.45
4.75
V
–
–
–
0.07
0.10
60
–
–
150
V
V
µs
–
250
500
µs
–
1.7
–
µA
–
–
100
µs
Voltage detection level Vdet1_F
Hysteresis width at the rising of Vcc in
voltage detection 1 circuit
Voltage detection 1 circuit response
time (2)
Voltage detection circuit self power
consumption
Waiting time until voltage detection
circuit operation starts (3)
Vdet1_0 to Vdet1_5 selected
Vdet1_6 to Vdet1_F selected
In operation At the falling of Vcc from
5 V to (Vdet1_0 − 0.1) V
In stop mode At the falling of Vcc from
5 V to (Vdet1_0 − 0.1) V
VCA26 = 1, VCC = 5.0 V
V
Notes:
1. Select the voltage detection level with bits VD1S0 to VD1S3 in the VD1LS register.
2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2 register to 0.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 59 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 5.11
Voltage Detection 2 Circuit Characteristics
(VCC = 1.8 to 5.5 V and Topr = −20 to 85 °C (N version)/ −40 to 85 °C (D version), unless
otherwise specified.)
Symbol
Vdet2
Parameter
Condition
Voltage detection level Vdet2_0 (1)
Hysteresis width at the rising of Vcc in
voltage detection 2 circuit
–
Voltage detection 2 circuit response time (2) In operation
Voltage detection circuit self power
consumption
Waiting time until voltage detection circuit
operation starts (3)
td(E-A)
Min.
3.70
At the falling of VCC
–
–
5. Electrical Characteristics
At the falling of Vcc from
5 V to (Vdet2_0 − 0.1) V
In stop mode At the falling of Vcc from
5 V to (Vdet2_0 − 0.1) V
VCA27 = 1, VCC = 5.0 V
Standard
Typ.
Max.
4.0
4.30
Unit
V
–
0.10
–
V
–
20
150
µs
–
200
500
µs
–
1.7
–
µA
–
–
100
µs
Notes:
1. The voltage detection level varies with detection targets. Select the level with the VCA24 bit in the VCA2 register.
2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.
3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
Table 5.12
Power-on Reset Circuit Characteristics (1)
(Topr = −20 to 85 °C (N version)/ −40 to 85 °C (D version), unless otherwise specified.)
Symbol
Parameter
Condition
External power VCC rise gradient
trth
Min.
0
Standard
Typ.
Max.
–
50000
Unit
mV/msec
Note:
1. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0.
Vdet0 (1)
Vdet0 (1)
trth
trth
External
Power VCC
0.5 V
tw(por) (2)
Voltage detection 0
circuit response time
Internal
reset signal
1
× 32
fOCO-S
1
× 32
fOCO-S
Notes:
1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit in the User’s Manual: Hardware for details.
2. tw(por) indicates the duration the external power VCC must be held below the valid voltage (0.5 V) to enable
a power-on reset. When turning on the power after it falls with voltage monitor 0 reset disabled, maintain
tw(por) for 1 ms or more.
Figure 5.3
Power-on Reset Circuit Characteristics
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 60 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 5.13
High-speed On-Chip Oscillator Circuit Characteristics
(VCC = 1.8 to 5.5 V and Topr = −20 to 85 °C (N version)/ −40 to 85 °C (D version), unless
otherwise specified.)
Symbol
–
–
–
5. Electrical Characteristics
Parameter
Min.
19.2
Standard
Typ.
20
Max.
20.8
MHz
19.0
20
21.0
MHz
17.694
18.432
19.169
MHz
17.510
18.432
19.353
MHz
–
–
5
530
30
–
µA
Condition
High-speed on-chip oscillator frequency after
reset
VCC = 1.8 V to 5.5 V
− 20 °C ≤ Topr ≤ 85 °C
High-speed on-chip oscillator frequency when
the FRA4 register correction value is written into
the FRA1 register and the FRA5 register
correction value into the FRA3 register (1)
VCC = 1.8 V to 5.5 V
− 40 °C ≤ Topr ≤ 85 °C
VCC = 1.8 V to 5.5 V
− 20 °C ≤ Topr ≤ 85 °C
VCC = 1.8 V to 5.5 V
− 40 °C ≤ Topr ≤ 85 °C
Oscillation stability time
Self power consumption at oscillation
VCC = 5.0 V, Topr = 25 °C
Unit
µs
Note:
1. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in
UART mode.
Table 5.14
Low-speed On-Chip Oscillator Circuit Characteristics
(VCC = 1.8 to 5.5 V and Topr = −20 to 85 °C (N version)/ −40 to 85 °C (D version), unless
otherwise specified.)
Symbol
fOCO-S
–
–
fOCO-WDT
–
–
Table 5.15
Parameter
Low-speed on-chip oscillator frequency
Oscillation stability time
Self power consumption at oscillation
Low-speed on-chip oscillator frequency for the
watchdog timer
Oscillation stability time
Self power consumption at oscillation
VCC = 5.0 V, Topr = 25°C
VCC = 5.0 V, Topr = 25°C
Min.
60
–
–
60
Standard
Typ.
125
–
2
125
Max.
250
35
–
250
–
–
–
2
35
–
Unit
kHz
µs
µA
kHz
µs
µA
Power Supply Circuit Characteristics
(VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = 25 °C, unless otherwise specified.)
Symbol
td(P-R)
Condition
Parameter
Condition
Time for internal power supply stabilization during
power-on (1)
Min.
–
Standard
Typ.
Max.
–
2000
Unit
µs
Note:
1. Waiting time until the internal power supply generation circuit stabilizes during power-on.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 61 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 5.16
5. Electrical Characteristics
LCD Drive Control Circuit Characteristics
(VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = −20 to 85 °C (N version)/
−40 to 85 °C (D version), unless otherwise specified.)
Symbol
Parameter
VLCD
VL2
VL1
LCD power supply voltage
VL2 voltage
VL1 voltage
f(FR)
ILCD
Frame frequency
LCD drive control circuit current
Condition
VLCD = VL3
Min.
2.2
VL1
1
50
–
Standard
Typ.
Max.
–
5.5
–
VL3
–
VL2 (2)
–
180
(1)
–
Unit
V
V
V
Hz
µA
Notes:
1. Refer to Table 5.19 DC Characteristics (2), Table 5.21 DC Characteristics (4), and Table 5.23 DC Characteristics (6).
2. The VL1 voltage should be VCC or below.
Table 5.17
Power-Off Mode Characteristics
(VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = −20 to 85 °C (N version)/
−40 to 85 °C (D version), unless otherwise specified.)
Symbol
–
Parameter
Power-off mode operating supply voltage
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Condition
Min.
1.8
Standard
Typ.
–
Max.
5.5
Unit
V
Page 62 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
5.1.4
DC Characteristics
Table 5.18
Symbol
VOH
DC Characteristics (1) [4.0 V ≤ Vcc ≤ 5.5 V]
(Topr = −20 to 85 °C (N version)/ −40 to 85 °C (D version), unless otherwise specified.)
Parameter
Output “H” voltage
VOL
Output “L” voltage
VT+-VT-
Hysteresis INT0, INT1, INT2,
INT3, INT5, INT7,
KI0, KI1, KI2, KI3,
KI4, KI5, KI6, KI7,
TRCIOA, TRCIOB,
TRCIOC, TRCIOD,
TRJ0IO, TRJ1IO,
TRCTRG, TRCCLK,
ADTRG,
RXD0, CLK0, SSI,
SCL, SDA, SSO
IIH
IIL
RPULLUP
RfXIN
RfXCIN
VRAM
5. Electrical Characteristics
RESET, WKUP0
Input “H” current
Input “L” current
Pull-up resistance
Feedback XIN
resistance
Feedback XCIN
resistance
RAM hold voltage
Standard
Min.
Typ.
VCC = 5V IOH = −20 mA VCC − 2.0
–
Max.
VCC
VCC = 5V IOH = −5 mA
VCC = 5V IOL = 20 mA
Condition
Port P8 (1)
Other pins
(1)
Port P8
Other pins
VI = 5 V, VCC = 5 V
VI = 0 V, VCC = 5 V
VI = 0 V, VCC = 5 V
During stop mode
VCC = 5V IOL = 5 mA
Unit
V
VCC − 2.0
–
–
–
VCC
2.0
V
V
–
0.05
–
0.5
2.0
–
V
V
0.1
0.8
–
V
–
–
20
–
–
–
40
2.0
5.0
µA
−5.0
80
–
µA
kΩ
MΩ
–
14
–
MΩ
1.8
–
–
V
Note:
1. This applies when the drive capacity of the output transistor is set to High by P8DRR register. When the drive capacity is set
to Low, the value of any other pin applies.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 63 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 5.19
5. Electrical Characteristics
DC Characteristics (2) [4.0 V ≤ Vcc ≤ 5.5 V]
(Topr = −20 to 85 °C (N version)/ −40 to 85 °C (D version), unless otherwise specified.)
Condition
Oscillation
Circuit
Symbol Parameter
HighSpeed
Off
Off
Off
Off
LowSpeed
125 kHz
125 kHz
125 kHz
Off
20 MHz
Off
Off
16 MHz
Off
Off
10 MHz
Off
Off
Off
Off
20 MHz
Highspeed
Off
Off
20 MHz
on-chip
Off
Off
4 MHz
oscillator
mode
Off
Off
Off
Lowspeed
on-chip
Off
Off
Off
oscillator
mode
LowOff
32 kHz
Off
speed
clock
mode
Off
32 kHz
Off
125 kHz
125 kHz
125 kHz
125 kHz
125 kHz
125 kHz
XIN
ICC
Power
Highsupply
speed
(1)
clock
current
mode
Wait
mode
Stop
mode
Poweroff mode
Notes:
1.
2.
3.
4.
On-Chip Oscillator
(2)
20 MHz
16 MHz
10 MHz
20 MHz
XCIN
Off
Off
Off
Off
CPU Clock
Standard
Low-PowerConsumption
Setting
Other
No division
–
No division
–
No division
–
No division FMR27 = 1
Flash memory off
MSTCR0 = BEh Program operation on RAM
MSTCR1 = 3Fh Module standby setting
enabled
Divide-by-8
–
Divide-by-8
–
Divide-by-8
–
No division
–
Divide-by-8
–
Divide-by-16 MSTCR0 = BEh
MSTCR1 = 3Fh
–
–
–
–
4.7
3.9
2.3
3.1
10
8
–
–
mA
mA
mA
mA
–
–
–
–
–
–
1.8
1.5
1.0
5.0
2.1
0.9
–
–
–
11
–
–
mA
mA
mA
mA
mA
mA
–
110 320 µA
–
63
220 µA
–
60
220 µA
Flash memory off
Program operation on RAM
–
46
–
µA
While a WAIT instruction is
executed
Peripheral clock operation
–
9.0
50
µA
While a WAIT instruction is
executed
Peripheral clock off
–
2.8
33
µA
While a WAIT LCD drive
instruction is control
executed
circuit (4)
Peripheral
When
clock off
external
Timer RH
division
operation in resistors are
real-time
used
clock mode
While a WAIT instruction is
executed
Peripheral clock off
Timer RH operation in realtime clock mode
–
4.6
–
µA
–
2.4
–
µA
Topr = 25 °C
Peripheral clock off
–
0.5
2.2
µA
Topr = 85 °C
Peripheral clock off
–
1.2
–
µA
Power-off 0
Topr = 25 °C
Power-off 0
Topr = 85 °C
Power-off 2
Topr = 25 °C
–
0.01 0.1
µA
–
0.03
–
µA
–
1.8
6.4
µA
Power-off 2
Topr = 85 °C
–
2.7
–
µA
125 kHz
No division FMR27 = 1
VCA20 = 0
125 kHz Divide-by-8 FMR27 = 1
VCA20 = 0
Off
No division FMR27 = 1
VCA20 = 0
Off
No division FMSTP = 1
VCA20 = 0
Off
Off
Off
125 kHz
–
Off
Off
Off
125 kHz
–
Off
32 kHz
Off
Off
–
Off
32 kHz
Off
Off
–
Off
Off
Off
Off
–
Off
Off
Off
Off
–
Off
Off
Off
Off
–
Off
Off
Off
Off
–
Off
32 kHz
Off
Off
–
Off
32 kHz
Off
Off
–
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 0
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
–
–
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
Max Unit
Min. Typ.
(3)
.
Vcc = 4.0 V to 5.5 V, single chip mode, output pins are open, and other pins are Vss.
XIN is set to square wave input.
Vcc = 5.0 V
VLCD = Vcc, external division resistors are used for VL3 to VL1, 1/3 bias, 1/4 duty, f(FR) = 64 Hz, SEG0 to SEG26 are selected, and segment
and common output pins are open. The standard value does not include the current that flows through external division resistors.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 64 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 5.20
DC Characteristics (3) [2.7 V ≤ Vcc < 4.0 V]
(Topr = −20 to 85 °C (N version)/ −40 to 85 °C (D version), unless otherwise specified.)
Symbol
VOH
5. Electrical Characteristics
Parameter
Output “H” voltage
Condition
Port P8 (1)
Other pins
VOL
Output “L” voltage
VT+-VT-
Hysteresis
IIH
IIL
RPULLUP
RfXIN
RfXCIN
VRAM
RESET, WKUP0
Input “H” current
Input “L” current
Pull-up resistance
Feedback resistance XIN
Feedback resistance XCIN
RAM hold voltage
Port P8 (1)
Other pins
INT0, INT1, INT2,
INT3, INT5, INT7,
KI0, KI1, KI2, KI3,
KI4, KI5, KI6, KI7,
TRCIOA, TRCIOB,
TRCIOC, TRCIOD,
TRJ0IO, TRJ1IO,
TRCTRG, TRCCLK,
ADTRG,
RXD0, CLK0, SSI,
SCL, SDA, SSO
VI = 3 V, VCC = 3 V
VI = 0 V, VCC = 3 V
VI = 0 V, VCC = 3 V
During stop mode
Standard
Min.
Typ.
IOH = −5 mA VCC − 0.5
–
Max.
VCC
IOH = −1 mA VCC − 0.5
IOL = 5 mA
–
–
–
VCC
0.5
V
V
–
0.05
–
0.4
0.5
–
V
V
0.1
0.8
–
V
–
–
25
–
–
1.8
–
–
80
2.0
14
–
5.0
−5.0
140
–
–
–
µA
IOL = 1 mA
Unit
V
µA
kΩ
MΩ
MΩ
V
Note:
1. This applies when the drive capacity of the output transistor is set to High by P8DRR register. When the drive capacity is set
to Low, the value of any other pin applies.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 65 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 5.21
5. Electrical Characteristics
DC Characteristics (4) [2.7 V ≤ Vcc < 4.0 V]
(Topr = −20 to 85 °C (N version)/ −40 to 85 °C (D version), unless otherwise specified.)
Condition
Oscillation
Circuit
20 MHz
10 MHz
20 MHz
Off
Off
Off
20 MHz
10 MHz
Off
Highspeed
Off
on-chip
Off
oscillator
mode
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
20 MHz
20 MHz
10 MHz
10 MHz
4 MHz
125 kHz
125 kHz
125 kHz
125 kHz
125 kHz
125 kHz
125 kHz
Lowspeed
on-chip
oscillator
mode
Lowspeed
clock
mode
Off
Off
Off
125 kHz
Off
Off
Off
125 kHz
Off
32 kHz
Off
Off
No division
FMR27 = 1
VCA20 = 0
Off
32 kHz
Off
Off
No division
FMSTP = 1
VCA20 = 0
Off
Off
Off
125 kHz
–
Off
Off
Off
125 kHz
–
Off
32 kHz
Off
Off
–
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 0
Off
32 kHz
Off
Off
–
Off
Off
Off
Off
–
Off
Off
Off
Off
–
Off
Off
Off
Off
–
Off
Off
Off
Off
–
Off
32 kHz
Off
Off
–
Off
32 kHz
Off
Off
–
Symbol Parameter
XIN
ICC
Power
Highsupply
speed
(1)
clock
current
mode
Wait
mode
Stop
mode
Poweroff mode
Notes:
1.
2.
3.
4.
Standard
On-Chip
Oscillator
HighLowSpeed Speed
Off
125 kHz
Off
125 kHz
Off
Off
(2)
XCIN
CPU Clock
Low-PowerConsumption
Setting
Other
No division
–
No division
–
No division FMR27 = 1
Flash memory off
MSTCR0 = BEh Program operation on RAM
MSTCR1 = 3Fh Module standby setting
enabled
Divide-by-8
–
Divide-by-8
–
No division
–
Divide-by-8
–
No division
–
Divide-by-8
–
Divide-by-16 MSTCR0 = BEh
MSTCR1 = 3Fh
No division FMR27 = 1
VCA20 = 0
Divide-by-8 FMR27 = 1
VCA20 = 0
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
–
–
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
Max Unit
Min. Typ.
(3)
.
–
–
–
4.7
2.3
2.9
10
6
–
mA
mA
mA
–
–
–
–
–
–
–
1.8
1.0
5.0
2.1
2.9
1.5
0.9
–
–
11
–
–
–
–
mA
mA
mA
mA
mA
mA
mA
–
106 300 µA
–
54
200 µA
–
54
200 µA
Flash memory off
Program operation on RAM
–
36
–
µA
While a WAIT instruction is
executed
Peripheral clock operation
–
9.0
50
µA
While a WAIT instruction is
executed
Peripheral clock off
–
2.5
31
µA
While a WAIT LCD drive
instruction is control circuit
(4)
executed
When external
Peripheral
division
clock off
resistors are
Timer RH
used
operation in
real-time clock
mode
While a WAIT instruction is
executed
Peripheral clock off
Timer RH operation in realtime clock mode
–
3.1
–
µA
–
1.7
–
µA
Topr = 25 °C
Peripheral clock off
–
0.5
2.2
µA
Topr = 85 °C
Peripheral clock off
–
1.2
–
µA
Power-off 0
Topr = 25 °C
Power-off 0
Topr = 85 °C
Power-off 2
Topr = 25 °C
–
0.01 0.1
µA
–
0.02
–
µA
–
1.3
4.5
µA
–
2.2
–
µA
Power-off 2
Topr = 85 °C
Vcc = 2.7 V to 4.0 V, single chip mode, output pins are open, and other pins are Vss.
XIN is set to square wave input.
Vcc = 3.0 V
VLCD = Vcc, external division resistors are used for VL3 to VL1, 1/3 bias, 1/4 duty, f(FR) = 64 Hz, SEG0 to SEG26 are selected, and segment
and common output pins are open. The standard value does not include the current that flows through external division resistors.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 66 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 5.22
DC Characteristics (5) [1.8 V ≤ Vcc < 2.7 V]
(Topr = −20 to 85 °C (N version)/ −40 to 85 °C (D version), unless otherwise specified.)
Symbol
VOH
5. Electrical Characteristics
Parameter
Output “H” voltage
Condition
Port P8 (1)
Other pins
VOL
Output “L” voltage
VT+-VT-
Hysteresis
IIH
IIL
RPULLUP
RfXIN
RfXCIN
VRAM
RESET, WKUP0
Input “H” current
Input “L” current
Pull-up resistance
Feedback resistance XIN
Feedback resistance XCIN
RAM hold voltage
Port P8 (1)
Other pins
INT0, INT1, INT2,
INT3, INT5, INT7,
KI0, KI1, KI2, KI3,
KI4, KI5, KI6, KI7,
TRCIOA, TRCIOB,
TRCIOC, TRCIOD,
TRJ0IO, TRJ1IO,
TRCTRG, TRCCLK,
ADTRG,
RXD0, CLK0, SSI,
SCL, SDA, SSO
VI = 1.8 V, VCC = 1.8 V
VI = 0 V, VCC = 1.8 V
VI = 0 V, VCC = 1.8 V
During stop mode
Standard
Min.
Typ.
IOH = −2 mA VCC − 0.5
–
Max.
VCC
IOH = −1 mA VCC − 0.5
IOL = 2 mA
–
–
–
VCC
0.5
V
V
–
0.05
–
0.4
0.5
–
V
V
0.1
0.8
–
V
–
–
85
–
–
1.8
–
–
220
2.0
14
–
4.0
−4.0
500
–
–
–
µA
IOL = 1 mA
Unit
V
µA
kΩ
MΩ
MΩ
V
Note:
1. This applies when the drive capacity of the output transistor is set to High by P8DRR register. When the drive capacity is set
to Low, the value of any other pin applies.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 67 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 5.23
DC Characteristics (6) [1.8 V ≤ Vcc < 2.7 V]
(Topr = −20 to 85 °C (N version)/ −40 to 85 °C (D version), unless otherwise specified.)
Oscillation
Circuit
Symbol Parameter
XIN
ICC
(2)
XCIN
Condition
On-Chip
Low-PowerOscillator
CPU Clock
Consumption
HighLowSetting
Speed Speed
Off
125 kHz No division
–
Off
125 kHz Divide-by-8
–
Standard
Other
Power
High8 MHz
Off
supply
speed
8 MHz
Off
(1)
clock
current
mode
Off
Off
5 MHz 125 kHz No division
–
Highspeed
Off
Off
5 MHz 125 kHz Divide-by-8
–
on-chip
Off
Off
4 MHz 125 kHz Divide-by-16 MSTCR0 = BEh
oscillator
MSTCR1 = 3Fh
mode
Off
Off
Off
125 kHz No division FMR27 = 1
LowVCA20 = 0
speed
on-chip
Off
Off
Off
125 kHz Divide-by-8 FMR27 = 1
oscillator
VCA20 = 0
mode
LowOff
32 kHz
Off
Off
No division FMR27 = 1
speed
VCA20 = 0
clock
mode
Off
32 kHz
Off
Off
No division FMSTP = 1
Flash memory off
VCA20 = 0
Program operation on RAM
Wait
mode
Stop
mode
Poweroff mode
Notes:
1.
2.
3.
4.
5. Electrical Characteristics
Off
Off
Off
125 kHz
–
Off
Off
Off
125 kHz
–
Off
32 kHz
Off
Off
–
Off
32 kHz
Off
Off
–
Off
Off
Off
Off
–
Off
Off
Off
Off
–
Off
Off
Off
Off
–
Off
Off
Off
Off
–
Off
32 kHz
Off
Off
–
Off
32 kHz
Off
Off
–
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 0
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
–
–
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
Max Unit
Min. Typ.
(3)
.
–
–
2.1
0.9
–
–
mA
mA
–
–
–
1.8
1.1
0.9
5
–
–
mA
mA
mA
–
106 300 µA
–
54
200 µA
–
54
200 µA
–
36
–
µA
While a WAIT instruction is
executed
Peripheral clock operation
–
9.0
50
µA
While a WAIT instruction is
executed
Peripheral clock off
–
2.5
31
µA
While a WAIT LCD drive
control circuit
instruction is
(4)
executed
When external
Peripheral
division
clock off
resistors are
Timer RH
used
operation in
real-time clock
mode
While a WAIT instruction is
executed
Peripheral clock off
Timer RH operation in realtime clock mode
–
2.4
–
µA
–
1.7
–
µA
Topr = 25 °C
Peripheral clock off
–
0.5
2.2
µA
Topr = 85 °C
Peripheral clock off
–
1.2
–
µA
Power-off 0
Topr = 25 °C
Power-off 0
Topr = 85 °C
Power-off 2
Topr = 25 °C
–
0.01 0.1
µA
–
0.02
–
µA
–
1.2
4
µA
–
2
–
µA
Power-off 2
Topr = 85 °C
Vcc = 1.8 V to 2.7 V, single chip mode, output pins are open, and other pins are Vss.
XIN is set to square wave input.
Vcc = 2.2 V
VLCD = Vcc, external division resistors are used for VL3 to VL1, 1/3 bias, 1/4 duty, f(FR) = 64 Hz, SEG0 to SEG26 are selected, and segment
and common output pins are open.The standard value does not include the current that flows through external division resistors.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 68 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
5.1.5
Table 5.24
AC Characteristics
Timing Requirements of Synchronous Serial Communication Unit (SSU)
(VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = −20 to 85 °C (N version)/
−40 to 85 °C (D version), unless otherwise specified.)
Symbol
Parameter
tSUCYC
SSCK clock cycle time
tHI
tLO
tRISE
SSCK clock “H” width
SSCK clock “L” width
SSCK clock rising
time
tFALL
SSCK clock falling
time
tSU
tH
5. Electrical Characteristics
Conditions
Min.
4
Standard
Typ.
–
Unit
Max.
-
tCYC (1)
tSUCYC
tSUCYC
Master
0.4
0.4
–
–
–
–
0.6
0.6
1
Slave
Master
–
–
–
–
1
1
–
100
1
–
–
–
1
–
–
1tCYC + 50
–
–
tCYC (1)
ns
1tCYC + 50
–
–
ns
–
–
–
–
–
–
–
–
–
–
1tCYC + 20
1.5tCYC + 100
1.5tCYC + 200
1.5tCYC + 100
1.5tCYC + 200
ns
ns
ns
ns
ns
Slave
SSO, SSI data input setup time
SSO, SSI data input hold time
tLEAD
SCS setup time
tLAG
tOD
tSA
Slave
SCS hold time
SSO, SSI data output delay time
SSI slave access time
tOR
SSI slave out open time
Slave
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
tCYC (1)
µs
tCYC (1)
µs
ns
Note:
1. 1tCYC = 1/f1(s)
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 69 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
5. Electrical Characteristics
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIL or VOL
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIL or VOL
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
CPHS, CPOS: Bits in SSMR register
Figure 5.4
I/O Timing of Synchronous Serial Communication Unit (SSU) (Master)
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 70 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
5. Electrical Characteristics
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIL or VOL
tLEAD
tHI
tFALL
tRISE
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
4-Wire Bus Communication Mode, Slave, CPHS = 0
VIH or VOH
SCS (input)
VIL or VOL
tLEAD
tHI
tFALL
tRISE
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
CPHS, CPOS: Bits in SSMR register
Figure 5.5
I/O Timing of Synchronous Serial Communication Unit (SSU) (Slave)
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 71 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
5. Electrical Characteristics
tHI
VIH or VOH
SSCK
VIL or VOL
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
Figure 5.6
tH
I/O Timing of Synchronous Serial Communication Unit (SSU) (Clock Synchronous
Communication Mode)
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 72 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 5.25
5. Electrical Characteristics
Timing Requirements of I2C bus Interface (1)
(VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = −20 to 85 °C (N version)/ −40 to 85 °C
(D version), unless otherwise specified.)
Symbol
Parameter
tSCL
SCL input cycle time
tSCLH
tSCLL
tsf
Standard
Condition
Min.
Typ.
Max.
Unit
–
–
ns
SCL input “H” width
3tCYC + 300
(1)
–
–
ns
SCL input “L” width
5tCYC + 500 (1)
–
–
ns
SCL, SDA input fall time
–
–
300
ns
tSP
SCL, SDA input spike pulse rejection time
–
–
1tCYC (1)
ns
tBUF
SDA input bus-free time
5tCYC (1)
–
–
ns
tSTAH
Start condition input hold time
3tCYC (1)
–
–
ns
tSTAS
Retransmit start condition input setup time
3tCYC (1)
–
–
ns
tSTOP
Stop condition input setup time
3tCYC (1)
–
–
ns
tSDAS
Data input setup time
1tCYC + 40 (1)
–
–
ns
tSDAH
Data input hold time
10
–
–
ns
12tCYC + 600 (1)
Note:
1. 1tCYC = 1/f1(s)
VIH
SDA
VIL
tBUF
tSTAH
tSCLH
tSTAS
tSP
tSTOP
SCL
P(2)
S(1)
tsf
Sr(3)
tSCLL
tsr
tSCL
P(2)
tSDAS
tSDAH
Notes:
1. Start condition
2. Stop condition
3. Retransmit start condition
Figure 5.7
I/O Timing of I2C bus Interface
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 73 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 5.26
5. Electrical Characteristics
External Clock Input (XIN, XCIN)
(VSS = 0 V and Topr = −20 to 85 °C (N version)/ −40 to 85 °C (D version), unless
otherwise specified.)
Standard
Symbol
Parameter
VCC = 2.2V, Topr = 25°C
VCC = 3V, Topr = 25°C
VCC = 5V, Topr = 25°C
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tc(XIN)
XIN input cycle time
200
–
50
–
50
–
tWH(XIN)
XIN input “H” width
90
–
24
–
24
–
ns
tWL(XIN)
XIN input “L” width
90
–
24
–
24
–
ns
ns
tc(XCIN)
XCIN input cycle time
20
–
20
–
20
–
µs
tWH(XCIN)
XCIN input “H” width
10
–
10
–
10
–
µs
tWL(XCIN)
XCIN input “L” width
10
–
10
–
10
–
µs
tC(XIN), tC(XCIN)
tWH(XIN),
tWH(XCIN)
External Clock
Input
tWL(XIN), tWL(XCIN)
Figure 5.8
Table 5.27
External Clock Input Timing Diagram
Timing Requirements of TRJiIO (i = 0 or 1)
(VSS = 0 V and Topr = −20 to 85 °C (N version)/ −40 to 85 °C (D version), unless
otherwise specified.)
Standard
Symbol
Parameter
VCC = 2.2V, Topr = 25°C
VCC = 3V, Topr = 25°C
VCC = 5V, Topr = 25°C
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tc(TRJIO)
TRJiIO input cycle time
500
–
300
–
100
–
ns
tWH(TRJIO)
TRJiIO input “H” width
200
–
120
–
40
–
ns
tWL(TRJIO)
TRJiIO input “L” width
200
–
120
–
40
–
ns
tC(TRJIO)
tWH(TRJIO)
TRJiIO input
tWL(TRJIO)
Figure 5.9
Input Timing of TRJiIO
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 74 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 5.28
5. Electrical Characteristics
Timing Requirements of Serial Interface
(VSS = 0 V and Topr = −20 to 85 °C (N version)/ −40 to 85 °C (D version), unless
otherwise specified.)
Standard
Symbol
Parameter
VCC = 2.2V, Topr = 25°C
Min.
VCC = 3V, Topr = 25°C
Max.
VCC = 5V, Topr = 25°C
Min.
Max.
Min.
Max.
Unit
tc(CK)
CLK0 input cycle time
800
–
300
–
200
–
tW(CKH)
CLK0 input “H” width
400
–
150
–
100
–
ns
ns
tW(CKL)
CLK0 input “L” width
400
–
150
–
100
–
ns
td(C-Q)
TXD0 output delay time
–
200
–
80
–
50
ns
th(C-Q)
TXD0 hold time
0
–
0
–
0
–
ns
tsu(D-C)
RXD0 input setup time
150
–
70
–
50
–
ns
th(C-D)
RXD0 input hold time
90
–
90
–
90
–
ns
tC(CK)
tW(CKH)
CLK0
tW(CKL)
th(C-Q)
TXD0
td(C-Q)
tsu(D-C)
th(C-D)
RXD0
Figure 5.10
Table 5.29
Input and Output Timing of Serial Interface
Timing Requirements of External Interrupt INTi (i = 0 to 3, 5, 7) and Key Input Interrupt
KIi (i = 0 to 7)
(VSS = 0 V and Topr = −20 to 85 °C (N version)/ −40 to 85 °C (D version), unless
otherwise specified.)
Standard
Symbol
tW(INH)
tW(INL)
VCC = 2.2V, Topr = 25°C
Parameter
VCC = 3V, Topr = 25°C
VCC = 5V, Topr = 25°C
Unit
Min.
Max.
Min.
Max.
Min.
Max.
INTi input “H” width, KIi input “H” width
1000 (1)
–
380 (1)
–
250 (1)
–
ns
INTi input “L” width, KIi input “L” width
1000 (2)
–
380 (2)
–
250 (2)
–
ns
Notes:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
INTi input
(i = 0 to 3, 5, 7)
tW(INL)
KIi input
(i = 0 to 7)
Figure 5.11
tW(INH)
Input Timing of External Interrupt INTi and Key Input Interrupt KIi
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 75 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
5.2
Electrical Characteristics (R8C/LA6A Group and R8C/LA8A Group)
5.2.1
Absolute Maximum Ratings
Table 5.30
Absolute Maximum Ratings
Symbol
Parameter
Condition
VCC/AVCC Supply voltage
VI
VO
5. Electrical Characteristics
Input voltage
Rated Value
Unit
−0.3 to 6.5
V
XIN
XIN-XOUT oscillation on
(oscillation buffer ON) (1)
−0.3 to 1.9
V
XIN
XIN-XOUT oscillation on
(oscillation buffer OFF) (1)
−0.3 to VCC + 0.3
V
P5_4/VL1
−0.3 to VL2 (2)
V
P5_5/VL2
VL1 to VL3
V
P5_6/VL3
VL2 to 6.5
V
Other pins
−0.3 to VCC + 0.3
V
XIN-XOUT oscillation on
(oscillation buffer ON) (1)
−0.3 to 1.9
V
XIN-XOUT oscillation on
(oscillation buffer OFF) (1)
−0.3 to VCC + 0.3
V
COM0 to COM3
−0.3 to VL3
V
SEG0 to SEG39
−0.3 to VL3
V
Output voltage XOUT
XOUT
Other pins
Pd
Power dissipation
Topr
Operating ambient temperature
Tstg
Storage temperature
−40°C ≤ Topr ≤ 85°C
−0.3 to VCC + 0.3
V
500
mW
−20 to 85 (N version)/
−40 to 85 (D version)
°C
−65 to 150
°C
Notes:
1. For the register settings for each operation, refer to 7. I/O Ports and 9. Clock Generation Circuit in the User’s Manual:
Hardware.
2. The VL1 voltage should be VCC or below.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 76 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
5.2.2
Recommended Operating Conditions
Table 5.31
Recommended Operating Conditions
(VCC = 1.8 to 5.5 V and Topr = −20 to 85°C (N version)/ −40 to 85°C (D version), unless
otherwise specified.)
Sum of all pins IOH(peak)
Min.
1.8
–
0.8 VCC
0.8 VCC
0.9 VCC
0.5 VCC
0.55 VCC
0.65 VCC
0.65 VCC
0.7 VCC
0.8 VCC
0.85 VCC
0.85 VCC
0.85 VCC
0
0
0
0
0
0
0
0
0
0
0
0
–
Standard
Typ.
–
0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Max.
5.5
–
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
0.2 VCC
0.2 VCC
0.05 VCC
0.2 VCC
0.2 VCC
0.2 VCC
0.4 VCC
0.3 VCC
0.2 VCC
0.55 VCC
0.45 VCC
0.35 VCC
−160
Sum of all pins IOH(avg)
–
–
−80
mA
–
–
–
–
–
–
–
–
–
–
−40
−10
−20
−5
160
mA
mA
mA
mA
mA
–
–
80
mA
–
–
–
–
2
2
–
–
18.432
0
0
–
–
–
–
–
–
32.768
–
–
-
40
10
20
5
20
8
–
50
20
20
8
20
8
20
8
mA
mA
mA
mA
MHz
MHz
kHz
kHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Symbol
Parameter
Conditions
VCC/AVCC Supply voltage
VSS/AVSS Supply voltage
VIH
Input “H” voltage Other than CMOS input
CMOS Input level
input
switching
function
(I/O port)
Input level selection
: 0.35 VCC
Input level selection
: 0.5 VCC
Input level selection
: 0.7 VCC
VIL
Input “L” voltage Other than CMOS input
CMOS Input level
input
switching
function
(I/O port)
Input level selection
: 0.35 VCC
Input level selection
: 0.5 VCC
Input level selection
: 0.7 VCC
IOH(sum)
IOH(sum)
IOH(peak)
IOH(avg)
IOL(sum)
IOL(sum)
IOL(peak)
IOL(avg)
f(XIN)
5. Electrical Characteristics
Peak sum output
“H” current
Average sum
output “H” current
Peak output “H”
current
Port P7_0, P7_1, P8 (2)
Other pins
Average output Port P7_0, P7_1, P8 (2)
“H” current (1)
Other pins
Peak sum output Sum of all pins IOL(peak)
“L” current
Average sum
Sum of all pins IOL(avg)
output “L” current
Peak output “L” Port P7_0, P7_1, P8 (2)
current
Other pins
Average output Port P7_0, P7_1, P8 (2)
“L” current (1)
Other pins
XIN clock input oscillation frequency
f(XCIN)
XCIN oscillation frequency
XCIN external clock input frequency
fOCO20M When used as the count source for timer RC (3)
fOCO-F fOCO-F frequency
−
System clock frequency
f(BCLK)
CPU clock frequency
4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
4.0 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC < 4.0 V
1.8 V ≤ VCC < 2.7 V
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
1.8 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC ≤ 5.5 V
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
2.7 V ≤ VCC ≤ 5.5 V
1.8 V ≤ VCC < 2.7 V
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
Notes:
1. The average output current indicates the average value of current measured during 100 ms.
2. This applies when the drive capacity of the output transistor is set to High by registers P7DRR and P8DRR. When the drive capacity
is set to Low, the value of any other pin applies.
3. fOCO20M can be used as the count source for timer RC in the range of VCC = 2.7 V to 5.5V.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 77 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
P0
P1
P2
P3
P4
P5_0 to P5_6
P6
P7_0 to P7_6
P8
P9_0 to P9_1
Figure 5.12
5. Electrical Characteristics
30 pF
Ports P0 to P4, P5_0 to P5_6, P6, P7_0 to P7_6, P8, and P9_0 to P9_1 Timing
Measurement Circuit
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 78 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
5.2.3
Peripheral Function Characteristics
Table 5.32
A/D Converter Characteristics
(VCC/AVCC = Vref = 1.8 to 5.5 V, VSS = 0 V, and Topr = −20 to 85°C (N version)/ −40 to
85°C (D version), unless otherwise specified.)
Symbol
–
Parameter
(2)
10-bit mode
8-bit mode
Tolerance level impedance
tCONV
Conversion time
Unit
–
–
10
Bit
–
–
±3
LSB
Vref = AVCC = 2.2 V
AN0 to AN11 input
–
–
±5
LSB
Vref = AVCC = 1.8 V
AN0 to AN11 input
–
–
±5
LSB
Vref = AVCC = 5.0 V
AN0 to AN11 input
–
–
±2
LSB
Vref = AVCC = 2.2 V
AN0 to AN11 input
–
–
±2
LSB
Vref = AVCC = 1.8 V
AN0 to AN11 input
–
–
±2
LSB
(1)
1
–
20
MHz
3.2 ≤ Vref = AVCC ≤ 5.5 V (1)
1
–
16
MHz
2.7 ≤ Vref = AVCC ≤ 5.5 V (1)
1
–
10
MHz
1.8 ≤ Vref = AVCC ≤ 5.5 V (1)
1
–
8
MHz
–
3
–
kΩ
10-bit mode
Vref = AVCC = 5.0 V, φAD = 20 MHz
2.2
–
–
µs
8-bit mode
Vref = AVCC = 5.0 V, φAD = 20 MHz
2.2
–
–
ms
0.8
–
–
µs
-
45
–
µA
1.8
–
AVCC
V
0
–
Vref
V
1.53
1.70
1.87
V
Sampling time
φAD = 20 MHz
IVref
Vref current
Vcc = 5 V, XIN = f1 = φAD = 20 MHz
Vref
Reference voltage
(3)
OCVREF On-chip reference voltage
Max.
AN0 to AN11 input
tSAMP
Analog input voltage
Typ.
Vref = AVCC = 5.0 V
4.0 ≤ Vref = AVCC ≤ 5.5 V
A/D conversion clock
–
VIA
Min.
Vref = AVCC
Absolute accuracy
φAD
Standard
Conditions
Resolution
–
5. Electrical Characteristics
2 MHz ≤ φAD ≤ 4 MHz
Notes:
1. The A/D conversion result will be undefined in wait mode, stop mode, power-off mode, when the flash memory stops, and in
low-current-consumption mode. Do not perform A/D conversion in these states or transition to these states during A/D
conversion.
2. This applies when the peripheral functions are stopped.
3. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in
8-bit mode.
Table 5.33
Symbol
Temperature Sensor Characteristics
(VSS = 0 V and Topr = −20 to 85 °C (N version)/−40 to 85 °C (D version), unless
otherwise specified.)
Parameter
Conditions
Standard
Unit
Min.
Typ.
Max.
550
600
650
mV
VTMP
Temperature sensor output voltage 1.8 V ≤ Vref = AVCC ≤ 5.5 V
φAD = 1.0 MHz to 5.0 MHz
Ambient temperature = 25 °C
–
Temperature coefficient
1.8 V ≤ Vref = AVCC ≤ 5.5 V
φAD = 1.0 MHz to 5.0 MHz
Ambient temperature = 25 °C
–
−2.1
–
mV/°C
–
Start-up time
1.8 V ≤ Vref = AVCC ≤ 5.5 V
φAD = 1.0 MHz to 5.0 MHz
–
–
200
µs
ITMP
Operating current
1.8 V ≤ Vref = AVCC ≤ 5.5 V
φAD = 1.0 MHz to 5.0 MHz
–
100
–
µA
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 79 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 5.34
Gain Amplifier Characteristics
(VSS = 0 V and Topr = −20 to 85 °C (N version)/−40 to 85 °C (D version), unless
otherwise specified.)
Symbol
Parameter
VGAIN
Gain amplifier operating range
φAD
A/D conversion clock
Table 5.35
5. Electrical Characteristics
Conditions
Standard
Unit
Min.
Typ.
Max.
0.4
–
AVCC – 1.0
V
1
–
5
MHz
Comparator B Characteristics
(VCC = 1.8 to 5.5 V and Topr = −20 to 85°C (N version)/ −40 to 85°C (D version), unless
otherwise specified.)
Symbol
Parameter
Condition
Vref
IVREF1, IVREF3 input reference voltage
VI
IVCMP1, IVCMP3 input voltage
−
Offset
td
Comparator output delay time (1)
VI = Vref ± 100 mV
ICMP
Comparator operating current
VCC = 5.0 V
Standard
Min.
Typ.
Max.
Unit
0
–
VCC − 1.4
-0.3
–
VCC + 0.3
V
–
5
100
mV
–
–
1
µs
–
12
–
µA
V
Note:
1. When the digital filter is disabled.
Table 5.36
Flash Memory (Program ROM) Characteristics
(VCC = 1.8 to 5.5 V and Topr = 0 to 60°C, unless otherwise specified.)
Symbol
Parameter
Conditions
Standard
Min.
Typ.
Max.
Unit
–
Program/erase endurance (1)
10,000 (2)
–
–
times
–
Byte program time
–
80
–
µs
–
Block erase time
–
0.12
–
s
td(SR-SUS)
Time delay from suspend request
until suspend
–
–
0.25 + CPU clock
× 3 cycles
ms
–
Time from suspend until erase
restart
–
–
30 + CPU clock
× 1 cycle
µs
–
–
30 + CPU clock
× 1 cycle
µs
td(CMDRST-READY) Time from when command is forcibly
terminated until reading is enabled
–
Program, erase voltage
1.8
–
5.5
V
–
Read voltage
1.8
–
5.5
V
–
Program, erase temperature
0
–
60
°C
–
Data hold time (6)
10
–
–
year
Ambient temperature = 85°C
Notes:
1. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 1,000), each block can be erased n times. For example, if 1,024 1-byte
writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
2. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit
the number of erase operations to a certain number.
4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
5. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
6. The data hold time includes time that the power supply is off or the clock is not supplied.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 80 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 5.37
Flash Memory (Data flash Block A and Block B) Characteristics
(VCC = 1.8 to 5.5 V and Topr = −20 to 85°C (N version)/ −40 to 85°C (D version), unless
otherwise specified.)
Symbol
–
5. Electrical Characteristics
Parameter
Conditions
Program/erase endurance (1)
Standard
Unit
Min.
Typ.
Max.
10,000
–
–
time
s
(2)
–
Byte program time
(program/erase endurance ≤ 10,000 times)
–
150
–
µs
–
Block erase time
(program/erase endurance ≤ 10,000 times)
–
0.05
1
s
td(SR-SUS)
Time delay from suspend request until
suspend
–
–
0.25 + CPU clock
× 3 cycles
ms
–
Time from suspend until erase restart
–
–
30 + CPU clock
× 1 cycle
µs
td(CMDRST-READY) Time from when command is forcibly
terminated until reading is enabled
–
–
30 + CPU clock
× 1 cycle
µs
–
Program, erase voltage
1.8
–
5.5
V
–
Read voltage
1.8
–
5.5
V
–
Program, erase temperature
−20 (6)
–
85
°C
–
time (7)
10
–
–
year
Data hold
Ambient temperature = 85 °C
Notes:
1. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 10,000), each block can be erased n times. For example, if 1,024 1-byte
writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
2. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A and B can further
reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the
number of erase operations to a certain number.
4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
5. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
6. −40°C for D version.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
Suspend request
(FMR21 bit)
FST7 bit
FST6 bit
Fixed time
Clock-dependent
time
Access restart
td(SR-SUS)
FST6, FST7: Bits in FST register
FMR21: Bit in FMR2 register
Figure 5.13
Time delay until Suspend
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 81 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 5.38
Symbol
Vdet0
Voltage Detection 0 Circuit Characteristics
(VCC = 1.8 to 5.5 V and Topr = −20 to 85°C (N version)/ −40 to 85°C (D version), unless
otherwise specified.)
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
Voltage detection level Vdet0_0 (1)
1.8
1.90
2.05
V
Voltage detection level Vdet0_1 (1)
2.15
2.35
2.50
V
Voltage detection level Vdet0_2 (1)
2.70
2.85
3.05
V
(1)
3.55
3.80
4.05
V
At the falling of Vcc from 5 V
to (Vdet0_0 − 0.1) V
–
50
500
µs
In stop mode At the falling of Vcc from 5 V
to (Vdet0_0 − 0.1) V
–
100
500
µs
VCA25 = 1, VCC = 5.0 V
–
1.5
–
µA
–
–
100
µs
Voltage detection level Vdet0_3
–
5. Electrical Characteristics
In operation
Voltage detection 0 circuit
response time (3)
–
Voltage detection circuit self power
consumption
td(E-A)
Waiting time until voltage detection
circuit operation starts (2)
Notes:
1. Select the voltage detection level with bits VDSEL0 and VDSEL1 in the OFS register.
2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2 register to 0.
3. Time until the voltage monitor 0 reset is generated after the voltage passes Vdet0.
Table 5.39
Symbol
Vdet1
Voltage Detection 1 Circuit Characteristics
(VCC = 1.8 to 5.5 V and Topr = −20 to 85°C (N version)/ −40 to 85°C (D version), unless
otherwise specified.)
Parameter
–
Standard
Min.
Typ.
Max.
Unit
Voltage detection level Vdet1_0 (1)
At the falling of VCC
2.00
2.20
2.40
V
Voltage detection level Vdet1_1 (1)
At the falling of VCC
2.15
2.35
2.55
V
Voltage detection level Vdet1_2 (1)
At the falling of VCC
2.30
2.50
2.70
V
Voltage detection level Vdet1_3
(1)
At the falling of VCC
2.45
2.65
2.85
V
Voltage detection level Vdet1_4
(1)
At the falling of VCC
2.60
2.80
3.00
V
Voltage detection level Vdet1_5 (1)
At the falling of VCC
2.75
2.95
3.15
V
Voltage detection level Vdet1_6 (1)
At the falling of VCC
2.85
3.10
3.40
V
Voltage detection level Vdet1_7
(1)
At the falling of VCC
3.00
3.25
3.55
V
Voltage detection level Vdet1_8
(1)
At the falling of VCC
3.15
3.40
3.70
V
Voltage detection level Vdet1_9 (1)
At the falling of VCC
3.30
3.55
3.85
V
Voltage detection level Vdet1_A (1)
At the falling of VCC
3.45
3.70
4.00
V
Voltage detection level Vdet1_B
(1)
At the falling of VCC
3.60
3.85
4.15
V
Voltage detection level Vdet1_C
(1)
At the falling of VCC
3.75
4.00
4.30
V
Voltage detection level Vdet1_D (1)
At the falling of VCC
3.90
4.15
4.45
V
Voltage detection level Vdet1_E (1)
At the falling of VCC
4.05
4.30
4.60
V
(1)
At the falling of VCC
4.20
4.45
4.75
V
Voltage detection level Vdet1_F
–
Condition
Hysteresis width at the rising of Vcc in
voltage detection 1 circuit
Vdet1_0 to Vdet1_5 selected
–
0.07
–
V
Vdet1_6 to Vdet1_F selected
–
0.10
–
V
Voltage detection 1 circuit response
time (2)
In operation
At the falling of Vcc from
5 V to (Vdet1_0 − 0.1) V
–
60
150
µs
In stop mode At the falling of Vcc from
5 V to (Vdet1_0 − 0.1) V
–
250
500
µs
VCA26 = 1, VCC = 5.0 V
–
1.7
–
µA
–
–
100
µs
–
Voltage detection circuit self power
consumption
td(E-A)
Waiting time until voltage detection
circuit operation starts (3)
Notes:
1. Select the voltage detection level with bits VD1S0 to VD1S3 in the VD1LS register.
2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2 register to 0.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 82 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 5.40
5. Electrical Characteristics
Voltage Detection 2 Circuit Characteristics
(VCC = 1.8 to 5.5 V and Topr = −20 to 85°C (N version)/ −40 to 85°C (D version), unless
otherwise specified.)
Symbol
Parameter
Standard
Condition
Max.
3.70
4.0
4.30
V
–
0.10
–
V
At the falling of Vcc from
5 V to (Vdet2_0 − 0.1) V
–
20
150
µs
In stop mode At the falling of Vcc from
5 V to (Vdet2_0 − 0.1) V
–
200
500
µs
VCA27 = 1, VCC = 5.0 V
–
1.7
–
µA
–
–
100
µs
Voltage detection level Vdet2_0 (1)
–
Hysteresis width at the rising of Vcc in
voltage detection 2 circuit
–
Voltage detection 2 circuit response time (2) In operation
At the falling of VCC
–
Voltage detection circuit self power
consumption
td(E-A)
Waiting time until voltage detection circuit
operation starts (3)
Unit
Typ.
Vdet2
Min.
Notes:
1. The voltage detection level varies with detection targets. Select the level with the VCA24 bit in the VCA2 register.
2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.
3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
Table 5.41
Power-on Reset Circuit Characteristics (1)
(Topr = −20 to 85°C (N version)/ −40 to 85°C (D version), unless otherwise specified.)
Symbol
trth
Parameter
Condition
Standard
Min.
Typ.
Max.
0
–
50000
External power VCC rise gradient
Unit
mV/msec
Note:
1. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0.
Vdet0 (1)
Vdet0 (1)
trth
trth
External
Power VCC
0.5 V
tw(por) (2)
Voltage detection 0
circuit response time
Internal
reset signal
1
× 32
fOCO-S
1
× 32
fOCO-S
Notes:
1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit in the User’s Manual: Hardware for details.
2. tw(por) indicates the duration the external power VCC must be held below the valid voltage (0.5 V) to enable
a power-on reset. When turning on the power after it falls with voltage monitor 0 reset disabled, maintain
tw(por) for 1 ms or more.
Figure 5.14
Power-on Reset Circuit Characteristics
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 83 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 5.42
High-speed On-Chip Oscillator Circuit Characteristics
(VCC = 1.8 to 5.5 V and Topr = −20 to 85°C (N version)/ −40 to 85°C (D version), unless
otherwise specified.)
Symbol
–
5. Electrical Characteristics
Parameter
High-speed on-chip oscillator frequency after
reset
High-speed on-chip oscillator frequency when
the FRA4 register correction value is written into
the FRA1 register and the FRA5 register
correction value into the FRA3 register (1)
–
Oscillation stability time
–
Self power consumption at oscillation
Standard
Condition
Unit
Min.
Typ.
Max.
VCC = 1.8 V to 5.5 V
− 20°C ≤ Topr ≤ 85°C
19.2
20
20.8
MHz
VCC = 1.8 V to 5.5 V
− 40°C ≤ Topr ≤ 85°C
19.0
20
21.0
MHz
VCC = 1.8 V to 5.5 V
− 20°C ≤ Topr ≤ 85°C
17.694
18.432
19.169
MHz
VCC = 1.8 V to 5.5 V
− 40°C ≤ Topr ≤ 85°C
17.510
18.432
19.353
MHz
–
5
30
µs
–
530
–
µA
VCC = 5.0 V, Topr = 25°C
Note:
1. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in
UART mode.
Table 5.43
Low-speed On-Chip Oscillator Circuit Characteristics
(VCC = 1.8 to 5.5 V and Topr = −20 to 85°C (N version)/ −40 to 85°C (D version), unless
otherwise specified.)
Symbol
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
fOCO-S
Low-speed on-chip oscillator frequency
60
125
250
–
Oscillation stability time
–
–
35
µs
–
Self power consumption at oscillation
–
2
–
µA
fOCO-WDT
Low-speed on-chip oscillator frequency for the
watchdog timer
60
125
250
kHz
–
Oscillation stability time
–
–
35
µs
–
Self power consumption at oscillation
–
2
–
µA
Table 5.44
VCC = 5.0 V, Topr = 25°C
Power Supply Circuit Characteristics
(VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = 25°C, unless otherwise specified.)
Symbol
td(P-R)
VCC = 5.0 V, Topr = 25°C
kHz
Parameter
Condition
Time for internal power supply stabilization during
power-on (1)
Standard
Min.
Typ.
Max.
–
–
2000
Unit
µs
Note:
1. Waiting time until the internal power supply generation circuit stabilizes during power-on.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 84 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 5.45
5. Electrical Characteristics
LCD Drive Control Circuit Characteristics
(VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = −20 to 85°C (N version)/ −40 to 85°C (D version),
unless otherwise specified.)
Symbol
Parameter
Condition
VLCD = VL3
Standard
Min.
Typ.
Max.
Unit
VLCD
LCD power supply voltage
2.2
–
5.5
V
VL2
VL2 voltage
VL1
–
VL3
V
VL1
VL1 voltage
1
–
VL2 (2)
V
f(FR)
Frame frequency
50
–
180
Hz
ILCD
LCD drive control circuit current
–
(1)
–
µA
Notes:
1. Refer to Table 5.48 DC Characteristics (2), Table 5.50 DC Characteristics (4), and Table 5.52 DC Characteristics (6).
2. The VL1 voltage should be VCC or below.
Table 5.46
Power-Off Mode Characteristics
(VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = −20 to 85°C (N version)/ −40 to 85°C (D version),
unless otherwise specified.)
Symbol
–
Parameter
Power-off mode operating supply voltage
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Condition
Standard
Min.
Typ.
Max.
1.8
–
5.5
Unit
V
Page 85 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
5.2.4
DC Characteristics
Table 5.47
Symbol
VOH
5. Electrical Characteristics
DC Characteristics (1) [4.0 V ≤ Vcc ≤ 5.5 V]
(Topr = −20 to 85°C (N version)/ −40 to 85°C (D version), unless otherwise specified.)
Parameter
Output “H” voltage
Condition
Port P7_0, P7_1, P8 (1) VCC = 5V IOH = −20 mA VCC − 2.0
Other pins
VOL
Output “L” voltage
VT+-VT-
Hysteresis INT0, INT1, INT2,
INT3, INT4, INT5,
INT6, INT7,
KI0, KI1, KI2, KI3,
KI4, KI5, KI6, KI7,
TRCIOA, TRCIOB,
TRCIOC, TRCIOD,
TRJ0IO, TRJ1IO,
TRJ2IO, TRCTRG,
TRCCLK, ADTRG,
RXD0, RXD2, CLK0,
CLK2, SSI, SCL,
SDA, SSO
Standard
Min.
Port P7_0, P7_1, P8
Other pins
RESET, WKUP0
(1)
Typ.
Max.
Unit
–
VCC
V
VCC = 5V IOH = −5 mA
VCC − 2.0
–
VCC
V
VCC = 5V IOL = 20 mA
–
–
2.0
V
VCC = 5V IOL = 5 mA
–
–
2.0
V
0.05
0.5
–
V
0.1
0.8
–
V
µA
IIH
Input “H” current
VI = 5 V, VCC = 5 V
–
–
5.0
IIL
Input “L” current
VI = 0 V, VCC = 5 V
–
–
−5.0
µA
VI = 0 V, VCC = 5 V
20
40
80
kΩ
RPULLUP Pull-up resistance
RfXIN
Feedback XIN
resistance
–
2.0
–
MΩ
RfXCIN
Feedback XCIN
resistance
–
14
–
MΩ
VRAM
RAM hold voltage
1.8
–
–
V
During stop mode
Note:
1. This applies when the drive capacity of the output transistor is set to High by registers P7DRR and P8DRR. When the drive
capacity is set to Low, the value of any other pin applies.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 86 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 5.48
5. Electrical Characteristics
DC Characteristics (2) [4.0 V ≤ Vcc ≤ 5.5 V]
(Topr = −20 to 85°C (N version)/ −40 to 85°C (D version), unless otherwise specified.)
Condition
Oscillation
Circuit
Symbol Parameter
HighSpeed
Off
Off
Off
Off
LowSpeed
125 kHz
125 kHz
125 kHz
Off
20 MHz
Off
Off
16 MHz
Off
Off
10 MHz
Off
Off
Off
Off
20 MHz
Highspeed
Off
Off
20 MHz
on-chip
Off
Off
4 MHz
oscillator
mode
Off
Off
Off
Lowspeed
on-chip
Off
Off
Off
oscillator
mode
LowOff
32 kHz
Off
speed
clock
mode
Off
32 kHz
Off
125 kHz
125 kHz
125 kHz
125 kHz
125 kHz
125 kHz
XIN
ICC
Power
Highsupply
speed
(1)
clock
current
mode
Wait
mode
Stop
mode
Poweroff mode
Notes:
1.
2.
3.
4.
On-Chip Oscillator
(2)
20 MHz
16 MHz
10 MHz
20 MHz
XCIN
Off
Off
Off
Off
CPU Clock
Standard
Low-PowerConsumption
Setting
Other
No division
–
No division
–
No division
–
No division FMR27 = 1
Flash memory off
MSTCR0 = BEh Program operation on RAM
MSTCR1 = 3Fh Module standby setting
enabled
Divide-by-8
–
Divide-by-8
–
Divide-by-8
–
No division
–
Divide-by-8
–
Divide-by-16 MSTCR0 = BEh
MSTCR1 = 3Fh
–
–
–
–
4.7
3.9
2.3
3.1
10
8
–
–
mA
mA
mA
mA
–
–
–
–
–
–
1.8
1.5
1.0
5.0
2.1
0.9
–
–
–
11
–
–
mA
mA
mA
mA
mA
mA
–
110 320 µA
–
63
220 µA
–
60
220 µA
Flash memory off
Program operation on RAM
–
46
–
µA
While a WAIT instruction is
executed
Peripheral clock operation
–
9.0
50
µA
While a WAIT instruction is
executed
Peripheral clock off
–
2.8
33
µA
While a WAIT LCD drive
instruction is control
executed
circuit (4)
Peripheral
When
clock off
external
Timer RH
division
operation in resistors are
real-time
used
clock mode
While a WAIT instruction is
executed
Peripheral clock off
Timer RH operation in realtime clock mode
–
4.6
–
µA
–
2.4
–
µA
Topr = 25°C
Peripheral clock off
–
0.5
2.2
µA
Topr = 85°C
Peripheral clock off
–
1.2
–
µA
Power-off 0
Topr = 25°C
Power-off 0
Topr = 85°C
Power-off 2
Topr = 25°C
–
0.01 0.1
µA
–
0.03
–
µA
–
1.8
6.4
µA
–
2.7
–
µA
125 kHz
No division FMR27 = 1
VCA20 = 0
125 kHz Divide-by-8 FMR27 = 1
VCA20 = 0
Off
No division FMR27 = 1
VCA20 = 0
Off
No division FMSTP = 1
VCA20 = 0
Off
Off
Off
125 kHz
–
Off
Off
Off
125 kHz
–
Off
32 kHz
Off
Off
–
Off
32 kHz
Off
Off
–
Off
Off
Off
Off
–
Off
Off
Off
Off
–
Off
Off
Off
Off
–
Off
Off
Off
Off
–
Off
32 kHz
Off
Off
–
Off
32 kHz
Off
Off
–
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 0
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
–
–
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
Max Unit
Min. Typ.
(3)
.
Power-off 2
Topr = 85°C
Vcc = 4.0 V to 5.5 V, single chip mode, output pins are open, and other pins are Vss.
XIN is set to square wave input.
Vcc = 5.0 V
VLCD = Vcc, external division resistors are used for VL3 to VL1, 1/3 bias, 1/4 duty, f(FR) = 64 Hz, SEG0 to SEG39 are selected, and segment
and common output pins are open. The standard value does not include the current that flows through external division resistors.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 87 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 5.49
DC Characteristics (3) [2.7 V ≤ Vcc < 4.0 V]
(Topr = −20 to 85°C (N version)/ −40 to 85°C (D version), unless otherwise specified.)
Symbol
VOH
Parameter
Output “H” voltage
Output “L” voltage
Hysteresis
Min.
Unit
Typ.
Max.
Port P7_0, P7_1, P8 (1) IOH = −5 mA VCC − 0.5
–
VCC
V
IOH = −1 mA VCC − 0.5
–
VCC
V
V
Port P7_0, P7_1, P8 (1) IOL = 5 mA
–
–
0.5
IOL = 1 mA
–
–
0.5
V
INT0, INT1, INT2,
INT3, INT4, INT5,
INT6, INT7,
KI0, KI1, KI2, KI3,
KI4, KI5, KI6, KI7,
TRCIOA, TRCIOB,
TRCIOC, TRCIOD,
TRJ0IO, TRJ1IO,
TRJ2IO, TRCTRG,
TRCCLK, ADTRG,
RXD0, RXD2, CLK0,
CLK2, SSI, SCL,
SDA, SSO
0.05
0.4
–
V
RESET, WKUP0
0.1
0.8
–
V
µA
Other pins
VT+-VT-
Standard
Condition
Other pins
VOL
5. Electrical Characteristics
IIH
Input “H” current
VI = 3 V, VCC = 3 V
–
–
5.0
IIL
Input “L” current
VI = 0 V, VCC = 3 V
–
–
−5.0
µA
VI = 0 V, VCC = 3 V
25
80
140
kΩ
RPULLUP Pull-up resistance
RfXIN
Feedback resistance XIN
–
2.0
–
MΩ
RfXCIN
Feedback resistance XCIN
–
14
–
MΩ
VRAM
RAM hold voltage
1.8
–
–
V
During stop mode
Note:
1. This applies when the drive capacity of the output transistor is set to High by registers P7DRR and P8DRR. When the drive
capacity is set to Low, the value of any other pin applies.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 88 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 5.50
5. Electrical Characteristics
DC Characteristics (4) [2.7 V ≤ Vcc < 4.0 V]
(Topr = −20 to 85°C (N version)/ −40 to 85°C (D version), unless otherwise specified.)
Condition
Oscillation
Circuit
20 MHz
10 MHz
20 MHz
Off
Off
Off
20 MHz
10 MHz
Off
Highspeed
Off
on-chip
Off
oscillator
mode
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
20 MHz
20 MHz
10 MHz
10 MHz
4 MHz
125 kHz
125 kHz
125 kHz
125 kHz
125 kHz
125 kHz
125 kHz
Lowspeed
on-chip
oscillator
mode
Lowspeed
clock
mode
Off
Off
Off
125 kHz
Off
Off
Off
125 kHz
Off
32 kHz
Off
Off
No division
FMR27 = 1
VCA20 = 0
Off
32 kHz
Off
Off
No division
FMSTP = 1
VCA20 = 0
Off
Off
Off
125 kHz
–
Off
Off
Off
125 kHz
–
Off
32 kHz
Off
Off
–
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 0
Off
32 kHz
Off
Off
–
Off
Off
Off
Off
–
Off
Off
Off
Off
–
Off
Off
Off
Off
–
Off
Off
Off
Off
–
Off
32 kHz
Off
Off
–
Off
32 kHz
Off
Off
–
Symbol Parameter
XIN
ICC
Power
Highsupply
speed
(1)
clock
current
mode
Wait
mode
Stop
mode
Poweroff mode
Notes:
1.
2.
3.
4.
Standard
On-Chip
Oscillator
HighLowSpeed Speed
Off
125 kHz
Off
125 kHz
Off
Off
(2)
XCIN
CPU Clock
Low-PowerConsumption
Setting
Other
No division
–
No division
–
No division FMR27 = 1
Flash memory off
MSTCR0 = BEh Program operation on RAM
MSTCR1 = 3Fh Module standby setting
enabled
Divide-by-8
–
Divide-by-8
–
No division
–
Divide-by-8
–
No division
–
Divide-by-8
–
Divide-by-16 MSTCR0 = BEh
MSTCR1 = 3Fh
No division FMR27 = 1
VCA20 = 0
Divide-by-8 FMR27 = 1
VCA20 = 0
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
–
–
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
Max Unit
Min. Typ.
(3)
.
–
–
–
4.7
2.3
2.9
10
6
–
mA
mA
mA
–
–
–
–
–
–
–
1.8
1.0
5.0
2.1
2.9
1.5
0.9
–
–
11
–
–
–
–
mA
mA
mA
mA
mA
mA
mA
–
106 300 µA
–
54
200 µA
–
54
200 µA
Flash memory off
Program operation on RAM
–
36
–
µA
While a WAIT instruction is
executed
Peripheral clock operation
–
9.0
50
µA
While a WAIT instruction is
executed
Peripheral clock off
–
2.5
31
µA
While a WAIT LCD drive
instruction is control circuit
(4)
executed
When external
Peripheral
division
clock off
resistors are
Timer RH
used
operation in
real-time clock
mode
While a WAIT instruction is
executed
Peripheral clock off
Timer RH operation in realtime clock mode
–
3.1
–
µA
–
1.7
–
µA
Topr = 25°C
Peripheral clock off
–
0.5
2.2
µA
Topr = 85°C
Peripheral clock off
–
1.2
–
µA
Power-off 0
Topr = 25°C
Power-off 0
Topr = 85°C
Power-off 2
Topr = 25°C
–
0.01 0.1
µA
–
0.02
–
µA
–
1.3
4.5
µA
–
2.2
–
µA
Power-off 2
Topr = 85°C
Vcc = 2.7 V to 4.0 V, single chip mode, output pins are open, and other pins are Vss.
XIN is set to square wave input.
Vcc = 3.0 V
VLCD = Vcc, external division resistors are used for VL3 to VL1, 1/3 bias, 1/4 duty, f(FR) = 64 Hz, SEG0 to SEG39 are selected, and segment
and common output pins are open. The standard value does not include the current that flows through external division resistors.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 89 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 5.51
DC Characteristics (5) [1.8 V ≤ Vcc < 2.7 V]
(Topr = −20 to 85°C (N version)/ −40 to 85°C (D version), unless otherwise specified.)
Symbol
VOH
Parameter
Output “H” voltage
Output “L” voltage
Hysteresis
Min.
Unit
Typ.
Max.
Port P7_0, P7_1, P8 (1) IOH = −2 mA VCC − 0.5
–
VCC
V
IOH = −1 mA VCC − 0.5
–
VCC
V
V
Port P7_0, P7_1, P8 (1) IOL = 2 mA
–
–
0.5
IOL = 1 mA
–
–
0.5
V
INT0, INT1, INT2,
INT3, INT4, INT5,
INT6, INT7,
KI0, KI1, KI2, KI3,
KI4, KI5, KI6, KI7,
TRCIOA, TRCIOB,
TRCIOC, TRCIOD,
TRJ0IO, TRJ1IO,
TRJ2IO, TRCTRG,
TRCCLK, ADTRG,
RXD0, RXD2, CLK0,
CLK2, SSI, SCL,
SDA, SSO
0.05
0.4
–
V
RESET, WKUP0
0.1
0.8
–
V
µA
Other pins
VT+-VT-
Standard
Condition
Other pins
VOL
5. Electrical Characteristics
IIH
Input “H” current
VI = 1.8 V, VCC = 1.8 V
–
–
4.0
IIL
Input “L” current
VI = 0 V, VCC = 1.8 V
–
–
−4.0
µA
VI = 0 V, VCC = 1.8 V
85
220
500
kΩ
RPULLUP Pull-up resistance
RfXIN
Feedback resistance XIN
–
2.0
–
MΩ
RfXCIN
Feedback resistance XCIN
–
14
–
MΩ
VRAM
RAM hold voltage
1.8
–
–
V
During stop mode
Note:
1. This applies when the drive capacity of the output transistor is set to High by registers P7DRR and P8DRR. When the drive
capacity is set to Low, the value of any other pin applies.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 90 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 5.52
DC Characteristics (6) [1.8 V ≤ Vcc < 2.7 V]
(Topr = −20 to 85°C (N version)/ −40 to 85°C (D version), unless otherwise specified.)
Oscillation
Circuit
Symbol Parameter
XIN
ICC
(2)
XCIN
Condition
On-Chip
Low-PowerOscillator
CPU Clock
Consumption
HighLowSetting
Speed Speed
Off
125 kHz No division
–
Off
125 kHz Divide-by-8
–
Standard
Other
Power
High8 MHz
Off
supply
speed
8 MHz
Off
(1)
clock
current
mode
Off
Off
5 MHz 125 kHz No division
–
Highspeed
Off
Off
5 MHz 125 kHz Divide-by-8
–
on-chip
Off
Off
4 MHz 125 kHz Divide-by-16 MSTCR0 = BEh
oscillator
MSTCR1 = 3Fh
mode
Off
Off
Off
125 kHz No division FMR27 = 1
LowVCA20 = 0
speed
on-chip
Off
Off
Off
125 kHz Divide-by-8 FMR27 = 1
oscillator
VCA20 = 0
mode
LowOff
32 kHz
Off
Off
No division FMR27 = 1
speed
VCA20 = 0
clock
mode
Off
32 kHz
Off
Off
No division FMSTP = 1
Flash memory off
VCA20 = 0
Program operation on RAM
Wait
mode
Stop
mode
Poweroff mode
Notes:
1.
2.
3.
4.
5. Electrical Characteristics
Off
Off
Off
125 kHz
–
Off
Off
Off
125 kHz
–
Off
32 kHz
Off
Off
–
Off
32 kHz
Off
Off
–
Off
Off
Off
Off
–
Off
Off
Off
Off
–
Off
Off
Off
Off
–
Off
Off
Off
Off
–
Off
32 kHz
Off
Off
–
Off
32 kHz
Off
Off
–
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 0
VCA27 = 0
VCA26 = 0
VCA25 = 0
VCA20 = 1
CM02 = 1
CM01 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
–
–
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
VCA27 = 0
VCA26 = 0
VCA25 = 0
CM10 = 1
Max Unit
Min. Typ.
(3)
.
–
–
2.1
0.9
–
–
mA
mA
–
–
–
1.8
1.1
0.9
5
–
–
mA
mA
mA
–
106 300 µA
–
54
200 µA
–
54
200 µA
–
36
–
µA
While a WAIT instruction is
executed
Peripheral clock operation
–
9.0
50
µA
While a WAIT instruction is
executed
Peripheral clock off
–
2.5
31
µA
While a WAIT LCD drive
control circuit
instruction is
(4)
executed
When external
Peripheral
division
clock off
resistors are
Timer RH
used
operation in
real-time clock
mode
While a WAIT instruction is
executed
Peripheral clock off
Timer RH operation in realtime clock mode
–
2.4
–
µA
–
1.7
–
µA
Topr = 25°C
Peripheral clock off
–
0.5
2.2
µA
Topr = 85°C
Peripheral clock off
–
1.2
–
µA
Power-off 0
Topr = 25°C
Power-off 0
Topr = 85°C
Power-off 2
Topr = 25°C
–
0.01 0.1
µA
–
0.02
–
µA
–
1.2
4
µA
–
2
–
µA
Power-off 2
Topr = 85°C
Vcc = 1.8 V to 2.7 V, single chip mode, output pins are open, and other pins are Vss.
XIN is set to square wave input.
Vcc = 2.2 V
VLCD = Vcc, external division resistors are used for VL3 to VL1, 1/3 bias, 1/4 duty, f(FR) = 64 Hz, SEG0 to SEG39 are selected, and segment
and common output pins are open.The standard value does not include the current that flows through external division resistors.
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 91 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
5.2.5
Table 5.53
5. Electrical Characteristics
AC Characteristics
Timing Requirements of Synchronous Serial Communication Unit (SSU)
(VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = −20 to 85°C (N version)/ −40 to 85°C
(D version), unless otherwise specified.)
Symbol
Parameter
Conditions
Standard
Min.
Typ.
Max.
4
–
-
Unit
tSUCYC
SSCK clock cycle time
tHI
SSCK clock “H” width
0.4
–
0.6
tSUCYC
tLO
SSCK clock “L” width
0.4
–
0.6
tSUCYC
tRISE
SSCK clock rising
time
Master
–
–
1
tCYC (1)
Slave
–
–
1
µs
tFALL
SSCK clock falling
time
Master
–
–
1
tCYC (1)
–
–
1
µs
tSU
SSO, SSI data input setup time
100
–
–
ns
tH
SSO, SSI data input hold time
1
–
–
tCYC (1)
tLEAD
SCS setup time
Slave
1tCYC + 50
–
–
ns
tLAG
SCS hold time
Slave
1tCYC + 50
–
–
ns
tOD
SSO, SSI data output delay time
–
–
1tCYC + 20
ns
tSA
SSI slave access time
–
–
1.5tCYC + 100
ns
tOR
SSI slave out open time
Slave
2.7 V ≤ VCC ≤ 5.5 V
tCYC (1)
1.8 V ≤ VCC < 2.7 V
–
–
1.5tCYC + 200
ns
2.7 V ≤ VCC ≤ 5.5 V
–
–
1.5tCYC + 100
ns
1.8 V ≤ VCC < 2.7 V
–
–
1.5tCYC + 200
ns
Note:
1. 1tCYC = 1/f1(s)
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 92 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
5. Electrical Characteristics
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIL or VOL
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIL or VOL
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
CPHS, CPOS: Bits in SSMR register
Figure 5.15
I/O Timing of Synchronous Serial Communication Unit (SSU) (Master)
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 93 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
5. Electrical Characteristics
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIL or VOL
tLEAD
tHI
tFALL
tRISE
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
4-Wire Bus Communication Mode, Slave, CPHS = 0
VIH or VOH
SCS (input)
VIL or VOL
tLEAD
tHI
tFALL
tRISE
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
CPHS, CPOS: Bits in SSMR register
Figure 5.16
I/O Timing of Synchronous Serial Communication Unit (SSU) (Slave)
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 94 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
5. Electrical Characteristics
tHI
VIH or VOH
SSCK
VIL or VOL
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
Figure 5.17
tH
I/O Timing of Synchronous Serial Communication Unit (SSU) (Clock Synchronous
Communication Mode)
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 95 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 5.54
5. Electrical Characteristics
Timing Requirements of I2C bus Interface (1)
(VCC = 1.8 to 5.5 V, VSS = 0 V, and Topr = −20 to 85°C (N version)/ −40 to 85°C (D version),
unless otherwise specified.)
Symbol
Parameter
tSCL
SCL input cycle time
tSCLH
tSCLL
tsf
Standard
Condition
Min.
Typ.
Max.
Unit
–
–
ns
SCL input “H” width
3tCYC + 300
(1)
–
–
ns
SCL input “L” width
5tCYC + 500 (1)
–
–
ns
SCL, SDA input fall time
–
–
300
ns
tSP
SCL, SDA input spike pulse rejection time
–
–
1tCYC (1)
ns
tBUF
SDA input bus-free time
5tCYC (1)
–
–
ns
tSTAH
Start condition input hold time
3tCYC (1)
–
–
ns
tSTAS
Retransmit start condition input setup time
3tCYC (1)
–
–
ns
tSTOP
Stop condition input setup time
3tCYC (1)
–
–
ns
tSDAS
Data input setup time
1tCYC + 40 (1)
–
–
ns
tSDAH
Data input hold time
10
–
–
ns
12tCYC + 600 (1)
Note:
1. 1tCYC = 1/f1(s)
VIH
SDA
VIL
tBUF
tSTAH
tSCLH
tSTAS
tSP
tSTOP
SCL
P(2)
S(1)
tsf
Sr(3)
tSCLL
tsr
tSCL
P(2)
tSDAS
tSDAH
Notes:
1. Start condition
2. Stop condition
3. Retransmit start condition
Figure 5.18
I/O Timing of I2C bus Interface
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 96 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 5.55
5. Electrical Characteristics
External Clock Input (XIN, XCIN)
(VSS = 0 V and Topr = −20 to 85°C (N version)/ −40 to 85°C (D version), unless otherwise
specified.)
Standard
Symbol
Parameter
VCC = 2.2V, Topr = 25°C
VCC = 3V, Topr = 25°C
VCC = 5V, Topr = 25°C
Min.
Max.
Min.
Max.
Min.
Unit
Max.
tc(XIN)
XIN input cycle time
200
–
50
–
50
–
ns
tWH(XIN)
XIN input “H” width
90
–
24
–
24
–
ns
tWL(XIN)
XIN input “L” width
90
–
24
–
24
–
ns
tc(XCIN)
XCIN input cycle time
20
–
20
–
20
–
µs
tWH(XCIN)
XCIN input “H” width
10
–
10
–
10
–
µs
tWL(XCIN)
XCIN input “L” width
10
–
10
–
10
–
µs
tC(XIN), tC(XCIN)
tWH(XIN),
tWH(XCIN)
External Clock
Input
tWL(XIN), tWL(XCIN)
Figure 5.19
Table 5.56
External Clock Input Timing Diagram
Timing Requirements of TRJiIO (i = 0 to 2)
(VSS = 0 V and Topr = −20 to 85°C (N version)/ −40 to 85°C (D version), unless otherwise
specified.)
Standard
Symbol
Parameter
VCC = 2.2V, Topr = 25°C
VCC = 3V, Topr = 25°C
Min.
Max.
Min.
VCC = 5V, Topr = 25°C
Max.
Min.
Max.
Unit
tc(TRJIO)
TRJiIO input cycle time
500
–
300
–
100
–
ns
tWH(TRJIO)
TRJiIO input “H” width
200
–
120
–
40
–
ns
tWL(TRJIO)
TRJiIO input “L” width
200
–
120
–
40
–
ns
tC(TRJIO)
tWH(TRJIO)
TRJiIO input
tWL(TRJIO)
Figure 5.20
Input Timing of TRJiIO
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 97 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Table 5.57
5. Electrical Characteristics
Timing Requirements of Serial Interface
(VSS = 0 V and Topr = −20 to 85°C (N version)/ −40 to 85°C (D version), unless otherwise
specified.)
Standard
Symbol
Parameter
VCC = 2.2V, Topr = 25°C
VCC = 3V, Topr = 25°C
VCC = 5V, Topr = 25°C
Min.
Max.
Min.
Max.
Min.
Unit
Max.
tc(CK)
CLKi input cycle time
800
–
300
–
200
–
ns
tW(CKH)
CLKi input “H” width
400
–
150
–
100
–
ns
tW(CKL)
CLKi input “L” width
400
–
150
–
100
–
ns
td(C-Q)
TXDi output delay time
–
200
–
80
–
50
ns
th(C-Q)
TXDi hold time
0
–
0
–
0
–
ns
tsu(D-C)
RXDi input setup time
150
–
70
–
50
–
ns
th(C-D)
RXDi input hold time
90
–
90
–
90
–
ns
i = 0, 2
tC(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
i = 0, 2
Figure 5.21
Table 5.58
Input and Output Timing of Serial Interface
Timing Requirements of External Interrupt INTi (i = 0 to 7) and Key Input Interrupt KIi
(i = 0 to 7)
(VSS = 0 V and Topr = −20 to 85°C (N version)/ −40 to 85°C (D version), unless otherwise
specified.)
Standard
Symbol
VCC = 2.2V, Topr = 25°C
Parameter
VCC = 3V, Topr = 25°C
VCC = 5V, Topr = 25°C
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tW(INH)
INTi input “H” width, KIi input “H” width
1000 (1)
–
380 (1)
–
250 (1)
–
ns
tW(INL)
INTi input “L” width, KIi input “L” width
1000 (2)
–
380 (2)
–
250 (2)
–
ns
Notes:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
INTi input
(i = 0 to 7)
tW(INL)
KIi input
(i = 0 to 7)
Figure 5.22
tW(INH)
Input Timing of External Interrupt INTi and Key Input Interrupt KIi
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Page 98 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
Package Dimensions
Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of
the Renesas Electronics web site.
JEITA Package Code
P-LQFP32-7x7-0.80
RENESAS Code
PLQP0032GB-A
Previous Code
32P6U-A
MASS[Typ.]
0.2g
HD
*1
D
24
17
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
16
25
bp
c
c1
HE
*2
E
b1
Reference
Symbol
32
9
1
ZE
Terminal cross section
8
ZD
c
A
F
A2
Index mark
A1
S
L
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
L1
y S
e
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Detail F
*3
bp
x
e
x
y
ZD
ZE
L
L1
Dimension in Millimeters
Min Nom Max
6.9 7.0 7.1
6.9 7.0 7.1
1.4
8.8 9.0 9.2
8.8 9.0 9.2
1.7
0.1 0.2
0
0.32 0.37 0.42
0.35
0.09 0.145 0.20
0.125
0°
8°
0.8
0.20
0.10
0.7
0.7
0.3 0.5 0.7
1.0
Page 99 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
JEITA Package Code
P-LQFP52-10x10-0.65
RENESAS Code
PLQP0052JA-A
Previous Code
52P6A-A
Package Dimensions
MASS[Typ.]
0.3g
HD
*1
D
39
27
40
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
26
bp
c
c1
*2
E
HE
b1
Reference
Symbol
14
1
Terminal cross section
ZE
52
13
ZD
Index mark
A
A2
c
F
A1
S
y S
e
L
*3
bp
RENESAS Code
PLQP0064KB-A
Previous Code
64P6Q-A / FP-64K / FP-64KV
Min
9.9
9.9
Nom
10.0
10.0
1.4
11.8 12.0
11.8 12.0
0.05
0.27
0.09
0°
L1
x
e
x
y
ZD
ZE
L
L1
Detail F
JEITA Package Code
P-LQFP64-10x10-0.50
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
Dimension in Millimeters
0.35
Max
10.1
10.1
12.2
12.2
1.7
0.1 0.15
0.32 0.37
0.30
0.145 0.20
0.125
8°
0.65
0.13
0.10
1.1
1.1
0.5 0.65
1.0
MASS[Typ.]
0.3g
HD
*1
D
48
33
49
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
32
bp
HE
64
1
c
Reference
Symbol
Terminal cross section
ZE
17
c1
*2
E
b1
16
Index mark
ZD
c
A
*3
A1
y S
e
A2
F
S
bp
L
x
L1
Detail F
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
e
x
y
ZD
ZE
L
L1
Dimension in Millimeters
Min Nom Max
9.9 10.0 10.1
9.9 10.0 10.1
1.4
11.8 12.0 12.2
11.8 12.0 12.2
1.7
0.05 0.1 0.15
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
8°
0.5
0.08
0.08
1.25
1.25
0.35 0.5 0.65
1.0
Page 100 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
JEITA Package Code
P-LQFP64-14x14-0.80
RENESAS Code
PLQP0064GA-A
Previous Code
64P6U-A/ 
Package Dimensions
MASS[Typ.]
0.7g
HD
*1
D
33
48
49
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
32
bp
c
Reference
Symbol
*2
E
HE
c1
b1
ZE
Terminal cross section
64
17
c
Index mark
A2
16
ZD
A
1
F
A1
S
L
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
L1
y S
e
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
Detail F
*3
bp
x
e
x
y
ZD
ZE
L
L1
Dimension in Millimeters
Min Nom Max
13.9 14.0 14.1
13.9 14.0 14.1
1.4
15.8 16.0 16.2
15.8 16.0 16.2
1.7
0.1 0.2
0
0.32 0.37 0.42
0.35
0.09 0.145 0.20
0.125
0°
8°
0.8
0.20
0.10
1.0
1.0
0.3 0.5 0.7
1.0
Page 101 of 102
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group
JEITA Package Code
P-LQFP80-12x12-0.50
RENESAS Code
PLQP0080KB-A
Previous Code
80P6Q-A
Package Dimensions
MASS[Typ.]
0.5g
HD
*1
D
60
41
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
40
61
bp
c
HE
*2
E
c1
b1
Reference
Symbol
Terminal cross section
ZE
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
80
21
1
20
ZD
Index mark
F
A1
*3
c
A
y S
bp
e
A2
S
e
x
y
ZD
ZE
L
L1
L
x
L1
Detail F
JEITA Package Code
P-LQFP80-14x14-0.65
RENESAS Code
PLQP0080JA-A
Previous Code
FP-80W / FP-80WV
Dimension in Millimeters
Min Nom Max
11.9 12.0 12.1
11.9 12.0 12.1
1.4
13.8 14.0 14.2
13.8 14.0 14.2
1.7
0.1 0.2
0
0.15 0.20 0.25
0.18
0.09 0.145 0.20
0.125
0°
10°
0.5
0.08
0.08
1.25
1.25
0.3 0.5 0.7
1.0
MASS[Typ.]
0.6g
HD
*1
D
41
60
61
40
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
HE
b1
ZE
80
Reference
Symbol
c
c1
*2
E
bp
Terminal cross section
21
1
20
ZD
c
A
F
A2
Index mark
A1
θ
S
y S
e
R01DS0011EJ0100 Rev.1.00
Dec 21, 2010
L
L1
*3
bp
Detail F
× M
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
θ
e
x
y
ZD
ZE
L
L1
Dimension in Millimeters
Min Nom Max
13.9 14.0 14.1
13.9 14.0 14.1
1.4
15.8 16.0 16.2
15.8 16.0 16.2
1.7
0.05 0.1 0.15
0.27 0.32 0.37
0.30
0.09 0.145 0.20
0.125
0°
8°
0.65
0.13
0.10
0.825
0.825
0.35 0.5 0.65
1.0
Page 102 of 102
REVISION HISTORY
Rev.
Date
0.01
0.02
Jan 18, 2010
Jul 16, 2010
1.00
Dec 21, 2010
Page
—
2
3
4
5
6
7
8
9
10
11
12
13
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group Datasheet
Description
Summary
First Edition issued
Table 1.1 revised
Table 1.2 revised
Tables 1.4 and 1.5 revised
Table 1.6 revised
Table 1.7 revised
Table 1.8 revised
Table 1.9 and Figure 1.1 revised
Table 1.10 and Figure 1.2 revised
Table 1.11 and Figure 1.3 revised
Table 1.12 revised
Figure 1.5 revised
Figure 1.6 revised
14
16
17
18
19
20
21
Figure 1.7 revised
Figure 1.9 revised
Figure 1.10 revised
Table 1.13 revised
Table 1.14 revised
Figure 1.11 revised
Figure 1.12 revised
25
26
30
31
Table 1.18 revised
Table 1.19 revised
Figure 3.1 revised
Table 4.1, Note 3 revised
35
41 to 44
All
2
3
4
6
7
10
12
13
14
15
16
18
19
20
22
23
24
25, 26
Table 4.5 revised
Package Dimensions revised
“Preliminary” and “Under development” deleted
Table 1.1 revised
Tables 1.2 and 1.3 Note 2 revised
Tables 1.4 and 1.5 Note 1 revised
Table 1.7 revised
Table 1.8 revised
Table 1.11 and Figure 1.3 revised
Figure 1.5 revised
Figure 1.6 revised
Figure 1.7 revised
Figure 1.8 revised
Figure 1.9 revised
Table 1.13 revised
Table 1.14 revised
Figure 1.11 revised
Table 1.15 revised
Table 1.16 revised
Table 1.17 revised
Tables 1.18 and 1.19 Pin Functions for R8C/LA5A Group added
C-1
REVISION HISTORY
Rev.
Date
1.00
Dec 21, 2010
Page
32
33 to 41
52 to 98
92
R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group Datasheet
Description
Summary
“The internal ROM (program ROM) is allocated lower addresses, beginning with
address 0FFFFh.” deleted
Figure 3.1 revised
Tables 4.1 to 4.9 SFR information for R8C/LA5A Group added
“5. Electrical Characteristics” added
Package Dimensions “PVQN0064LB-A” deleted
All trademarks and registered trademarks are the property of their respective owners.
C-2
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
 The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
 The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
 The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
 When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
 The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
Notice
1.
All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas
Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to
be disclosed by Renesas Electronics such as that disclosed through our website.
2.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
3.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
4.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
5.
When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and
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the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is
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6.
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Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas
Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for
which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the
use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics.
The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools;
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"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically
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"Specific":
Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical
implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
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You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
9.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or system manufactured by you.
10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2)
"Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
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