Dual MOSFET Driver with Bootstrapping ADP3415 FEATURES All-in-One Synchronous Buck Driver One PWM Signal Generates Both Drives Anticross Conduction Protection Circuitry Programmable Transition Delay Zero-Crossing Synchronous Drive Control Synchronous Override Control Undervoltage Lockout Shutdown Quiescent Current <100 A APPLICATIONS Mobile Computing CPU Core Power Converters Multiphase Desktop CPU Supplies Single-Supply Synchronous Buck Converters Standard-to-Synchronous Converter Adaptations FUNCTIONAL BLOCK DIAGRAM ADP3415 UVLO VCC BST DRVH IN SD SW OVERLAP PROTECTION CIRCUIT DLY VCC DRVL DRVLSD GND GENERAL DESCRIPTION The ADP3415 is a dual MOSFET driver optimized for driving two N-channel FETs that are the two switches in the nonisolated synchronous buck power converter topology. Each driver size is optimized for performance in notebook PC regulators for CPUs in the 20 A range. The high-side driver can be bootstrapped atop the switched node of the buck converter as needed to drive the upper switch and is designed to accommodate the high voltage slew rate associated with high performance, high frequency switching. The ADP3415 features an overlapping protection circuit (OPC); undervoltage lockout (UVLO) that holds the switches off until the driver is assured of having sufficient voltage for proper operation; a programmable transition delay; and a synchronous drive disable pin. The quiescent current, when the device is disabled, is less than 100 µA. The ADP3415 is specified over the extended commercial temperature range of 0°C to 100°C and is available in a 10-lead MSOP package. 5V FROM DUTY RATIO MODULATOR IN FROM SYSTEM ENABLE CONTROL SD FROM SYSTEM STATE LOGIC VCC VDCIN BST DRVH ADP3415 DRVLSD DLY VOUT SW DRVL GND Figure 1. Typical Application Circuit REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved. ADP3415–SPECIFICATIONS1 (TA = 0ⴗC to 100ⴗC, VCC = 5 V, VBST – VSW = 5 V, SD = 5 V, CDRVH = CDRVL = 3 nF, unless otherwise noted.) Parameter Conditions SUPPLY (VCC) Quiescent Current2 Shutdown Mode Operating Mode Symbol Min VSD = 0.8 V VSD = 5 V, No Switching VCCUVLO VCCHUVLO 3.9 LOW-SIDE DRIVER SHUTDOWN (DRVLSD) Input Voltage High3 Input Voltage Low3 Propagation Delay3, 4 (See Figure 3) VIH VIL tpdlDRVLSD tpdhDRVLSD 2.0 SHUTDOWN (SD) Input Voltage High3 Input Voltage Low3 VIH VIL 2.0 INPUT (IN) Input Voltage High3 Input Voltage Low3 VIH VIL 2.0 THERMAL SHUTDOWN (THSD) THSD Threshold THSD Hysteresis TSD THSD (See Figure 4) LOW-SIDE DRIVER (DRVL) Output Resistance, DRVL–VCC Output Resistance, DRVL–GND DRVL Transition Times4 (See Figure 4) DRVL Propagation Delay4, 5, 6 (See Figure 4) SW Transition Timeout7 Zero-Crossing Threshold Max Unit 30 1.2 65 2 µA mA 4.15 0.05 4.5 V V ICCQ UNDERVOLTAGE LOCKOUT (UVLO) UVLO Threshold UVLO Hysteresis HIGH-SIDE DRIVER (DRVH) Output Resistance, DRVH–BST Output Resistance, DRVH–SW DRVH Transition Times4 (See Figure 4) DRVH Propagation Delay4, 5 Typ trDRVH tfDRVH tpdhDRVH 20 10 TJ = TA TJ = TA 165 10 VBST – VSW = 4.6 V 1.5 0.85 20 25 22 VBST – VSW = 4.6 V, VDLY = 0 V RDLY ≥ 120 kΩ 10 100 tpdlDRVH trDRVL tfDRVL tpdhDRVL tpdlDRVL tSWTO VZC 40 VBST – VSW = 4.6 V VBST – VSW = 4.6 V VBST – VSW = 4.6 V VBST – VSW = 4.6 V VBST – VSW = 4.6 V 10 1.6 1.0 25 20 30 10 130 1.6 0.8 50 30 V V ns ns 0.8 V V 0.8 V V °C °C 3.5 2.0 30 35 40 200 70 Ω Ω ns ns ns ns ns 3.0 3.0 40 30 38 25 300 Ω Ω ns ns ns ns ns V NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 2 Including IBSTQ quiescent current. 3 The signal source driving the pin must have 70 µA (typ) pull-down strength to make a high-to-low transient, and 20 µA (typ) pull-up strength to make a low-to-high transient. The pin does not represent load (<100 nA) in static low (<0.8 V) and static high (>2.0 V) logic states (see TPC 3.) The pin can be driven with standard TTL logic level source. 4 Guaranteed by characterization. 5 For propagation delays, tpdh refers to the specified signal going high, tpdl refers to it going low. 6 Propagation delay measured until DRVL begins its transition. 7 The turn-on of DRVL is initiated after IN goes low by either V SW crossing a ~1.6 V threshold or by expiration of t SWTO. Specifications subject to change without notice. –2– REV. B ADP3415 ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V BST to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +30 V BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V SW to GND . . . . . . . . . . . . . . . . . . . . . . . . . –2.0 V to +25 V SD, IN, DRVLSD to GND . . . . . . . . . . . . . . –0.3 V to +7.3 V Operating Ambient Temperature Range . . . . . . 0°C to 100°C Operating Junction Temperature Range . . . . . . 0°C to 125°C JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155°C/W JC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C IN 1 SD 2 10 ADP3415 BST DRVH TOP VIEW DRVLSD 3 (Not to Scale) 8 SW 9 DLY 4 7 GND VCC 5 6 DRVL *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to GND. PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 IN TTL-Level Input Signal. Has primary control of the drive outputs. 2 SD Shutdown. When high, this pin enables normal operation. When low, DRVH and DRVL are forced low and the supply current (ICCQ) is minimized as specified. 3 DRVLSD Drive-Low Shutdown. When DRVLSD is low, DRVL is kept low. When DRVLSD is high, DRVL is enabled and controlled by IN and by the adaptive OPC function. 4 DLY High-Side Turn-On Delay. A resistor from this pin to ground programs an extended delay from turn-off of the lower FET to turn-on of the upper FET. 5 VCC Input Supply. This pin should be bypassed to GND with a ~10 µF ceramic capacitor. 6 DRVL Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) FET. 7 GND Ground. Should be directly connected to the ground plane, close to the source of the lower FET. 8 SW This pin should be connected to the buck switching node, close to the upper FET’s source. It is the floating return for the upper FET drive signal. Also, it is used to monitor the switched voltage for the OPC function. 9 DRVH Buck Drive. Output drive for the upper (buck) FET. 10 BST Floating Bootstrap Supply for the Upper FET. A capacitor connected between BST and SW pins holds this bootstrapped supply voltage for the high-side FET driver as it is switched. The capacitor should be an MLC type and should have substantially greater capacitance (e.g., ~ 20×) than the input capacitance of the upper FET. ORDERING GUIDE Model Temperature Guide Package Description Package Option Quantity per Reel Branding ADP3415LRM-REEL ADP3415LRM-REEL7 ADP3415LRMZ-REEL* 0°C to 100°C 0°C to 100°C 0°C to 100°C MSOP MSOP MSOP RM-10 RM-10 RM-10 3,000 1,000 3,000 P1E P1E P1E *Z = Pb-free part. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3415 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. B –3– ADP3415 VCC VCC UVLO VTOK VUVLOTH BIAS EN SD BIAS THERM SD THSD DBST VDCIN BST IN DRVH TON DLY DLY + R CLR Q S DRVH CBST Q1 SW SET RDLY VCC R DRVL TON DLY DRVL Q Q2 S GND ADP3415 DRVLSD Figure 2. Functional Block Diagram IN DRVLSD tpdlDRVLSD tpdhDRVLSD DRVL Figure 3. DRVLSD Propagation Delay –4– REV. B ADP3415 IN tpdl DRVL DRVL tpdh DRVL tpdl DRVH tf DRVL tr DRVL tpdh DRVH DRVH-SW tr DRVH tf DRVH Figure 4. Switching Timing Diagram (Propagation Delay Referenced to 50%, Rise and Fall Time to 10% and 90% Points) IN tSWTO DRVL CROWBAR ACTION SW DRVH Figure 5. Switching Waveforms–SW Node Failure Mode–DRVL Timeout REV. B –5– ADP3415–Typical Performance Characteristics 37 VCC = 5V CLOAD = 3nF 2V/DIV 35 DRVH 33 RISE TIME TIME – ns 31 DRVL 29 27 IN 25 VCC = 5V CLOAD = 3nF VSW = 0V 20ns/DIV FALL TIME 23 21 TIME – ns 0 25 50 75 100 125 JUNCTION TEMPERATURE – ⴗC TPC 1. DRVH Fall and DRVL Rise Times TPC 4. DRVL Rise and Fall Times vs. Temperature 30 VCC = 5V CLOAD = 3nF 2V/DIV 28 DRVL FALL TIME TIME – ns 26 DRVH 24 22 RISE TIME IN 20 VCC = 5V CLOAD = 3nF RDLY = 40k⍀ 20ns/DIV 18 16 TIME – ns 25 50 75 125 100 JUNCTION TEMPERATURE – ⴗC TPC 2. DRVL Fall and DRVH Rise Times TPC 5. DRVH Rise and Fall Times vs. Temperature 100 70 VCC = 5V TA = 25ⴗC VCC = 5V TA = 25ⴗC CLOAD = 3nF 90 80 60 70 50 60 HIGH-TO-LOW TRANSITION TIME – ns PEAK CURRENT – A 0 50 40 DRVL 40 30 30 DRVH 20 20 10 LOW-TO-HIGH TRANSITION 0 0 1 2 3 INPUT VOLTAGE – V 4 10 5 1 2 3 4 5 6 7 8 9 10 LOAD CAPACITANCE – nF TPC 3. Input Voltage vs. Input Current TPC 6. DRVH and DRVL Rise Time vs. Load Capacitance –6– REV. B ADP3415 52 VCC = 5V 47 CLOAD = 3nF 45 tpdlDRVH 35 SUPPLY CURRENT – mA 42 37 32 TIME – ns VCC = 5V TA = 25ⴗC CLOAD = 3nF 40 27 22 17 tpdlDRVL 12 30 25 20 15 10 5 7 0 200 2 0 25 50 75 100 JUNCTION TEMPERATURE – ⴗC 125 TPC 7. DRVH and DRVL Propagation Delay vs. Temperature 400 600 800 IN FREQUENCY – kHz 1000 1200 TPC 10. Supply Current vs. Frequency 10.5 52 10.0 VCC = 5V TA = 25ⴗC 47 SUPPLY CURRENT – mA 9.5 42 TIME – ns 37 DRVH 32 27 DRVL 22 8.0 7.5 VCC = 5V fIN = 250kHz CLOAD = 3nF 6.5 12 6.0 0 7 1 2 3 4 7 5 6 LOAD CAPACITANCE – nF 8 9 10 TPC 8. DRVH and DRVL Fall Time vs. Load Capacitance 182 142 OPEN DELAY PIN 122 102 82 62 42 SHORTED TO GROUND 22 2 0 25 50 75 100 JUNCTION TEMPERATURE – ⴗC 25 50 75 100 JUNCTION TEMPERATURE – ⴗC TPC 11. Supply Current vs. Temperature VCC = 5V fIN = 200kHz CLOAD = 3nF 162 TIME – ns 8.5 7.0 17 125 TPC 9. tpdhDRVH vs. Temperature REV. B 9.0 –7– 125 ADP3415 overlap protection circuit waits for the voltage at the SW pin to fall from VDCIN to 1.6 V. Once the voltage on the SW pin has fallen to 1.6 V, Q2 will begin to turn ON. By waiting for the voltage on the SW pin to reach 1.6 V, the overlap protection circuit ensures that Q1 is OFF before Q2 turns on, regardless of variations in temperature, supply voltage, gate charge, and drive current. There is, however, a timeout circuit that will override the waiting period for the SW pin to reach 1.6 V. After the timeout period has expired, DRVL will be asserted regardless of the SW voltage. THEORY OF OPERATION The ADP3415 is a dual MOSFET driver optimized for driving two N-channel FETs in a synchronous buck converter topology. A single duty ratio modulation signal is all that is required to command the proper drive signal for the high-side and the low-side FETs. A more detailed description of the ADP3415 and its features follows. Refer to the Functional Block Diagram (Figure 2). Drive State Input The drive state input, IN, should be connected to the duty ratio modulation signal of a switch-mode controller. IN can be driven by 2.5 V to 5.0 V logic. The FETs will be driven so that the SW node follows the polarity of IN. To prevent the overlap of the gate drives during Q2’s turn OFF and Q1’s turn ON, the overlap circuit provides a programmable delay that is set by a resistor on the DLY pin. When IN goes high, Q2 will begin to turn OFF (after a propagation delay), but before Q1 can turn ON, the overlap protection circuit waits for the voltage at DRVL to go low. Once the voltage at DRVL is low, the overlap protection circuit initiates a delay timer that is programmed by the external resistor RDLY. The delay resistor adds an additional specified delay. The delay allows time for current to commutate from the body diode of Q2 to an external Schottky diode, which allows turn-off losses to be reduced. Although not as foolproof as the adaptive delay, the programmable delay adds a safety margin to account for variations in size, gate charge, and internal delay of the external power MOSFETs. Low-Side Driver The supply rails for the low-side driver, DRVL, are VCC and GND. In its conventional application, it drives the gate of the synchronous rectifier FET. When the driver is enabled, the driver’s output is 180° out of phase with the duty ratio input aside from overlap protection circuit, propagation, and transition delays. When the driver is shut down or the entire ADP3415 is in shutdown or in undervoltage lockout, the low-side gate is held low. High-Side Driver Low-Side Driver Shutdown The supply rail for the high-side driver, DRVH, is between the BST and SW pins and is created by an external bootstrap supply circuit. In its conventional application, it drives the gate of the (top) main buck converter FET. The low-side driver shutdown, DRVLSD, allows a control signal to shut down the synchronous rectifier. This signal should be modulated by system state logic to achieve maximum battery life under light load conditions and maximum efficiency under heavy load conditions. Under heavy load conditions, DRVLSD should be high so that the synchronous switch is modulated for maximum efficiency. Under light load conditions, DRVLSD should be low to prevent needless switching losses due to charge shuttling caused by polarity reversal of the inductor current when the average current is low. The bootstrap circuit comprises a Schottky diode, DBST, and bootstrap capacitor, CBST. When the ADP3415 is starting up, the SW pin is at ground, so the bootstrap capacitor will charge up to VCC through DBST. As the supply voltage ramps up and exceeds the UVLO threshold, the driver is enabled. When the input pin, IN, goes high, the high-side driver will begin to turn the high-side FET (Q1) ON by transferring charge from CBST to the gate of the FET. As Q1 turns ON, the SW pin will rise up to VDCIN, forcing the BST pin to VDCIN + VC(BST), which is enough gate to source voltage to hold Q1 ON. To complete the cycle, when IN goes low, Q1 is switched OFF as DRVH discharges the gate to the voltage at the SW pin. When the low-side FET, Q2, turns ON, the SW pin is held at ground. This allows the bootstrap capacitor to charge up to VCC again. When the DRVLSD input is low, the low-side driver stays low. When the DRVLSD input is high, the low-side driver is enabled and controlled by the driver signals as previously described. Low-Side Driver Timeout Circuit In normal operation, the DRVH signal tracks the IN signal and turns OFF the Q1 high-side switch with a few tens of ns tpdlDRVH delay following the falling edge of the input signal. When Q1 is turned OFF, then DRVL is allowed to go high, Q2 to turn ON, and the SW node voltage to collapse to zero. But in a faulty scenario, such as the case of a high-side Q1 switch drain-source short circuit when even DRVH goes low, the SW node cannot fall to zero. The high-side driver’s output is in phase with the duty ratio input. When the driver is in undervoltage lockout, the high-side gate is held low. Overlap Protection Circuit The overlap protection circuit (OPC) prevents both of the main power switches, Q1 and Q2, from being ON at the same time. This prevents excessive shoot-through currents from flowing through both power switches and minimizes the associated losses that can occur during their ON-OFF transitions. The overlap protection circuit accomplishes this by adaptively controlling the delay from Q1’s turn OFF to Q2’s turn ON and by programming the delay from Q2’s turn OFF to Q1’s turn ON. The ADP3415 has a timer circuit to address this scenario. Every time the IN goes low, a DRVL on-time delay timer gets triggered (see Figure 2). Should the SW node voltage not trigger the low side turn-on, the DRVL on-time delay circuit will do it instead, when it times out with tSWTO delay (see Figure 5). If the high-side Q1 is still turned ON, i.e., its drain is shorted to the source, the low-side Q2 turn-on will create a direct short circuit across the VDCIN voltage rail, and the crowbar action will blow the fuse in the VDCIN current patch. The opening of the fuse saves the load (CPU) from potential damage that the high-side switch short circuit could have caused. To prevent the overlap of the gate drives during Q1’s turn OFF and Q2’s turn ON, the overlap circuit monitors the voltage at the SW pin. When IN goes low, Q1 will begin to turn OFF (after a propagation delay), but before Q2 can turn ON, the –8– REV. B ADP3415 Shutdown Bootstrap Circuit For optimal system power management, when the output voltage is not needed, the ADP3415 can be shut down to conserve power. The bootstrap circuit requires a charge storage capacitor, CBST, and a Schottky diode, D1, as shown in Figure 2. Selecting these components can be done after the high-side FET has been chosen. When the SD pin is high, the ADP3415 is enabled for normal operation. Pulling the SD pin low forces the DRVH and DRVL outputs low, turning the buck converter OFF and reducing the VCC supply current to less than 40 µA. The bootstrap capacitor must have a voltage rating that is able to handle the maximum battery voltage plus 5 V. The capacitance is determined using the following equation Undervoltage Lockout CBST = The undervoltage lockout (UVLO) circuit holds both FET driver outputs low during VCC supply ramp-up. The UVLO logic becomes active and in control of the driver outputs at a supply voltage of no greater than 1.5 V. The UVLO circuit waits until the VCC supply has reached a voltage high enough to bias logic level FETs fully ON, around 4.1 V, before releasing control of the drivers to the control pins. A Schottky diode is recommended for the bootstrap diode due to its low forward drop, which maximizes the drive available for the high-side FET. The bootstrap diode must also be able to withstand the maximum battery voltage plus 5 V. The average forward current can be estimated by The thermal shutdown circuit protects the ADP3415 against damage due to excessive power dissipation. Under extreme conditions, high ambient temperature and high power dissipation, the die temperature may rise up to the thermal shutdown threshold of 165°C. If the die temperature exceeds 165°C, the thermal shutdown circuit will turn the output drivers OFF. The drivers remain disabled until the junction temperature has decreased by 10°C, at which point the drivers are again enabled. IF ( AVG ) ≈ QGATE × f MAX Delay Resistor Selection The delay resistor, RDLY, is used to add an additional delay when the low-side FET drive turns off and when the high-side drive starts to turn on. The delay resistor programs a specified additional delay besides the 20 ns of fixed delay. For the supply input (VCC) of the ADP3415, a local bypass capacitor is recommended to reduce the noise and to supply some of the peak currents drawn. Use a 10 µF MLC capacitor. Keep the ceramic capacitor as close as possible to the ADP3415. Multilayer ceramic (MLC) capacitors provide the best combination of low ESR and small size and can be obtained from the following vendors: REV. B (2) where fMAX is the maximum switching frequency of the controller. APPLICATION INFORMATION Supply Capacitor Selection GRM235Y5V106Z16 EMK325F106ZF C23Y5V1C106ZP (1) where QGATE is the total gate charge of the high-side FET, and ⌬VBST is the voltage droop allowed on the high-side FET drive. For example, the IRFR8503 has a total gate charge of about 15 nC. For an allowed droop of 150 mV, the required bootstrap capacitance is 100 nF. Use an MLC capacitor. Thermal Shutdown Murata Taiyo-Yuden Tokin QGATE ∆VBST Printed Circuit Board Layout Considerations Use the following general guidelines when designing printed circuit boards: 1. Trace out the high current paths and use short, wide traces to make these connections. www.murata.com www.t-yuden.com www.tokin.com 2. Locate the VCC bypass capacitor as close as possible to the VCC and GND pins. –9– ADP3415 OUTLINE DIMENSIONS 10-Lead Micro Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 3.00 BSC 10 6 4.90 BSC 3.00 BSC 1 5 PIN 1 0.50 BSC 0.95 0.85 0.75 1.10 MAX 0.15 0.00 0.27 0.17 SEATING PLANE 0.23 0.08 8ⴗ 0ⴗ 0.80 0.60 0.40 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187BA –10– REV. B ADP3415 Revision History Location Page 1/04—Data Sheet changed from REV. A to REV. B. Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1/03—Data Sheet changed from REV. 0 to REV. A. Edits to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 REV. B –11– –12– C01681–0–1/04(B)